Three-dimensional Hall device, preparation method thereof and Hall sensor

Abstract

The invention relates to a three-dimensional Hall device, a preparation method thereof and a Hall sensor. The three-dimensional Hall device comprises a barrier layer arranged in a substrate; the isolation structure is arranged in the substrate and is positioned on one side, close to the front surface of the substrate, of the barrier layer; the shallow well layer is arranged in the device region; a plurality of first doping layers and a plurality of second doping layers which are arranged at intervals are arranged in the shallow well layer; each first doping layer is connected with a first electrode, and each second doping layer is connected with a second electrode, so that a first induction electrode pair and a first bias electrode pair are formed; the plurality of deep trap layers are arranged in the substrate and are positioned on one side, deviating from the shallow trap layer, of the isolation structure; a plurality of third doped layers and a plurality of fourth doped layers which are arranged at intervals are arranged in each deep trap layer, each third doped layer is connected with a third electrode, and each fourth doped layer is connected with a fourth electrode, so that a second induction electrode pair and a second bias electrode pair are formed. The preparation difficulty and the preparation cost of the three-dimensional Hall device can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional Hall device and its fabrication method, and a Hall sensor. Background Technology

[0002] Hall sensors are widely used magnetic sensors, consisting of a Hall device and a signal conditioning circuit. When detecting magnetic fields in space, transverse Hall devices (measuring the component of the magnetic field perpendicular to the device surface) and longitudinal Hall devices (measuring the component parallel to the device surface) are limited to specific directions and cannot provide complete three-dimensional magnetic field information. In applications requiring omnidirectional, high-precision magnetic field detection, three-dimensional Hall devices are crucial to the functionality of Hall sensors.

[0003] Three-dimensional Hall devices typically consist of lateral Hall devices and longitudinal Hall devices. The magnetic sensing surface of a lateral Hall device is parallel to the device surface, requiring a shallower active well depth. Conversely, the magnetic sensing surface of a longitudinal Hall device is perpendicular to the device surface, requiring a deeper active well. Therefore, to improve device performance, multiple ion implantations are necessary during the fabrication of three-dimensional Hall devices to form active wells of different depths suitable for lateral and longitudinal Hall devices. However, current fabrication processes for three-dimensional Hall devices are quite complex. Summary of the Invention

[0004] Therefore, it is necessary to provide a three-dimensional Hall device, its fabrication method, and a Hall sensor to address the above-mentioned problems.

[0005] To achieve the above objectives, in a first aspect, this application provides a three-dimensional Hall effect device, comprising:

[0006] Substrate;

[0007] A barrier layer is disposed within the substrate;

[0008] An isolation structure is disposed within the substrate and located on the side of the barrier layer closest to the front side of the substrate, the isolation structure enclosing to form a device region;

[0009] A shallow well layer is disposed within the device region; the shallow well layer contains a plurality of first doped layers and a plurality of second doped layers arranged at intervals; a first electrode is connected to each first doped layer, and a second electrode is connected to each second doped layer to form a first sensing electrode pair and a first bias electrode pair.

[0010] Multiple deep well layers are disposed within the substrate and located on the side of the isolation structure opposite to the shallow well layers; each deep well layer has multiple third doped layers and multiple fourth doped layers arranged at intervals, each of the third doped layers is connected to a third electrode, and each of the fourth doped layers is connected to a fourth electrode to form a second sensing electrode pair and a second bias electrode pair.

[0011] In one embodiment, the center of the shallow well layer coincides with the center of the device region.

[0012] In one embodiment, the orthographic projection of the shallow well layer onto the substrate is a first pattern, which is a centrally symmetric pattern.

[0013] In one embodiment, the orthographic projection of the first doped layer and the second doped layer onto the substrate forms a second pattern, the second pattern being centrally symmetrical about the shallow well layer.

[0014] In one embodiment, the shallow well layer includes a first sub-layer and four second sub-layers, two of which are located on either side of the first sub-layer along a first direction, and the remaining two of which are located on either side of the first sub-layer along a second direction.

[0015] In the two second sub-layers located on both sides of the first sub-layer along the first direction, each second sub-layer has a first doped layer; in the two second sub-layers located on both sides of the first sub-layer along the second direction, each second sub-layer has a second doped layer.

[0016] The first direction, the second direction, and the thickness direction of the substrate are perpendicular to each other.

[0017] In one embodiment, the plurality of deep well layers are arranged symmetrically.

[0018] In one embodiment, the plurality of third doped layers and the plurality of fourth doped layers within the same deep well layer are arranged alternately along the extension direction of the deep well layer.

[0019] The orthogonal projections of the plurality of third doped layers and the plurality of fourth doped layers onto the substrate form a third pattern, which is symmetrical about the center of the deep well layer.

[0020] In one embodiment, the three-dimensional Hall device includes four deep well layers, two of which are located on both sides of the isolation structure along a first direction, and the remaining two of which are located on both sides of the isolation structure along a second direction.

[0021] Each deep well layer contains three third doped layers and two fourth doped layers arranged alternately in sequence; the first direction, the second direction, and the thickness direction of the substrate are perpendicular to each other.

[0022] In one embodiment, the barrier layer is made of at least one of silicon oxide, silicon oxynitride, or silicon nitride.

[0023] Secondly, this application provides a Hall sensor, including the three-dimensional Hall device in any embodiment of the first aspect.

[0024] Thirdly, this application provides a method for fabricating a three-dimensional Hall sensor, comprising:

[0025] Provide substrate;

[0026] A barrier layer and an isolation structure are formed within the substrate; the isolation structure is located on the side of the barrier layer near the front side of the substrate and encloses a device region.

[0027] A shallow well layer is formed in the device region, and a plurality of deep well layers are formed in the substrate; the deep well layers are located on the side of the isolation structure opposite to the shallow well layer.

[0028] A plurality of first doped layers and a plurality of second doped layers are formed at intervals within the shallow well layer, and a plurality of third doped layers and a plurality of fourth doped layers are formed at intervals within the deep well layer.

[0029] A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on the first doped layer, the second doped layer, the third doped layer, and the fourth doped layer, respectively, to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair, and a second bias electrode pair.

[0030] The three-dimensional Hall device and its fabrication method, as well as the Hall sensor provided in this application, achieve three-dimensional detection by setting a barrier layer and an isolation structure within a substrate, with the isolation structure located on the side of the barrier layer closer to the front side of the substrate. A shallow well layer is placed within the device region enclosed by the isolation structure, and a deep well layer is located on the side of the isolation structure away from the shallow well layer. This allows the Hall device to achieve three-dimensional detection. Furthermore, during the fabrication of the shallow and deep well layers, the barrier layer acts as a barrier, requiring only one ion implantation to form shallow and deep well layers with different implantation depths. This reduces the number of steps and lowers the fabrication difficulty and cost of the three-dimensional Hall device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a three-dimensional Hall device provided in an embodiment of this application.

[0033] Figure 2for Figure 1 The diagram shows a partial structural schematic of the three-dimensional Hall effect device.

[0034] Figure 3 for Figure 1 The diagram shows a schematic diagram of the AA cross-section structure of the three-dimensional Hall device.

[0035] Figure 4 for Figure 1 A planar schematic diagram of the shallow well layer of the three-dimensional Hall device shown.

[0036] Figure 5 This is a schematic diagram of the planar arrangement of the deep well layer and isolation structure of another three-dimensional Hall device provided in an embodiment of this application.

[0037] Figure 6 This is a schematic diagram showing the arrangement of the third and fourth doped layers within the deep well layer of another three-dimensional Hall device provided in an embodiment of this application.

[0038] Figure 7 This is a schematic flowchart illustrating a method for fabricating a three-dimensional Hall device according to an embodiment of this application.

[0039] Figures 8-16 for Figure 7 A schematic diagram of the cross-sectional structure of the device during the fabrication process shown.

[0040] Explanation of reference numerals in the attached figures:

[0041] 10. Three-dimensional Hall device; 11. Substrate; 11a. Device region; 12. Barrier layer; 13. Isolation structure; 14. Shallow well layer; 141. First sublayer; 142. Second sublayer; 151. First doped layer; 152. Second doped layer; 16. Deep well layer; 171. Third doped layer; 172. Fourth doped layer; 181. First electrode; 182. Third electrode; 183. Fourth electrode; 19. Dielectric layer; 20. Dielectric material layer; 21. Contact hole; 30. Metal layer. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0047] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0048] Firstly, referring to Figure 1 , Figure 2 and Figure 3 As shown, this application provides a three-dimensional Hall device 10. The three-dimensional Hall device 10 includes a substrate 11, a barrier layer 12, an isolation structure 13, a shallow well layer 14, and a plurality of deep well layers 16.

[0049] Specifically, a barrier layer 12 is disposed within a substrate 11. An isolation structure 13 is disposed within the substrate 11 and located on the side of the barrier layer 12 closest to the front side of the substrate 11, the isolation structure 13 enclosing to form a device region 11a. A shallow well layer 14 is disposed within the device region 11a; the shallow well layer 14 has a plurality of first doped layers 151 and a plurality of second doped layers 152 arranged at intervals; a first electrode 181 is connected to each first doped layer 151, and a second electrode (not shown) is connected to each second doped layer 152 to form a first sensing electrode pair and a first bias electrode pair. A plurality of deep well layers 16 are disposed within the substrate 11 and located on the side of the isolation structure 13 opposite to the shallow well layer 14; each deep well layer 16 has a plurality of third doped layers 171 and a plurality of fourth doped layers 172 arranged at intervals, a third electrode 182 is connected to each third doped layer 171, and a fourth electrode 183 is connected to each fourth doped layer 172 to form a second sensing electrode pair and a second bias electrode pair.

[0050] It should be noted that if the plurality of first electrodes 181 constitute a first sensing electrode pair, then the plurality of second electrodes constitute a first bias electrode pair; if the plurality of first electrodes 181 constitute a first bias electrode pair, then the plurality of second electrodes constitute a first sensing electrode pair; if the plurality of third electrodes 182 constitute a second sensing electrode pair, then the plurality of fourth electrodes 183 constitute a second bias electrode pair; if the plurality of third electrodes 182 constitute a second bias electrode pair, then the plurality of fourth electrodes 183 constitute a second sensing electrode pair.

[0051] Furthermore, the depth of the deep well layer 16 is greater than the depth of the shallow well layer 14. The shallow well layer 14, the first electrode 181 and the second electrode on the shallow well layer 14 constitute a lateral Hall device. During operation, a voltage or current is applied to the first bias electrode pair, and a magnetic field component perpendicular to the shallow well layer 14 is detected. The potential difference between the first sensing electrode pair is the Hall voltage. The deep well layer 16, the third electrode 182 and the fourth electrode 183 on the deep well layer 16 constitute a longitudinal Hall device. During operation, a voltage or current is applied to the second bias electrode pair, and the potential difference between the second sensing electrode pair is the Hall voltage.

[0052] It is understood that the material of substrate 11 can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium-silicon compound, silicon-on-insulator (SOI), or low-temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art. Substrate 11 can provide a supporting foundation for the structural layers on substrate 11. Isolation structure 13 can be a deep trench isolation structure or a shallow trench isolation structure. The first doped layer 151, the second doped layer 152, the third doped layer 171, and the fourth doped layer 172 can be heavily doped layers.

[0053] The three-dimensional Hall device 10 provided in this application embodiment comprises a barrier layer 12 and an isolation structure 13 disposed within a substrate 11, with the isolation structure 13 positioned on the side of the barrier layer 12 closest to the front surface of the substrate 11. A shallow well layer 14 is disposed within the device region 11a enclosed by the isolation structure 13, and a deep well layer 16 is located on the side of the isolation structure 13 opposite to the shallow well layer 14. This allows the Hall device to achieve three-dimensional detection. Furthermore, during the fabrication of the shallow well layer 14 and the deep well layer 16, the barrier layer 12 acts as a barrier, requiring only one ion implantation to form the shallow well layer 14 and the deep well layer 16 with different implantation depths. This reduces the number of steps and lowers the fabrication difficulty and cost of the three-dimensional Hall device 10.

[0054] In one embodiment, the center of the shallow well layer 14 coincides with the center of the device region 11a. Here, the center of the shallow well layer 14 can be understood as the center of the shape of the orthographic projection of the shallow well layer 14 onto the substrate 11. The center of the device region 11a can be understood as the center of the pattern enclosed by the orthographic projection of the isolation structure 13 onto the substrate 11.

[0055] The above arrangement is beneficial for arranging the first doped layer 151 and the second doped layer 152 within the shallow well layer 14, and also beneficial for symmetrical arrangement of the first doped layer 151 and the second doped layer 152.

[0056] Furthermore, the barrier layer 12 can be disposed at the center of the three-dimensional Hall device 10. Specifically, the center of the barrier layer 12 coincides with the center of the three-dimensional Hall device 10 (such as the center of the substrate 11), the centroid of the isolation structure 13 coincides with the center of the three-dimensional Hall device 10 (such as the center of the substrate 11), and the center of the shallow well layer 14 coincides with the center of the three-dimensional Hall device 10 (such as the center of the substrate 11). It should be noted that, due to manufacturing errors, approximate coincidence can also be considered as coincidence.

[0057] In one embodiment, the orthographic projection of the shallow well layer 14 onto the substrate 11 is a first pattern, which is a centrally symmetric pattern. Here, it is equivalent to the shallow well layer 14 being a centrally symmetric pattern when viewed from above.

[0058] This helps to make the device structure more symmetrical, reduce initial misalignment, and improve the measurement accuracy of the device.

[0059] For example, from a top view, the shape of the shallow trap layer 14 can be a centrally symmetric shape such as a quadrilateral or an octagon.

[0060] In one embodiment, the orthographic projection of the first doped layer 151 and the second doped layer 152 onto the substrate 11 forms a second pattern, which is centrally symmetrical about the shallow well layer 14. That is, from a top view, all doped layers (the first doped layer 151 and the second doped layer 152) within the shallow well layer 14 are centrally symmetrical about the shallow well layer 14.

[0061] This helps to make the device structure more symmetrical, reduce initial misalignment, and improve the measurement accuracy of the device.

[0062] In one embodiment, reference Figure 4 As shown, the shallow well layer 14 includes a first sub-layer 141 and four second sub-layers 142. Two second sub-layers 142 are located on either side of the first sub-layer 141 along the first direction X, and the remaining two second sub-layers 142 are located on either side of the first sub-layer 141 along the second direction Y. Each of the two second sub-layers 142 located on either side of the first sub-layer 141 along the first direction X contains a first doped layer 151; each of the two second sub-layers 142 located on either side of the first sub-layer 141 along the second direction Y contains a second doped layer 152. The first direction X, the second direction Y, and the thickness direction Z of the substrate 11 are all perpendicular to each other. This effectively makes the shallow well layer 14 shaped like a "+". This helps to make the device structure more symmetrical, reduce initial misalignment, and improve the measurement accuracy of the device.

[0063] In one embodiment, multiple deep well layers 16 are symmetrically arranged. This facilitates a more symmetrical device structure, reduces initial misalignment, and improves the measurement accuracy of the device.

[0064] For example, the number of deep well layers 16 can be 2, 4, or 8, etc.

[0065] In one embodiment, a plurality of third doped layers 171 and a plurality of fourth doped layers 172 within the same deep well layer 16 are arranged alternately along the extension direction of the deep well layer 16. Here, the extension direction of the deep well layer 16 can be the length direction of the deep well layer 16. The orthographic projection of the plurality of third doped layers 171 and the plurality of fourth doped layers 172 onto the substrate 11 forms a third pattern, which is centrally symmetrical about the deep well layer 16. That is, from a top view, all doped layers (third doped layer 171 and fourth doped layer 172) within the same deep well layer 16 are centrally symmetrical about the deep well layer 16.

[0066] This helps to make the device structure more symmetrical, reduce initial misalignment, and improve the measurement accuracy of the device.

[0067] In one embodiment, such as Figure 1-3 As shown, the three-dimensional Hall device 10 includes four deep well layers 16. Two deep well layers 16 are located on both sides of the isolation structure 13 along the first direction X, and the remaining two deep well layers 16 are located on both sides of the isolation structure 13 along the second direction Y. Each deep well layer 16 contains three third doped layers 171 and two fourth doped layers 172 arranged alternately in sequence. The first direction X, the second direction Y, and the thickness direction Z of the substrate 11 are perpendicular to each other.

[0068] Furthermore, the four deep well layers 16 are symmetrical about the center of the shallow well layer 14 (or the center of the device region 11a). All doped layers (the third doped layer 171 and the fourth doped layer 172) within the same deep well layer 16 are symmetrical about the center of the deep well layer 16.

[0069] This minimizes initial misalignment and improves the measurement accuracy of the device.

[0070] In one embodiment, reference Figure 5 As shown, the three-dimensional Hall device 10 includes eight deep well layers 16, which are arranged at intervals around the center of the shallow well layer 14 (or the center of the device region 11a), and are symmetrical about the center of the shallow well layer 14 (or the center of the device region 11a). It is understood that the number of deep well layers 16 can also be 16, 32, etc., and the embodiments of this application do not particularly limit the number and arrangement of the deep well layers 16.

[0071] In one embodiment, reference Figure 6As shown, each deep well layer 16 contains two third doped layers 171 and two fourth doped layers 172 arranged alternately in sequence. This application embodiment does not particularly limit the number or arrangement of the deep well layers 16. It is understood that the number of third doped layers 171 and fourth doped layers 172 within the deep well layer 16 can be other numbers, and this application embodiment does not particularly limit the number of third doped layers 171 and fourth doped layers 172.

[0072] In one embodiment, the barrier layer 12 is made of at least one of silicon oxide, silicon oxynitride, or silicon nitride. This improves the barrier performance of the barrier layer 12 while reducing manufacturing costs.

[0073] In one embodiment, the substrate 11 is a P-type substrate 11, and the shallow well layer 14, deep well layer 16, first doped layer 151, second doped layer 152, third doped layer 171, and fourth doped layer 172 are all N-type doped. It is understood that the doping types described above can also be reversed.

[0074] Secondly, embodiments of this application provide a Hall sensor, including the three-dimensional Hall device 10 in any embodiment of the first aspect. Further, the Hall sensor may also include a signal conditioning circuit electrically connected to the three-dimensional Hall device 10.

[0075] Thirdly, referring to Figure 7 and combined Figures 8-16 As shown in the figure, this application provides a method for fabricating a three-dimensional Hall sensor, which specifically includes the following steps:

[0076] S100: A substrate 11 is provided. Exemplarily, a P-type substrate 11 can be formed by ion implantation. A structural diagram of the substrate 11 is shown below. Figure 8 As shown.

[0077] S200: A barrier layer 12 and an isolation structure 13 are formed within the substrate 11. (Refer to...) Figure 11 As shown, the isolation structure 13 is located on the side of the barrier layer 12 near the front of the substrate 11, and encloses the device region 11a.

[0078] S300: A shallow well layer 14 is formed in device region 11a, and multiple deep well layers 16 are formed in substrate 11. (Refer to...) Figure 12 As shown, the deep well layer 16 is located on the side of the isolation structure 13 opposite to the shallow well layer 14. Exemplarily, photoresist can be applied to the front side of the substrate 11 to define a doping window, and the shallow well layer 14 can be formed above the barrier layer 12 by a single high-energy N-type ion implantation, while the deep well layer 16 is formed around the isolation structure 13.

[0079] S400: A plurality of first doped layers 151 and a plurality of second doped layers 152 are formed at intervals within the shallow well layer 14, and a plurality of third doped layers 171 and a plurality of fourth doped layers 172 are formed at intervals within the deep well layer 16. The structure after the formation of the first doped layer 151, the second doped layer 152, the third doped layer 171, and the fourth doped layer 172 is as follows. Figure 13 As shown. For example, photoresist can be applied to the front side of substrate 11 to define a doping window, and a first doped layer 151, a second doped layer 152, a third doped layer 171, and a fourth doped layer 172 can be formed by a single high-energy N-type ion implantation.

[0080] S500: A first electrode 181, a second electrode, a third electrode 182, and a fourth electrode 183 are formed on the first doped layer 151, the second doped layer 152, the third doped layer 171, and the fourth doped layer 172, respectively, to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair, and a second bias electrode pair.

[0081] The method for fabricating a three-dimensional Hall device 10 provided in this application involves setting a barrier layer 12 and an isolation structure 13 within a substrate 11, with the isolation structure 13 positioned on the side of the barrier layer 12 closest to the front surface of the substrate 11. A shallow well layer 14 is disposed within the device region 11a enclosed by the isolation structure 13, and a deep well layer 16 is located on the side of the isolation structure 13 opposite to the shallow well layer 14. This allows the Hall device to achieve three-dimensional detection. Furthermore, during the fabrication of the shallow well layer 14 and the deep well layer 16, the barrier layer 12 acts as a barrier, requiring only one ion implantation to form the shallow well layer 14 and the deep well layer 16 with different implantation depths. This reduces the number of steps and lowers the fabrication difficulty and cost of the three-dimensional Hall device 10.

[0082] In one embodiment, S200: forming a barrier layer 12 and an isolation structure 13 within the substrate 11, specifically including the following steps:

[0083] S210: Locally implant barrier ions into the substrate 11. For example, as... Figure 9 As shown, oxygen ions can be injected.

[0084] S220: Anneal the substrate 11 to form the barrier layer 12. The structure of the barrier layer 12 after formation is as follows. Figure 10 As shown.

[0085] S230: Trenches are etched on substrate 11 to form a trench, and dielectric material is deposited within the trench to form isolation structure 13. The structure of isolation structure 13 after formation is as follows. Figure 11 As shown. Exemplarily, trenches can be formed by dry etching, and silicon dioxide can be deposited using a chemical vapor deposition process to form the isolation structure 13.

[0086] In one embodiment, S500: A first electrode 181, a second electrode, a third electrode 182, and a fourth electrode 183 are formed on the first doped layer 151, the second doped layer 152, the third doped layer 171, and the fourth doped layer 172, respectively, to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair, and a second bias electrode pair, specifically including the following steps:

[0087] S510: A dielectric material layer 20 is formed on the front side of the substrate 11. The structure of the dielectric material layer 20 after its formation is as follows. Figure 14 As shown.

[0088] S520: Contact holes 21 are etched on the dielectric material layer 20, and a dielectric layer 19 is formed. The structure after the contact holes 21 are formed is as follows. Figure 15 As shown.

[0089] S530: A metal layer 30 is formed on the dielectric layer 19. The structure after the metal layer 30 is formed is as follows. Figure 16 As shown.

[0090] S540: The metal layer 30 is patterned to form a first electrode 181, a second electrode, a third electrode 182, and a fourth electrode 183. (See attached structural reference image for the formed first electrode 181, second electrode, third electrode 182, and fourth electrode 183.) Figure 3 As shown.

[0091] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A three-dimensional Hall effect device, characterized in that, include: Substrate; A barrier layer is disposed within the substrate; An isolation structure is disposed within the substrate and located on the side of the barrier layer closest to the front side of the substrate, the isolation structure enclosing to form a device region; A shallow well layer is disposed within the device region; the shallow well layer contains a plurality of first doped layers and a plurality of second doped layers arranged at intervals; a first electrode is connected to each first doped layer, and a second electrode is connected to each second doped layer to form a first sensing electrode pair and a first bias electrode pair. Multiple deep well layers are disposed within the substrate and located on the side of the isolation structure opposite to the shallow well layers; each deep well layer has multiple third doped layers and multiple fourth doped layers arranged at intervals, each of the third doped layers is connected to a third electrode, and each of the fourth doped layers is connected to a fourth electrode to form a second sensing electrode pair and a second bias electrode pair.

2. The three-dimensional Hall device according to claim 1, characterized in that, The center of the shallow well layer coincides with the center of the device region.

3. The three-dimensional Hall effect device according to claim 1, characterized in that, The orthographic projection of the shallow well layer onto the substrate is a first pattern, which is a centrally symmetric pattern.

4. The three-dimensional Hall device according to claim 1, characterized in that, The orthographic projection of the first doped layer and the second doped layer onto the substrate forms a second pattern, which is symmetrical about the center of the shallow well layer.

5. The three-dimensional Hall effect device according to claim 1, characterized in that, The shallow well layer includes a first sub-layer and four second sub-layers, with two second sub-layers located on both sides of the first sub-layer along a first direction, and the remaining two second sub-layers located on both sides of the first sub-layer along a second direction. In the two second sub-layers located on both sides of the first sub-layer along the first direction, each second sub-layer has a first doped layer; in the two second sub-layers located on both sides of the first sub-layer along the second direction, each second sub-layer has a second doped layer. The first direction, the second direction, and the thickness direction of the substrate are perpendicular to each other.

6. The three-dimensional Hall device according to claim 1, characterized in that, The multiple deep well layers are arranged symmetrically.

7. The three-dimensional Hall device according to claim 1, characterized in that, The plurality of third doped layers and the plurality of fourth doped layers within the same deep well layer are arranged alternately along the extension direction of the deep well layer; The orthogonal projections of the plurality of third doped layers and the plurality of fourth doped layers onto the substrate form a third pattern, which is symmetrical about the center of the deep well layer.

8. The three-dimensional Hall effect device according to claim 1, characterized in that, The three-dimensional Hall device includes four deep well layers, two of which are located on both sides of the isolation structure along a first direction, and the remaining two deep well layers are located on both sides of the isolation structure along a second direction. Each deep well layer contains three third doped layers and two fourth doped layers arranged alternately in sequence; the first direction, the second direction, and the thickness direction of the substrate are perpendicular to each other.

9. The three-dimensional Hall device according to claim 1, characterized in that, The barrier layer is made of at least one of silicon oxide, silicon oxynitride, or silicon nitride.

10. A Hall sensor, characterized in that, Includes the Hall device as described in any one of claims 1-9.

11. A method for fabricating a Hall device, characterized in that, include: Provide substrate; A barrier layer and an isolation structure are formed within the substrate; The isolation structure is located on the side of the barrier layer closest to the front side of the substrate, and encloses the device area; A shallow well layer is formed in the device region, and a plurality of deep well layers are formed in the substrate; the deep well layers are located on the side of the isolation structure opposite to the shallow well layer. A plurality of first doped layers and a plurality of second doped layers are formed at intervals within the shallow well layer, and a plurality of third doped layers and a plurality of fourth doped layers are formed at intervals within the deep well layer. A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on the first doped layer, the second doped layer, the third doped layer, and the fourth doped layer, respectively, to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair, and a second bias electrode pair.

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