Method for thinning silicon carbide wafer and silicon carbide wafer

Abstract

The invention relates to the technical field of semiconductors, and provides a method for thinning a silicon carbide wafer and the silicon carbide wafer, and the method for thinning the silicon carbide wafer comprises the steps: forming a plurality of metal catalyst particles which are arranged at intervals on the back surface of the silicon carbide wafer to be thinned; and putting the silicon carbide wafer to be thinned with the metal catalyst particles into a first corrosive liquid to corrode the silicon carbide wafer to be thinned to obtain the thinned silicon carbide wafer. In the embodiment of the invention, by adopting the thinning method in which the metal catalyst particles are combined with the chemical corrosive liquid, not only can a thinner and more uniform silicon carbide wafer be obtained, but also the performance of the metal contact layer on the back surface of the wafer can be improved, meanwhile, the processing efficiency is improved, the overall cost is reduced, the wafer damage is reduced, and the yield is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for thinning a silicon carbide wafer and a silicon carbide wafer. Background Technology

[0002] Compared to traditional silicon-based wafers, silicon carbide (SiC) wafers have higher breakdown field strength, lower loss, higher thermal conductivity, and better high-temperature stability, enabling silicon carbide-based devices to operate at higher voltages, higher frequencies, and higher temperatures, significantly improving the efficiency and reliability of electronic systems.

[0003] However, despite the superior properties of silicon carbide wafers providing an ideal platform for high-end devices, several key challenges remain in device design and manufacturing. One of these is optimizing on-resistance, which directly impacts device performance and energy efficiency. On-resistance is primarily contributed by the wafer's inherent resistance, and for power devices in particular, reducing on-resistance is crucial for improving device efficiency.

[0004] Therefore, thinning silicon carbide wafers has become an important technical means. Reducing wafer thickness can effectively reduce on-resistance, thereby improving the overall performance of devices. Traditional thinning methods mostly employ physical grinding, such as diamond grinding wheels. While this can reduce wafer thickness and on-resistance to some extent, it has significant drawbacks. Physical grinding often leads to poor edge thinning, limited production capacity, increased scratch depth, and a higher risk of wafer breakage. Furthermore, physical grinding causes significant wear on the grinding wheel, increasing thinning costs, and the thinning thickness is typically limited to 70μm, which is particularly insufficient for high-power applications seeking ultimate performance.

[0005] Given the above background, exploring novel and efficient thinning technologies to overcome the limitations of existing thinning methods is of great significance for promoting the commercialization and performance optimization of silicon carbide devices. By finding thinning methods that can achieve thinner, more uniform, scratch-free, low-cost, and mass-production-suitable thinning, the potential of silicon carbide materials can be further explored, promoting their application in a wider range of fields.

[0006] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0007] The main objective of this application is to provide a method for thinning silicon carbide wafers and a silicon carbide wafer, so as to solve the problem that the thinning technology in the prior art cannot meet the requirements of silicon carbide devices for low on-resistance.

[0008] To achieve the above objectives, according to one aspect of this application, a method for thinning a silicon carbide wafer is provided, comprising: forming a plurality of spaced metal catalyst particles on the back side of the silicon carbide wafer to be thinned; placing the silicon carbide wafer to be thinned, having the metal catalyst particles, into a first etching solution to etch the silicon carbide wafer to be thinned, thereby obtaining a thinned silicon carbide wafer.

[0009] In some embodiments of this application, the first corrosive liquid includes hydrogen peroxide solution and hydrofluoric acid solution.

[0010] In some embodiments of this application, the volume ratio of the hydrogen peroxide solution to the hydrofluoric acid solution in the first corrosive liquid is 0.8:2.5~1.2:3; the concentration of the hydrogen peroxide solution is 25%~30%, and the concentration of the hydrofluoric acid solution is 40%~60%.

[0011] In some embodiments of this application, the material of the metal catalyst particles includes at least one of gold, silver, and platinum.

[0012] In some embodiments of this application, the particle size of the metal catalyst particles is 20 nm to 250 nm.

[0013] In some embodiments of this application, the step of forming the metal catalyst particles on the back side of the silicon carbide wafer to be thinned includes: growing a metal catalyst layer on the back side of the silicon carbide wafer to be thinned using an electron beam process or a thermal evaporation process; and annealing the silicon carbide wafer having the metal catalyst layer to form a plurality of the metal catalyst particles.

[0014] In some embodiments of this application, the thickness of the metal catalyst layer is 5 nm to 30 nm.

[0015] In some embodiments of this application, after etching the silicon carbide wafer to be thinned to obtain the thinned silicon carbide wafer, the method further includes: removing the metal catalyst particles using a second etching solution, wherein the composition of the second etching solution is different from that of the first etching solution.

[0016] According to another aspect of this application, a silicon carbide wafer is provided, which is formed by thinning the silicon carbide wafer by the method described in any of the above embodiments.

[0017] In some embodiments of this application, the thickness of the silicon carbide wafer is less than or equal to 10 μm.

[0018] The beneficial effects of this application are as follows:

[0019] This application relates to the field of semiconductor technology, and provides a method for thinning a silicon carbide wafer and a silicon carbide wafer. The method for thinning a silicon carbide wafer includes: forming a plurality of spaced metal catalyst particles on the back side of the silicon carbide wafer to be thinned; placing the silicon carbide wafer with the metal catalyst particles into a first etching solution to etch the silicon carbide wafer to be thinned, thereby obtaining a thinned silicon carbide wafer. In the embodiments of this application, by using the above-mentioned thinning method of metal catalyst particles combined with chemical etching solution, not only can a thinner and more uniform silicon carbide wafer be obtained, but the performance of the metal contact layer on the back side of the wafer can also be improved. At the same time, the processing efficiency is improved, the overall cost is reduced, wafer damage is reduced, and the yield is increased. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding figures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings are not proportionally limited. To more clearly illustrate the technical solutions in the embodiments of this application or in conventional technology, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0021] Figure 1 A method for thinning silicon carbide wafers according to embodiments of this application;

[0022] Figure 2 This is a schematic diagram of the structure of a silicon carbide wafer to be processed according to an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of a silicon carbide wafer thinning process according to an embodiment of this application;

[0024] Figure 4 This is a schematic diagram of a silicon carbide wafer thinning process according to an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of another silicon carbide wafer thinning process provided according to an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the structure of a thinned silicon carbide wafer according to an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the structure of a silicon carbide wafer after forming a back conductive layer according to an embodiment of this application.

[0028] The above figures include the following reference numerals:

[0029] 1. Silicon carbide substrate; 2. Epitaxial layer; 3. Semiconductor device layer; 4. Protective layer; 5. Metal catalyst particles; 6. Thinned substrate; 7. Back conductive layer. Detailed Implementation

[0030] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] When a component "includes" another component, unless otherwise stated, other components are not excluded, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is said to be "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or there can be another component present in between. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located in between.

[0033] The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this text generally indicates that the preceding and following related objects have an "or" relationship.

[0034] The terms "first," "second," etc., are used to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. It should be understood that such terms can be used interchangeably where appropriate to describe embodiments of this application.

[0035] When an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element. Furthermore, in the specification and claims, terms such as "mounted," "connected," "joined," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0036] The orientations or positional relationships indicated by terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "up," "down," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. Furthermore, in the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description.

[0037] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0039] Metal catalysts: Metal catalysts are metals or metal compounds that can significantly increase the reaction rate in a chemical reaction without changing their chemical properties before and after the reaction. Catalysts accelerate the reaction process by providing an alternative reaction pathway and lowering the activation energy of the reaction. In metal catalysis, the characteristics of the metal surface (such as electronic structure and chemisorption capacity) enable it to effectively bind with reactant molecules, promoting the interaction between reactant molecules and thus accelerating the reaction.

[0040] Electron beam deposition: Electron beam deposition is a high-precision physical vapor deposition (PVD) technique primarily used to grow various metal, alloy, or compound thin films on substrate surfaces. This process involves bombarding a metal target with a focused, high-speed electron beam, causing it to evaporate and condense onto the substrate surface in a vacuum environment, forming the desired thin film layer.

[0041] Thermal evaporation process: Thermal evaporation process is a thin film deposition technology. Its working principle is to heat the evaporation material (target) to the evaporation point by a heating source (usually a resistance wire or electron beam), so that it turns into a gaseous state and then condenses on the substrate to form a thin film.

[0042] As described in the background section, existing technologies typically employ physical grinding to thin wafers and reduce their on-resistance. However, physical grinding often leads to problems such as poor edge thinning, limited production capacity, increased scratch depth, and increased risk of wafer breakage. To address the issue that traditional thinning methods cannot meet the low on-resistance requirements of silicon carbide devices, embodiments of this application provide a method for thinning silicon carbide wafers to obtain thinner and more uniform silicon carbide wafers, while improving processing efficiency, reducing overall costs, and minimizing damage to the wafer during the thinning process.

[0043] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0044] Figure 1 The method for thinning silicon carbide wafers according to embodiments of this application, such as Figure 1 As shown, the method for thinning silicon carbide wafers includes the following steps S1 and S2:

[0045] Step S1: Form multiple spaced metal catalyst particles on the back side of the silicon carbide wafer to be thinned;

[0046] Step S2: Place the silicon carbide wafer to be thinned, which contains metal catalyst particles, into the first etching solution to etch the silicon carbide wafer to be thinned, and obtain the thinned silicon carbide wafer.

[0047] In the aforementioned silicon carbide wafer thinning method, chemical etching is used instead of physical grinding to thin the silicon carbide wafer. The uniformity of the chemical reaction is far superior to that of physical methods, ensuring a uniform thinning process across the entire back side of the wafer and avoiding the problems of localized over-thinning or uneven thinning commonly found in physical grinding. Furthermore, the chemical etching method does not require complex equipment such as diamond grinding wheels, reducing the high costs associated with grinding wheel wear. In addition, chemical etching can simultaneously thin multiple wafers in a single process, significantly improving production efficiency and reducing the processing cost per wafer.

[0048] By forming metal catalyst particles on the back side of the silicon carbide wafer to be thinned, and having gaps between the particled metal catalysts, when the silicon carbide wafer to be thinned is placed in the first etching solution, the first etching solution can enter the gaps between the metal catalyst particles and come into contact with the silicon carbide wafer to be thinned. This utilizes the metal catalyst to lower the activation energy of the etching reaction, allowing more silicon carbide molecules to participate in the reaction, promoting the chemical reaction rate between silicon carbide and the first etching solution in the step, and making the etching process more efficient. The combination of the chemical etching process and the metal catalyst allows the thinning of the silicon carbide wafer to be completed in a shorter time.

[0049] In the embodiments of this application, by using the above-mentioned thinning method of combining metal catalyst particles with chemical etching solution, not only can thinner and more uniform silicon carbide wafers be obtained, but the performance of the metal contact layer on the back of the wafer can also be improved. At the same time, the processing efficiency is improved, the overall cost is reduced, wafer damage is reduced, and the yield is increased.

[0050] The following provides a detailed description of the possible implementation methods for steps S1 and S2 described above.

[0051] In some embodiments of this application, step S1 above, namely, the step of forming metal catalyst particles on the back side of the silicon carbide wafer to be thinned, may include the following steps S11 to S12:

[0052] Step S11: Grow a metal catalyst layer on the back side of the silicon carbide wafer to be thinned using an electron beam process or a thermal evaporation process.

[0053] Step S12: Anneal the silicon carbide wafer with the metal catalyst layer to form multiple metal catalyst particles.

[0054] In step S11 above, regardless of whether electron beam or thermal evaporation is used, the deposition of metal vapor on the back side of the wafer will undergo a transformation from a gaseous to a solid state. In a vacuum environment, metal vapor can be directly and uniformly deposited on the wafer surface to form a metal catalyst layer. This process allows for precise control of the thickness of the metal catalyst layer, thereby enabling better control over the depth and uniformity of thinning during subsequent chemical etching.

[0055] In step S12 above, the annealing process involves the metal catalyst particles undergoing minute melting and recrystallization under high temperature. During this process, the metal particles tend to form a more ordered and uniform structure, while increasing the number and quality of active sites on the catalyst. Furthermore, during annealing, under lower pressure and higher temperature, metal atoms penetrate deeper into the wafer surface, forming a more stable metal-semiconductor interface. This bonding enhances the physical adsorption of the metal catalyst layer, making it less prone to detachment during subsequent chemical etching, thus ensuring the continuity and effectiveness of the thinning process.

[0056] In summary, forming a metal catalyst layer through electron beam or thermal evaporation processes, followed by annealing, can improve the performance of metal catalyst particles from multiple angles, including enhancing their adhesion to the wafer, improving activity and uniformity, achieving precise thickness control, and supporting mass production.

[0057] Based on the above steps S11 and S12, it should be understood that in this application, a dense metal catalyst layer is first formed, and then the dense metal catalyst layer is locally polymerized by annealing to form multiple spaced metal catalyst particles, so that the first etching liquid can enter the gaps between the metal catalyst particles and contact the back side of the silicon carbide wafer to be thinned.

[0058] In some embodiments of this application, the annealing temperature in step S12 is 200~300°C. Annealing can be achieved at a relatively low temperature.

[0059] In some embodiments of this application, the first corrosive liquid includes hydrogen peroxide (H2O2) and hydrofluoric acid (HF).

[0060] The principle of the first etching solution etching the silicon carbide substrate involves the following two steps: First, due to the strong oxidizing properties of hydrogen peroxide (H₂O₂), in the presence of a metal catalyst, it can oxidize the silicon atoms on the silicon carbide surface to form silicon dioxide (SiO₂). This process can specifically occur around the metal catalyst particles, as the catalyst lowers the activation energy of the oxidation reaction and accelerates the oxidation rate. The generated silicon dioxide (SiO₂) then reacts with hydrofluoric acid (HF), an etchant that effectively dissolves silicon dioxide. Thus, under the catalysis of the metal catalyst, the silicon dioxide reacts with hydrofluoric acid to form soluble fluorosilicic acid and water, which are then gradually removed.

[0061] Through the successive occurrence of these two reaction steps, hydrogen peroxide and hydrofluoric acid, assisted by metal catalyst particles, work together on the silicon carbide surface to achieve chemical thinning of the silicon carbide substrate. The aforementioned corrosion process is a cyclical process of oxidation and dissolution. The silicon dioxide generated by the oxidation reaction is then dissolved by hydrofluoric acid. This continuous dynamic equilibrium process is carried out efficiently under the catalysis of the metal catalyst, avoiding many problems in traditional physical thinning methods. It can improve the uniformity of thinning, increase thinning efficiency, and reduce costs. Furthermore, the oxides generated first are easily removed by acid, making the reaction process easier to control.

[0062] It should be understood that the aforementioned first corrosive liquid includes hydrogen peroxide solution and hydrofluoric acid solution, meaning that the first corrosive liquid can be formed by mixing hydrogen peroxide solution and hydrofluoric acid solution. The aforementioned hydrogen peroxide solution can be formed by dissolving hydrogen peroxide solute in deionized water, and the hydrofluoric acid solution can be formed by dissolving hydrofluoric acid in deionized water, but is not limited thereto.

[0063] In some embodiments of this application, the volume ratio of hydrogen peroxide solution to hydrofluoric acid solution in the first etching solution is 0.8:2.5 to 1.2:3; the concentration of hydrogen peroxide solution is 25% to 30%, and the concentration of hydrofluoric acid solution is 40% to 60%. Exemplarily, the volume ratio of hydrogen peroxide solution to hydrofluoric acid solution in the first etching solution can be 0.8:2.5, 1:2.5, 1.2:3, or any other value within the above range. Further, deionized water is used to mix the hydrogen peroxide solution and hydrofluoric acid solution in the first etching solution, and the volume ratio of hydrogen peroxide solution, hydrofluoric acid solution, and deionized water is 0.8:2.5:7 to 1.2:3:8, for example, 1:2.5:7. The concentration of the hydrogen peroxide solution is, for example, 25%, 26%, 27%, 28%, 29%, 30%, or any other value within the above concentration range; the concentration of the hydrofluoric acid solution is, for example, 40%, 45%, 49%, 50%, 55%, 60%, or any other value within the above concentration range; and the concentrations of both can be any combination of the above concentration values. During the etching process of the first etching solution, increasing the concentration of hydrogen peroxide accelerates the oxidation reaction rate, while increasing the concentration of hydrofluoric acid accelerates the dissolution rate of silicon dioxide. Excessive hydrogen peroxide leads to an excessively thick surface oxide layer, increasing the difficulty of subsequent cleaning, while excessively high hydrofluoric acid concentration may cause unnecessary erosion of the silicon carbide wafer. An appropriate ratio of hydrogen peroxide to hydrofluoric acid can control the rate of the entire etching process, ensuring that the thinning process is both efficient and controllable, helping to maintain the dynamic balance of the reaction, avoiding localized over-oxidation or corrosion, ensuring the uniformity of thinning on the back side of the wafer, and reducing the generation of surface defects.

[0064] By setting the mass ratio of hydrogen peroxide and hydrofluoric acid in the first etching solution within the above-mentioned range, the above-mentioned oxidation and corrosion balance can be maintained, the generation of side reactions during the corrosion process can be reduced, and neither excessive oxidation leading to surface roughness nor insufficient corrosion affecting the thinning efficiency can be avoided, thereby balancing the uniformity of silicon carbide wafer thinning and the corrosion efficiency.

[0065] In some embodiments of this application, the material of the metal catalyst particles includes at least one of gold, silver, and platinum.

[0066] The aforementioned metal catalysts, gold, silver, and platinum, are all precious metals with excellent catalytic performance. They significantly reduce the activation energy of chemical corrosion reactions, accelerating the oxidation of silicon carbide and the subsequent dissolution of silica. The high catalytic activity of these metals means that efficient corrosion thinning can be achieved under milder conditions (such as lower temperatures and shorter times), thereby saving energy and shortening the production cycle. Furthermore, these metal catalysts exhibit high stability in chemical corrosion environments, resisting the erosion of corrosive solutions and maintaining their integrity and catalytic function. This stability ensures the continuous action of the metal catalyst throughout the thinning process, preventing catalyst failure due to corrosion. In addition, the metal catalyst particles need to withstand high temperatures during subsequent annealing. The high melting points of gold, silver, and platinum enable them to remain stable at high temperatures, ensuring that catalyst performance is unaffected by temperature, thus optimizing the microstructure and performance of the wafer.

[0067] In practical applications, the aforementioned metal catalyst particles may include only one of the gold, silver, and platinum materials, or they may include an alloy formed from two or more of these materials, to meet different needs.

[0068] In some embodiments of this application, the thickness of the metal catalyst layer is 5-30 nm, and can be, for example, 5 nm, 7 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm or any other value within the above range.

[0069] Thicker metal layers can provide more catalytic active sites, but this also means higher material costs and may lead to wafer deformation or cracking. This application sets the thickness of the metal catalyst layer within the aforementioned range, ensuring sufficient catalytic activity to accelerate the etching and thinning process and achieve a uniform thinning effect, while avoiding the increased costs caused by excessive use of precious metals. It also helps reduce the stress effect on the wafer, enhancing the wafer's structural stability and lowering the risk of wafer breakage during etching. Furthermore, the thickness of the metal catalyst layer within the aforementioned range is still relatively low. A lower thickness helps maintain the uniformity of the catalyst layer, thereby achieving a more uniform thinning effect during chemical etching, avoiding localized excessive thinning or thickening, and making the subsequent removal of the metal catalyst layer easier, reducing processing time and costs, while also minimizing damage to the wafer itself.

[0070] In some embodiments of this application, the particle size of the metal catalyst particles is 20nm to 250nm, and exemplary values ​​are 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, or any other value within the above range.

[0071] It should be understood that the aforementioned metal catalyst particles can be formed by the local aggregation of a whole layer of metal catalyst after annealing. Therefore, the particle size of each metal catalyst particle may be the same, different, or partially the same. That is, multiple metal catalyst particles with different particle sizes may be disposed on the silicon carbide wafer.

[0072] Smaller particle sizes provide more active sites, accelerating the reaction between the etchant and the substrate material, improving thinning efficiency, and helping to ensure uniform dispersion on the silicon carbide wafer to be thinned. Larger particles, on the other hand, tend to aggregate, forming an uneven distribution, affecting the reaction rate of the etchant and the uniformity of thinning. In this application, the particle size of the metal catalyst particles is set within the aforementioned range, which helps to balance the etching rate and the uniformity of thinning.

[0073] For ease of understanding, Figure 2 This is a schematic diagram of the structure of a silicon carbide wafer to be processed according to an embodiment of this application, as shown below. Figure 2As shown, the silicon carbide wafer to be processed may include: a silicon carbide substrate 1, a silicon carbide epitaxial layer 2, and a semiconductor device layer 3. The silicon carbide epitaxial layer 2 is disposed on the silicon carbide substrate 1, and the semiconductor device layer 3 is disposed on the silicon carbide epitaxial layer 2. The surface of the silicon carbide substrate 1 used to dispose of the silicon carbide epitaxial layer 2 and the semiconductor device layer 3 is the front side of the silicon carbide substrate 1, and the surface of the silicon carbide substrate 1 opposite to the front side is the back side of the silicon carbide substrate 1, which is also the back side of the silicon carbide wafer to be thinned.

[0074] Since semiconductor devices are disposed on the front side of the silicon carbide wafer to be thinned, a protective layer can be formed on the front side of the wafer before step S1, i.e., before forming metal catalyst particles on the back side of the wafer. This protective layer isolates the etching solution from the semiconductor devices on the front side of the wafer, preventing the etching solution from penetrating and damaging the semiconductor devices during the thinning process. The material of the protective layer needs to have good chemical and thermal stability to prevent the chemicals in the etching solution from reacting with the various material layers in the front semiconductor devices, such as metal layers, insulating materials, and semiconductor materials, and to prevent performance degradation or structural damage to the front semiconductor devices at high temperatures. For example, the protective layer can be a UV film or sealing wax, but is not limited to these.

[0075] In some embodiments of this application, after etching the silicon carbide wafer to be thinned to obtain the thinned silicon carbide wafer, a second etching solution can be used to remove the metal catalyst particles, so that a flat surface can be formed on the back side of the thinned silicon carbide wafer for setting other structures, such as a back electrode. The composition of the second etching solution differs from that of the first etching solution. For example, the second etching solution can be an aqueous solution of iodine and potassium iodide, which has strong oxidizing properties and easily removes precious metals such as gold, silver, and platinum from the metal catalyst particles.

[0076] For ease of understanding, the following is a specific embodiment of the silicon carbide wafer thinning process provided according to the present application:

[0077] Step S01: Form a silicon carbide epitaxial layer 2 and a semiconductor device layer 3 on a silicon carbide substrate 1. After completing step S01, a structure such as... Figure 2 The silicon carbide wafer to be thinned is shown. Specifically, an epitaxial layer 2 can be grown on the silicon carbide substrate 1 using a chemical vapor deposition (CVD) process, and then a semiconductor device, such as a MOSFET or SBD, can be formed on the epitaxial layer 2.

[0078] Step S02: Form a protective layer 4 on the front side of the silicon carbide wafer to be thinned. For example, Figure 3 This is a schematic diagram of a silicon carbide wafer thinning process according to an embodiment of this application. After completing step S02, a structure as shown can be formed. Figure 3 The structure shown uses a UV film or sealing wax to form a protective layer 4 on the front side of the silicon carbide wafer to be thinned, which is used to isolate the potential damage to the front structure by subsequent chemical etching solutions.

[0079] Step S03: Form a plurality of spaced metal catalyst particles 5 on the back side of the silicon carbide wafer to be thinned. For example, Figure 4 This is a schematic diagram of another silicon carbide wafer thinning process according to an embodiment of this application. After completing step S03, a structure as shown can be formed. Figure 4 The structure shown includes a metal catalyst particle 5 formed from at least one of gold (Au), silver (Ag), platinum (Pt), etc., via an electron beam process or a thermal evaporation process, for use in catalyzing backside chemical corrosion.

[0080] Step S04: The silicon carbide wafer to be thinned, containing metal catalyst particles 5, is placed in the first etching solution to etch the silicon carbide wafer, thereby obtaining the thinned silicon carbide wafer. For example, Figure 5 This is a schematic diagram of another silicon carbide wafer thinning process according to an embodiment of this application. In step S04, the silicon carbide wafer to be thinned, which has metal catalyst particles 5, can be flipped and placed into the first etching solution for etching. After completing step S04, a structure as shown can be formed. Figure 5 The structure shown includes a thinned silicon carbide wafer comprising a thinned substrate 6, an epitaxial layer 2, and a semiconductor device layer 3. The thinning thickness can be controlled within the range of less than 10 μm. It has a protective layer 4 on the front side and metal catalyst particles 5 on the back side.

[0081] Step S05: Sequentially remove the metal catalyst particles 5 and the protective layer 4. For example, Figure 6 This is a schematic diagram of the structure of a thinned silicon carbide wafer according to an embodiment of this application. After completing step S05, the wafer is formed as shown below. Figure 6 The structure shown shows that after the metal catalyst particles on the back side of the silicon carbide wafer are removed, the silicon carbide surface, which has been uniformly thinned, is exposed, providing a clean interface for the subsequent growth of back-side metal.

[0082] Step S06: Form a back conductive layer 7 on the back side of the silicon carbide wafer. For example, Figure 7 This is a schematic diagram of a silicon carbide wafer after forming a back conductive layer according to an embodiment of this application. After completing step S06, the wafer is formed as shown in the diagram. Figure 7 The structure shown can be used to achieve ohmic contact between the conductive layer 7 on the back side of the wafer and the silicon carbide substrate 1 by depositing metals such as titanium (Ti) and nickel (Ni) and using laser annealing process, thereby completing the back side metallization.

[0083] Based on the same concept, embodiments of this application also provide a silicon carbide wafer, which is formed by thinning a silicon carbide wafer using the method described in any of the above embodiments. By utilizing the catalytic effect of a metal catalyst layer to thin the wafer through chemical etching, an ultra-thin and uniform thinning effect is achieved on the back side of the wafer, avoiding problems such as uneven edge thinning and scratches common in traditional physical thinning methods. Using the aforementioned silicon carbide wafer as a substrate is beneficial for improving the consistency and stability of semiconductor device performance.

[0084] In some embodiments of this application, the thickness of the silicon carbide wafer after being etched by the first etching solution is less than or equal to 10 μm. The embodiments of this application achieve wafer thinning through the aforementioned chemical etching, enabling the silicon carbide wafer to reach a thickness of less than 10 μm, which is difficult to achieve using physical methods such as mechanical polishing. Ultra-thin silicon carbide wafers help reduce the on-resistance of devices and improve the efficiency and performance of power electronic devices.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for thinning a silicon carbide wafer, characterized in that, include: Multiple spaced metal catalyst particles are formed on the back side of the silicon carbide wafer to be thinned; The silicon carbide wafer to be thinned, which contains the metal catalyst particles, is placed in a first etching solution to etch the silicon carbide wafer to be thinned, thereby obtaining a thinned silicon carbide wafer.

2. The method for thinning a silicon carbide wafer according to claim 1, characterized in that, The first corrosive solution includes hydrogen peroxide solution and hydrofluoric acid solution.

3. The method for thinning a silicon carbide wafer according to claim 2, characterized in that, The volume ratio of the hydrogen peroxide solution to the hydrofluoric acid solution in the first corrosive solution is 0.8:2.5~1.2:3; the concentration of the hydrogen peroxide solution is 25%~30%, and the concentration of the hydrofluoric acid solution is 40%~60%.

4. The method for thinning a silicon carbide wafer according to claim 1, characterized in that, The material of the metal catalyst particles includes at least one of gold, silver, and platinum.

5. The method for thinning a silicon carbide wafer according to claim 1, characterized in that, The particle size of the metal catalyst particles is 20 nm to 250 nm.

6. The method for thinning a silicon carbide wafer according to claim 1, characterized in that, The step of forming the metal catalyst particles on the back side of the silicon carbide wafer to be thinned includes: A metal catalyst layer is grown on the back side of the silicon carbide wafer to be thinned using an electron beam process or a thermal evaporation process. A silicon carbide wafer having the metal catalyst layer is annealed to form a plurality of the metal catalyst particles.

7. The method for thinning a silicon carbide wafer according to claim 6, characterized in that, The thickness of the metal catalyst layer is 5 nm to 30 nm.

8. The method for thinning a silicon carbide wafer according to claim 1, characterized in that, After etching the silicon carbide wafer to be thinned to obtain the thinned silicon carbide wafer, the method further includes: The metal catalyst particles are removed using a second corrosive liquid, the composition of which differs from that of the first corrosive liquid.

9. A silicon carbide wafer, characterized in that, The silicon carbide wafer is formed by thinning a silicon carbide wafer using any one of claims 1 to 8.

10. The silicon carbide wafer according to claim 9, characterized in that, The thickness of the silicon carbide wafer is less than or equal to 10 μm.

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