Package substrate and preparation method thereof, and semiconductor package

Abstract

The invention discloses a package substrate and a preparation method thereof, and a semiconductor package, and belongs to the technical field of semiconductors. The packaging substrate comprises a circuit base layer, a plurality of circuit adding layers and a solder mask which are sequentially arranged in a stacked mode, each circuit adding layer comprises an insulating medium, a patterned metal layer and a hole interconnection, the patterned metal layer is arranged on the side, away from the circuit base layer, of the insulating medium, and the hole interconnection at least partially penetrates through the insulating medium; the circuit base layer is electrically connected with the patterned metal layer of the adjacent circuit adding layer through corresponding hole interconnection, and the patterned metal layers of any two adjacent circuit adding layers are electrically connected through corresponding hole interconnection; at least part of the line adding layers are embedded line adding layers, and the patterned metal layers of the embedded line adding layers are embedded in the surfaces of one sides of the corresponding insulating media. By combining the ETS process-based embedded circuit added layer into the PCB added layer, a highly fine and high-density circuit can be obtained in the PCB added layer at low cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to packaging substrates and their preparation methods, and semiconductor packages. Background Technology

[0002] A packaging substrate, also known as an IC carrier board, connects bare chips (DIEs) to printed circuit boards (PCBs) and transmits signals within them, and is widely used in semiconductor packaging. With the miniaturization and high-density development of semiconductor packages, it is necessary to reduce the linewidth and solder ball spacing of the packaging substrate to improve its packaging density.

[0003] In PCB layer addition, PCB circuit fabrication currently typically employs tenting technology, which is relatively low-cost, but produces circuits larger than or equal to 50μm, making it unsuitable for fine-grained circuitry. While semi-additive processes (SAP) and modified semi-additive processes (MSAP) can be used for fine-grained circuitry, they place high demands on processing equipment and are costly. Therefore, achieving fine-grained circuitry at a low cost, based on available PCB resources, is essential.

[0004] Public content

[0005] This disclosure provides a packaging substrate and its preparation method, as well as a semiconductor package, which can solve the technical problems existing in related technologies. The technical solutions are as follows.

[0006] On one hand, a packaging substrate is provided, the packaging substrate comprising: a circuit base layer, a plurality of circuit add-on layers and a solder mask layer arranged in sequence, each of the circuit add-on layers comprising: an insulating dielectric, a patterned metal layer and a via interconnect, the patterned metal layer being disposed on the side of the insulating dielectric away from the circuit base layer, and the via interconnect at least partially penetrating the insulating dielectric; the circuit base layer and the patterned metal layer of the adjacent circuit add-on layer, as well as any two adjacent patterned metal layers of the circuit add-on layer, are electrically connected through corresponding via interconnects; wherein at least some of the plurality of circuit add-on layers are embedded circuit add-on layers, and the patterned metal layer of the embedded circuit add-on layer is embedded in one side surface of its respective insulating dielectric.

[0007] The packaging substrate provided in this disclosure achieves PCB build-up (BU) by setting multiple circuit build-up layers on the circuit base layer. At least a portion of the multi-layer circuit build-up layers are embedded circuit build-up layers based on ETS technology. According to the principle of ETS technology, the patterned metal layer of the embedded circuit build-up layer can be pre-processed on the carrier board using ETS technology to represent high-precision fine circuits. Subsequently, by laminating and embedding the patterned metal layer of the embedded circuit build-up layer into the insulating medium, removing the carrier board, and etching the copper seed layer, the embedded circuit build-up layer can be bonded to the circuit base layer or other circuit build-up layers through the insulating medium. Furthermore, by drilling (e.g., laser drilling) and metallizing the insulating medium of the embedded circuit build-up layer, interconnecting holes can be formed in the insulating medium of the embedded circuit build-up layer to achieve interlayer connection between the embedded circuit build-up layer and its adjacent circuit base layer or other circuit build-up layers. As can be seen, the packaging substrate provided in this disclosure, by combining the embedded circuit addition layer based on ETS process into the PCB addition layer, can obtain highly fine and high-density circuits in the PCB addition layer. The ETS process is simple to operate and has low cost, enabling this disclosure embodiment to realize the processing of fine circuits at low cost based on PCB resources, overcoming the technical bottleneck and high cost problem of PCB in processing fine circuits.

[0008] In some possible implementations, some of the multiple line add-ins are exposed line add-ins, wherein the patterned metal layers of the exposed line add-ins are protruding and arranged on one side surface of their respective insulating media; wherein the line width and line spacing of the patterned metal layers of the exposed line add-ins are greater than the line width and line spacing of the patterned metal layers of the embedded line add-ins.

[0009] In some possible implementations, the patterned metal layer includes: traces and pads electrically connected to the traces, the pads also being electrically connected to the via interconnects; the pads of the buried circuit layer include at least one of via-less pads and via pads.

[0010] In some possible implementations, the pads of the embedded circuit add-on layer are via pads. Accordingly, the via interconnects of the embedded circuit add-on layer include a first type of via interconnect, which includes: a via portion and a stepped pad connected to the via portion; the via portion penetrates the insulating medium and the pad of the embedded circuit add-on layer, and the stepped pad overlaps to the surface of the pad of the embedded circuit add-on layer.

[0011] In some possible implementations, the thickness of the stepped pad is greater than the thickness of the overlapping pad; wherein the pad thickness is the dimension of the pad along the direction perpendicular to the insulating medium.

[0012] In some possible implementations, the pads of the embedded circuit add-in layer are hole-free pads. Correspondingly, the via interconnects of the embedded circuit add-in layer include a second type of via interconnect. The second type of via interconnect penetrates the insulating medium of the current embedded circuit add-in layer, and the two ends of the second type of via interconnect are respectively connected to the pads of the current embedded circuit add-in layer and the pads of another circuit add-in layer adjacent to the current embedded circuit add-in layer. The second type of via interconnect is formed by curing conductive paste.

[0013] In some possible implementations, an exposed circuit overlay is stacked on the embedded circuit overlay in a direction away from the circuit substrate. The via interconnects of the embedded circuit overlay and the exposed circuit overlay are integrally formed and connected to form a third type of via interconnect. The pads of the embedded circuit overlay are via pads, and the pads of the exposed circuit overlay are non-via pads. The third type of via interconnect sequentially penetrates the insulating medium and pads of the embedded circuit overlay and the insulating medium of the exposed circuit overlay. The sidewalls of the third type of via interconnect are connected to the pads of the embedded circuit overlay, and one end of the third type of via interconnect is connected to the pads of the exposed circuit overlay.

[0014] On the other hand, a method for preparing a packaging substrate is provided, wherein the packaging substrate is as described in any of the above descriptions, and the method for preparing the packaging substrate includes:

[0015] A circuit base layer is provided, and multiple circuit add-in layers and solder mask layers are sequentially prepared on the circuit base layer to obtain the packaging substrate;

[0016] Wherein, at least a portion of the multiple line addition layers are embedded line addition layers, and the method for preparing the embedded line addition layer includes:

[0017] By using the embedded circuit fabrication process, a patterned metal layer is prepared on a carrier board to obtain an embedded circuit addition intermediate.

[0018] Under the guidance of the alignment device, the embedded line addition intermediate is aligned with the line base layer or other prepared line addition layers at the interlayer interconnection position. The embedded line addition intermediate is pressed onto the line base layer or other prepared line addition layers through a prepreg, and the prepreg forms an insulating medium.

[0019] Remove the carrier board, and before or after the lamination operation, prepare the hole interconnects of the embedded circuit layer at the interlayer interconnection positions of the embedded circuit layer intermediate to obtain the embedded circuit layer.

[0020] The packaging substrate fabrication method provided in this disclosure performs Any Layer Embedded Pattern (AEP) design in the PCB add-on layer, enabling high-precision and high-density embedded circuitry in any layer. This results in superior and easier-to-control linewidth / spacing precision. Furthermore, this packaging substrate fabrication method utilizes the relatively simple ETS process to pre-process high-density embedded circuitry layers. With high-precision alignment assistance, interlayer bonding is achieved using a prepreg. Subsequently, interlayer interconnections are performed on the newly added circuit add-on layer, with vias formed between any two adjacent circuit add-on layers. This method is relatively simple to operate, has low cost, and avoids the need for simultaneous drilling of multiple circuit add-on layers using large-diameter mechanical drilling, ensuring the realization of high-density circuitry.

[0021] In some possible implementations, the pads of the embedded circuit addition layer are via pads, and the via interconnects of the embedded circuit addition layer include a first type of via interconnects; the preparation of the first type of via interconnects occurs after the lamination operation, and the method for preparing the first type of via interconnects includes: drilling holes at the interlayer interconnection locations of the insulating medium of the embedded circuit addition layer, and forming the first type of via interconnects at the drilling locations by an electroplating process.

[0022] In some possible implementations, the pads of the embedded circuit add-in are via-less pads, and the via interconnects of the embedded circuit add-in include a second type of via interconnect; the preparation of the second type of via interconnect occurs before the lamination operation, and the method for preparing the second type of via interconnect includes: pre-pressing the prepreg onto the circuit substrate or other prepared circuit add-in, the prepreg forming the insulating medium; drilling holes at the interlayer interconnect locations of the insulating medium of the embedded circuit add-in under the guidance of an alignment device, filling the drilled locations with conductive paste, and then performing the lamination operation, thereby forming the second type of via interconnect from the conductive paste.

[0023] In some possible implementations, an exposed circuit overlay is stacked on the embedded circuit overlay in a direction away from the base layer of the circuit. The via interconnects of the embedded circuit overlay and the exposed circuit overlay cooperate to form a third type of via interconnect. The pads of the embedded circuit overlay are via pads, and the pads of the exposed circuit overlay are non-via pads. The third type of via interconnect is prepared after the lamination operation, and the method for preparing the third type of via interconnect includes: after forming the insulating medium and patterned metal layer of the embedded circuit overlay through the lamination operation, pre-pressing another half-cured sheet onto the insulating medium of the embedded circuit overlay, the other half-cured sheet forming the insulating medium of the exposed circuit overlay; simultaneously drilling holes at the interlayer interconnection positions of the insulating medium of the exposed circuit overlay and the insulating medium of the embedded circuit overlay, and forming the third type of via interconnect at the drilling positions through an electroplating process.

[0024] In another aspect, a semiconductor package is provided, the semiconductor package comprising: a package substrate and electronic components, the package substrate being prepared as described above or by any of the above-described preparation methods; the electronic components being connected to the outermost of a plurality of line augmentation layers of the package substrate. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a first exemplary packaging substrate provided in an embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of an exemplary printed circuit substrate provided in an embodiment of this disclosure;

[0027] Figure 3 The first exemplary fabrication process of the second exemplary packaging substrate provided in this disclosure embodiment;

[0028] Figure 4 The second exemplary packaging substrate fabrication process provided in this disclosure embodiment;

[0029] Figure 5 The third step in the fabrication process of the second exemplary packaging substrate provided in this disclosure embodiment;

[0030] Figure 6 The fourth step in the fabrication process of the second exemplary packaging substrate provided in this disclosure embodiment;

[0031] Figure 7 This is a schematic diagram of the fabrication process of the second exemplary packaging substrate and a structural diagram of the second exemplary packaging substrate provided in the embodiments of this disclosure;

[0032] Figure 8This is a schematic diagram of the structure of a third exemplary packaging substrate provided in an embodiment of the present disclosure;

[0033] Figure 9 This is a schematic diagram of the structure of the fourth exemplary packaging substrate provided in the embodiments of this disclosure;

[0034] Figure 10 This is a schematic diagram of the structure of the fifth exemplary packaging substrate provided in the embodiments of this disclosure;

[0035] Figure 11 This is a schematic diagram of the structure of the sixth exemplary packaging substrate provided in the embodiments of this disclosure;

[0036] Figure 12 This is a schematic diagram of an exemplary semiconductor package provided in an embodiment of the present disclosure.

[0037] The reference numerals in the attached figures represent:

[0038] 001. Packaging substrate; 002. Electronic components;

[0039] 1. Base course of the railway line;

[0040] 2. Line addition layer; 201. Buried line addition layer; 202. Exposed line addition layer;

[0041] 21. Insulating medium;

[0042] 22. Patterned metal layer; 221. Trace; 222. Pad;

[0043] 23. Hole interconnection;

[0044] 231. Type 1 hole interconnect; 2311. Via portion; 2312. Step pad;

[0045] 232. Second type of hole interconnect;

[0046] 233. Third type of hole interconnect;

[0047] 3. Solder resist layer;

[0048] 4. Carrier plate;

[0049] 5. Copper seed layer.

[0050] In the above figures, the number of circuit layers included in the circuit addition layer of the package substrate is shown to be relatively small, such as two or three. This is to simplify the structure of the package substrate for easy illustration. It does not limit the number of circuit layers included in the circuit addition layer to be more. Based on the structural form shown in the figures, the number and structure of the circuit addition layer of the package substrate can be expanded. Detailed Implementation

[0051] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0052] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "length", "width", "thickness", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0053] Currently, the demand for chips is gradually increasing, with expectations for thinner and lighter chips, faster data transmission rates, and lower power consumption. This means that simply relying on advanced chip manufacturing processes to improve chip performance is no longer sufficient to meet the demand. Advanced chip manufacturing processes are difficult to break through, and Moore's Law is facing an insurmountable bottleneck. Therefore, in the post-Moore's Law era, advanced packaging has become the breakthrough direction for improving chip packaging density and I / O.

[0054] In traditional chip packaging architecture, the chip die is redistributed through a redistribution layer (RDL), and then connected to a carrier board through flip-chip, wire bonding and other connection methods to complete the packaging. The package module is fixed on the PCB board through surface mount technology (SMT), forming a 2.5D / 3D packaging structure of die (RDL) + flip chip ball grid array (Flip chip BGA, FCBGA) + PCB. It has a high pin count and package density and is widely used in various types of high-performance computing chip packaging.

[0055] As the number of pins and the package density increase, the following physical properties of the PCB board—ball pitch and line width / spacing—directly determine the trace density, number of trace layers, and processing cost of the package substrate.

[0056] Currently, PCB circuit fabrication typically employs tenting technology, which is relatively inexpensive, but produces traces larger than or equal to 50μm, making it unsuitable for fine-grained circuitry. While semi-additive processes (SAP) and modified semi-additive processes (MSAP) can be used for fine-grained circuitry, they place high demands on processing equipment and are costly. Therefore, achieving fine-grained circuitry at a low cost, while utilizing PCB resources, is essential.

[0057] To address the technical problems existing in related technologies, this disclosure provides a packaging substrate 001, with attached... Figure 1 An example of the structure of a package substrate 001 is shown in the attached figure. Figure 1 As shown, the packaging substrate 001 includes: a circuit base layer 1, a plurality of circuit add-on layers 2, and a solder mask layer 3 arranged in sequence. Each circuit add-on layer 2 includes: an insulating medium 21, a patterned metal layer 22, and an interconnect 23. The patterned metal layer 22 is disposed on the side of the insulating medium 21 away from the circuit base layer 100, and the interconnect 23 at least partially penetrates the insulating medium 21. The circuit base layer 1 and the patterned metal layer 22 of the adjacent circuit add-on layer 2, as well as any two adjacent patterned metal layers 22, are electrically connected through corresponding interconnects 23. Among the plurality of circuit add-on layers 2, at least some of the circuit add-on layers 2 are embedded circuit add-on layers 201, and the patterned metal layer 22 of the embedded circuit add-on layer 201 is embedded in one side surface of its corresponding insulating medium 21.

[0058] It should be noted that the "embedded trace layer" involved in the embodiments of this disclosure refers to the fabrication of a trace layer through an embedded trace substrate (ETS) fabrication process.

[0059] The process of fabricating embedded circuits using ETS technology is typically as follows: A copper seed layer 5 (e.g., ultra-thin copper foil) is formed on one or both sides of a carrier board 4. After forming rough copper teeth on the copper seed layer 5, a dry film (i.e., a mask) is applied over it. A patterned metal layer is obtained through processes such as pattern exposure, development, electroplating, and film removal, resulting in a high-precision, fine circuit. Then, insulating resin (a prepreg is used in this embodiment) is pre-pressed onto the prepared patterned metal layer, embedding the patterned metal layer into one side of the insulating resin.

[0060] When the embedded line addition layer 201 of this embodiment is fabricated using the ETS process, it can be combined with Figures 3-5 An illustrative example is provided, as shown in the attached document. Figure 3As shown, patterned electroplating is performed on one side of the substrate 4 with the copper seed layer 5 to obtain a high-precision embedded circuit add-in layer 201. (See attached diagram) Figure 4 As shown, under the guidance of the alignment device, the embedded wiring layer 201 supported by the carrier plate 4 is connected to the wiring base layer 1 or other wiring layer 2 via a semi-cured sheet. Figure 4 An example is shown where an exposed circuit add-in layer 202 is aligned and bonded. After lamination, a prepreg forms the insulating medium 21 of the embedded circuit add-in layer 201. A high-precision patterned metal layer 22 is embedded on one side surface of the insulating medium 21. The carrier board 4 is removed, and the copper seed layer 5 is etched away to expose the patterned metal layer 22 of the embedded circuit add-in layer 201. Then, as shown in the attached diagram... Figure 5 As shown, via interconnects 23 are fabricated in the embedded circuit layer 201 to achieve interlayer interconnection.

[0061] The embedded circuit enhancement layer 201 based on ETS technology, because its patterned metal layer 22 (e.g., copper layer) is embedded in the insulating medium 21, can avoid the circuit being laterally etched during the etching operation, thus giving it a strong advantage in fine circuit fabrication. For example, the line width / spacing of the embedded circuit enhancement layer 201 can be less than 15μm / 15μm, line width compensation is not required, or the line width compensation is <2μm, and the circuit accuracy is + / -2μm. The circuit etching process is eliminated, and the line width accuracy is defined by exposure, reducing line width and impedance fluctuations and improving impedance accuracy. For example, compared with Tenting and mSAP processes, the impedance fluctuation is improved to 8%-10%.

[0062] It should be noted that the "line substrate 1" involved in the embodiments of this disclosure can be a semi-finished product of a multilayer printed circuit board, that is, an intermediate state of a multilayer PCB board, which may include one or more line layers, for example, Figure 2 The example illustrates a single-layer circuit layer 1, which includes a fiberglass dielectric and a circuit layer protruding on the surface of the fiberglass dielectric. This circuit layer can be fabricated using conventional PCB circuit manufacturing processes, such as tenting. The circuit layer includes traces and multiple pads connected to the traces. The multiple pads of the circuit layer are used for interlayer interconnection with the circuit layer 2.

[0063] Figure 1 An example was given using a two-layer configuration for line layer 2, combined with... Figure 2 , Figure 2 The example also illustrates the placement of a first line addition layer 2 (BU01) on the base layer 1. This first line addition layer 2 (BU01) can also be fabricated using conventional PCB fabrication processes, such as tenting, making it an exposed line addition layer 202. It is evident that... Figure 1The example illustrates that the one closer to the base layer 1 in the two-layer line addition 2 is the exposed line addition 202 (i.e., the first line addition 2, BU01), and the one further away from the base layer 1 is the buried line addition 201 (i.e., the second line addition 2, BU02).

[0064] The packaging substrate 001 provided in this embodiment achieves PCB build-up (BU) by setting multiple circuit build-up layers 2 on the circuit base layer 1. At least a portion of the circuit build-up layers 2 are embedded circuit build-up layers 201 based on ETS process. According to the principle of ETS process, the patterned metal layer 22 of the embedded circuit build-up layer 201 can be pre-processed on the carrier board 4 through ETS process and exhibit high-precision fine circuits. Subsequently, by pressing and embedding the patterned metal layer 22 of the embedded circuit build-up layer 201 into the insulating medium 21, removing the carrier board 4, and etching the copper seed layer 5, the embedded circuit build-up layer 201 can be bonded to the circuit base layer 1 or other circuit build-up layers 2 through the insulating medium 21. Based on this, by drilling (e.g., laser drilling) and metallizing the insulating medium 21 of the embedded circuit addition layer 201, interconnecting holes 23 can be formed in the insulating medium 21 of the embedded circuit addition layer 201, thereby realizing the interlayer connection between the embedded circuit addition layer 201 and its adjacent circuit base layer 1 or other circuit addition layers 2. It can be seen that the packaging substrate 001 provided in this embodiment, by combining the embedded circuit addition layer 201 based on ETS technology into the PCB addition layer, can obtain highly fine and high-density circuits in the PCB addition layer. The ETS process is simple to operate and has low cost, enabling this embodiment to achieve the processing of fine circuits at low cost based on PCB resources, overcoming the technical bottlenecks and high costs of PCB processing fine circuits.

[0065] The packaging substrate involved in this embodiment has multiple circuit enhancement layers 2. These multiple circuit enhancement layers can be arranged only on one side of the circuit base layer 1 (not shown in the figure), or symmetrically arranged on opposite sides of the circuit base layer 1 (see [reference]). Figure 1 When arranged on both sides, it is more advantageous for increasing the packaging density of the packaging substrate 001.

[0066] In some examples, all line addition layers 2 can be set as buried line addition layers 201 (not shown in the figure). In other examples, some buried line addition layers 201 can be set as buried line addition layers 201, while other line addition layers 2 can be set as exposed line addition layers 202. The patterned metal layers 22 of the exposed line addition layers 202 are protruding and arranged on one side surface of their respective insulating media 21. They can be prepared using conventional PCB circuit manufacturing processes, such as tenting processes. This makes the line width and line spacing of the patterned metal layers 22 of the exposed line addition layers 202 larger than those of the patterned metal layers 22 of the buried line addition layers 201. The combination of buried line addition layers 201 and exposed line addition layers 202 forms a multilayer line addition layer 2, which makes the circuit layout more flexible and allows the package substrate 001 to have both fine and thick lines at the same time.

[0067] When the multi-layer line addition layer 2 is a combination of buried line addition layer 201 and exposed line addition layer 202, its combination form can be set to various types according to actual needs, including but not limited to the following examples: line base layer 1 - single-layer exposed line addition layer 202 - single-layer or multi-layer buried line addition layer 201; line base layer 1 - single-layer exposed line addition layer 202 - single-layer or multi-layer buried line addition layer 201 - single-layer exposed line addition layer 202; line base layer 1 - single-layer or multi-layer buried line addition layer 201 - single-layer exposed line addition layer 202; line base layer 1 - multi-layer exposed line addition layer 202 - multi-layer buried line addition layer 201 - single-layer exposed line addition layer 202; line base layer 1 - multi-layer buried line addition layer 201 - single-layer or multi-layer exposed line addition layer 202, etc.

[0068] by Figure 1 Taking the package substrate 001 as an example, it illustrates a combination of a circuit base layer 1, a single-layer exposed circuit enhancement layer 202, a single-layer embedded circuit enhancement layer 201, and a solder mask layer 3. By providing an exposed circuit enhancement layer 202 on the circuit base layer 1 as the first circuit enhancement layer 2 (BU01), a relatively thick circuit is formed in the middle of the package substrate 001. Furthermore, an embedded circuit enhancement layer 201 is provided on the first circuit enhancement layer 2 (BU01) as the second circuit enhancement layer 2 (BU02) to achieve fine circuit processing in the package substrate 001.

[0069] Regarding the line addition layer 2 (i.e., buried line addition layer 201 and exposed line addition layer 202) involved in the embodiments of this disclosure, in combination with Figure 4 It is known that each patterned metal layer 22 includes: a trace 221 and a pad 222 electrically connected to the trace 221, and the pad 222 is also electrically connected to the via interconnect 23. The trace 221 is used as a signal transmission wiring.

[0070] The pads 222 of the embedded circuit addition layer 201 include at least one of the non-hole pads and the through pads. Similarly, the through pads refer to pads with vias in a direction perpendicular to the insulating medium 21, so that the pads have a discontinuous structure, so as to facilitate laser drilling of the insulating medium 21 exposed in the discontinuous area of ​​the pads, ensuring the feasibility of drilling and fine control.

[0071] The type of pad 222 for the buried circuit add-on layer 201 can be determined based on the type of via interconnect 23. The pad 222 for the exposed circuit add-on layer 202 is typically a via-less pad.

[0072] Combination Figure 1 The package substrate 001 shown is used to illustrate the arrangement of the circuit addition layer 2 and the interlayer interconnection method therein, such as... Figure 1 As shown, the packaging substrate 001 includes: a circuit base layer 1, two circuit enhancement layers 2, and a solder mask layer 3 arranged in sequence. The first circuit enhancement layer 2 (BU01) is an exposed circuit enhancement layer 202, which includes a patterned metal layer 22 protruding from the surface of its insulating medium 21, and the patterned metal layer 22 includes multiple pads 222. The second circuit enhancement layer 2 (BU02) is an embedded circuit enhancement layer 201, which includes a patterned metal layer 22 protruding from the surface of its insulating medium 21, and the patterned metal layer 22 includes multiple pads 222. The line width and line spacing of the patterned metal layer 22 of the first circuit enhancement layer 2 (BU01) are both greater than those of the patterned metal layer 22 of the second circuit enhancement layer 2 (BU02). In other words, the patterned metal layer 22 of the second circuit enhancement layer 2 (BU02) exhibits high-precision fine circuitry.

[0073] The multiple pads 222 of the first line addition layer 2 (BU01) are one-to-one with the multiple pads 222 of the second line addition layer 2 (BU02), and each pad 222 of the first line addition layer 2 (BU01) is electrically connected to the pads 222 of the second line addition layer 2 (BU02) in a one-to-one correspondence through the hole interconnect 23 of the second line addition layer 2 (BU02).

[0074] In this embodiment of the present disclosure, the via interconnect 23 of the embedded circuit enhancement layer 201 may be located inside the via of the insulating medium 21 and connected to the pad 222. Alternatively, the via interconnect 23 of the embedded circuit enhancement layer 201 may include not only the portion located inside the via of the insulating medium 21, but also the portion located on the surface of the insulating medium 21. The following are exemplary descriptions of these embodiments:

[0075] In some examples, as shown in the appendix Figure 5 - Appendix Figure 7As shown, the pad 222 of the embedded circuit addition layer 201 is a via pad. Correspondingly, the via interconnect 23 of the embedded circuit addition layer 201 includes a first type of via interconnect 231. The first type of via interconnect 231 includes: a via portion 2311 and a stepped pad 2312 connected to the via portion 2311. The via portion 2311 penetrates the insulating medium 21 and the pad 222 of the embedded circuit addition layer 201. The stepped pad 2312 overlaps the surface of the pad 222 of the embedded circuit addition layer 201.

[0076] Further integration Figure 5 It can be seen that the second line addition layer 2 (BU02) is a buried line addition layer 201. One end of the via portion 2311 of its first type of via interconnect 231 is connected to the pad 222 of the first line addition layer 2 (BU01), and the other end of the via portion 2311 is connected to the stepped pad 2312. The stepped pad 2312 overlaps with the pad 222 of the buried line addition layer 201, thereby realizing the interlayer conduction between the first line addition layer 2 (BU01) and the second line addition layer 2 (BU02).

[0077] In the direction parallel to the insulating medium 21, the radial dimension of the stepped pad 2312 of the first type of hole interconnect 231 is usually smaller than the radial dimension of the overlapping pad 222, so as to avoid the stepped pad 2312 from depositing on the insulating medium 21 and causing line interference while achieving interconnection.

[0078] When the embedded line addition layer 201 is set to be multi-layered, the hole interconnection 23 of the multi-layer embedded line addition layer 201 can all be the first type of hole interconnection 231, or some of the embedded line addition layers 201 can be the first type of hole interconnection 231. The design can be carried out according to the actual needs.

[0079] Furthermore, as shown in the appendix Figure 10 As shown, the thickness of the stepped pad 2312 can be greater than the thickness of the pad 222 of the current embedded circuit layer 201; wherein, the pad thickness is the dimension of the pad 222 along the direction perpendicular to the insulating medium 21.

[0080] The embedded circuit layer 201 where the stepped pad 2312 is currently located can be locally thickened or entirely thickened. For example, the embedded circuit layer 201 can be thickened based on the MSAP electroplating process. The increased thickness of the patterned metal layer not only facilitates the conductivity and current flow between interconnect structures, but also improves the heat dissipation effect between interconnect structures.

[0081] In other examples, such as the appendix Figure 8As shown, the pads 222 of the embedded circuit add-in layer 201 are hole-free pads. Correspondingly, the via interconnects 23 of the embedded circuit add-in layer 201 include second-type via interconnects 232. The second-type via interconnects 232 penetrate the insulating medium 21 of the current embedded circuit add-in layer 201, and both ends of the second-type via interconnects 232 are respectively connected to the pads 222 of the current embedded circuit add-in layer 201 and the pads 222 of another circuit add-in layer 2 adjacent to the current embedded circuit add-in layer 201. The second-type via interconnects 232 are formed by curing conductive paste.

[0082] In this example, the second type of via interconnect 232 can be formed before the pad 222 of the current embedded circuit addition layer 201. For example, by drilling holes in the prepreg corresponding to the insulating medium 21 of the current embedded circuit addition layer 201 and filling the holes with conductive paste, such as metal conductive paste (copper paste, etc.), and then heating and curing the prepreg and conductive paste, the second type of via interconnect 232 can be prepared to achieve interlayer interconnection.

[0083] The second type of via interconnect 232 will not form a step on the surface of the pad 222 of the current embedded line addition layer 201, so as to avoid step differences between interconnect structures, thereby reducing signal loss.

[0084] When the embedded line addition layer 201 is set to be multi-layered, the hole interconnection 23 of the multi-layer embedded line addition layer 201 can all be the second type of hole interconnection 232, or some of the hole interconnection 23 of the embedded line addition layer 201 can be the second type of hole interconnection 232. The design can be carried out according to the actual needs.

[0085] In some other examples, such as the appendix Figure 9 As shown, along the direction away from the base layer 1, an exposed circuit layer 202 is stacked on the embedded circuit layer 201. The via interconnects 23 of the embedded circuit layer 201 and the via interconnects 23 of the exposed circuit layer 202 are integrally formed and connected to form a third type of via interconnect 233. The pads 222 of the embedded circuit layer 201 are via pads, and the pads 222 of the exposed circuit layer 202 are non-via pads. The third type of via interconnect 233 sequentially penetrates the insulating medium 21 and the pads 222 of the embedded circuit layer 201 and the insulating medium 21 of the exposed circuit layer 202. The sidewalls of the third type of via interconnect 233 are connected to the pads 222 of the embedded circuit layer 201, and one end of the third type of via interconnect 233 is connected to the pads 222 of the exposed circuit layer 202.

[0086] Laser drilling can be performed simultaneously on the insulating medium 21 of both the embedded circuit layer 201 and the exposed circuit layer 202. For example, Figure 9 An example is demonstrated by drilling deep V-holes and then forming a third type of via interconnect 233 within the drilled holes using an electroplating process. This achieves an integral connection between the via interconnect 23 of the buried circuit addition layer 201 and the via interconnect 23 of the exposed circuit addition layer 202. This configuration not only avoids the formation of stepped pads on the surface of the pads 222 of the buried circuit addition layer 201, thus preventing transmission losses due to step differences between interconnect pads, but also simplifies the structure of the interlayer interconnect and the fabrication process.

[0087] When multiple combinations of embedded line addition layer 201 and exposed line addition layer 202 are configured, the via interconnects 23 involved in these multiple combinations can all be third type via interconnects 233, or the via interconnects 23 of some combinations can be third type via interconnects 233, and the design can be carried out according to actual needs.

[0088] The following will be combined with the appendix Figure 7 - Appendix Figure 11 The following is an illustrative example of a combination scheme for adding a second layer to a multi-layer circuit, with appendix. Figure 7 - Appendix Figure 11 Only a small number of line addition layers 2 are illustrated. Based on the concept of the combination scheme of line addition layers 2 involved below, further adaptive modifications (such as increasing the number of line addition layers 2), equivalent replacements or improvements can be made, all of which fall within the structural scope of the packaging substrate 001 provided in the embodiments of this disclosure.

[0089] In some implementation schemes (1), as shown in the appendix Figure 7 As shown, the packaging substrate 001 includes a circuit base layer 1, a first circuit addition layer 2 (BU01), a second circuit addition layer 2 (BU02), a third circuit addition layer 2 (BU03), a fourth circuit addition layer 2 (BU04), and a solder mask layer 3, arranged in sequence. The first circuit addition layer 2 (BU01) and the fourth circuit addition layer 2 (BU04) are both exposed circuit addition layers 202, while the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) are both buried circuit addition layers 201. The via interconnects 23 of the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) both use a first type of via interconnect 231. The pads 222 of the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) are via pads.

[0090] For the second line addition layer 2 (BU02), the via portion 2311 of its first type of via interconnect 231 penetrates the insulating medium 21 and pad 222 of the second line addition layer 2 (BU02), and the two ends of the via portion 2311 of the first type of via interconnect 231 are respectively connected to the pad 222 of the first line addition layer 2 (BU01) and the current stepped pad 2312, and the stepped pad 2312 of the first type of via interconnect 231 overlaps to the surface of the pad 222 of the second line addition layer 2 (BU02).

[0091] For the third line addition layer 2 (BU03), the via portion 2311 of its first type of via interconnect 231 penetrates the insulating medium 21 and pad 222 of the third line addition layer 2 (BU03), and the two ends of the via portion 2311 of the first type of via interconnect 231 are respectively connected to the stepped pad 2312 of the second line addition layer 2 (BU02) and the current stepped pad 2312. The stepped pad 2312 of the first type of via interconnect 231 overlaps to the surface of the pad 222 of the third line addition layer 2 (BU03).

[0092] In some implementation schemes (2), as shown in the appendix Figure 8 As shown, the packaging substrate 001 includes a circuit base layer 1, a first circuit addition layer 2 (BU01), a second circuit addition layer 2 (BU02), a third circuit addition layer 2 (BU03), a fourth circuit addition layer 2 (BU04), and a solder mask layer 3, arranged in sequence. The first circuit addition layer 2 (BU01) and the fourth circuit addition layer 2 (BU04) are both exposed circuit addition layers 202, while the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) are both buried circuit addition layers 201. The via interconnects 23 of the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) both adopt the second type of via interconnect 232 (i.e., solid pillars). The pads 222 of the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) are via-less pads.

[0093] For the second line addition layer 2 (BU02), its second type of via interconnect 232 penetrates the insulating medium 21 of the second line addition layer 2 (BU02), and the two ends of the second type of via interconnect 232 are respectively connected to the pad 222 of the second line addition layer 2 (BU02) and the pad 222 of the first line addition layer 2 (BU01).

[0094] For the third line addition layer 2 (BU03), its second type of via interconnect 232 penetrates the insulating medium 21 of the third line addition layer 2 (BU03), and the two ends of the second type of via interconnect 232 are respectively connected to the pad 222 of the third line addition layer 2 (BU03) and the pad 222 of the second line addition layer 2 (BU02).

[0095] In some implementation schemes (3), as shown in the appendix Figure 9 As shown, the packaging substrate 001 includes a circuit base layer 1, a first circuit addition layer 2 (BU01), a second circuit addition layer 2 (BU02), a third circuit addition layer 2 (BU03), a fourth circuit addition layer 2 (BU04), and a solder mask layer 3, arranged in sequence. The first circuit addition layer 2 (BU01), the third circuit addition layer 2 (BU03), and the fourth circuit addition layer 2 (BU04) are all exposed circuit addition layers 202, while the second circuit addition layer 2 (BU02) is a buried circuit addition layer 201. The via interconnects 23 of the second circuit addition layer 2 (BU02) and the third circuit addition layer 2 (BU03) are integrally formed to form a third type of via interconnect 233. The pads 222 of the second circuit addition layer 2 (BU02) are via pads.

[0096] The third type of via interconnect 233 sequentially penetrates the insulating medium 21 and pad 222 of the second line addition layer 2 (BU02) and the insulating medium 21 of the third line addition layer 2 (BU03), and the sidewall of the third type of via interconnect 233 is connected to the pad 222 of the second line addition layer 2 (BU02). The two ends of the third type of via interconnect 233 are respectively connected to the pad 222 of the first line addition layer 2 (BU01) and the pad 222 of the third line addition layer 2 (BU03).

[0097] Of course, it is not excluded that, for the scheme of stacking buried line addition layer 201 and exposed line addition layer 202, the structural form of the hole interconnection 23 is not limited to the above-described implementation scheme (3), and can also be as follows: Figure 10 and Figure 11 As shown, further examples are given below.

[0098] In some implementation schemes (4), as shown in the appendix Figure 10 As shown, the packaging substrate 001 includes a circuit base layer 1, a first circuit addition layer 2 (BU01), a second circuit addition layer 2 (BU02), a third circuit addition layer 2 (BU03), and a solder mask layer 3 arranged in sequence. The first circuit addition layer 2 (BU01) and the third circuit addition layer 2 (BU03) are both exposed circuit addition layers 202, and the second circuit addition layer 2 (BU02) is a buried circuit addition layer 201.

[0099] The via interconnect 23 of the second circuit addition layer 2 (BU02) adopts the first type of via interconnect 231. The pad 222 of the second circuit addition layer 2 (BU02) is a via pad.

[0100] For the second line addition layer 2 (BU02), the via portion 2311 of its first type of via interconnect 231 penetrates the insulating medium 21 and pad 222 of the second line addition layer 2 (BU02), and the two ends of the via portion 2311 of the first type of via interconnect 231 are respectively connected to the pad 222 of the first line addition layer 2 (BU01) and the current stepped pad 2312. The stepped pad 2312 of the first type of via interconnect 231 overlaps the surface of the pad 222 of the second line addition layer 2 (BU02), and the thickness of the stepped pad 2312 is greater than the thickness of the pad 222 of the second line addition layer 2 (BU02) that it overlaps with.

[0101] For the third line addition layer 2 (BU03), an interconnect 23 is arranged through the insulating medium 21 of the third line addition layer 2 (BU03). The two ends of the interconnect 23 of the third line addition layer 2 (BU03) are respectively connected to the stepped pad 2312 of the first type of interconnect 231 and the pad 222 of the third line addition layer 2 (BU03).

[0102] In some implementation schemes (5), as shown in the appendix Figure 11 As shown, the packaging substrate 001 includes a circuit base layer 1, a first circuit addition layer 2 (BU01), a second circuit addition layer 2 (BU02), a third circuit addition layer 2 (BU03), and a solder mask layer 3 arranged in sequence. The first circuit addition layer 2 (BU01) and the third circuit addition layer 2 (BU03) are both exposed circuit addition layers 202, and the second circuit addition layer 2 (BU02) is a buried circuit addition layer 201.

[0103] The via interconnect 23 of the second line addition layer 2 (BU02) is a second type of via interconnect 232. The pads 222 of the second line addition layer 2 (BU02) and the third line addition layer 2 (BU03) are via-less pads.

[0104] For the second line addition layer 2 (BU02), its second type of via interconnect 232 penetrates the insulating medium 21 of the second line addition layer 2 (BU02), and the two ends of the second type of via interconnect 232 are respectively connected to the pad 222 of the second line addition layer 2 (BU02) and the pad 222 of the first line addition layer 2 (BU01).

[0105] For the third line addition layer 2 (BU03), an interconnect 23 is arranged through the insulating medium 21 of the third line addition layer 2 (BU03). The two ends of the interconnect 23 of the third line addition layer 2 (BU03) are respectively connected to the pad 222 of the second line addition layer 2 (BU02) and the pad 222 of the third line addition layer 2 (BU03).

[0106] For any of the aforementioned packaging substrates 001, the insulating medium 21 of the embedded circuit enhancement layer 201 and the insulating medium 21 of the exposed circuit enhancement layer 202 can both be prepared using prepreg (PP). Prepreg, also known as prepreg material, can play a good bonding role. The prepreg includes resin and reinforcing material. The reinforcing material includes, but is not limited to, glass fiber (referred to as glass fiber), paper base, composite reinforcing material, etc. For example, the reinforcing material of the insulating medium involved in the embodiments of this disclosure can be glass fiber. In addition, the resin type can be epoxy resin, for example. In this way, during lamination, the epoxy resin of the prepreg melts, flows, and solidifies, thereby pressing the circuit layers of each layer together and forming a reliable insulating medium.

[0107] For any of the aforementioned packaging substrates 001, the patterned metal layer 22 can be formed using a metal with good conductivity, for example, copper.

[0108] In summary, the structure of the multilayer circuit addition layer 2 can be adaptively determined according to the actual application requirements and application scenarios of the packaging substrate 001. The embedded circuit addition layer 201 is prepared using the ETS process, and the exposed circuit addition layer 202 is prepared using the conventional PCB addition process. This allows for the arrangement of high-precision and high-density fine circuit layers in any layer of the PCB addition layer. Thus, the wiring density can be increased and fine circuit processing can be achieved at low cost in any inner layer of the PCB-based packaging substrate 001.

[0109] On the other hand, this disclosure also provides a method for preparing any of the above-mentioned packaging substrates 001, and the packaging substrate 001 mentioned herein can refer to any of the packaging substrates 001 described above. (Appendix) Figure 3 - Appendix Figure 7 An example of a fabrication process for a package substrate 001 is provided, in conjunction with the attached... Figure 3 - Appendix Figure 7 The method for preparing the packaging substrate 001 includes: providing a circuit base layer 1, and sequentially preparing multiple circuit enhancement layers 2 and solder resist layers 3 on the circuit base layer 1 to obtain the packaging substrate 001.

[0110] Among them, at least a portion of the multiple line addition layers 2 are embedded line addition layers 201, and the preparation method of the embedded line addition layer 201 includes:

[0111] Step S1, as attached Figure 3 As shown, a patterned metal layer 22 is fabricated on a carrier board 4 using an embedded circuit fabrication process to obtain an embedded circuit layer intermediate.

[0112] Step S2: Under the guidance of the alignment device, the embedded line addition intermediate is aligned with the interlayer interconnection position of the line base layer 1 or other prepared line addition layers 2. The embedded line addition intermediate is pressed onto the line base layer 1 or other prepared line addition layers 2 through the prepreg, and the prepreg forms the insulating medium 21.

[0113] Step S3: Remove the carrier plate 4, and before or after the lamination operation, prepare the hole interconnection 23 of the embedded circuit layer 201 at the interlayer interconnection position of the embedded circuit layer intermediate to obtain the embedded circuit layer 201.

[0114] The substrate 4 has a roughened copper seed layer 5, and a patterned metal layer 22 is formed on the copper seed layer 5 of the substrate 4. Therefore, the structure of the embedded circuit layer addition intermediate is as shown in the attached figure. Figure 3 As shown, it includes a patterned metal layer 22, a copper seed layer 5, and a carrier plate 4 arranged in sequence.

[0115] After completing the fabrication of the patterned metal layer 22 with fine lines, Figure 4 For example, the patterned metal layer 22 is laminated with the first line enhancement layer 2 (BU01), wherein the first line enhancement layer 2 (BU01) can be pre-prepared on the line base layer 1.

[0116] When performing step S2, it is necessary to ensure that the interlayer interconnection positions of the embedded line addition intermediate body and the line base layer 1 or other prepared line addition layers 2 are aligned, as shown in the attached figure. Figure 4 As shown, multiple pads 222 of the first line addition layer 2 (BU01) are aligned one-to-one with multiple pads 222 of the second line addition layer 2 (BU02) to achieve high-precision alignment, which is particularly important for the interlayer interconnect accuracy of the packaging substrate 001.

[0117] This disclosure embodiment achieves high-precision alignment between layers by using an alignment device. The alignment device used is selected from at least one of X-ray alignment devices and visual alignment devices (e.g., Bonding visual alignment devices, charge-coupled device (CCD) visual alignment devices). All of the above alignment devices have advantages such as high positioning accuracy and high reliability.

[0118] During positioning, a point on the layer to be aligned can be used as a target. For example, pad 222 on the second line addition layer 2 (BU02) can be used as a target (for example, the pad size can be designed to be large), and pad 222 on the first line addition layer 2 (BU01) can be used as another target. The positioning device can complete the precise alignment by identifying the two targets.

[0119] Taking X-ray alignment equipment as an example, the X-ray beam can penetrate through each layer to develop an image of the target, thereby locating its center to ensure that the two targets overlap and achieve positioning.

[0120] Taking a CCD vision alignment device as an example, the two targets mentioned above are calculated to determine the target positions, so as to ensure that the two targets overlap and achieve positioning.

[0121] Steps S1-S3 complete the fabrication and interlayer interconnection of the embedded circuit layer 201. Based on this, it can be determined whether further step S4 needs to be implemented according to the specific structural form of the circuit layer 2.

[0122] Step S4, as attached Figure 6 Based on the structure of the circuit layer 2, it is determined whether to continue adding layers. After the circuit layer 2 is prepared, a solder resist layer 3 is prepared on the outermost circuit layer 2 to obtain the packaging substrate 001.

[0123] Among them, the appendix Figure 6 An example is provided of fabricating a third line addition layer 2 (BU03) in the form of an embedded line addition layer on top of the second line addition layer 2 (BU02). (See attached image.) Figure 7 An example is provided where a fourth line addition layer 2 (BU04) in the form of an exposed line addition layer is prepared on the third line addition layer 2 (BU03) as a surface layer, and a solder mask layer 3 is prepared on the fourth line addition layer 2 (BU04) to complete the preparation of the package substrate 001.

[0124] Solder resist layer 3, commonly known as green oil, is prepared using solder resist to protect the outermost traces from oxidation and the effects of moisture, mechanical stress, etc.

[0125] It should be noted that in the process of preparing the multilayer circuit layer 2, if the circuit layer 2 is an embedded circuit, the preparation method of the circuit layer 2 in the embedded circuit form shall be referred to above. If the circuit layer 2 is an exposed circuit, the known PCB circuit processing technology can be used to complete the preparation of the packaging substrate 001.

[0126] In summary, the method for fabricating the packaging substrate 001 provided in this embodiment of the present disclosure, by performing Any Layer Embedded Pattern (AEP) design in the PCB add-on layer, can achieve high precision and high density of embedded circuits in any layer, resulting in superior precision and easier control over line width / spacing. Furthermore, the method for fabricating the packaging substrate 001 utilizes the relatively simple ETS process to pre-process a high-density embedded circuit layer. With high-precision alignment assistance, interlayer bonding is achieved through a prepreg. Subsequently, interlayer interconnection is performed on the newly added circuit add-on layer 2, with via interconnects 23 formed between any two adjacent circuit add-on layers 2. This method is relatively simple to operate, has low cost, and avoids the need for simultaneous drilling of multiple circuit add-on layers using large-diameter mechanical drilling, ensuring the realization of high-density circuitry.

[0127] Depending on the specific structure of the line addition layer 2 in the packaging substrate 001, different interlayer interconnection operations can be implemented. In conjunction with the various packaging substrates 001 mentioned above, the fabrication processes of different types of packaging substrates 001 will be further illustrated here.

[0128] In some examples, in conjunction with the packaging substrate 001 involved in the above implementation scheme (1), wherein, as shown in the attached Figure 7 As shown, the pad 222 of the embedded circuit addition layer 201 is a via pad, and the via interconnect 23 of the embedded circuit addition layer 201 includes a first type of via interconnect 231; the preparation of the first type of via interconnect 231 occurs after the lamination operation, and the preparation method of the first type of via interconnect 231 includes: drilling holes at the interlayer interconnection position of the insulating medium 21 of the embedded circuit addition layer 201, and forming the first type of via interconnect 231 at the drilling position by electroplating process.

[0129] Accordingly, the method for preparing the packaging substrate 001 involved in implementation scheme (1) is as follows:

[0130] Step S11, as attached Figure 3 As shown, a patterned metal layer 22 is fabricated on a carrier board 4 using an embedded circuit fabrication process to obtain an embedded circuit layer intermediate.

[0131] Step S12, as attached Figure 4 As shown, under the guidance of the alignment device, the embedded circuit layer intermediate is aligned with the interlayer interconnection position of the prepared first circuit layer 2 (BU01). The embedded circuit layer intermediate is pressed onto the first circuit layer 2 (BU01) through a prepreg, and the prepreg forms the insulating medium 21 of the embedded circuit layer 201 (BU02).

[0132] Step S13, as attached Figure 5As shown, after removing the carrier board 4 and performing the lamination operation, holes are drilled at the interlayer interconnection locations of the insulating medium 21 of the embedded circuit layer 201 (i.e., the locations where vias on the via pads are exposed). The formed holes penetrate the insulating medium 21 and expose the pads 222 on the first circuit layer 2 (BU01). This drilling can be laser drilling. Then, a first type of via interconnect 231 is formed at the drilled locations using an electroplating process to obtain the second circuit layer 2 (BU02) in the form of an embedded circuit.

[0133] As attached Figure 5 As shown, the via portion 2311 of the first type of via interconnect 231 penetrates the insulating medium 21 and pad 222 of the second line addition layer 2 (BU02), and the two ends of the via portion 2311 of the first type of via interconnect 231 are respectively connected to the pad 222 of the first line addition layer 2 (BU01) and the current step pad 2312. The step pad 2312 of the first type of via interconnect 231 overlaps the surface of the pad 222 of the second line addition layer 2 (BU02).

[0134] Pad 222 is a via pad, which can be obtained by forming discontinuous pads using the ETS process. In this way, the vias on the first pad 213 are formed simultaneously, offering the advantages of simple and efficient operation. Of course, it is also possible to form a continuous pad 222 using the ETS process, and then perform conformal mask (CFM) etching on the pad 222 to form vias.

[0135] Step S14, Combining Figure 6 Following the same fabrication method as the second circuit addition layer 2 (BU02), a third circuit addition layer 2 (BU03) is fabricated on the second circuit addition layer 2 (BU02). In the third circuit addition layer 2 (BU03), the via portion 2311 of the first type of hole interconnect 231 penetrates the insulating medium 21 and the pad 222 of the third circuit addition layer 2 (BU03). The two ends of the via portion 2311 of the first type of hole interconnect 231 are respectively connected to the stepped pad 2312 of the second circuit addition layer 2 (BU02) and the current stepped pad 2312. The stepped pad 2312 of the first type of hole interconnect 231 overlaps to the surface of the pad 222 of the third circuit addition layer 2 (BU03).

[0136] Step S15, Combining Figure 7 A fourth layer (BU04) was fabricated on the third layer (BU03) using conventional PCB fabrication technology. Based on the structural arrangement of the multiple layer 2s, it was determined whether to add another layer on the fourth layer (BU04). Figure 7The example shows that no further layering is allowed. Therefore, a solder mask layer 3 is prepared on the fourth line layer 2 (BU04) to obtain the packaging substrate 001 involved in the implementation scheme (1).

[0137] In addition, the preparation method of the package substrate 001 shown in embodiment (4) can also adopt the preparation method of the package substrate 001 shown in embodiment (1) above. The difference is that in embodiment (4), the thickness of the stepped pad 2312 of the first type of hole interconnect 231 is greater than the thickness of the pad 222 of the second line addition layer 2 (BU02) that is overlapped. This can be achieved by MSAP process.

[0138] In some examples, the packaging substrate 001 involved in the above implementation scheme (2) is, as shown in the attached... Figure 8 As shown, the pads 222 of the embedded circuit add-in layer 201 are hole-free pads, and the via interconnects 23 of the embedded circuit add-in layer 201 include second-type via interconnects 232. The preparation of the second-type via interconnects 232 occurs before the lamination operation, and the preparation method of the second-type via interconnects 232 includes: pre-pressing a prepreg onto the circuit base layer 1 or another prepared circuit add-in layer 2, wherein the prepreg forms an insulating medium 21; under the guidance of an alignment device, drilling is performed at the interlayer interconnect positions of the insulating medium 21 of the embedded circuit add-in layer 201, and conductive paste is filled into the drilling positions, and then a lamination operation is performed, thereby forming the second-type via interconnects 232 from the conductive paste.

[0139] Accordingly, the method for preparing the packaging substrate 001 involved in implementation scheme (2) is as follows:

[0140] Step S21: Using the embedded circuit fabrication process, a patterned metal layer 22 is fabricated on the carrier board 4 to obtain an embedded circuit add-in intermediate. The operation flow of step S21 can still be found elsewhere. Figure 3 .

[0141] Step S22: Pre-press the prepreg onto the prepared first circuit enhancement layer 2 (BU01), which provides the insulating medium 21 for the second circuit enhancement layer 2 (BU02) in the form of embedded circuits. Guided by an alignment device, holes are drilled at the interlayer interconnect locations of the insulating medium 21 of the second circuit enhancement layer 2 (BU02) to expose the pads 222 of the first circuit enhancement layer 2 (BU01). Conductive paste is then filled into the drilled locations, followed by a pressing operation to form a second type of via interconnect 232 from the conductive paste. The conductive paste can be copper paste; after curing, it forms a solid cylindrical form of the second type of via interconnect 232.

[0142] Step S23: Remove the carrier board 4 to complete the fabrication of the second circuit addition layer 2 (BU02), as shown in the attached figure. Figure 8 As shown, the second type of via interconnect 232 penetrates the insulating medium 21 of the second line addition layer 2 (BU02), and the two ends of the second type of via interconnect 232 are respectively connected to the pad 222 of the second line addition layer 2 (BU02) and the pad 222 of the first line addition layer 2 (BU01).

[0143] Step S24: Following the same preparation method as the second line addition layer 2 (BU02), a third line addition layer 2 (BU03) is prepared on the second line addition layer 2 (BU02). In the third line addition layer 2 (BU03), the second type of via interconnect 232 penetrates the insulating medium 21 of the third line addition layer 2 (BU03), and the two ends of the second type of via interconnect 232 are respectively connected to the pads 222 of the third line addition layer 2 (BU03) and the pads 222 of the second line addition layer 2 (BU02).

[0144] Step S25: Using conventional PCB fabrication technology, a fourth line addition layer 2 (BU04) is prepared on the third line addition layer 2 (BU03). Based on the structural arrangement of the multiple line addition layers 2, it is determined whether to continue adding layers on the fourth line addition layer 2 (BU04). Figure 8 The example shows that no further layering is allowed. Therefore, a solder mask layer 3 is prepared on the fourth line layer 2 (BU04) to obtain the packaging substrate 001 involved in the implementation scheme (2).

[0145] In addition, the preparation method of the packaging substrate 001 shown in embodiment (5) can also adopt the preparation method of the packaging substrate 001 shown in embodiment (2) mentioned above, and will not be repeated here.

[0146] In some examples, the packaging substrate 001 involved in the above implementation scheme (3) is described, wherein, as shown in the attached... Figure 9 As shown, an exposed circuit layer 202 is stacked on the embedded circuit layer 201 along the direction away from the base layer 1. The hole interconnects 23 of the embedded circuit layer 201 and the hole interconnects 23 of the exposed circuit layer 202 cooperate to form a third type of hole interconnect 233. The pads 222 of the embedded circuit layer 201 are through-hole pads, and the pads 222 of the exposed circuit layer 202 are through-hole pads.

[0147] The third type of via interconnect 233 is prepared after the lamination operation, and the preparation method of the third type of via interconnect 233 includes: after forming the insulating medium 21 and the patterned metal layer 22 of the embedded circuit addition layer 201 by lamination operation, pre-pressing another half-cured sheet onto the insulating medium 21 of the embedded circuit addition layer 201, and the other half-cured sheet forms the insulating medium 21 of the exposed circuit addition layer 202; simultaneously drilling holes at the interlayer interconnection positions of the insulating medium 21 of the exposed circuit addition layer 202 and the insulating medium 21 of the embedded circuit addition layer 201, and forming the third type of via interconnect 233 at the drilling positions by electroplating process.

[0148] Accordingly, the method for preparing the packaging substrate 001 involved in implementation scheme (3) is as follows:

[0149] Step S31: Using the embedded circuit fabrication process, a patterned metal layer 22 is prepared on the carrier board 4 to obtain an embedded circuit layer intermediate.

[0150] Step S32: Under the guidance of the alignment device, the embedded circuit layer intermediate is aligned with the interlayer interconnection position of the prepared first circuit layer 2 (BU01). The embedded circuit layer intermediate is pressed onto the first circuit layer 2 (BU01) through a prepreg. The prepreg forms the insulating medium 21 of the second circuit layer 2 (BU02) in the form of an embedded circuit.

[0151] Step S33: Remove the carrier board 4, and after the pressing operation, pre-press the other half of the cured sheet onto the insulating medium 21 of the embedded circuit layer 201. This other half of the cured sheet forms the insulating medium 21 of the third circuit layer 2 (BU03). Simultaneously, drill holes at the interlayer interconnection locations of the insulating medium 21 of the second circuit layer 2 (BU02) and the third circuit layer 2 (BU03), and form a third type of hole interconnection 233 at the drilled locations using an electroplating process. Laser drilling can be used for this drilling.

[0152] Step S34: Using conventional PCB circuit processing technology, a patterned metal layer 22 of the third circuit addition layer 2 (BU03) is formed on the insulating medium 21 of the third circuit addition layer 2 (BU03), thus completing the preparation of the third circuit addition layer 2 (BU03).

[0153] The third type of via interconnect 233 sequentially penetrates the insulating medium 21 and pad 222 of the second line addition layer 2 (BU02) and the insulating medium 21 of the third line addition layer 2 (BU03), and the sidewall of the third type of via interconnect 233 is connected to the pad 222 of the second line addition layer 2 (BU02). The two ends of the third type of via interconnect 233 are respectively connected to the pad 222 of the first line addition layer 2 (BU01) and the pad 222 of the third line addition layer 2 (BU03).

[0154] Step S35: Using conventional PCB fabrication technology, a fourth line addition layer 2 (BU04) is prepared on the third line addition layer 2 (BU03). Based on the structural arrangement of the multiple line addition layers 2, it is determined whether to continue adding layers on the fourth line addition layer 2 (BU04). Figure 9 The example shows that no further layering is allowed. Therefore, a solder mask layer 3 is prepared on the fourth line layer 2 (BU04) to obtain the packaging substrate 001 involved in the implementation scheme (3).

[0155] In one aspect, embodiments of this disclosure also provide a semiconductor package, with... Figure 12 An example of a type containing Figure 7 The semiconductor package of the packaging substrate 001 shown is as follows: Figure 12 As shown, the semiconductor package includes a packaging substrate 001 and electronic components 002. The packaging substrate 001 is as described above, or it is prepared using any of the methods described above for preparing the packaging substrate 001. The electronic components 002 are connected to the outermost line augmentation layer 2 of the plurality of line augmentation layers 2 of the packaging substrate 001.

[0156] The semiconductor package provided in this disclosure has all the advantages of the packaging substrate 001 and its preparation method mentioned above, which will not be repeated here.

[0157] In some examples, the electronic components 002 mentioned above include, but are not limited to: dies, chips, wafers, integrated devices, integrated passive devices, die packages, integrated circuit devices, device packages, integrated circuit packages, semiconductor devices, stacked packaged devices, intermediaries, etc.

[0158] The semiconductor packages provided in this disclosure can be applied to various scenarios, including but not limited to: central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuit (ASIC) devices, system-on-a-chip (SOCs), high-performance computing (HPC) devices, artificial intelligence (AI) devices, data center switches, mobile phone devices, computer devices, wearable devices, communication devices, navigation devices, set-top boxes, music players, video players, Internet of Things (IoT) devices, indoor baseband processing units, servers, routers, etc.

[0159] The above description is only for the purpose of enabling those skilled in the art to understand the technical solutions disclosed herein, and is not intended to limit the scope of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A packaging substrate, characterized in that, The packaging substrate (001) includes: a circuit base layer (1), a plurality of circuit addition layers (2) and a solder mask layer (3) arranged in sequence. Each circuit addition layer (2) includes: an insulating medium (21), a patterned metal layer (22) and a via interconnect (23). The patterned metal layer (22) is disposed on the side of the insulating medium (21) away from the circuit base layer (100). The via interconnect (23) at least partially penetrates the insulating medium (21). The patterned metal layer (22) between the circuit base layer (1) and the adjacent circuit augmentation layer (2), as well as between any two adjacent patterned metal layers (22) of the circuit augmentation layer (2), are electrically connected through the corresponding hole interconnect (23). Among them, at least some of the multiple line addition layers (2) are embedded line addition layers (201), and the patterned metal layer (22) of the embedded line addition layer (201) is embedded in one side surface of its corresponding insulating medium (21).

2. The packaging substrate according to claim 1, characterized in that, Some of the multiple line addition layers (2) are exposed line addition layers (202), and the patterned metal layer (22) of the exposed line addition layer (202) is protruding and arranged on one side surface of its corresponding insulating medium (21). The line width and line spacing of the patterned metal layer (22) of the exposed line augmentation layer (202) are greater than those of the patterned metal layer (22) of the embedded line augmentation layer (201).

3. The packaging substrate according to any one of claims 1-2, characterized in that, The patterned metal layer (22) includes: a trace (221) and a pad (222) electrically connected to the trace (221), the pad (222) also being electrically connected to the via interconnect (23); The pads (222) of the embedded circuit addition layer (201) include at least one of holeless pads and hole pads.

4. The packaging substrate according to claim 3, characterized in that, The pads (222) of the buried circuit addition layer (201) are via pads. Correspondingly, the via interconnects (23) of the buried circuit addition layer (201) include a first type of via interconnect (231), which includes: a via portion (2311) and a stepped pad (2312) connected to the via portion (2311). The via portion (2311) penetrates the insulating medium (21) and pad (222) of the current embedded circuit layer (201), and the stepped pad (2312) overlaps to the surface of the pad (222) of the current embedded circuit layer (201).

5. The packaging substrate according to claim 4, characterized in that, The thickness of the stepped pad (2312) is greater than the thickness of the overlapping pad (222); The thickness of the pad is the dimension of the pad (222) in the direction perpendicular to the insulating medium (21).

6. The packaging substrate according to claim 3, characterized in that, The pads (222) of the buried circuit addition layer (201) are hole-free pads, and correspondingly, the hole interconnects (23) of the buried circuit addition layer (201) include a second type of hole interconnects (232). The second type of via interconnect (232) penetrates the insulating medium (21) of the current embedded line addition layer (201), and the two ends of the second type of via interconnect (232) are respectively connected to the pad (222) of the current embedded line addition layer (201) and the pad (222) of another line addition layer (2) adjacent to the current embedded line addition layer (201); The second type of hole interconnect (232) is formed by curing a conductive paste.

7. The packaging substrate according to claim 3, characterized in that, Along the direction away from the base layer (1), an exposed line layer (202) is stacked on the embedded line layer (201). The hole interconnects (23) of the embedded line layer (201) and the hole interconnects (23) of the exposed line layer (202) are integrally formed and connected to form a third type of hole interconnect (233). The pads (222) of the embedded circuit addition layer (201) are via pads, and the pads (222) of the exposed circuit addition layer (202) are non-via pads. The third type of via interconnect (233) sequentially penetrates the insulating medium (21) and pads (222) of the embedded circuit addition layer (201) and the insulating medium (21) of the exposed circuit addition layer (202), and the sidewalls of the third type of via interconnect (233) are connected to the pads (222) of the embedded circuit addition layer (201), and one end of the third type of via interconnect (233) is connected to the pads (222) of the exposed circuit addition layer (202).

8. A method for preparing a packaging substrate, characterized in that, The packaging substrate (001) is as described in any one of claims 1-7, and the method for preparing the packaging substrate (001) includes: A circuit base layer (1) is provided, and a plurality of circuit enhancement layers (2) and solder mask layers (3) are sequentially prepared on the circuit base layer (1) to obtain the packaging substrate (001); Wherein, at least a portion of the multiple line addition layers (2) are embedded line addition layers (201), and the method for preparing the embedded line addition layer (201) includes: Using the embedded circuit fabrication process, a patterned metal layer (22) is prepared on the carrier board (4) to obtain an embedded circuit layering intermediate; Under the guidance of the alignment device, the embedded line layer intermediate is aligned with the interlayer interconnection position of the line base layer (1) or other prepared line layer (2). The embedded line layer intermediate is pressed onto the line base layer (1) or other prepared line layer (2) through a prepreg, and the prepreg forms an insulating medium (21). Remove the carrier plate (4), and before or after the pressing operation, prepare the hole interconnects (23) of the embedded circuit layer (201) at the interlayer interconnection position of the embedded circuit layer intermediate to obtain the embedded circuit layer (201).

9. The method for preparing a packaging substrate according to claim 8, characterized in that, The pads (222) of the embedded circuit addition layer (201) are via pads, and the via interconnects (23) of the embedded circuit addition layer (201) include via interconnects (231) of the first type. The fabrication of the first type of via interconnect (231) occurs after the pressing operation, and the method for fabricating the first type of via interconnect (231) includes: Holes are drilled at the interlayer interconnection locations of the insulating medium (21) of the embedded line addition layer (201), and the first type of hole interconnection (231) is formed at the drilled locations by an electroplating process.

10. The method for preparing the packaging substrate according to claim 8, characterized in that, The pads (222) of the buried circuit addition layer (201) are hole-free pads, and the hole interconnects (23) of the buried circuit addition layer (201) include second type of hole interconnects (232); The fabrication of the second type of via interconnect (232) occurs prior to the pressing operation, and the method for fabricating the second type of via interconnect (232) includes: The prepreg is prepressed onto the circuit base layer (1) or other prepared circuit add-ins (2), and the prepreg forms the insulating medium (21); Under the guidance of the alignment device, holes are drilled at the interlayer interconnection positions of the insulating medium (21) of the embedded line addition layer (201), and conductive paste is filled into the drilled positions. Then, the pressing operation is performed, thereby forming the second type of hole interconnection (232) by the conductive paste.

11. The method for preparing a packaging substrate according to claim 8, characterized in that, Along the direction away from the base layer (1), an exposed circuit layer (202) is stacked on the embedded circuit layer (201). The hole interconnects (23) of the embedded circuit layer (201) and the hole interconnects (23) of the exposed circuit layer (202) cooperate to form a third type of hole interconnect (233). The pads (222) of the embedded circuit layer (201) are through pads, and the pads (222) of the exposed circuit layer (202) are non-through pads. The fabrication of the third type of via interconnect (233) occurs after the pressing operation, and the method for fabricating the third type of via interconnect (233) includes: After the insulating medium (21) and patterned metal layer (22) of the embedded circuit augmentation layer (201) are formed by the pressing operation, another half-cured sheet is pre-pressed onto the insulating medium (21) of the embedded circuit augmentation layer (201), and the other half-cured sheet forms the insulating medium (21) of the exposed circuit augmentation layer (202). At the interlayer interconnection positions of the insulating medium (21) of the exposed line addition layer (202) and the insulating medium (21) of the embedded line addition layer (201), holes are drilled simultaneously, and the third type of hole interconnection (233) is formed at the drilled positions by electroplating.

12. A semiconductor package, characterized in that, The semiconductor package includes: a packaging substrate (001) and electronic components (002), wherein the packaging substrate (001) is prepared according to any one of claims 1-7 or by any one of claims 8-11; The electronic component (002) is connected to the outermost line layer (2) of the multiple line layer (2) of the packaging substrate (001).

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