Semiconductor package and solid state circuit breaker including same

Abstract

The invention provides a semiconductor package and a solid state circuit breaker including the same. A semiconductor package may include: a package substrate provided with a plurality of pins connected to the outside, the plurality of pins including a drain pin, a source pin, a Kelvin pin, and a gate pin; a first die; a second die spaced apart from the first die in the first direction; and a multilayer conductive connection structure on the package substrate and including a first conductive pattern and a second conductive pattern over and partially overlapping the first conductive pattern, in which the first die and the second die are connected in parallel, the gate electrodes of the first die and the second die are electrically connected to the gate pin via one of the first conductive pattern and the second conductive pattern, the Kelvin electrode of the first die is electrically connected to the Kelvin pin, and the Kelvin electrode of the second die is electrically connected to the Kelvin pin via the other of the first conductive pattern and the second conductive pattern.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package and a solid state circuit breaker including the same. BACKGROUND

[0002] Unlike a conventional mechanical circuit breaker that uses mechanical contacts to open and close a circuit, a solid state circuit breaker (SSCB) uses semiconductor power devices instead of mechanical contacts to cut off current in the event of a fault. Compared to a conventional mechanical circuit breaker, a solid state circuit breaker can achieve higher performance, reliability, and efficiency, is smaller in size, lighter in weight, and breaks without an arc. For example, a conventional mechanical circuit breaker achieves a breaking speed of only a millisecond, whereas a solid state circuit breaker is capable of achieving a breaking speed of a microsecond. Turn-on and turn-off of the solid state circuit breaker are achieved by controlling carriers and channels of the carriers inside the power devices.

[0003] In the solid state circuit breaker, a main requirement for the power devices is to have a low on-resistance and a high switching consistency. In order to achieve a low on-resistance, it is common to connect a plurality of power devices in parallel or to connect a plurality of dies in parallel within one package. However, when a plurality of power devices are connected in parallel or a plurality of dies are connected in parallel, it is difficult to achieve simultaneous turn-off of the plurality of power devices or the plurality of dies at a microsecond level, i.e., it is difficult to achieve a high switching consistency. If the switching consistency is poor, a situation in which one die has already turned off while another die has not yet turned off can occur, and in this case, a short-circuit current is large, causing the die that has not yet turned off to be more easily damaged. SUMMARY

[0004] According to an aspect of the present disclosure, it is possible to provide a semiconductor package structure having improved switching consistency while ensuring a low on-resistance and a solid state circuit breaker including the same.

[0005] According to another aspect of the present disclosure, it is possible to provide a semiconductor package structure having improved reliability and a solid state circuit breaker including the same.

[0006] According to another aspect of the present disclosure, it is possible to provide a semiconductor package structure having a good heat dissipation effect and a solid state circuit breaker including the same.

[0007] However, the technical problems to be solved by the present disclosure are not limited to the above-described technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] According to some embodiments of the present disclosure, a semiconductor package structure can include a package substrate provided with a plurality of pins connected to the outside, the plurality of pins including a drain pin, a source pin, a Kelvin pin, and a gate pin; a first die disposed adjacent to a first side of the package substrate and having a source electrode, a drain electrode, a Kelvin electrode, and a gate electrode; a second die spaced apart from the first die in a first direction such that the first die is located between the first side of the package substrate and the second die and having a source electrode, a drain electrode, a Kelvin electrode, and a gate electrode; and a multi-layer conductive connection structure on the package substrate, the multi-layer conductive connection structure including a first conductive pattern and a second conductive pattern above the first conductive pattern and overlapping a portion of the first conductive pattern, wherein the first die and the second die are connected in parallel, wherein the gate electrode of the first die and the gate electrode of the second die are electrically connected to the gate pin via one of the first conductive pattern and the second conductive pattern, wherein the Kelvin electrode of the first die is electrically connected to the Kelvin pin, and the Kelvin electrode of the second die is electrically connected to the Kelvin pin via the other of the first conductive pattern and the second conductive pattern.

[0009] According to some embodiments of the present disclosure, the Kelvin electrode of the first die can also be electrically connected to the Kelvin pin via the other of the first conductive pattern and the second conductive pattern.

[0010] According to some embodiments of the present disclosure, the source electrodes and the drain electrodes of the first die and the second die and the source pin and the drain pin of the package substrate can be located in a main loop, the Kelvin electrodes and the gate electrodes of each of the first die and the second die and the Kelvin pin and the gate pin of the package substrate can be located in a driving loop, a current in the driving loop can be less than a current in the main loop, and the Kelvin electrodes of the first die and the second die can not be located in the main loop. A direction of a current flowing through the first conductive pattern can be configured to be opposite to a direction of a current flowing through the second conductive pattern.

[0011] According to some embodiments of the present disclosure, the gate electrode of the first die and the gate electrode of the second die can be electrically connected to the gate pin via the second conductive pattern, wherein the gate electrode of the first die and the gate electrode of the second die can be connected to the second conductive pattern by a first bonding wire and a second bonding wire, respectively, and the second conductive pattern is connected to the gate pin by a third bonding wire. The Kelvin electrode of the first die and the Kelvin electrode of the second die can be connected to the first conductive pattern by a fourth bonding wire and a fifth bonding wire, respectively, and the first conductive pattern is connected to the Kelvin pin by a sixth bonding wire, or the Kelvin electrode of the first die can be directly connected to the Kelvin pin by the fourth bonding wire, and the Kelvin electrode of the second die can be connected to the first conductive pattern by the fifth bonding wire, and the first conductive pattern is connected to the Kelvin pin by the sixth bonding wire.

[0012] According to some embodiments of the disclosure, the gate electrode of the first die and the gate electrode of the second die can be electrically connected to the gate pin via the first conductive pattern, wherein the gate electrode of the first die and the gate electrode of the second die can be connected to the first conductive pattern by the first bonding wire and the second bonding wire, respectively, and the first conductive pattern is connected to the gate pin by the third bonding wire. The Kelvin electrode of the first die and the Kelvin electrode of the second die can be connected to the second conductive pattern by the fourth bonding wire and the fifth bonding wire, respectively, and the second conductive pattern is connected to the Kelvin pin by the sixth bonding wire, or the Kelvin electrode of the first die can be directly connected to the Kelvin pin by the fourth bonding wire, and the Kelvin electrode of the second die can be connected to the second conductive pattern by the fifth bonding wire, and the second conductive pattern is connected to the Kelvin pin by the sixth bonding wire.

[0013] According to some embodiments of the disclosure, the first bonding wire to the sixth bonding wire can not overlap each other in a vertical direction perpendicular to the surface of the package substrate.

[0014] According to some embodiments of the disclosure, the multilayer conductive connection structure can further include a second insulating substrate formed between the first conductive pattern and the second conductive pattern, and the first conductive pattern can have a greater width than the second conductive pattern and the second insulating substrate such that the first conductive pattern has a portion exposed by the second conductive pattern and the second insulating substrate for wire bonding.

[0015] According to some embodiments of the disclosure, the second conductive pattern can extend in the first direction, and the first conductive pattern can include a main portion extending in the first direction and overlapping the second conductive pattern and a plurality of branch portions protruding from the main portion, and a portion of each of the plurality of branch portions can be exposed by the second conductive pattern and the second insulating substrate.

[0016] According to some embodiments of the disclosure, the package substrate can have a substrate conductive pattern formed on a surface thereof, and the drain electrode of the backside of the first die and the drain electrode of the backside of the second die can be bonded to the substrate conductive pattern, and the substrate conductive pattern can be connected to the drain pin.

[0017] According to some embodiments of the disclosure, the substrate conductive pattern can be below the first conductive pattern such that the first insulating substrate is therebetween, or can be in the same plane as the first conductive pattern and spaced apart from the first conductive pattern.

[0018] According to some embodiments of the disclosure, the multilayer conductive connection structure can be formed by a multilayer ceramic substrate or a multilayer polymer substrate, or a multilayer structure consisting of the multilayer conductive connection structure and the package substrate together can be formed by a multilayer ceramic substrate or a multilayer polymer substrate.

[0019] According to some embodiments of the disclosure, the multi-layer conductive connection structure can be formed by attaching two or more direct copper bonded ceramic (DBC) substrates having different widths, or a multi-layer structure composed of the multi-layer conductive connection structure and a package substrate can be formed by attaching two or more direct copper bonded ceramic (DBC) substrates having different widths.

[0020] According to some embodiments of the disclosure, the source electrode of the first die and the source electrode of the second die can be connected to a source pin through at least one source lead wire extending in the first direction. The drain pin, the source pin, the Kelvin pin, and the gate pin can be arranged in sequence along the first side of the package substrate.

[0021] According to some embodiments of the disclosure, the first die and the second die can be silicon (Si), silicon carbide (SiC), or gallium nitride (GaN)-based metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) or gallium nitride (GaN)-based high electron mobility transistors (HEMTs).

[0022] According to some embodiments of the disclosure, a solid state circuit breaker can include the above semiconductor package. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a planar layout illustrating a semiconductor package according to a first comparative example.

[0025] Figure 2 is a planar layout illustrating a semiconductor package according to a second comparative example.

[0026] Figure 3 is a planar layout illustrating a semiconductor package according to an embodiment of the disclosure.

[0027] Figure 4 is a simulation graph illustrating current and power changes over time for a semiconductor package of Figure 1 and a semiconductor package of Figure 3

[0028] Figure 5 is a planar layout illustrating a semiconductor package according to another embodiment of the disclosure.

[0029] Figure 6 part (a) and part (b) of Figure 5 ​The cross-sectional view and exploded planar view of the multilayer conductive interconnect structure included in the semiconductor package.

[0030] Figure 7 It is used for comparison Figure 1 Semiconductor packaging and Figure 5 Simulated graphs of current versus time and power versus time for semiconductor packages.

[0031] Figure 8 This illustrates a planar layout of a semiconductor package according to another embodiment of the present disclosure.

[0032] Figure 9 yes Figure 8 A cross-sectional view of the multilayer conductive connection structure of a semiconductor package.

[0033] Figure 10 This illustrates a planar layout of a semiconductor package according to another embodiment of the present disclosure.

[0034] Figure 11 This is a schematic diagram illustrating a solid-state circuit breaker including a semiconductor package according to another embodiment of the present disclosure. Detailed Implementation

[0035] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this disclosure, but not all embodiments.

[0036] Therefore, the following detailed description of embodiments of the present disclosure provided in conjunction with the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely to illustrate selected embodiments of the disclosure. All other embodiments obtained by those skilled in the art based on the embodiments in this disclosure without inventive effort are within the scope of protection of this disclosure.

[0037] Unless the context otherwise defines, the singular form includes the plural form. Throughout this specification, the terms “comprising,” “having,” etc., are used herein to specify the presence of the stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0038] Furthermore, even though ordinal terms such as "first" and "second" may be used to describe various components, these components are not limited by these terms, which are only used to distinguish one component from other components. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0039] In the description of the present disclosure, it should be understood that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the disclosed product is placed, or the orientation or positional relationship commonly understood by those skilled in the art, and are only for the convenience of describing the present disclosure and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0040] Figure 1 is a planar layout showing a semiconductor package 1a according to a first comparative example.

[0041] With reference to Figure 1 , the semiconductor package 1a can include a package substrate Sub1 and a first die Die1 and a second die Die2 mounted on the package substrate Sub1 and connected in parallel to each other. The semiconductor package 1a can have, for example, a TO-247 package form (including a backplate hole form and a backplate non-hole form), but the present disclosure is not limited thereto. The package substrate Sub1 can have a plurality of pins for connection with the outside raised on a first side thereof, but the present disclosure is not limited thereto, and the plurality of pins can have other arrangement forms, for example, can not be located on the same side. As shown in Figure 1 , the plurality of pins can include a drain pin D, a source pin S, a Kelvin pin K, and a gate pin G arranged in order on the first side of the package substrate Sub1, but the present disclosure is not limited thereto. The first die Die1 can be arranged adjacent to the first side of the package substrate Sub1. The second die Die2 can be spaced apart from the first side of the package substrate Sub1 in a first direction so that the first die Die1 is located between the first side of the package substrate Sub1 and the second die Die2. The first die Die1 and the second die Die2 can be dies identical to each other, or can be different dies. The first die Die1 and the second die Die2 can be silicon (Si), silicon carbide (SiC), or gallium nitride (GaN)-based metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), or gallium nitride (GaN)-based high electron mobility transistors (HEMTs), but the present disclosure is not limited thereto.

[0042] Each of the first die Die1 and the second die Die2 can include a source electrode SE, a drain electrode (not shown), a Kelvin electrode KE, and a gate electrode GE, wherein the source electrode SE, the Kelvin electrode KE, and the gate electrode GE are located on a front side of each die, and the drain electrode is located on a back side of each die.

[0043] The source electrode SE of the first die Die 1 and the source electrode SE of the second die Die 2 are connected to the source pin S via at least one source wire 18 extending in a first direction. The source wire 18 may be formed of aluminum wire and have a relatively large cross-sectional area or diameter to withstand large currents. The drain electrode on the back side of the first die Die 1 and the drain electrode on the back side of the second die Die 2 may be connected to a substrate conductive pattern (not shown separately) located on the package substrate, which in turn is connected to the drain pin D. The source electrode SE, drain electrode, at least one source wire 18 of the first die Die 1 and the second die Die 2, the substrate conductive pattern of the package substrate Sub1, the drain pin D, and the source pin S form a main loop in which a large current flows.

[0044] The Kelvin electrode KE of each of the first die Die 1 and the second die Die 2 can be connected to the corresponding source electrode SE. The Kelvin electrode KE can be considered as the portion of the corresponding source electrode SE that is not located in the main circuit. The Kelvin electrode KE can also be referred to as the Kelvin source or auxiliary source. The Kelvin electrode KE of the first die Die 1 is connected to the Kelvin pin K via bonding lead 13, and the gate electrode GE of the first die Die 1 is connected to the gate pin G via bonding lead 11, thereby forming the drive circuit of the first die Die 1. The current in the drive circuit can be much smaller than the current in the main circuit.

[0045] like Figure 1 As shown, the gate electrode GE of the second die Die 2 is connected to the gate pin G via bonding lead 12, but no bonding lead is drawn from the Kelvin electrode KE of the second die Die 2. Therefore, the drive circuit of the second die Die 2 needs to pass through a portion of the source wire 18 and then through the Kelvin electrode KE of the first die Die 1 to connect to the Kelvin pin K. The source wire 18 has a large diameter and a certain length, thus having a certain inductance, and its dI / dt is relatively large when a large current is turned off for a short time. Therefore, the voltage drop in this portion is sufficient to affect the drive voltage of the die. This voltage drop in the source wire 18 is included in the drive circuit of the second die Die 2. Therefore, there is a natural voltage difference between the drive voltages of the first die Die 1 and the second die Die 2, which causes the turn-on and turn-off of the first die Die 1 and the second die Die 2 to be somewhat inconsistent. Specifically, the turn-off energy or turn-off current of the second die Die 2 is significantly greater than that of the first die Die 1. During short-circuit testing, because the second die (Die 2) turns off more slowly than the first die (Die 1), the second die (Die 2) may be more prone to failure than the first die (Die 1). For example, the second die (Die 2) may burn out in an actual short-circuit test.

[0046] Figure 2 is a plan layout showing a semiconductor package 1b according to a second comparative example.

[0047] Referring to Figure 2 , the semiconductor package 1b can be substantially the same configuration as the semiconductor package 1a shown in Figure 1 , except that the Kelvin electrode KE of the second die Die2 is connected to the Kelvin electrode KE at the upper right corner of the first die Die1 by a bonding wire 14.

[0048] In comparison with the semiconductor package 1a shown in Figure 1 , the semiconductor package 1b according to the second comparative example does not show a significant improvement in switching consistency. This can be because the bonding wire 14 for connecting the Kelvin electrode KE of the second die Die2 is connected in parallel with a portion of the source lead 18 in the main circuit and then to the Kelvin pin K through the Kelvin electrode KE of the first die Die1, and thus a large voltage drop still exists in the drive circuit of the second die Die2 compared with the drive circuit of the first die Die1. In addition, in the semiconductor package 1b according to the second comparative example, the breakage of the dies can occur due to the need for twice bonding the bonding wire on the Kelvin electrodes KE of the two dies.

[0049] Figure 3 is a plan layout showing a semiconductor package 1c according to an embodiment of the present disclosure. Figure 4 is a simulation graph showing the current and power as a function of time for the semiconductor package 1a and Figure 1 the semiconductor package 1c for comparison. Figure 3 Referring to

[0050] , the semiconductor package 1c can be similar to the configuration of the semiconductor package 1a shown in Figure 3 , except that it further includes a bonding wire 14 connecting the Kelvin electrode KE of the second die Die2 to the Kelvin pin K. This bonding wire 14 bypasses the first die Die1 connection to the Kelvin pin. That is, this bonding wire 14 does not pass through the first die Die1 or any portion connected to the first die Die1. Figure 1 In the upper portion of

[0051] , I(Die1) denotes the current of the first die Die1 in the semiconductor package 1a of Figure 4 , I(Die2) denotes the current of the second die Die2 in the semiconductor package 1a of Figure 1 ; I(Die1)_K denotes the current of the first die Die1 in the semiconductor package 1c of Figure 1 , I(Die2)_K denotes the current of the second die Die2 in the semiconductor package 1c of Figure 3 Figure 3 ​The current of the second die (Die2) in the semiconductor package 1c. Figure 4 In the lower part, P(Die1) represents the... Figure 1 The power of the first die Die1 in the semiconductor package 1a, P(Die2) represents the power of the first die Die1 in the semiconductor package 1a. Figure 1 The power of the second die Die2 in semiconductor package 1a; P(Die1)_K represents the power of the second die Die2 in semiconductor package 1a. Figure 3 The power of the first die Die1 in the semiconductor package 1c, P(Die2)_K represents the power of the first die Die1 in the semiconductor package 1c. Figure 3 The power of the second die (Die2) in the semiconductor package 1c.

[0052] Reference Figure 4 As can be seen, during the shutdown process, with Figure 1 Compared to semiconductor package 1a, Figure 3 The turn-off current or turn-off energy of the first die Die1 and the second die Die2 of the semiconductor package 1c still have a large difference, and the improvement in switching consistency is not obvious.

[0053] Specifically, for Figure 1 The semiconductor package 1a (which has no bonding leads 14) has a turn-off energy ratio of 1:1.9 for the first die Die 1 and the second die Die 2; Figure 3 The semiconductor package 1c (which has bonding leads 14) has a turn-off energy ratio of 1:1.8 for the first die Die1 and the second die Die2.

[0054] Furthermore, in this embodiment, the bonding lead 14 of the Kelvin electrode KE for the second die Die 2 may come into contact with the bonding lead 11 of the gate electrode GE for the first die Die 1 and the bonding lead 12 of the gate electrode GE for the second die Die 2, thereby causing a short circuit. This would reduce the reliability of the semiconductor package 1c.

[0055] Figure 5 This illustrates a planar layout of a semiconductor package 2a according to another embodiment of the present disclosure. Figure 6 Parts (a) and (b) are respectively Figure 5 Cross-sectional and plan views of the multilayer conductive connection structure 20 included in the semiconductor package 2a.

[0056] Reference Figure 5 and Figure 6 Semiconductor package 2a can be similar to Figure 3semiconductor package 1c, except that the semiconductor package 2a can further include a multilayer conductive connection structure 20 mounted on the package substrate Subl. The multilayer conductive connection structure 20 can have a bottom layer conductive pattern 21, a first insulating substrate Sub2, an intermediate layer conductive pattern 22, a second insulating substrate Sub3, and a top layer conductive pattern 23 stacked in order from the bottom to the top.

[0057] The second insulating substrate Sub3 can have a width greater than that of the top layer conductive pattern 23 to support the top layer conductive pattern 23. The second insulating substrate Sub3 can have a width narrower than the intermediate layer conductive pattern 22 so that a portion of the intermediate layer conductive pattern 22 can be exposed by the second insulating substrate Sub3. The gate electrodes GE of the first and second dies Die 1 and Die 2, respectively, can be connected to the top layer conductive pattern 23 through bonding wires 11 and 12, respectively, and the top layer conductive pattern 23 is further connected to the gate pin G through a bonding wire 13. The Kelvin electrodes KE of the first and second dies Die 1 and Die 2, respectively, are connected to the portion of the intermediate layer conductive pattern 22 exposed by the second insulating substrate Sub3 through bonding wires 14 and 15, respectively, and the portion of the intermediate layer conductive pattern 22 exposed by the second insulating substrate Sub3 is further connected to the Kelvin pin K through a bonding wire 16. Thus, in the semiconductor package 2a illustrated, Figure 5 In the semiconductor package 2a illustrated, the Kelvin electrode KE of the second die Die 2 can be electrically connected to the Kelvin pin K via the multilayer conductive connection structure 20, specifically, via the bonding wire 15, the intermediate layer conductive pattern 22 of the multilayer conductive connection structure 20, and the bonding wire 16. Here, the intermediate layer conductive pattern 22 can also be referred to as a first conductive pattern, and the top layer conductive pattern 23 can also be referred to as a second conductive pattern.

[0058] The top layer conductive pattern 23 can extend in the first direction. The intermediate layer conductive pattern 22 can include a main body portion M extending in the first direction and overlapping the top layer conductive pattern 23, and a plurality of branch portions B protruding from the main body portion M. The plurality of branch portions B can be formed at positions corresponding to the Kelvin electrodes KE of the first and second dies Die 1 and Die 2, respectively, and an end portion of the main body portion M adjacent to the gate pin G, and a portion of each branch portion B can be exposed by the second insulating substrate Sub3.

[0059] The bottom layer conductive pattern 21 can be directly bonded to a substrate conductive pattern on the package substrate Subl to fix the multilayer conductive connection structure 20 to the package substrate Subl. In some cases, the bottom layer conductive pattern 21 can be omitted.

[0060] According to some embodiments, the multilayer conductive connection structure 20 can be formed by attaching two direct copper-clad ceramic (DBC) substrates with different widths, wherein the DBC substrate with a larger width is located at the bottom and the DBC substrate with a smaller width is located at the top. Each DBC substrate may include a ceramic substrate in the middle and copper layers on both sides of the ceramic substrate. The two DBC substrates can be bonded together by solder P, for example by silver sintering. Figure 6 As shown in part (a), the intermediate conductive pattern 22 can be formed from two adjacent copper layers of two DBC substrates and solder P located therebetween. According to some other embodiments, the intermediate conductive pattern 22 of the multilayer conductive connection structure 20 can be formed as a single layer.

[0061] The foregoing description of the multilayer conductive connection structure 20 suggests that it can be formed by attaching two direct copper-clad ceramic (DBC) substrates with different widths, but this disclosure is not limited thereto. The multilayer conductive connection structure 20 can be formed from a multilayer ceramic substrate or a multilayer polymer substrate with conductive patterns formed at different levels. Therefore, the bottom conductive pattern 21, the middle conductive pattern 22, and the top conductive pattern 23 can be formed from conductive materials other than copper, such as other metals or alloys. Furthermore, the processes for forming multilayer ceramic substrates or multilayer polymer substrates are well known in the art.

[0062] Despite Figure 5 The diagram shows that the plurality of branch portions B protrude from the body portion M toward the first die Die1 and the second die Die2, but at least one of the branch portions B to which the connecting leads 14 and 15 are connected may also protrude from the body portion M away from the first die Die1 and the second die Die2.

[0063] Reference Figure 5 and Figure 6 As can be seen, the direction of the current in the top conductive pattern 23 and the middle conductive pattern 22 can be opposite, which helps to reduce the influence of inductance and thus further improve the current balance of the first die Die1 and the second die Die2.

[0064] Figure 7 It is used for comparison Figure 1 Semiconductor package 1a and Figure 5 Simulated graphs of current versus time and power versus time for semiconductor package 2a.

[0065] exist Figure 7 In the upper part, I(Die1) indicates that in Figure 1 The current of the first die Die1 in the semiconductor package 1a, I(Die2) represents the current in Figure 1The current of the second die Die2 in semiconductor package 1a; I(Die1)_idea represents the current in Figure 5 The current of the first die Die1 in the semiconductor package 2a, I(Die2)_idea represents the current in Figure 5 The current of the second die Die2 in the semiconductor package 2a. Figure 7 In the lower part, P(Die1) represents the... Figure 1 The power of the first die Die1 in the semiconductor package 1a, P(Die2) represents the power of the first die Die1 in the semiconductor package 1a. Figure 1 The power of the second die Die2 in semiconductor package 1a; P(Die1)_idea represents the power of the second die Die2 in semiconductor package 1a. Figure 5 The power of the first die Die1 in semiconductor package 2a, P(Die2)_idea represents the power of the first die Die1 in semiconductor package 2a. Figure 5 The power of the second die Die2 in the semiconductor package 2a.

[0066] from Figure 7 It can be seen that during the shutdown process, for Figure 5 The semiconductor package 2a (which has a multilayer conductive connection structure for connecting the first die Die 1 and the second die Die 2) further improves the consistency of the currents of the first die Die 1 and the second die Die 2, and the turn-off energies of the first die Die 1 and the second die Die 2 are also closer. Specifically, without the multilayer conductive connection structure 20, the turn-off energy ratio of the first die Die 1 and the second die Die 2 is 1:1.9; with the multilayer conductive connection structure 20, the turn-off energy ratio of the first die Die 1 and the second die Die 2 is 1:1.4. Therefore, the first die Die 1 and the second die Die 2 have significantly improved switching consistency.

[0067] In addition, Figure 5 In the semiconductor package 2a, the bonding leads 11, 12, 13, 14, 15 and 16 do not overlap each other in a direction perpendicular to the surface of the package substrate Sub1, thereby preventing short circuits between them, and thus the semiconductor package 2a can have improved reliability.

[0068] In addition, according to Figure 5 The semiconductor package 2a of the illustrated embodiment is easy to manufacture and has a low manufacturing cost. For example, when the multilayer conductive connection structure 20 is formed by attaching DBC substrates of different widths, the manufacturing cost can be kept low because DBCs have low cost. Furthermore, since the DBC substrate itself has good heat dissipation characteristics, it is not necessary to provide additional heat dissipation components.

[0069] Figure 8is a plan layout showing a semiconductor package 2b according to another embodiment of the present disclosure. Figure 9 is Figure 8 a cross-sectional view of a multilayer conductive connection structure 20' of the semiconductor package 2b.

[0070] With reference to Figure 8 , the semiconductor package 2b can be similar to Figure 5 the semiconductor package 2a, except that a package substrate Sub1' of the semiconductor package 2b forms a multilayer structure together with the multilayer conductive connection structure 20'.

[0071] The multilayer structure formed by the package substrate Sub1' together with the multilayer conductive connection structure 20' can have a bottom layer conductive pattern 21, the package substrate Sub1', an intermediate layer conductive pattern 22', a second insulating substrate Sub3, and a top layer conductive pattern 23 stacked in this order. The intermediate layer conductive pattern 22' can have a first portion P1 overlapping the first and second dies Die1 and Die2 and a second portion P2 overlapping the top layer conductive pattern 23 and spaced apart from the first portion P1. The second insulating substrate Sub3 can have a width narrower than the second portion P2 of the intermediate layer conductive pattern 22', so that a portion of the second portion P2 of the intermediate layer conductive pattern 22' is exposed by the second insulating substrate Sub3. The Kelvin electrodes KE of the first and second dies Die1 and Die2 can be connected to the exposed portion of the second portion P2 of the intermediate layer conductive pattern 22' by bonding wires 14 and 15, respectively. The exposed portion of the second portion P2 of the intermediate layer conductive pattern 22' can be connected to the Kelvin pin K by a bonding wire 16. The gate electrodes GE of the first and second dies Die1 and Die2 can be connected to the top layer conductive pattern 23 by bonding wires 11 and 12, respectively, which in turn are connected to the gate pin G by a bonding wire 13. The first portion P1 of the intermediate layer conductive pattern 22' is connected to the drain pin D.

[0072] The top layer conductive pattern 23 can extend in a first direction, and the second portion P2 of the intermediate layer conductive pattern 22' can include a main portion extending in the first direction and overlapping the top layer conductive pattern 23 and a plurality of branch portions protruding from the main portion. The plurality of branch portions are formed at positions corresponding to the Kelvin electrodes KE of the first and second dies Die1 and Die2 and an end portion of the main portion adjacent to the gate pin G, and a portion of each branch portion is exposed by the second insulating substrate Sub3.

[0073] According to some embodiments, the multi-layer structure formed by the package substrate Sub1' together with the multi-layer conductive connection structure 20' can be formed by attaching two direct copper bonded (DBC) substrates with different widths, where the DBC substrate with the larger width is at the lower part and the DBC substrate with the smaller width is at the upper part. Each DBC substrate can include a ceramic substrate in the middle and copper layers on both sides of the ceramic substrate. The two DBC substrates can be joined together by solder P, for example, by silver sintering (Ag sintering). At this time, the portion of the second portion P2 of the middle layer conductive pattern 22' that overlaps with the top layer conductive pattern 23 can include multiple layers, for example, include the copper layers of the two DBC substrates adjacent to each other and the solder P in between, as shown in Figure 9 .

[0074] According to other embodiments, when the multi-layer structure formed by the package substrate Sub1' together with the multi-layer conductive connection structure 20' is formed by other methods, the first portion P1 and the second portion P2 of the middle layer conductive pattern 22' can be on the same plane, and the second portion P2 can be formed as a single layer without including multiple layers.

[0075] Figure 8 The semiconductor package 2b can achieve similar effects as the semiconductor package 2a shown in Figure 5 . In addition, when the package substrate Sub1' is formed by itself by a DBC substrate and the first die Die1 and the second die Die2 are mounted on the package substrate Sub1', a better heat dissipation effect can be achieved, for example, a better system-level heat dissipation effect can be achieved in certain application scenarios.

[0076] Figure 10 is a planar layout showing a semiconductor package 2c according to another embodiment of the present disclosure.

[0077] Referring to Figure 10 , the semiconductor package 2c can be similar to the semiconductor package 2a of Figure 5 , except that the Kelvin electrodes KE of the first die Die1 and the second die Die2 are connected to the top layer conductive pattern 23 of the multi-layer conductive connection structure 20'' by bonding wires and the gate electrodes GE of the first die Die1 and the second die Die2 are connected to the exposed portions of the middle layer conductive pattern 22 of the multi-layer conductive connection structure 20'' by bonding wires.

[0078] Specifically, the gate electrodes GE of the first die Die1 and the second die Die2 can be connected to exposed portions of the intermediate layer conductive pattern 22 through the bonding wires 11 and 12, respectively, and the exposed portions of the intermediate layer conductive pattern 22 are connected to the gate pin G through the bonding wire 13. The Kelvin electrodes KE of the first die Die1 and the second die Die2 can be connected to the top layer conductive pattern 23 through the bonding wire 14 and the bonding wire 15, respectively, and the top layer conductive pattern 23 is connected to the Kelvin pin K through the bonding wire 16.

[0079] The top layer conductive pattern 23 can extend in the first direction. The intermediate layer conductive pattern 22 can include a main portion extending in the first direction and overlapping the top layer conductive pattern 23, and a plurality of branch portions protruding from the main portion, the plurality of branch portions being formed at positions corresponding to the gate electrodes GE of the first die Die1 and the second die Die2 and an end portion of the main portion adjacent to the Kelvin pin G, respectively, and a portion of each branch portion B is exposed by the second insulating substrate Sub3. Although it is shown in Figure 10 Figure 10 The top layer conductive pattern 23 can extend in the first direction. The intermediate layer conductive pattern 22 can include a main portion extending in the first direction and overlapping the top layer conductive pattern 23, and a plurality of branch portions protruding from the main portion, the plurality of branch portions being formed at positions corresponding to the gate electrodes GE of the first die Die1 and the second die Die2 and an end portion of the main portion adjacent to the Kelvin pin G, respectively, and a portion of each branch portion B is exposed by the second insulating substrate Sub3. Although it is shown in

[0080] Figure 10 The semiconductor package 2c can obtain similar effects to the semiconductor package 2a shown in Figure 5 Figure 5 The semiconductor package 2c can obtain similar effects to the semiconductor package 2a shown in

[0081] In addition, Figure 10 The configuration of the multilayer conductive connection structure 20'' shown in Figure 8 Figure 8

[0082] Figure 11 is a schematic view showing a solid state circuit breaker including a semiconductor package according to another embodiment of the present disclosure.

[0083] The solid state circuit breaker 100 according to the embodiment of the present disclosure can include a control unit 40, a sampling unit 50, and a solid state switching unit 60. The solid state switching unit 60 can include the semiconductor package according to the above-described embodiments of the present disclosure.

[0084] At the end of the detailed description, those of ordinary skill in the art will understand that many changes and modifications to the various example embodiments of the present disclosure can be made without departing from the principles of the present disclosure. Therefore, the described example embodiments of the present disclosure are used only in a generic and descriptive sense, and not for purposes of limitation. The example embodiments are not necessarily mutually exclusive from each other. For example, some example embodiments can include one or more features described with reference to or uniquely described with respect to one or more of the drawings, and can also include one or more other features described with reference to or uniquely described with respect to one or more other drawings. The present disclosure shows only two dies disposed in one semiconductor package in the drawings, but the present disclosure is not limited thereto, and three or more dies can be disposed in one semiconductor package in a similar manner, arranged in a row or arranged in a matrix. For example, for the semiconductor package shown in Figure 5 The intermediate layer conductive pattern can have other shapes (e.g., a rectangular shape) as long as the intermediate layer conductive pattern has a portion exposed by the top layer conductive pattern and the second insulating substrate for wire bonding, for the semiconductor package shown in Figure 5 , Figure 8 , Figure 10 The multilayer conductive connection structure can be formed by other multilayer ceramic substrates or multilayer polymer substrates other than DBC, for the semiconductor package shown in Figure 5 , Figure 8 , Figure 10 The semiconductor package in the drawings shows only the gate electrode and the Kelvin electrode electrically connected to the multilayer conductive connection structure in a manner of wire bonding, but the present disclosure is not limited thereto, and other manners (e.g., a manner of soldering via a conductive rod or a conductive strip) can be used for the electrical connection.

Claims

1. A semiconductor package, comprising: The packaging substrate is provided with multiple pins for external connection, the multiple pins including drain pin, source pin, Kelvin pin and gate pin; The first die is arranged adjacent to a first side of the packaging substrate and has a source electrode, a drain electrode, a Kelvin electrode and a gate electrode; The second die is spaced apart from the first die in a first direction such that the first die is located between the first side of the packaging substrate and the second die, and has a source electrode, a drain electrode, a Kelvin electrode and a gate electrode. as well as A multilayer conductive connection structure is provided on the packaging substrate, comprising a first conductive pattern and a second conductive pattern above and overlapping a portion of the first conductive pattern. The first die and the second die are connected in parallel. The gate electrode of the first die and the gate electrode of the second die are electrically connected to the gate pin via one of the first conductive pattern and the second conductive pattern. The Kelvin electrode of the first die is electrically connected to the Kelvin pin, and the Kelvin electrode of the second die is electrically connected to the Kelvin pin via another of the first conductive pattern and the second conductive pattern.

2. The semiconductor package of claim 1, wherein the Kelvin electrode of the first die is also electrically connected to the Kelvin pin via the other of the first conductive pattern and the second conductive pattern.

3. The semiconductor package according to claim 1, wherein the source electrodes and drain electrodes of both the first die and the second die, and the source pins and drain pins of the package substrate are located in the main circuit. The Kelvin and gate electrodes of both the first and second dies, as well as the Kelvin and gate pins of the package substrate, are located in a drive circuit, where the current is less than that in the main circuit. Wherein, the Kelvin electrode of the first die and the Kelvin electrode of the second die are not located in the main circuit, and The direction of the current flowing through the first conductive pattern is configured to be opposite to the direction of the current flowing through the second conductive pattern.

4. The semiconductor package of claim 1, wherein the gate electrode of the first die and the gate electrode of the second die are electrically connected to the gate pin via the second conductive pattern. The gate electrode of the first die and the gate electrode of the second die are respectively connected to the second conductive pattern via a first bonding lead and a second bonding lead, and the second conductive pattern is then connected to the gate pin via a third bonding lead. The Kelvin electrodes of the first die and the second die are connected to the first conductive pattern via a fourth bonding lead and a fifth bonding lead, respectively. The first conductive pattern is then connected to the Kelvin pin via a sixth bonding lead. The Kelvin electrode of the first die is directly connected to the Kelvin pin via a fourth bonding lead, the Kelvin electrode of the second die is connected to the first conductive pattern via a fifth bonding lead, and the first conductive pattern is then connected to the Kelvin pin via a sixth bonding lead.

5. The semiconductor package of claim 1, wherein the gate electrode of the first die and the gate electrode of the second die are electrically connected to the gate pin via the first conductive pattern. The gate electrode of the first die and the gate electrode of the second die are respectively connected to the first conductive pattern via a first bonding lead and a second bonding lead, and the first conductive pattern is then connected to the gate pin via a third bonding lead. The Kelvin electrodes of the first die and the second die are connected to the second conductive pattern via a fourth bonding lead and a fifth bonding lead, respectively. The second conductive pattern is then connected to the Kelvin pin via a sixth bonding lead. The Kelvin electrode of the first die is directly connected to the Kelvin pin via a fourth bonding lead, the Kelvin electrode of the second die is connected to the second conductive pattern via a fifth bonding lead, and the second conductive pattern is then connected to the Kelvin pin via a sixth bonding lead.

6. The semiconductor package according to claim 4 or 5, wherein the first bonding lead to the sixth bonding lead does not overlap with each other in a vertical direction perpendicular to the surface of the package substrate.

7. The semiconductor package of claim 1, wherein the multilayer conductive interconnect structure further comprises a second insulating substrate formed between the first conductive pattern and the second conductive pattern, the first conductive pattern having a wider width than the second conductive pattern and the second insulating substrate such that the first conductive pattern has a portion exposed by the second conductive pattern and the second insulating substrate for wire bonding.

8. The semiconductor package of claim 7, wherein the second conductive pattern extends in the first direction, the first conductive pattern including a body portion extending in the first direction and overlapping with the second conductive pattern and a plurality of branch portions protruding from the body portion, a portion of each of the plurality of branch portions being exposed by the second conductive pattern and the second insulating substrate.

9. The semiconductor package of claim 1, wherein the package substrate has a substrate conductive pattern formed on its surface, the drain electrode on the back side of the first die and the drain electrode on the back side of the second die are bonded to the substrate conductive pattern, and the substrate conductive pattern is connected to the drain pin.

10. The semiconductor package of claim 9, wherein the substrate conductive pattern is below the first conductive pattern such that the first insulating substrate is between them, or is on the same plane as the first conductive pattern and spaced apart from the first conductive pattern.

11. The semiconductor package of claim 1, wherein the multilayer conductive connection structure is formed by a multilayer ceramic substrate or a multilayer polymer substrate, or The multilayer structure, which is composed of the multilayer conductive connection structure and the packaging substrate, is formed by a multilayer ceramic substrate or a multilayer polymer substrate.

12. The semiconductor package of claim 11, wherein the multilayer conductive interconnect structure is formed by attaching two or more direct copper-clad ceramic (DBC) substrates of different widths, or The multilayer structure, which is composed of the multilayer conductive connection structure and the packaging substrate, is formed by attaching two or more direct copper-clad ceramic (DBC) substrates with different widths.

13. The semiconductor package of claim 1, wherein the source electrode of the first die and the source electrode of the second die are connected to the source pin via at least one source wire extending in the first direction. The drain pin, the source pin, the Kelvin pin, and the gate pin are arranged sequentially along the first side of the package substrate.

14. The semiconductor package of claim 1, wherein the first die and the second die are metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) based on Si, SiC or GaN, or high electron mobility transistors (HEMTs) based on GaN.

15. A solid-state circuit breaker comprising a semiconductor package according to any one of claims 1-14.

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