Well potential abnormality detection circuit and well potential comprising same
By designing a trap potential anomaly detection circuit and utilizing a detection device composed of a MOS transistor and an XOR gate, the timeliness problem of trap potential anomaly detection is solved, and rapid detection and protection against trap potential anomalies are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-03-31
AI Technical Summary
Existing technologies cannot detect and prevent abnormal trap potentials in a timely manner, which can lead to damage to latch-up and ESD devices, and lack immediate protective measures.
Design a trap potential abnormality detection circuit. Utilize a detection device composed of a MOS transistor and an XOR gate. The circuit determines trap potential abnormalities by detecting changes in the drain voltage of the detection device and outputs an abnormality signal to protect the circuit.
It enables rapid detection of abnormal trap potential, outputs an abnormal signal, and takes timely protective measures to prevent damage to latch-up and ESD devices.
Smart Images
Figure CN121762908A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of detection circuit technology for abnormal well potential in integrated circuits, and specifically to a detection circuit for abnormal well potential and a well potential including the detection circuit. Background Technology
[0002] In standard CMOS integrated circuits, devices are fabricated on a substrate, typically a P-type substrate. P-type and N-type wells are then fabricated on this substrate. NMOS devices are fabricated within P-type wells, and PMOS devices within N-type wells. To ensure proper operation of CMOS devices, the PN junction formed by the device's source / drain terminals and its own well needs to be reverse-biased. However, in practical circuit applications, the PN junction may be forward-biased in some cases, such as latch-up in output interface devices and ESD devices. In output interface devices, overshoot and undershoot at the port can cause the internal PN junction to become forward-biased, leading to positive feedback in the parasitic PNPN structure and triggering latch-up. In ESD devices, the PN junction breaks down under electrostatic stress, and current flows into the well. The well's resistance raises or lowers the well potential, ultimately causing the parasitic PNP or NPN transistors to conduct and release electrostatic energy. Latch-up is something that needs to be prevented in the design. ESD device design requires the parasitic transistors to conduct. Both of these events can cause abnormal well potentials. Detecting these abnormal well potentials helps to promptly identify latch-up areas or to shut down the power supply in time to prevent latch-up events from burning out the device. If an ESD device can promptly obtain information that its parasitic components are conducting, it can promptly shut down the trigger circuit that enables the parasitic components to conduct, thereby protecting the trigger circuit.
[0003] Based on the above description, conventional latch-up identification involves locating the device after an abnormal increase in power supply current and burning it out, and then taking remedial measures such as adding a protection ring on the layout. ESD devices are conventionally shut down using a preset RC time constant. The disadvantage is that the operating status of the ESD device is not detected in real time, so corresponding measures need to be taken to deal with changes in manufacturing process or abnormal opening under non-ESD events. Summary of the Invention
[0004] This application provides a trap potential anomaly detection circuit and a trap potential including the detection circuit, which can effectively solve the above problems.
[0005] The specific technical solution of this embodiment is as follows: On one hand, embodiments of this application provide a trap potential abnormality detection circuit. The trap potential includes a first circuit, an XOR gate, and a resistor. The first circuit includes multiple inverters connected in series. The trap potential abnormality detection circuit includes a detection device, which includes a MOS transistor. The gate terminal of the MOS transistor is connected to the output terminal of the first circuit and the first input terminal of the XOR gate. The drain terminal of the MOS transistor is connected to the input terminal of the first circuit, the resistor, and the second input terminal of the XOR gate.
[0006] In some embodiments, the MOS transistor is an NMOS transistor, and both the source and substrate of the NMOS transistor are grounded.
[0007] In some embodiments, the MOS transistor is a PMOS transistor, and the source and substrate terminals of the PMOS transistor are connected to a power supply.
[0008] On the other hand, embodiments of this application provide a trap potential, including: An XOR gate includes a first input, a second input, and an output. The first circuit includes multiple inverters connected in series, and the output of the first circuit is connected to the first input of the XOR gate. The resistor has its first end connected to the input terminal of the first circuit and the second input terminal of the XOR gate, respectively. An abnormal well potential detection circuit includes a detection device, which includes a MOSFET. The gate of the MOSFET is connected to the output of a first circuit and the first input of an XOR gate. The drain of the MOSFET is connected to the input of the first circuit, the first end of a resistor, and the second input of the XOR gate.
[0009] In some embodiments, the first circuit includes an even number of inverters connected end-to-end.
[0010] In some embodiments, the first circuit includes four inverters connected end-to-end.
[0011] In some embodiments, the MOS transistor is a PMOS transistor, with the source and substrate terminals of the PMOS transistor connected to a power supply, and the second terminal of the resistor grounded.
[0012] In some embodiments, the MOS transistor is an NMOS transistor, and both the source and substrate of the NMOS transistor are grounded, with the second end of the resistor connected to the power supply.
[0013] Compared with the prior art, the embodiments of this application have the following beneficial effects: The sink potential abnormality detection circuit and the sink potential including the detection circuit provided in this application embodiment can directly detect whether the sink potential is abnormal through the detection device. If abnormal, the gate of the MOS device cannot control the device to turn on and off, the parasitic device will conduct, causing the drain voltage of the detection device to remain unchanged. Finally, the abnormality is judged by the output of the XOR gate. The present invention has a simple structure, can quickly detect the region of abnormal sink potential, output an abnormal signal, and provide a signal for subsequent protection measures. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 This is a circuit diagram for detecting abnormal NMOS well potential. Figure 2 This is a circuit diagram for detecting abnormal PMOS well potential. Figure 3 This is a circuit diagram of a specific embodiment of the present invention.
[0016] in: 11. Detection device; 12. Resistor; 13. First inverter; 14. Second inverter; 15. Third inverter; 16. Fourth inverter; 17. XOR gate. Detailed Implementation
[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0019] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0020] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0021] On one hand, embodiments of this application provide a trap potential abnormality detection circuit. The detection circuit is used to detect whether the trap potential is abnormal. The trap potential to be detected includes a first circuit, an XOR gate 17 and a resistor 12. The first circuit includes multiple inverters connected in series.
[0022] The trap potential abnormality detection circuit includes a detection device 11, which includes a MOSFET. The gate of the MOSFET is connected to the output of the first circuit and the first input of the XOR gate 17, and the drain of the MOSFET is connected to the input of the first circuit, the resistor 12, and the second input of the XOR gate 17.
[0023] In the first circuit, multiple inverters are connected sequentially, with the input terminal of the inverter being the tail terminal and the output terminal being the head terminal. That is, the output terminal of the previous inverter is connected to the input terminal of the next inverter.
[0024] A MOSFET can be either an NMOS transistor or a PMOS transistor.
[0025] The output terminal of the first circuit refers to the output terminal of the last inverter among multiple inverters connected end to end in sequence; the input terminal of the first circuit refers to the input terminal of the first inverter among multiple inverters connected end to end in sequence.
[0026] In some embodiments, the MOS transistor is an NMOS transistor, and the source and substrate terminals of the NMOS transistor are grounded.
[0027] In some other embodiments, the MOS transistor is a PMOS transistor, and the source and substrate terminals of the PMOS transistor are connected to a power supply.
[0028] On the other hand, embodiments of this application provide a well potential including an anomaly detection circuit, comprising an XOR gate 17, a first circuit, a resistor 12, and a well potential anomaly detection circuit according to any of the above embodiments. The XOR gate 17 includes a first input terminal, a second input terminal, and an output terminal; the first circuit includes multiple inverters connected in series, and the output terminal of the first circuit is connected to the first input terminal of the XOR gate; the first terminal of the resistor 12 is connected to the input terminal of the first circuit and the second input terminal of the XOR gate; the well potential anomaly detection circuit includes a detection device 11, which includes a MOSFET. The gate terminal of the MOSFET is connected to the output terminal of the first circuit and the first input terminal of the XOR gate 17, and the drain terminal of the MOSFET is connected to the input terminal of the first circuit, the first terminal of the resistor 12, and the second input terminal of the XOR gate 17.
[0029] The output of XOR gate 17 is the output of the anomaly detection.
[0030] In some embodiments, the first circuit includes an even number of inverters connected end-to-end. For example, with Figure 1 and Figure 2 As shown, the multiple inverters include a first inverter 13, a second inverter 14, a third inverter 15, and a fourth inverter 16. The output terminal of the first inverter 13 is connected to the input terminal of the second inverter 14, and the output terminal of the third inverter 15 is connected to the input terminal of the fourth inverter 16. An even number of cascaded inverters may also be included between the second inverter 14 and the third inverter 15.
[0031] In some embodiments, the first circuit includes four inverters connected end-to-end.
[0032] In some embodiments, the MOS transistor is a PMOS transistor, with the source and substrate terminals of the PMOS transistor connected to a power supply, and the second terminal of resistor 12 grounded.
[0033] In some embodiments, the MOS transistor is an NMOS transistor, and both the source and substrate of the NMOS transistor are grounded, with the second end of resistor 12 connected to the power supply.
[0034] Figure 1The NMOS detection device 11 shown is placed inside the well potential to be detected. The NMOS detection device 11 includes an NMOS transistor. The source and substrate terminals of the NMOS transistor are grounded. The gate terminal is connected to the output of inverter 16, and the drain terminal is connected to the input of inverter 13 and one end of resistor 12. The other end of resistor 12 is connected to the power supply. The output of inverter 13 is connected to inverter 14. The output of inverter 14 can be connected to an even number of cascaded inverters or directly to the input of inverter 15. The output of inverter 15 is connected to the input of inverter 16. The output of inverter 16 is connected to one input of XOR gate 17. The other input of XOR gate 17 is connected to the drain of NMOS detection device 11. The output of XOR gate 17 is the output terminal for anomaly detection.
[0035] Its working principle is as follows: The NMOS sensor 11 and resistor 12 form a common-source amplifier, the output of which is connected to the input of an even number of inverters connected in series. Figure 3 Given four inverters 13-16 connected in series, with the output of inverter 16 connected to the input of a common-source amplifier formed by NMOS sensor 11 and resistor 12, and the gate of NMOS sensor 11, this structure forms a five-stage ring oscillator. The small-signal voltage gain of each stage is A0, and the transfer function H(s) of each stage is:
[0036] Where: ω0 is the 3dB bandwidth of each stage of the circuit. It is a complex frequency variable.
[0037] The total loop transfer function H(s) of the ring oscillator is:
[0038] According to the "Barkhausen criterion", the oscillation frequency ω of this ring oscillator osc :
[0039] The small-signal voltage gain of each stage is A0, at the oscillation frequency ω. osc The minimum gain required is:
[0040] Considering the variations in the manufacturing process, the gain of each stage is selected to be greater than 4 times.
[0041] Inverters 13-16 are general inverters with a small-signal gain greater than 4. NMOS sensor 11 and resistor 12 form a common-source amplifier. NMOS sensor 11 is a device with a transconductance greater than 1mS, and resistor 12 is a resistor with a transconductance greater than 4KΩ.
[0042] Eventually, the ring oscillator's oscillation swing will reach the power supply voltage swing. The aforementioned ring oscillator will initially oscillate at a small-signal frequency, gradually transitioning to a large-signal frequency. This large-signal frequency is determined by the delay of each inverter. The delay of each stage is T. D The final oscillation frequency is 10T. D If it is necessary to reduce the oscillation frequency, an even number of inverters can be cascaded.
[0043] In this specific embodiment, under normal circuit oscillation, the drain and gate terminals of the NMOS detection device 11 are always inverted, and the source and gate levels are XORed by the XOR gate 17 to output a high level.
[0044] The NMOS sensing device 11 is located at the P-well position to be detected. If the well potential at this position is abnormal, causing the PN junction to be forward biased, the parasitic NPN of the NMOS sensing device 11 will be activated. At the same time, current flows from the drain of the NMOS sensing device 11 into its own well, and then from the well into the source. At this time, current always flows through resistor 12, pulling down the drain voltage of the NMOS sensing device 11. Simultaneously, the low level at the drain of the NMOS sensing device 11 passes through inverters 13-16, outputting a low level. At this time, due to the activation of the parasitic NPN, the gate of the NMOS sensing device 11 loses its control capability and cannot shut off the current. Therefore, the loop of the ring oscillator is broken, and the levels of each circuit node remain unchanged. The drain and gate of the NMOS sensing device 11 are now in phase, and the source and gate levels are XORed by XOR gate 17 to output a low level.
[0045] In a specific embodiment, the NMOS device can be equivalently replaced with a PMOS device, as the principle remains the same. Figure 1 The PMOS detection device 11 shown is placed inside the N-well potential to be detected. The source and substrate terminals of the PMOS device are connected to the power supply, the gate terminal is connected to the output of inverter 16, and the drain terminal is connected to the input of inverter 13 and one end of resistor 11. The other end of resistor 11 is grounded. The output of inverter 13 is connected to inverter 14. The output of inverter 14 can be connected to an even number of cascaded inverters or directly to the input of inverter 15. The output of inverter 15 is connected to the input of inverter 16. The output of inverter 16 is connected to one input of a two-input XOR gate 17. The other input of XOR gate 17 is connected to the drain of PMOS detection device 11. The output of XOR gate 17 is the output of the anomaly detection.
[0046] Specific applications are not limited to, for example, placing it in the same well as an ESD device to detect whether the ESD device has been electrostatically activated. Similarly, it can be placed in the same well as an input / output port device to detect whether latch-up occurs during operation.
[0047] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A trap potential anomaly detection circuit, wherein the trap potential includes a first circuit, an XOR gate, and a resistor, the first circuit including a plurality of inverters connected in series, characterized in that, The device includes a detection device, which includes a MOS transistor. The gate of the MOS transistor is connected to the output of the first circuit and the first input of the XOR gate, and the drain of the MOS transistor is connected to the input of the first circuit, the resistor, and the second input of the XOR gate.
2. The trap potential anomaly detection circuit as described in claim 1, characterized in that, The MOS transistor is an NMOS transistor, and both the source and substrate terminals of the NMOS transistor are grounded.
3. The trap potential anomaly detection circuit as described in claim 1, characterized in that, The MOS transistor is a PMOS transistor, and the source and substrate terminals of the PMOS transistor are connected to a power supply.
4. A trap potential, characterized in that, include: An XOR gate includes a first input, a second input, and an output. The first circuit includes multiple inverters connected in series, and the output of the first circuit is connected to the first input of the XOR gate. A resistor, the first end of which is connected to the input terminal of the first circuit and the second input terminal of the XOR gate; An abnormal well potential detection circuit includes a detection device, which includes a MOS transistor. The gate terminal of the MOS transistor is connected to the output terminal of the first circuit and the first input terminal of the XOR gate. The drain terminal of the MOS transistor is connected to the input terminal of the first circuit, the first terminal of the resistor, and the second input terminal of the XOR gate.
5. The trap potential as described in claim 4, characterized in that, The first circuit includes an even number of inverters connected in sequence.
6. The trap potential as described in claim 5, characterized in that, The first circuit includes four inverters connected in sequence.
7. The well potential as described in claim 4, characterized in that, The MOS transistor is a PMOS transistor, and the source and substrate terminals of the PMOS transistor are connected to a power supply, while the second terminal of the resistor is grounded.
8. The trap potential as described in claim 4, characterized in that, The MOS transistor is an NMOS transistor, and both the source and substrate terminals of the NMOS transistor are grounded. The second terminal of the resistor is connected to the power supply.