Memory circuit and control method thereof, memory and electronic equipment

Abstract

The invention provides a storage circuit and a control method thereof, a memory and electronic equipment, and relates to the technical field of storage, and a ferroelectric capacitor can be fully overturned. The memory circuit includes a first ferroelectric memory cell, a first current mirror, a first voltage generating circuit, a comparison circuit, and a first voltage terminal. The first current mirror comprises a first branch circuit and a second branch circuit, one end of the first branch circuit and one end of the second branch circuit are electrically connected to a first voltage end, and the first branch circuit and the second branch circuit have the same current. The output end of the first ferroelectric storage unit and the other end of the first branch are electrically connected to a first node, the other end of the second branch is electrically connected to the output end of the first voltage generation circuit, the input end of the comparison circuit is electrically connected to a second node, and the output end of the comparison circuit is electrically connected to the output end of the storage circuit.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage circuit and its control method, a memory, and an electronic device. Background Technology

[0002] With the rapid development of the chip industry, memory performance and storage density have gradually become important factors limiting chip performance. Ferroelectric random access memory (FeRAM), based on hafnium-based materials, is an emerging type of memory that approaches dynamic random access memory (DRAM) in terms of reliability and speed. The ferroelectric memory arrays in FeRAM can be stacked in back-end processes and possess non-volatile storage characteristics. These advantages make FeRAM a promising candidate for applications in customized DRAM and embedded non-volatile memory (NVM). The storage cells in a ferroelectric memory array consist of transistors and ferroelectric capacitors (FeCap).

[0003] In the prior art, assuming that when the information read is digital signal 1, the ferroelectric capacitor undergoes polarization reversal and reads the digital signal through the bit line (BL). This causes the potential on the bit line to rise and accumulate over time, resulting in a decrease in the potential difference between the plate line electrically connected to both ends of the ferroelectric capacitor and the bit line. Consequently, the effective ferroelectric switching voltage used to control the switching of the ferroelectric capacitor decreases, and the switching of the ferroelectric capacitor becomes slower and less complete. This phenomenon is the self-suppression phenomenon when the FeRAM reads digital signal 1. This phenomenon will affect the uniformity and reliability of the FeRAM and will also reduce the memory window (MW) of the FeRAM. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a storage circuit and its control method, a memory, and an electronic device, ensuring that the potential at the first node is always maintained at the initial voltage. This guarantees that the potential difference between the board line and the bit line does not decrease due to data reading, preventing insufficient switching of the ferroelectric capacitor. Furthermore, to enable normal data reading by the storage circuit, a second node can be added. The potential at the second node is closely related to the charge output by the first ferroelectric storage cell when reading data. Therefore, the potential at the second node can be used to determine whether the digital signal read by the storage circuit is 0 or 1.

[0005] In a first aspect, this application provides a storage circuit comprising a first ferroelectric storage cell, a first current mirror, a first voltage generating circuit, a comparator circuit, and a first voltage terminal. The first current mirror includes a first branch and a second branch, one end of the first branch and one end of the second branch being electrically connected to the first voltage terminal, and the first branch and the second branch carrying the same current. The output terminal of the first ferroelectric storage cell is electrically connected to the other end of the first branch at a first node, and the other end of the second branch is electrically connected to the output terminal of the first voltage generating circuit and the input terminal of the comparator circuit at a second node. The output terminal of the comparator circuit is electrically connected to the output terminal of the storage circuit.

[0006] During the read phase, the first ferroelectric memory cell inputs a voltage to the first node (the first bit line). If the voltage input from the first ferroelectric memory cell to the first node is positive, charge can be drawn from the first node using the first branch of the first current mirror, maintaining the voltage of the first node at the initial voltage of the pre-charging phase (before the read phase). If the voltage input from the first ferroelectric memory cell to the first node is negative, charge can be drawn from the first branch of the first current mirror, maintaining the voltage of the first node at the initial voltage of the pre-charging phase (before the read phase).

[0007] The potential on the first node (first line) remains at the initial voltage. On the one hand, the potential difference between the plate line at both ends of the first ferroelectric storage cell and the first line is stable at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the first line is always at a large value, so that the polarization reversal of the ferroelectric capacitor will not become slower or even insufficient due to the decrease in the potential difference between the plate line and the first line, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0008] Furthermore, to satisfy the working principle of the first current mirror and ensure that the current in the first branch is the same as the current in the second branch, when the first branch draws charge from the first node, since both the first and second branches are electrically connected to the first voltage terminal, the second branch also draws charge from the second node that is electrically connected to it. Similarly, when the first node draws charge from the first branch, since both the first and second branches are electrically connected to the first voltage terminal, the second node also draws charge from the second branch that is electrically connected to it.

[0009] During the reading phase, when the polarization of the ferroelectric capacitor in the first ferroelectric storage cell reverses, the first ferroelectric storage cell outputs a polarization current; when the polarization of the ferroelectric capacitor does not reverse, the first ferroelectric storage cell outputs a dielectric current. The amount of charge output when the polarization of the ferroelectric capacitor reverses is greater than the amount of charge output when the polarization of the ferroelectric capacitor does not reverse. Therefore, if the first branch draws charge from the first node, the amount of charge drawn by the first branch from the first node when the polarization of the ferroelectric capacitor reverses is greater than the amount of charge drawn by the first branch from the first node when the polarization of the ferroelectric capacitor does not reverse. Consequently, the amount of charge drawn by the second branch from the second node when the polarization of the ferroelectric capacitor reverses is greater than the amount of charge drawn by the second mass from the second node when the polarization of the ferroelectric capacitor does not reverse. If the first node draws charge from the first branch, the amount of charge drawn by the first node from the first branch when the ferroelectric capacitor undergoes polarization reversal is greater than the amount of charge drawn by the first node from the first branch when the ferroelectric capacitor does not undergo polarization reversal. Consequently, the amount of charge drawn by the second node from the second branch when the ferroelectric capacitor undergoes polarization reversal is greater than the amount of charge drawn by the second node from the second branch when the ferroelectric capacitor does not undergo polarization reversal. That is, the remaining voltage at the second node differs depending on whether the ferroelectric capacitor undergoes polarization reversal or not.

[0010] In this way, the second node inputs the remaining voltage to the comparison circuit, which can then determine whether the data read from the first ferroelectric storage unit is digital signal 0 or digital signal 1 based on the received voltage.

[0011] In some possible implementations, the first branch includes a first transistor, and the second branch includes a second transistor, with the first and second transistors being identical. The first terminal of the first transistor is electrically connected to a first node, the gate of the first transistor, and the gate of the second transistor. The second terminals of both the first and second transistors are electrically connected to a first voltage terminal, and the first terminal of the second transistor is electrically connected to a second node. During the readout phase, the first voltage terminal is used to input a first voltage to the second terminals of both the first and second transistors.

[0012] The connection method between the first transistor and the second transistor, as well as the identical structural parameters of the first transistor and the second transistor, enable the first current mirror to have the same input current and output current. Thus, when reading digital signal 0 and digital signal 1, the first branch sends the received current (polarization current or dielectric current) to the second branch. Depending on the different currents, the second branch can extract different amounts of charge from the second node, or the second node can extract different amounts of charge from the second branch.

[0013] In some possible implementations, in the first current mirror, since the current input to the first branch and the current output from the second branch are always the same, when the first current mirror is operating, in order to ensure that the first branch replicates the same polarization current or dielectric current to the second branch, the initial current flowing through the first branch should be the same as the initial current flowing through the second branch before the polarization current or dielectric current flows to the first branch. However, the current in the first branch is susceptible to the influence of the first node, and the current in the second branch is susceptible to the influence of the second node, which may cause the initial current in the first branch to be different from the initial current flowing through the second branch.

[0014] Based on this, the memory chip also includes a third transistor and a fourth transistor. The third transistor is connected in series between the first node and the first transistor, and the fourth transistor is connected in series between the second node and the second transistor. During the read phase, the third transistor is used to input a clamping voltage to the first terminal of the first transistor, and the fourth transistor is used to input a clamping voltage to the first terminal of the second transistor.

[0015] During the reading phase, both the third and fourth transistors are turned on. The second terminal of the third transistor inputs a clamping voltage to the first terminal of the first transistor, and the second terminal of the fourth transistor inputs a clamping voltage to the first terminal of the second transistor. This makes the potential of the connection node between the third and first transistors the same as the potential of the connection node between the fourth and second transistors. This ensures that, with the first and second transistors having the same resistance, the initial current flowing through the first branch is the same as the initial current flowing through the second branch.

[0016] In some possible implementations, the first voltage generation circuit includes a second voltage terminal and a storage capacitor electrically connected between the second node and the second voltage terminal. During the reading phase, the second voltage terminal is used to input a second voltage to the second node through the storage capacitor.

[0017] If the first voltage generation circuit includes a second voltage terminal, during the reading phase, the second voltage terminal is used to input a second voltage to the second node. However, due to the presence of parasitic capacitance, the voltage value received by the second node will not reach the voltage value output by the second voltage terminal. Therefore, the first voltage generation circuit can also include a storage capacitor. In this way, the first voltage generation circuit can first input the second voltage to the first electrode of the storage capacitor, and the first electrode of the storage capacitor couples the second voltage to the second electrode of the storage capacitor and the second node, thereby improving the problem that the voltage output by the second voltage terminal is largely diverted by parasitic capacitance, causing the voltage value received by the second node to not reach the voltage value output by the second voltage terminal.

[0018] In some possible implementations, the first voltage generating circuit also includes an inverter electrically connected between the second voltage terminal and the storage capacitor. Since signal transmission typically involves losses, connecting the inverter between the second voltage terminal and the storage capacitor can enhance the signal.

[0019] In some possible implementations, the storage circuitry also includes a third voltage terminal and a pre-charge circuit, the pre-charge circuit being electrically connected between the third voltage terminal and the first node.

[0020] The storage circuit also includes a board line and a first bit line (i.e., the bit line in the claims). The first ferroelectric storage cell is electrically connected between the first bit line and the board line. The first bit line, the output terminal of the first ferroelectric storage cell, and one end of the first branch are electrically connected to the first node. During the pre-charging phase, the third voltage terminal is used to charge the first bit line with an initial voltage through the pre-charging circuit, preparing for the reading phase. Furthermore, during the reading phase, by controlling the voltage on the board line, the potential difference between the board line and the first bit line can be controlled to control the first ferroelectric storage cell to read data.

[0021] In some possible implementations, the pre-charge circuit includes a first switch and a second switch. The first switch is electrically connected between the input terminal of the first branch and the output terminal of the second branch, and the second switch is electrically connected between a third voltage terminal and a second node. During the pre-charge phase, both the first and second switches are turned on, and the third voltage terminal inputs an initial voltage to the first bit line through the second and first switches.

[0022] In some possible implementations, the third voltage terminal can not only precharge the first line, but also precharge the second node via the second switch during the precharging phase. In this case, the second switch is turned on, and the third voltage terminal precharges the second node to the charging voltage via the second switch. At the same time, the first switch is turned off, so the charging voltage of the third voltage terminal does not affect the potential on the first line.

[0023] During the pre-charging phase, the third voltage terminal inputs a charging voltage to the second node; during the reading phase, the second voltage terminal inputs a second voltage to the second node. Thus, before the second node is charged by the second branch, the voltage on the second node is the sum of the charging voltage and the second voltage. This embodiment of the application inputs voltage to the second node multiple times to ensure that the voltage on the second node is sufficiently large, thereby increasing the difference between the third voltage of the second node when reading digital signal 1 and the third voltage of the second node when reading digital signal 0, and increasing the MW of the storage circuit.

[0024] Furthermore, during the read phase, both the first and second switches are open. This isolates the second node (the second node is isolated from the first node via the first switch, and from the third voltage terminal via the second switch). Therefore, the second node is not affected by the parasitic capacitance on the first bit line. The parasitic capacitance on the second node is very small and has minimal impact on the MW of the storage circuit.

[0025] In some possible implementations, during the read phase: the ferroelectric memory cell is used to input charge to the first node. A first branch is used to copy a first current from the first branch to a second branch, and maintain the potential of the first node at the initial voltage based on a first voltage and an initial voltage. The second branch is used to change the potential of the second node from a second voltage to a third voltage based on the first current, the first voltage, and the second voltage. A comparator circuit is used to receive the third voltage input to the second node and, based on the third voltage, determine whether the data read from the first ferroelectric memory cell is a digital signal 0 or 1.

[0026] Specifically, in some possible implementations, both the first and second transistors are N-type transistors, and both the initial and second voltages are greater than the first voltage, with the initial voltage being low. The first branch is used to draw charge from the first node based on the first voltage and the initial voltage, so that the potential of the first node is maintained at the initial voltage. The second branch is used to draw charge from the second node based on the first current, the first voltage, and the second voltage, so that the potential of the second node is reduced from the second voltage to the third voltage. Since both the first and second transistors are N-type transistors, and the first voltage input from the first voltage terminal to both transistors is less than the initial voltage, the charge at the first node can move towards the first branch.

[0027] When both the initial voltage and the second voltage are greater than the first voltage, and the initial voltage is at a low level, when the first ferroelectric storage cell reads data, it inputs charge to the first node. Because the initial voltage is greater than the first voltage, a potential difference exists between the first node and the first branch, causing the first branch to draw charge from the first node. Thus, while the first node receives charge from the first ferroelectric storage cell, it also has charge drawn from it by the first branch, maintaining the initial voltage at the first node. In other words, the charge input by the first ferroelectric storage cell to the first node does not accumulate at the first node.

[0028] Furthermore, according to the working principle of the first current mirror, the first branch replicates the first current flowing through the first branch to the second branch. Then, the second branch will change the potential of the second node from the second voltage to the third voltage based on the first current, the first voltage input to the first current mirror, and the second voltage of the second node.

[0029] It should be understood that the current flowing through the first branch and the second branch is the first current, the first voltage terminal simultaneously inputs the first voltage to the first branch and the second branch, and the second voltage of the second node is greater than the first voltage. If the first branch draws charge from the first node, the second branch will also draw charge from the second node, so that the potential of the second node is reduced from the second voltage to the third voltage.

[0030] During the reading phase, when the polarization of the ferroelectric capacitor in the first ferroelectric memory cell reverses, the first ferroelectric memory cell outputs a polarization current; when the polarization of the ferroelectric capacitor does not reverse, the first ferroelectric memory cell outputs a dielectric current. The amount of charge input to the first node when the polarization of the ferroelectric capacitor reverses is greater than the amount of charge input to the first node when the polarization of the ferroelectric capacitor does not reverse. Therefore, when the polarization of the ferroelectric capacitor reverses, the amount of charge drawn from the first node by the first branch is greater than the amount of charge drawn from the first node by the first branch when the polarization of the ferroelectric capacitor does not reverse.

[0031] It is known that when a ferroelectric capacitor undergoes polarization reversal, the amount of charge drawn from the first node by the first branch is greater than the amount drawn from the first node by the first branch when the ferroelectric capacitor does not undergo polarization reversal. Therefore, when a ferroelectric capacitor undergoes polarization reversal, the amount of charge drawn from the second node by the second branch is also greater than the amount drawn from the second node by the second branch when the ferroelectric capacitor does not undergo polarization reversal. That is, whether or not the ferroelectric capacitor undergoes polarization reversal, the remaining third voltage after the charge is drawn from the second node is different.

[0032] In this way, the second node inputs the remaining third voltage to the comparison circuit, which can then determine whether the data read from the first ferroelectric storage unit is digital signal 0 or digital signal 1 based on the third voltage.

[0033] In this application, due to whether or not the polarization of the ferroelectric capacitor reverses, the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage cell is different, the amount of charge input to the first node is different, the first current flowing through the first branch and the second branch is also different, the amount of charge drawn by the first branch from the first node is different, and the potential difference between the second node and the second branch is different. Therefore, when the first ferroelectric storage cell reads different data, the second branch can draw charge from the second node according to the first current, the first voltage, and the second voltage, so that the potential of the second node drops from the second voltage to the third voltage. It can be seen that the remaining potential third voltage on the second node is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage cell. Therefore, the third voltage can be input to the comparison circuit using the second node, so that the comparison circuit can determine whether the data read by the first ferroelectric storage cell is digital signal 0 or digital signal 1 based on the third voltage.

[0034] Meanwhile, whether reading digital signal 1 or digital signal 0, the charge on the first line (first node) electrically connected to the first ferroelectric memory cell is extracted by the first branch, so that the potential on the first line remains at the initial voltage. On the one hand, the potential difference between the plate line and the first line is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the first line is always at a large value, so that the polarization reversal of the ferroelectric capacitor will not become slower or even insufficient due to the decrease in the potential difference between the plate line and the first line, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the memory circuit and also increases the memory window of the ferroelectric circuit.

[0035] Furthermore, in some possible implementations, if the ferroelectric capacitor in the first ferroelectric memory cell undergoes polarization reversal when reading the digital signal 1, then the first ferroelectric memory cell will output a polarization current. This polarization current flows through the first node to the first branch, and the first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second branch will draw a first charge from the second node, and the potential of the second node will decrease significantly. When the first ferroelectric memory cell reads the digital signal 0, it will output a small amount of dielectric current. This dielectric current flows through the first node to the first branch, and the first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second branch will draw a second charge from the second node, and the potential of the second node will decrease slightly. The first charge is greater than the second charge.

[0036] In this case, the third voltage when the first ferroelectric storage cell reads digital signal 1 is less than the third voltage when the first ferroelectric storage cell reads digital signal 0.

[0037] When the first ferroelectric memory cell reads the digital signal 0, the polarization of the ferroelectric capacitor in the first ferroelectric memory cell reverses. During this process, the first ferroelectric memory cell outputs a polarization current. This current flows through the first node to the first branch, which copies the same polarization current to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second branch draws a first charge from the second node, significantly reducing the potential of the second node. When the first ferroelectric memory cell reads the digital signal 1, it outputs a small dielectric current. This current flows through the first node to the first branch, which copies the same dielectric current to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second branch draws a second charge from the second node, slightly reducing the potential of the second node. The first charge is greater than the second charge.

[0038] In this case, the third voltage when the first ferroelectric storage cell reads digital signal 1 is greater than the third voltage when the first ferroelectric storage cell reads digital signal 0.

[0039] In some other possible implementations, both the first and second transistors are P-type transistors, and both the initial and second voltages are lower than the first voltage, with the initial voltage being high. The first node is used to draw charge from the first branch based on the first voltage and the initial voltage, so that the potential of the first node remains at the initial voltage. The second node is used to draw charge from the second branch based on the first current, the first voltage, and the second voltage, so that the potential of the second node increases from the second voltage to the third voltage. Since both the first and second transistors are P-type transistors, and the first voltage input from the first voltage terminal to both transistors is greater than the initial voltage, charge in the first branch can move towards the first node.

[0040] When both the initial voltage and the second voltage are lower than the first voltage, and the initial voltage is at a high level, when the first ferroelectric memory cell reads data, it inputs charge to the first node. Because the initial voltage is lower than the first voltage, a potential difference exists between the first node and the first branch, causing the first node to draw charge from the first branch. Thus, while receiving charge from the first ferroelectric memory cell, the first node also draws charge from the first branch, maintaining its initial voltage. In other words, the charge input by the first ferroelectric memory cell to the first node does not accumulate at the first node.

[0041] Furthermore, according to the working principle of the first current mirror, the first branch replicates the first current flowing through the first branch to the second branch. Then, the second branch will change the potential of the second node from the second voltage to the third voltage based on the first current, the first voltage input to the first current mirror, and the second voltage of the second node.

[0042] It should be understood that the current flowing through the first branch and the second branch is the first current, the first voltage terminal simultaneously inputs the first voltage to the first branch and the second branch, and the second voltage of the second node is less than the first voltage. If the first node draws charge from the first branch, the second node will also draw charge from the second branch, so that the potential of the second node increases from the second voltage to the third voltage.

[0043] During the reading phase, when the polarization of the ferroelectric capacitor in the first ferroelectric memory cell reverses, the first ferroelectric memory cell outputs a polarization current; when the polarization of the ferroelectric capacitor does not reverse, the first ferroelectric memory cell outputs a dielectric current. The amount of charge input to the first node when the polarization of the ferroelectric capacitor reverses is greater than the amount of charge input to the first node when the polarization of the ferroelectric capacitor does not reverse. Therefore, the amount of charge drawn from the first branch by the first node when the polarization of the ferroelectric capacitor reverses is greater than the amount of charge drawn from the first branch by the first node when the polarization of the ferroelectric capacitor does not reverse.

[0044] It is known that when a ferroelectric capacitor undergoes polarization reversal, the amount of charge drawn from the first branch by the first node is greater than the amount drawn from the first branch by the first node when the ferroelectric capacitor does not undergo polarization reversal. Therefore, when a ferroelectric capacitor undergoes polarization reversal, the amount of charge drawn from the second branch by the second node is also greater than the amount drawn from the second branch by the second node when the ferroelectric capacitor does not undergo polarization reversal. That is, whether or not the ferroelectric capacitor undergoes polarization reversal, the third voltage after the second node draws charge is different.

[0045] In this way, the second node inputs the third voltage to the comparison circuit, which can then determine whether the data read from the first ferroelectric storage unit is a digital signal 0 or a digital signal 1 based on the third voltage.

[0046] In this application, due to whether or not the polarization of the ferroelectric capacitor reverses, the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage cell is different, the amount of charge input to the first node is different, the first current flowing through the first branch and the second branch is also different, the amount of charge drawn by the first node from the first branch is different, and the potential difference between the second node and the second branch is different. Therefore, when the first ferroelectric storage cell reads different data, the second node can draw charge from the second branch according to the first current, the first voltage, and the second voltage, so that the potential of the second node increases from the second voltage to the third voltage. It can be seen that the potential of the second node, the third voltage, is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage cell. Therefore, the third voltage can be input to the comparison circuit using the second node, so that the comparison circuit can determine whether the data read by the first ferroelectric storage cell is digital signal 0 or digital signal 1 based on the third voltage.

[0047] Meanwhile, whether reading digital signal 1 or digital signal 0, the first line (first node) electrically connected to the first ferroelectric memory cell draws charge from the first branch, keeping the potential on the first line at the initial voltage. On the one hand, the potential difference between the plate line and the first line is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the first line is always at a large value, so that the polarization reversal of the ferroelectric capacitor will not become slower or even insufficient due to the decrease in the potential difference between the plate line and the first line, thus preventing self-suppression. This improves the uniformity and reliability of the memory circuit and also increases the memory window of the ferroelectric circuit.

[0048] Furthermore, in some possible implementations, if the ferroelectric capacitor in the first ferroelectric memory cell undergoes polarization reversal when reading the digital signal 1, then the first ferroelectric memory cell will output a polarization current. This polarization current flows through the first node to the first branch, and the first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second node will draw a first charge from the second branch, and the potential of the second node will increase significantly. When the first ferroelectric memory cell reads the digital signal 0, it will output a small dielectric current. This dielectric current flows through the first node to the first branch, and the first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second node will draw a second charge from the second branch, and the potential of the second node will increase slightly. The first charge is greater than the second charge.

[0049] In this case, the third voltage when the first ferroelectric storage cell reads digital signal 1 is greater than the third voltage when the first ferroelectric storage cell reads digital signal 0.

[0050] When the first ferroelectric memory cell reads the digital signal 0, the polarization of the ferroelectric capacitor in the first ferroelectric memory cell reverses. During this process, the first ferroelectric memory cell outputs a polarization current. This current flows through the first node to the first branch, where it copies an identical polarization current to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second node draws a first charge from the second branch, causing a significant increase in its potential. When the first ferroelectric memory cell reads the digital signal 1, it outputs a small dielectric current. This current flows through the first node to the first branch, where it copies an identical dielectric current to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second node draws a second charge from the second branch, causing a slight increase in its potential. The first charge is greater than the second charge.

[0051] In this case, the third voltage when the first ferroelectric storage cell reads digital signal 1 is less than the third voltage when the first ferroelectric storage cell reads digital signal 0.

[0052] In some possible implementations, the storage circuit also includes a reference voltage terminal. During the read phase: the reference voltage terminal is used to input a reference voltage to the comparator circuit. The reference voltage value is between the third voltage when the first ferroelectric storage cell reads digital signal 0 and the third voltage when the first ferroelectric storage cell reads digital signal 1. The comparator circuit is used to determine whether the data read from the first ferroelectric storage cell is digital signal 0 or digital signal 1 based on the third voltage and the reference voltage. The following section, in conjunction with the circuit connection relationship of the comparator circuit, describes how the comparator circuit determines whether the data read from the first ferroelectric storage cell is digital signal 0 or digital signal 1 based on the reference voltage and the third voltage.

[0053] The comparator circuit includes a fourth voltage terminal, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a ground terminal; the storage circuit also includes an output terminal. During the read phase, the fourth voltage terminal is at a high level, and the ground terminal is at a low level.

[0054] The gates of the first P-type transistor and the first N-type transistor are electrically connected to the second terminal of the second P-type transistor, the first terminal of the second N-type transistor, and the reference voltage terminal. The first terminal of the first P-type transistor is electrically connected to the fourth voltage terminal. The second terminal of the first P-type transistor is electrically connected to the first terminal of the first N-type transistor and the output terminal. The second terminal of the first N-type transistor is electrically connected to the ground terminal. The gates of the second P-type transistor and the second N-type transistor are electrically connected to the second node. The first terminal of the second P-type transistor is electrically connected to the fourth voltage terminal. The second terminal of the second N-type transistor is electrically connected to the ground terminal.

[0055] For example, taking the setting that the polarization of the ferroelectric capacitor reverses when the first ferroelectric storage cell reads digital signal 1 as an example, the third voltage when reading digital signal 1 is less than the third voltage when reading digital signal 0.

[0056] When reading digital signal 1, the third voltage of the second node is low, and the second P-type transistor is turned on. The reference voltage at the reference voltage terminal is greater than the third voltage when the first ferroelectric memory cell reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell reads digital signal 0. Therefore, even though the reference voltage terminal is electrically connected to the gates of the first P-type transistor and the first N-type transistor, the conduction level of the first P-type transistor and the first N-type transistor is less than that of the second P-type transistor. The second P-type transistor can charge more quickly and transmit the high level of the fourth voltage terminal to the gate of the first N-type transistor and the reference voltage terminal, pulling the reference voltage terminal high. Further, the first N-type transistor is turned on, and the ground terminal transmits a low level to the output terminal through the first N-type transistor. The output terminal outputs a low level, confirming that the data read by the first ferroelectric memory cell is digital signal 1.

[0057] When reading digital signal 0, the third voltage of the second node B is high, and the second N-type transistor is turned on. The reference voltage at the reference voltage terminal is greater than the third voltage when the first ferroelectric memory cell reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell reads digital signal 0. Therefore, even though the reference voltage terminal is electrically connected to the gates of the first P-type transistor and the first N-type transistor, the conduction level of the first P-type transistor and the first N-type transistor is less than that of the second N-type transistor. The second N-type transistor can charge more quickly and transmit the low level from the ground terminal to the gate of the first P-type transistor and the reference voltage terminal, pulling the reference voltage terminal low. Further, the first P-type transistor is turned on, and the fourth voltage terminal transmits a high level to the output terminal through the first P-type transistor. The output terminal outputs a high level, confirming that the data read by the first ferroelectric memory cell is digital signal 0.

[0058] For example, if the first ferroelectric memory cell is set to reverse polarization when reading digital signal 0, the third voltage when reading digital signal 0 is less than the third voltage when reading digital signal 1.

[0059] When reading digital signal 0, the third voltage of the second node is low, and the second P-type transistor is turned on. The reference voltage at the reference voltage terminal is greater than the third voltage when the first ferroelectric memory cell reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell reads digital signal 1. Therefore, even though the reference voltage terminal is electrically connected to the gates of the first P-type transistor and the first N-type transistor, the conduction level of the first P-type transistor and the first N-type transistor is less than that of the second P-type transistor. The second P-type transistor can charge more quickly and transmit the high level of the fourth voltage terminal to the gate of the first N-type transistor and the reference voltage terminal, pulling the reference voltage terminal high. Further, the first N-type transistor is turned on, and the ground terminal transmits a low level to the output terminal through the first N-type transistor. The output terminal outputs a low level, confirming that the data read by the first ferroelectric memory cell is digital signal 0.

[0060] When reading digital signal 1, the third voltage of the second node is high, and the second N-type transistor is turned on. The reference voltage at the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell reads digital signal 1. Therefore, even though the reference voltage terminal is electrically connected to the gates of the first P-type transistor and the first N-type transistor, the conduction level of the first P-type transistor and the first N-type transistor is less than that of the second N-type transistor. The second N-type transistor can charge more quickly and transmit the low level from the ground terminal to the gate of the first P-type transistor and the reference voltage terminal, pulling the reference voltage terminal low. Further, the first P-type transistor is turned on, and the fourth voltage terminal transmits a high level to the output terminal through the first P-type transistor. The output terminal outputs a high level, confirming that the data read by the first ferroelectric memory cell is digital signal 1.

[0061] In some possible implementations, the storage circuit also includes a reference voltage generation circuit, which includes a second ferroelectric storage cell, a third ferroelectric storage cell, a second current mirror, a second voltage generation circuit, and a third node; the circuit structures of the second and third ferroelectric storage cells are the same as the circuit structure of the first ferroelectric storage cell; the second current mirror includes a third branch and a fourth branch.

[0062] During the reading phase: A second voltage generation circuit is used to input a fourth voltage to the third node, which is the same as the second voltage. A second ferroelectric storage cell is used to input a second current to the third branch, which represents the second ferroelectric storage cell reading a digital signal of 1. A third ferroelectric storage cell is used to input a third current to the fourth branch, which represents the third ferroelectric storage cell reading a digital signal of 0. The third branch is used to receive the second and third currents and copy the average of the second and third currents to the fourth branch. The third node is used to transfer charge to the fourth branch according to the average of the second and third currents, so that the potential of the third node drops from the second voltage to a fifth voltage, and the fifth voltage is input to the reference voltage terminal; wherein, the fifth voltage is half of the fourth voltage.

[0063] Since the circuit structures of the second and third ferroelectric memory units are the same as those of the first ferroelectric memory unit, the fourth voltage at the third node is the same as the second voltage at the second node, and the current of the fourth branch is the average of the second current when the second ferroelectric memory unit reads digital signal 1 and the third current when the third ferroelectric memory unit reads digital signal 0. The fourth branch will extract the average charge between digital signal 0 and digital signal 1 from the third node. The remaining fifth voltage at the third node is also between the third voltage when the first ferroelectric memory unit reads digital signal 1 and the third voltage when the first ferroelectric memory unit reads digital signal 0. Therefore, the fifth voltage can be used as a reference voltage to determine whether the data corresponding to the third voltage input to the comparison circuit from the second node is digital signal 0 or digital signal 1.

[0064] Furthermore, since the circuit structures of the second and third ferroelectric memory units are the same as those of the first ferroelectric memory unit, when the performance of the first ferroelectric memory unit changes due to external changes (such as temperature, voltage, etc.), the performance of the second and third ferroelectric memory units also changes in the same way. Therefore, the reference voltage generation circuit can be used to achieve automatic adjustment under different environments.

[0065] Furthermore, in order to ensure that when external changes (such as temperature, voltage, etc.) cause changes in the performance of the first ferroelectric memory cell, the performance of the second and third ferroelectric memory cells also changes in the same way, the circuit structure of the second voltage generation circuit can be the same as that of the first voltage generation circuit. The second ferroelectric memory cell is also electrically connected to the second bit line, and the third ferroelectric memory cell is also electrically connected to the third bit line. Moreover, the parasitic capacitance on the second bit line and the parasitic capacitance on the third bit line are the same as those on the first bit line.

[0066] In some possible implementations, the third branch includes a fifth transistor and a sixth transistor, and the fourth branch includes a seventh transistor; the channel widths of the fifth, sixth, and seventh transistors are all the same; the gates of the fifth and sixth transistors, the first terminal of the fifth transistor, the first terminal of the sixth transistor, and the gate of the seventh transistor are all electrically connected to the output terminals of the second and third ferroelectric memory cells; the second terminals of the fifth, sixth, and seventh transistors are all electrically connected to the fifth voltage terminal, and the first terminal of the seventh transistor is electrically connected to the third node.

[0067] According to the transistor current formula, in the third branch, the fifth and sixth transistors are connected in parallel, and the channel width of the fifth transistor is the same as that of the sixth transistor. Therefore, the total current flowing through the third branch is the sum of the second current flowing through the fifth transistor and the third current flowing through the sixth transistor. Furthermore, since the channel widths of the fifth, sixth, and seventh transistors are all the same, the ratio of the total channel width of the third branch to the channel width of the fourth branch is 2:1. The third branch can replicate the average of the second and third currents to the fourth branch.

[0068] Alternatively, the third branch includes a fifth transistor, the fourth branch includes a sixth transistor, the channel width of the fifth transistor is twice the channel width of the sixth transistor; the gate of the fifth transistor, the gate of the sixth transistor, and the first terminal of the fifth transistor are all electrically connected to the output terminals of the second ferroelectric memory cell and the third ferroelectric memory cell; the second terminals of the fifth transistor and the sixth transistor are all electrically connected to the fifth voltage terminal; and the first terminal of the sixth transistor is electrically connected to the third node.

[0069] According to the transistor current formula, the channel width of the fifth transistor is twice that of the sixth transistor. Therefore, the current flowing through the sixth transistor is twice the current flowing through the fifth transistor. The current in the third branch formed by the fifth transistor is the sum of the second and third currents. Therefore, the third branch can replicate the average of the second and third currents to the fourth branch.

[0070] In some possible implementations, the storage circuit also includes a third switch electrically connected between the reference voltage terminal and the first node. During the read phase, the third switch is open to prevent the signal from the reference voltage terminal from being input to the first node through the third switch. During the write phase, the third switch is open to allow the write signal from the reference voltage terminal to be input to the first ferroelectric storage cell through the first node.

[0071] Secondly, this application also provides a control method for a storage circuit. The storage unit includes a first ferroelectric storage unit, a first current mirror, a first voltage generating circuit, a comparison circuit, and a first voltage terminal. The first ferroelectric storage unit and the first branch of the first current mirror are electrically connected to a first node, and the second branch of the first current mirror is electrically connected to the first voltage generating circuit and the comparison circuit to a second node.

[0072] The control method for the storage circuit includes: In a pre-charging phase, pre-charging the first node to make its potential an initial voltage. In a reading phase: inputting a first voltage to a first current mirror through a first voltage terminal. Inputting charge to the first node using a first ferroelectric storage cell. Inputting a second voltage to the second node through a first voltage generation circuit; either the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is low; or the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is high. Using a first branch, maintaining the potential of the first node at the initial voltage based on the first voltage and the initial voltage, and replicating the first current of the first branch to the second branch. Using the second branch, changing the potential of the second node from the second voltage to a third voltage based on the first current, the first voltage, and the second voltage. Receiving the third voltage through a comparison circuit, and determining whether the data read from the first ferroelectric storage cell is a digital signal 0 or 1 based on the third voltage.

[0073] In some possible implementations, both the first and second transistors are N-type transistors, and both the initial and second voltages are greater than the first voltage. A first branch draws charge from the first node based on the first and initial voltages to maintain the potential of the first node at the initial voltage. A second branch draws charge from the second node based on the first current, the first voltage, and the second voltage to reduce the potential of the second node from the second voltage to the third voltage.

[0074] In some possible implementations, if the ferroelectric capacitor in the first ferroelectric memory cell undergoes polarization reversal when the first ferroelectric memory cell reads digital signal 1, then the third voltage when the first ferroelectric memory cell reads digital signal 1 is less than the third voltage when the first ferroelectric memory cell reads digital signal 0. If the ferroelectric capacitor in the first ferroelectric memory cell undergoes polarization reversal when the first ferroelectric memory cell reads digital signal 0, then the third voltage when the first ferroelectric memory cell reads digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads digital signal 0.

[0075] In some possible implementations, both the first and second transistors are N-type transistors, and both the initial and second voltages are lower than the first voltage. The first node draws charge from the first branch based on the first and initial voltages to maintain its potential at the initial voltage. The second node draws charge from the second branch based on the first current, the first voltage, and the second voltage to increase its potential from the second voltage to the third voltage.

[0076] In some possible implementations, if the ferroelectric capacitor in the first ferroelectric memory cell undergoes a polarization reversal when the first ferroelectric memory cell reads digital signal 1, then the third voltage when the first ferroelectric memory cell reads digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads digital signal 0. Similarly, if the ferroelectric capacitor in the first ferroelectric memory cell undergoes a polarization reversal when the first ferroelectric memory cell reads digital signal 0, then the third voltage when the first ferroelectric memory cell reads digital signal 0 is greater than the third voltage when the first ferroelectric memory cell reads digital signal 1.

[0077] In some possible implementations, after precharging the first node during the precharging phase, the control method of the storage circuit also includes: precharging the second node during the precharging phase.

[0078] In some possible implementations, the storage circuit also includes a reference voltage terminal. During the read phase: a reference voltage is input to the comparator circuit via the reference voltage terminal. The reference voltage value is between the third voltage when the first ferroelectric storage cell reads digital signal 0 and the third voltage when the first ferroelectric storage cell reads digital signal 1. The comparator circuit uses the third voltage and the reference voltage to determine whether the data read from the first ferroelectric storage cell is digital signal 0 or digital signal 1.

[0079] In some possible implementations, the storage circuit also includes a third switch electrically connected between the reference voltage terminal and the first node. During the read phase, the third switch is turned off. During the write phase, the third switch is turned on, and the write signal from the reference voltage terminal is input to the first ferroelectric storage cell through the third switch and the first node.

[0080] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0081] Thirdly, this application provides a storage circuit, which includes a ferroelectric storage cell, a clamping circuit, a voltage generating circuit, and a comparator circuit. The output terminal of the ferroelectric storage cell is electrically connected to one end of the clamping circuit at a first node; the other end of the clamping circuit, the voltage generating circuit, and the input terminal of the comparator circuit are electrically connected to a second node, and the output terminal of the comparator circuit is electrically connected to the output terminal of the storage circuit.

[0082] In this application, when reading data, the ferroelectric storage cell inputs a voltage to the first node. Since the voltage of the first node is higher than the voltage of the second node, the ferroelectric storage cell inputs a second voltage to the second node through the first node. Whether the ferroelectric capacitor undergoes polarization reversal or not, the data read by the ferroelectric storage cell (digital signal 1 or digital signal 0) is different, and the voltage input by the ferroelectric storage cell to the second node is different. Therefore, after receiving the voltage input to the second node, the comparator circuit can determine whether the data read by the ferroelectric storage cell is digital signal 1 or digital signal 0 based on the received voltage.

[0083] Meanwhile, whether reading digital signal 1 or digital signal 0, the voltage on the bit line (first node) is clamped at the initial voltage of 0V by the clamping circuit. On the one hand, the potential difference between the plate line and the bit line is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the bit line is always at a large value, so that the polarization reversal of the ferroelectric capacitor will not become slower or even insufficient due to the decrease in the potential difference between the plate line and the bit line, thus avoiding self-suppression. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0084] Furthermore, as mentioned earlier, in the prior art, the comparator circuit reads the digital signal 1 or digital signal 0 by acquiring the charge on the bit line. The bit line is usually connected to multiple ferroelectric memory cells and is relatively long. In the memory chip, the bit line inevitably forms parasitic capacitance with multiple conductive structures, which has a negative impact on the MW of the memory circuit.

[0085] In this application, the voltage on the bit line (first node) is clamped at the initial voltage by the clamping circuit, and the parasitic capacitance cannot be transmitted to the second node through the bit line. The comparison circuit of this application determines whether the data is a digital signal 0 or a digital signal 1 based on the voltage transmitted by the second node. Therefore, the parasitic capacitance will not have a negative impact on the MW of the storage circuit.

[0086] In some possible implementations, the voltage generation circuit includes a first voltage terminal and a storage capacitor electrically connected between the second node and the first voltage terminal. During the pre-charging phase, the first voltage terminal is used to input a first voltage to the second node via the storage capacitor. During the reading phase, the ferroelectric storage cell is used to input a second voltage to the second node via the first node and a clamping circuit. During the reading phase, the first voltage terminal is used to input a third voltage to the second node via the storage capacitor.

[0087] If the voltage generation circuit includes a first voltage terminal, during the reading phase, the first voltage terminal is used to input a third voltage to the second node. However, due to the presence of parasitic capacitance, the voltage value received by the second node will not reach the voltage value output by the first voltage terminal. Therefore, the voltage generation circuit can also include a storage capacitor electrically connected between the second node and the first voltage terminal. The first voltage terminal is electrically connected to the first electrode of the storage capacitor, and the second node is electrically connected to the second electrode of the storage capacitor. In this way, the voltage generation circuit can first input the third voltage to the first electrode, and the first electrode couples the third voltage to the second electrode and the second node, thus improving the problem that the voltage output by the first voltage terminal is largely diverted by the parasitic capacitance, causing the voltage value received by the second node to not reach the voltage value output by the first voltage terminal.

[0088] In some possible implementations, signal loss often occurs during transmission. Therefore, the voltage generation circuit also includes an inverter, which is electrically connected between the first voltage terminal and the storage capacitor to enhance the signal.

[0089] In some possible implementations, the clamping circuit includes a first transistor and a second transistor. The first transistor is an N-type transistor, and the second transistor is a P-type transistor. The first transistor is electrically connected between the first node and the second transistor. While the ferroelectric memory cell inputs a second voltage to the second node through the first node and the clamping circuit, both the first and second transistors are turned on. Because the second transistor is a P-type transistor, it can clamp the node connected to the first transistor. Since the potential of the node connected to the first transistor is the same as the potential of the first node, the second transistor is used to clamp the potential of the first node at 0V through the first transistor.

[0090] While the voltage generation circuit inputs the third voltage to the second node, the first transistor is turned off to prevent the potential of the first node from increasing when the potential of the second node rises, thus affecting the potential of the first node through the second transistor and the first transistor.

[0091] In some possible implementations, the storage circuit also includes a third transistor and a second voltage terminal. During the pre-charge phase, the second voltage terminal is used to pre-charge the first node to 0V via the third transistor in preparation for the read phase. During the read phase, the first voltage is less than 0V, the second voltage is greater than 0V, and the voltage of the first node is greater than the sum of the first voltage and the second voltage.

[0092] In some possible implementations, the third transistor is electrically connected between the second node and the second voltage terminal, and the second voltage terminal precharges the first node to 0V through the third transistor, the second node, the second transistor, and the first transistor. Alternatively, the third transistor is electrically connected between the third node and the second voltage terminal, the third node being the connection point between the first transistor and the second transistor, and the second voltage terminal precharges the first node to 0V through the third transistor, the third node, and the first transistor.

[0093] In some possible implementations, during the read phase, the second node is used to input a fourth voltage to the comparator circuit, the fourth voltage being the sum of the first, second, and third voltages. The comparator circuit receives the fourth voltage input from the second node and, based on the fourth voltage, determines whether the data read from the ferroelectric memory cell is a digital signal 0 or 1; wherein the fourth voltage is within the operating voltage range of the comparator voltage.

[0094] In this application, when reading data, the second voltage of the ferroelectric storage cell is first input to the first node. Since the potential of the first node is higher than that of the second node, the ferroelectric storage cell inputs its second voltage to the second node through the first node. Whether the ferroelectric capacitor undergoes polarization reversal or not, the data read by the ferroelectric storage cell (digital signal 1 or digital signal 0) is different, and the second voltage input to the second node by the ferroelectric storage cell is different. Besides the second voltage, the first voltage when the ferroelectric storage cell reads digital signal 1 is the same as the first voltage when reading digital signal 0, and the third voltage when the ferroelectric storage cell reads digital signal 1 is the same as the third voltage when reading digital signal 0. Therefore, after receiving the fourth voltage input from the second node, the comparator circuit can determine whether the data read by the ferroelectric storage cell is digital signal 1 or digital signal 0 based on the fourth voltage.

[0095] Meanwhile, whether reading digital signal 1 or digital signal 0, the voltage on the bit line (first node) is clamped at the initial voltage by the clamping circuit. On the one hand, the potential difference between the plate line and the bit line is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor. On the other hand, the potential difference between the plate line and the bit line is always at a large value, so that the polarization reversal of the ferroelectric capacitor will not become slower or even insufficient due to the decrease in the potential difference between the plate line and the bit line, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0096] Furthermore, as mentioned earlier, in the prior art, the comparator circuit reads the digital signal 1 or digital signal 0 by acquiring the charge on the bit line. The bit line is usually connected to multiple ferroelectric memory cells and is relatively long. In the memory chip, the bit line inevitably forms parasitic capacitance with multiple conductive structures, which has a negative impact on the MW of the memory circuit.

[0097] In this application, the voltage on the bit line (first node) is clamped at the initial voltage by the clamping circuit, and the parasitic capacitance cannot be transmitted to the second node through the bit line. The comparison circuit of this application confirms whether the data is a digital signal 0 or a digital signal 1 based on the fourth voltage transmitted from the second node. Therefore, the parasitic capacitance will not have a negative impact on the MW of the storage circuit.

[0098] In some possible implementations, the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage. For example, the second node is first pulled down by 5V using a voltage generation circuit (the first voltage is -5V), and after the second node receives the second voltage, it is then pulled up by 5V using a voltage generation circuit (the third voltage is 5V). The resulting fourth voltage is the second voltage input from the ferroelectric storage cell to the second node.

[0099] In some possible implementations, the storage circuit also includes a third voltage terminal and a fourth transistor, which is an N-type transistor. The gate of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the third voltage terminal, and the second terminal of the fourth transistor is electrically connected to the input terminal of the comparator circuit.

[0100] As mentioned earlier, the fourth voltage is positive regardless of whether the digital signal is 1 or 0, but the fourth voltage when reading digital signal 1 is different from the fourth voltage when reading digital signal 0.

[0101] When the first ferroelectric memory cell reads digital signal 1, the polarization of the ferroelectric capacitor reverses; when the first ferroelectric memory cell reads digital signal 0, the polarization of the ferroelectric capacitor does not reverse. Therefore, the fourth voltage when reading digital signal 1 is greater than the fourth voltage when reading digital signal 0. The conduction level of the fourth transistor when reading digital signal 1 is greater than that when reading digital signal 0. More current flows through the fourth transistor when reading digital signal 1, and thus more charge accumulates at the input of the comparator circuit within a certain time. The comparator circuit receives more voltage, and the comparator circuit determines whether the data read by the ferroelectric memory cell is digital signal 0 or digital signal 1 based on the magnitude of the received voltage.

[0102] When the first ferroelectric memory cell reads digital signal 0, the polarization of the ferroelectric capacitor reverses; when the first ferroelectric memory cell reads digital signal 1, the polarization of the ferroelectric capacitor does not reverse. Therefore, the fourth voltage when reading digital signal 0 is greater than the fourth voltage when reading digital signal 1. The conduction level of the fourth transistor when reading digital signal 0 is greater than that when reading digital signal 1. More current flows through the fourth transistor when reading digital signal 0, resulting in more charge accumulating at the input of the comparator circuit within a certain time. The comparator circuit receives a larger voltage and determines whether the data read by the ferroelectric memory cell is digital signal 0 or digital signal 1 based on the magnitude of the received voltage.

[0103] In this case, since the gate of the fourth transistor is electrically connected to the second node, the fourth voltage controls the conduction level of the fourth transistor and the magnitude of the current flowing through it. Therefore, the comparator circuit still indirectly determines whether the data read by the ferroelectric memory cell is a digital signal 0 or a digital signal 1 based on the fourth voltage. Furthermore, the fourth voltage can be amplified through charge accumulation to improve the read quality and resolution of the memory circuit.

[0104] Fourthly, this application provides a control method for a storage circuit, the storage circuit including a ferroelectric storage unit, a clamping circuit, a voltage generating circuit, and a comparison circuit; the ferroelectric storage unit and the clamping circuit are electrically connected to a first node; the clamping circuit, the voltage generating circuit, and the comparison circuit are electrically connected to a second node.

[0105] During the pre-charging phase: the first node is pre-charged to 0V, and the second node is pre-charged to a first voltage (less than 0V) using a voltage generation circuit. During the reading phase, the ferroelectric memory cell inputs a second voltage (greater than 0V) to the second node through the first node and a clamping circuit. The clamping circuit clamps the potential of the first node to its initial voltage. The voltage generation circuit inputs a third voltage to the second node, resulting in a fourth voltage. A comparator circuit receives the fourth voltage input from the second node and determines whether the data read by the ferroelectric memory cell is a digital signal 0 or 1 based on this fourth voltage; the fourth voltage is within the operating voltage range of the comparator voltage.

[0106] In some possible implementations, the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage.

[0107] In some possible implementations, the storage circuit also includes a third transistor and a second voltage terminal; during the pre-charge phase, the first node is pre-charged to 0V, including: during the pre-charge phase, the third transistor is turned on, and the second voltage terminal pre-charges the first node to 0V through the third transistor.

[0108] The fourth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the fourth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0109] Fifthly, this application provides a memory, including a controller and the storage circuit described in the first or third aspect, wherein the controller is used to control the storage circuit to read and write data.

[0110] The fifth aspect and any implementation thereof correspond to the first and third aspects, and to any implementation thereof. The technical effects of the fifth aspect and any implementation thereof can be found in the first and third aspects, and to any implementation thereof, as described above; they will not be repeated here.

[0111] In a sixth aspect, this application provides an electronic device, including a circuit board and the memory described in the fifth aspect, the memory being disposed on the circuit board.

[0112] The sixth aspect and any implementation thereof correspond to the first and third aspects, and to any implementation thereof. The technical effects of the sixth aspect and any implementation thereof can be found in the first and third aspects, and to any implementation thereof, as described above; they will not be repeated here. Attached Figure Description

[0113] Figure 1a A diagram showing the relationship between the memory and other modules in an electronic device provided in this application embodiment;

[0114] Figure 1b An interaction diagram of the various modules in the memory provided in the embodiments of this application;

[0115] Figure 2 A circuit diagram of a ferroelectric memory array provided in an embodiment of this application;

[0116] Figure 3 Timing diagram of ferroelectric storage cells reading data for related technologies;

[0117] Figure 4a A circuit diagram of the storage circuit provided in the embodiments of this application;

[0118] Figure 4b for Figure 4a The circuit diagram shown is a timing diagram of its operation.

[0119] Figure 5a A circuit diagram of the storage circuit provided in the embodiments of this application;

[0120] Figure 5b for Figure 5a The circuit diagram shown is a timing diagram of its operation.

[0121] Figure 6 A circuit diagram of the storage circuit provided in the embodiments of this application;

[0122] Figure 7a A circuit diagram of the storage circuit provided in the embodiments of this application;

[0123] Figure 7b A circuit diagram of the storage circuit provided in the embodiments of this application;

[0124] Figure 8 A circuit diagram of the storage circuit provided in the embodiments of this application;

[0125] Figure 9a A circuit diagram of the storage circuit provided in the embodiments of this application;

[0126] Figure 9b for Figure 9a The circuit diagram shown is a timing diagram of its operation.

[0127] Figure 10 A circuit diagram of the storage circuit provided in the embodiments of this application;

[0128] Figure 11 A circuit diagram of the storage circuit provided in the embodiments of this application;

[0129] Figure 12 A circuit diagram of the storage circuit provided in an embodiment of this application. Detailed Implementation

[0130] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0131] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0132] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0133] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0134] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0135] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device that includes a memory.

[0136] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, storage devices, radar, and base stations.

[0137] Figure 1a This application provides a schematic diagram of the structure of a memory in an electronic device. The electronic device includes a memory and other chips or independent devices, which may include a processor. Figure 1bAs shown, the memory includes a storage array, a controller, a row decoder, a column decoder, etc. The processor can send the address of the selected storage unit to the row decoder and column decoder through the controller. After decoding the received address, the row decoder and column decoder determine the storage unit in the storage array as the selected storage unit, and then perform read and write operations on the selected storage unit.

[0138] In some embodiments, the memory of this application can be a ferroelectric memory, including ferroelectric random access memory (FeRAM or FRAM) and ferroelectric field-effect transistor (FeFET) memory. As a novel type of memory, ferroelectric memory offers significant improvements in non-volatility and capacity density compared to traditional DRAM. The memory cell in a ferroelectric memory includes a transistor and a ferroelectric capacitor, with the ferroelectric capacitor storing information based on the ferroelectric effect. A ferroelectric capacitor includes two electrodes and a ferroelectric material, such as a ferroelectric thin film, disposed between the two electrodes. Due to the nonlinear characteristics of ferroelectric materials, their dielectric constant can not only be adjusted but also become very large near the phase transition temperature. Therefore, compared to traditional capacitors, ferroelectric capacitors can have a larger dielectric constant and a smaller volume. In this application, the number of transistors and ferroelectric capacitors in the memory cell is not limited; the memory cell includes at least one transistor and at least one ferroelectric capacitor.

[0139] The working principle of ferroelectric memory is as follows: when an electric field is applied to the ferroelectric capacitor of the memory cell, the central atom remains in a low-energy state along with the electric field; conversely, when the electric field is reversed and applied to the ferroelectric capacitor, the central atom moves in the direction of the electric field within the crystal and remains in another low-energy state. A large number of central atoms move and couple within the crystal unit cell to form ferroelectric domains, which then generate polarization charges under the influence of an electric field. The polarization charges formed by ferroelectric domains reversing under an electric field are higher, while the polarization charges formed by ferroelectric domains without reversal under an electric field are lower. This binary stable state of ferroelectric materials allows them to be used as memory. Ferroelectric thin films can use common ferroelectric materials, such as Hf. 0.5 Zr 0.5 O2, or antiferroelectric materials, such as PbZrO3, NH4H2PO4, etc.

[0140] Figure 2 A circuit diagram of a memory array is shown, comprising multiple memory cells, each including a transistor and a ferroelectric capacitor connected to the transistor. For each memory cell, the gate of its transistor is connected to the word line WL, the first terminal of the transistor is connected to the bit line BL, and the second terminal is connected to the board line PL via the ferroelectric capacitor.

[0141] When reading and writing data using the ferroelectric storage cells of a ferroelectric memory, voltage needs to be applied to the ferroelectric capacitor using the plate line PL and bit line BL. However, existing reading methods can affect the reliability of the ferroelectric memory. Figure 3 As shown, before reading data, the bit line BL is pre-charged to 0V and then placed in a floating state. Next, during the read phase, a voltage is applied to the transistor via the word line WL to turn it on, and a positive voltage is applied to the plate line PL. If the ferroelectric capacitor undergoes polarization reversal, the potential on the bit line BL rises to a higher potential; if the ferroelectric capacitor does not undergo polarization reversal, the potential on the bit line BL rises to a lower potential. A comparator circuit then compares the potential on BL with the reference voltage Vref to read the stored information 0 / 1 of the ferroelectric memory cell.

[0142] However, as mentioned in the background art, assuming that when the information read is digital signal 1, the ferroelectric capacitor undergoes polarization reversal and reads the digital signal through the bit line BL. This causes the potential on the bit line BL to rise and accumulate over time, resulting in a decrease in the potential difference between the plate line PL and the bit line BL, which are electrically connected to both ends of the ferroelectric capacitor. This reduces the effective ferroelectric switching voltage used to control the switching of the ferroelectric capacitor, causing the ferroelectric capacitor to switch slower and slower and the switching to be insufficient. This phenomenon is the self-suppression phenomenon when the FeRAM reads digital signal 1. This phenomenon will affect the uniformity and reliability of the ferroelectric memory, and will also reduce the storage window of the ferroelectric memory.

[0143] Based on this, this application provides a storage circuit. During the reading phase, a first current mirror is used to maintain the potential on the first bit line BL1 at its initial voltage, ensuring that the potential difference between the board line PL and the first bit line BL1 does not decrease due to data reading, thus preventing insufficient switching of the ferroelectric capacitor. Furthermore, to enable normal data reading by the storage circuit, another node can be added. The potential at this node is closely related to the charge output by the first ferroelectric storage unit during data reading and the voltage on the first current mirror. Therefore, the potential at this node can be used to determine whether the digital signal read by the storage circuit is 0 or 1.

[0144] like Figures 4a-4b and Figures 5a-5b As shown, when the initial voltage of the first line BL1 is different (high level or low level) during the pre-charging stage, the potential change trend of the first line BL1 is different when the polarization of the ferroelectric capacitor FE-Cap reverses during the reading stage. Therefore, this application describes the working principle of the storage circuit when the initial voltage of the first line BL1 is low level and high level respectively.

[0145] It should be understood that during the reading phase, if the initial voltage of the first line BL1 is low, the voltage on the board line PL is high; if the initial voltage of the first line BL1 is high, the voltage on the board line PL is low.

[0146] like Figure 4a As shown, the storage circuit includes a first ferroelectric storage unit 11, a first current mirror 12, a first voltage generating circuit 13, a comparator circuit 14, and a first voltage terminal Vss1. The first current mirror includes a first branch and a second branch. One end of the first branch is electrically connected to one end of the second branch and is connected to the first voltage terminal, and the current in the first branch and the second branch is the same. The output terminal of the first ferroelectric storage unit 11 is electrically connected to the other end of the first branch at a first node A. The other end of the second branch is electrically connected to the input terminals of the first voltage generating circuit 13 and the comparator circuit 14 at a second node B. The output terminal of the comparator circuit 14 is electrically connected to the output terminal of the storage circuit.

[0147] The aforementioned first current mirror 12 may include a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 are identical; that is, the parameters of each film layer in the first transistor T1 are the same as the parameters of each film layer in the second transistor T2. The first transistor T1 and the second transistor T2 can be N-type transistors, or they can be P-type transistors. Specifically, if the initial voltage of the first bit line BL1 is low, then both the first transistor T1 and the second transistor T2 are N-type transistors; if the initial voltage of the first bit line BL1 is high, then both the first transistor T1 and the second transistor T2 are P-type transistors.

[0148] The following is combined with Figure 4a and Figure 4b A detailed explanation of the working principle of the storage circuit.

[0149] Figure 4a and Figure 4b The circuit diagram and timing diagram of the storage circuit are shown respectively when both the first transistor T1 and the second transistor T2 are N-type transistors. In addition, Figure 4b The timing diagram shown is based on the example where all other transistors in the storage circuit are N-type transistors and the ferroelectric capacitor FE-Cap is flipped to read digital signal 1. The first voltage generation circuit 13 includes an inverter. The timing diagram corresponds to the potential of the gate of each transistor.

[0150] During the pre-charging phase, the potential of the first node A (first bit line BL1) is the initial voltage, which is a low level, for example, the initial voltage can be 0V.

[0151] During the reading phase, the operation of each module in the storage circuit is as follows:

[0152] The first voltage terminal Vss1 is used to input a first voltage to the first current mirror 12, and the first voltage generating circuit 13 is used to input a second voltage to the second node B. Here, the first voltage terminal Vss1 is grounded, the first voltage input to the first current mirror 12 is low level, the second voltage is high level, the second voltage is greater than the first voltage, and the initial voltage is greater than the first voltage.

[0153] When the first ferroelectric storage cell 11 reads data, it inputs charge (positive charge) to the first node A (first bit line BL1). Since the initial voltage is greater than the first voltage, a potential difference exists between the first node A and the first branch. The first branch draws charge from the first node A (those skilled in the art should know that charge moves from a high potential to a low potential). Thus, while the first node A receives the charge input from the first ferroelectric storage cell 11, it is also having charge drawn from it by the first branch. Therefore, the first node A remains at its initial voltage. That is, the charge input by the first ferroelectric storage cell 11 to the first node A does not accumulate at the first node A.

[0154] Furthermore, according to the working principle of the first current mirror 12, the first branch replicates the first current flowing through the first branch to the second branch. Then, the second branch will change the potential of the second node B from the second voltage to the third voltage based on the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0155] It should be understood that, when the first transistor T1 and the second transistor T2 are identical, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vss1 simultaneously inputs a low level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is greater than the first voltage, if the first branch draws charge from the first node A, the second branch will also draw charge from the second node B, so that the potential of the second node B decreases from the second voltage to the third voltage.

[0156] Those skilled in the art should know that during the reading phase, when the polarization of the ferroelectric capacitor FE-Cap in the first ferroelectric storage cell 11 reverses, the first ferroelectric storage cell 11 outputs a polarization current; when the polarization of the ferroelectric capacitor FE-Cap does not reverse, the first ferroelectric storage cell 11 outputs a dielectric current. The amount of charge input to the first node A when the polarization of the ferroelectric capacitor FE-Cap reverses is greater than the amount of charge input to the first node A when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, when the polarization of the ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the first node A by the first branch is greater than the amount of charge drawn from the first node A by the first branch when the polarization of the ferroelectric capacitor FE-Cap reverses.

[0157] It is known that when the polarization of the ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the first node A by the first branch is greater than the amount of charge drawn from the first node A by the first branch when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, when the polarization of the ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the second node B by the second branch is also greater than the amount of charge drawn from the second node B by the second branch when the polarization of the ferroelectric capacitor FE-Cap does not reverse. That is, whether the polarization of the ferroelectric capacitor FE-Cap reverses or not, the remaining third voltage after the charge is drawn from the second node B is different.

[0158] Furthermore, the second node B inputs the remaining third voltage to the comparator circuit 14, which can then determine whether the data read from the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0159] In this application, due to whether or not the ferroelectric capacitor FE-Cap undergoes polarization reversal, the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11 is different, the amount of charge input to the first node A is different, the first current flowing through the first branch and the second branch is also different, the amount of charge drawn by the first branch from the first node A is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric storage unit 11 reads different data, the second branch can draw charge from the second node B according to the first current, the first voltage, and the second voltage, so that the potential of the second node B drops from the second voltage to the third voltage. It can be seen that the remaining potential third voltage on the second node B is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11. Therefore, the third voltage can be input to the comparison circuit 14 using the second node B, so that the comparison circuit 14 can determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0160] Meanwhile, whether reading digital signal 1 or digital signal 0, the charge on the first line BL1 is extracted by the first branch, keeping the potential on the first line BL1 at 0V (or close to 0V). On the one hand, the potential difference between the plate line PL and the first line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the first line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap will not become slower or even insufficient due to the decrease in the potential difference between the plate line PL and the first line BL1, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0161] In some possible implementations, the data read by the first ferroelectric storage unit 11 (digital signal 1 or digital signal 0) is different, and the magnitude of the third voltage is related to the data read when the polarization of the pre-set ferroelectric capacitor FE-Cap reverses.

[0162] For example, suppose that when the first ferroelectric storage unit 11 reads the digital signal 1, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads the digital signal 0, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads the digital signal 1, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second branch will draw a first charge from the second node B, and the potential of the second node B will decrease significantly. When the first ferroelectric storage unit 11 reads the digital signal 0, it will output a small amount of dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second branch will draw a second charge from the second node B, and the potential of the second node B will decrease slightly. The first charge is greater than the second charge.

[0163] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0164] For example, suppose that when the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads digital signal 0, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second branch will draw a first charge from the second node B, and the potential of the second node B will decrease significantly. When the first ferroelectric storage unit 11 reads digital signal 1, it will output a small amount of dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second branch will draw a second charge from the second node B, and the potential of the second node B will decrease slightly. The first charge is greater than the second charge.

[0165] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0166] In some embodiments, in the first current mirror 12, since the current input to the first branch and the current output from the second branch are always the same, when the first current mirror 12 is operating, in order to ensure that the first branch replicates the same polarization current or dielectric current to the second branch, the initial current flowing through the first branch should be the same as the initial current flowing through the second branch before the polarization current or dielectric current flows to the first branch. However, the current in the first branch is easily affected by the first node A, and the current in the second branch is easily affected by the second node B, which may cause the initial current in the first branch to be different from the initial current flowing through the second branch.

[0167] Based on this, the storage circuit in this embodiment further includes a third transistor T3 and a fourth transistor T4. The third transistor T3 is connected in series between the first node A and the first transistor T1 (the first terminal of the third transistor T3 is electrically connected to the first node A, and the second terminal of the third transistor T3 is electrically connected to the first terminal of the first transistor T1). The fourth transistor T4 is connected in series between the second node B and the second transistor T2 (the first terminal of the fourth transistor T4 is electrically connected to the second node B, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the second transistor T2). Furthermore, both the third transistor T3 and the fourth transistor T4 are N-type transistors.

[0168] During the reading phase, both the third transistor T3 and the fourth transistor T4 are turned on. The second terminal of the third transistor T3 inputs a clamping voltage to the first terminal of the first transistor T1, and the second terminal of the fourth transistor T4 inputs a clamping voltage to the first terminal of the second transistor T2. This makes the potential of the connection node C between the third transistor T3 and the first transistor T1 the same as the potential of the connection node D between the fourth transistor T4 and the second transistor T2. This ensures that, with the first transistor T1 and the second transistor T2 having the same resistance, the initial current flowing through the first branch is the same as the initial current flowing through the second branch.

[0169] Furthermore, due to the presence of a clamping voltage, the voltage of the first current mirror 12 stops increasing after reaching a certain value. Therefore, if the first branch draws charge from the first node A, the voltage of the first current mirror 12 saturates. Since the data reading phase is still in progress, the first branch stops drawing charge from the first node A, leaving residual charge on the first line BL1. This results in a potential greater than 0V on the first line BL1, reducing the potential difference between the board line PL and the first line BL1. Based on this, the storage circuit may not include the third transistor T3 and the fourth transistor T4.

[0170] Of course, it should be understood that even if the storage circuit includes the third transistor T3 and the fourth transistor T4, the first branch can still draw charge from the first node A. Therefore, compared with the prior art, it is still possible to increase the potential difference between the board line PL and the first line BL1, which can improve the self-suppression phenomenon.

[0171] In some embodiments, the first voltage generation circuit 13 includes a second voltage terminal V_boost, which is used to input a second voltage to the second node B during the reading phase. However, due to the presence of parasitic capacitance, the voltage value received by the second node B will not reach the voltage value output by the second voltage terminal V_boost. Therefore, the first voltage generation circuit 13 may further include a tank capacitor (TC), which is electrically connected between the second node B and the second voltage terminal V_boost. The second voltage terminal V_boost is electrically connected to the first electrode of the tank capacitor TC, and the second node B is electrically connected to the second electrode of the tank capacitor TC. In this way, the first voltage generation circuit 13 can first input the second voltage to the first electrode, which then couples the second voltage to the second electrode and the second node B. This improves the problem that the voltage output by the second voltage terminal V_boost is largely diverted by parasitic capacitance, causing the voltage value received by the second node B to not reach the voltage value output by the second voltage terminal V_boost.

[0172] Furthermore, since the first and second electrodes of the energy storage capacitor TC are isolated by the insulating material between them, after the first electrode couples the second voltage to the second electrode and the second node B, even if the second voltage terminal V_boost still provides the second voltage to the first electrode, the potential of the second electrode and the second node B is no longer affected by the second voltage terminal V_boost and the first electrode. Therefore, after the second node B is charged by the second branch, the potential on the second node B decreases, instead of remaining at 0V (or approaching 0V) like the first node A, even if it is charged by the first branch.

[0173] In some possible ways of implementation, such as Figure 6 As shown, signal loss usually occurs during transmission. Based on this, the first voltage generation circuit 13 may also include an inverter 131, which is electrically connected between the second voltage terminal V_boost and the storage capacitor TC to enhance the signal.

[0174] It should be noted here that the second voltage required by the second node B is a high level. If the first voltage generating circuit 13 does not include the inverter 131, the voltage output by the second voltage terminal V_boost is also a high level; if the first voltage generating circuit 13 includes the inverter 131, the voltage output by the second voltage terminal V_boost is a low level.

[0175] In some embodiments, such as Figure 6 As shown, the storage circuit also includes a third voltage terminal V3 and a pre-charge circuit 15, which is electrically connected between the third voltage terminal V3 and the first node A. During the pre-charge phase before the reading phase, the third voltage terminal V3 is used to input an initial voltage of 0V to the first line BL1 through the pre-charge circuit 15, preparing for the reading phase. Furthermore, during the reading phase, by controlling the voltage on the board line PL, the potential difference between the board line PL and the first line BL1 can be controlled to control the first ferroelectric storage cell 11 to read data.

[0176] Optionally, the pre-charge circuit 15 includes a first switch ISO and a second switch PCH. The first switch ISO is electrically connected between the input terminal of the first branch and the output terminal of the second branch, and the second switch PCH is electrically connected between the third voltage terminal V3 and the second node B. During the pre-charge phase, both the first switch ISO and the second switch PCH are turned on, and the third voltage terminal V3 inputs an initial voltage of 0V to the first bit line BL1 through the second switch PCH and the first switch ISO.

[0177] In some possible implementations, during the pre-charging phase, after pre-charging the first line BL1 using the third voltage terminal V3, the second node B can also be pre-charged using the third voltage terminal V3. In this case, the second switch PCH is turned on, and the third voltage terminal V3 pre-charges the second node B to the charging voltage (greater than 0V) through the second switch PCH. Simultaneously, the first switch ISO is turned off; therefore, the charging voltage of the third voltage terminal V3 does not affect the potential on the first line BL1.

[0178] During the pre-charging phase, the third voltage terminal V3 inputs a charging voltage to the second node B; during the reading phase, the second voltage terminal V_boost inputs a second voltage to the second node B. Thus, before the second node B is charged by the second branch, the voltage on the second node B is the sum of the charging voltage and the second voltage. This embodiment of the application inputs voltage to the second node B multiple times to ensure that the voltage on the second node B is sufficiently large, thereby increasing the difference between the third voltage of the second node B when reading digital signal 1 and the third voltage of the second node B when reading digital signal 0, and increasing the MW of the storage circuit.

[0179] In other embodiments, as mentioned above, in the prior art, the comparator circuit 14 reads the digital signal 1 or digital signal 0 by acquiring the charge on the first bit line BL1. The first bit line BL1 is usually connected to multiple ferroelectric memory cells and is relatively long. In the memory chip, the first bit line BL1 inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures. The parasitic capacitance Cbl1 has a negative impact on the MW of the memory circuit.

[0180] According to the formula charge (Q) = voltage (U) × capacitance (C), the larger the parasitic capacitance Cbl1 on the first line BL1, the smaller the voltage U on the first line BL1, the larger the potential difference between the plate line PL and the first line BL1, the larger the effective switching voltage of the ferroelectric capacitor FE-Cap, and the more fully the ferroelectric capacitor FE-Cap switches.

[0181] As can be seen, the presence of parasitic capacitance Cbl1 causes a trade-off between the effective switching voltage of the storage circuit MW and the ferroelectric capacitor FE-Cap, thus limiting the design.

[0182] In the scheme of this application, the comparator circuit 14 no longer reads the digital signal 1 or digital signal 0 by acquiring the voltage on the first bit line BL1, but instead reads the digital signal 1 or digital signal 0 by acquiring the voltage on the second node B. In this way, even if the first bit line BL1 has a large parasitic capacitance Cbl1, it will not have a negative impact on the MW of the storage circuit. At the same time, according to the formula of charge (Q) = voltage (U) × capacitance (C), the parasitic capacitance Cbl1 of the first bit line BL1 can also increase the effective switching voltage, so that the ferroelectric capacitor FE-Cap can switch more fully.

[0183] Based on this, during the reading phase, the embodiments of this application can also disconnect the first switch ISO and the second switch PCH. In this way, the second node B is isolated (the second node B is isolated from the first node A through the first switch ISO, and the second node B is isolated from the third voltage terminal V3 through the second switch PCH). Therefore, the parasitic capacitance of the second node B is very small, and its impact on the MW of the storage circuit is also very small.

[0184] In some embodiments, such as Figure 6 As shown, the storage circuit also includes a reference voltage terminal Vref. During the reading phase, the reference voltage terminal Vref can input a reference voltage to the comparator circuit 14. The comparator circuit 14 determines whether the data read from the first ferroelectric storage cell 11 is a digital signal 0 or a digital signal 1 based on the received third voltage and the reference voltage.

[0185] Contrary to existing technologies, if the first ferroelectric memory cell 11 is configured to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 1, the third voltage in existing technologies when reading digital signal 1 is greater than the third voltage when reading digital signal 0; while in this application, the third voltage when reading digital signal 1 is less than the third voltage when reading digital signal 0. If the first ferroelectric memory cell 11 is configured to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 0, the third voltage in existing technologies when reading digital signal 0 is greater than the third voltage when reading digital signal 1; while in this application, the third voltage when reading digital signal 0 is less than the third voltage when reading digital signal 1.

[0186] Based on this, the comparison circuit 14 of this application should combine the data read when the polarization of the set ferroelectric capacitor FE-Cap reverses, and determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 according to the received fourth voltage and reference voltage.

[0187] The working principle of the comparator circuit 14 for reading data will be explained in detail below with reference to the circuit structure of the comparator circuit 14.

[0188] like Figure 6 As shown, the comparator circuit 14 includes a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, and a ground terminal Vss2. The storage circuit also includes an output terminal OUT. During the read phase, the fourth voltage terminal V4 is at a high level, and the ground terminal Vss2 is at a low level.

[0189] The gates of the first P-type transistor P1 and the first N-type transistor N1 are electrically connected to the second terminal of the second P-type transistor, the first terminal of the second N-type transistor, and the reference voltage terminal Vref. The first terminal of the first P-type transistor P1 is electrically connected to the fourth voltage terminal V4. The second terminal of the first P-type transistor P1 is electrically connected to the first terminal of the first N-type transistor N1 and the output terminal OUT. The second terminal of the first N-type transistor N1 is electrically connected to the ground terminal Vss2. The gates of the second P-type transistor P2 and the second N-type transistor N2 are electrically connected to the second node B. The first terminal of the second P-type transistor P2 is electrically connected to the fourth voltage terminal V4. The second terminal of the second N-type transistor N2 is electrically connected to the ground terminal Vss2. The output terminal OUT is electrically connected between the second node B and the second terminal of the first P-type transistor P1 and the first terminal of the first N-type transistor N1.

[0190] For example, if the first ferroelectric storage unit 11 is set to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 1, the third voltage when reading digital signal 1 is less than the third voltage when reading digital signal 0.

[0191] When reading digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss2 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0192] When reading digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss2 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0193] For example, if the first ferroelectric storage cell 11 is set to reverse polarization when reading digital signal 0, the third voltage when reading digital signal 0 is less than the third voltage when reading digital signal 1.

[0194] When reading digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss2 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0195] When reading digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss2 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0196] In some embodiments, such as Figure 7a and Figure 7b As shown, the storage circuit also includes a reference voltage generation circuit 16 and a fifth voltage terminal Vss3. The reference voltage generation circuit 16 provides a reference voltage for the comparator circuit 14. The reference voltage generation circuit 16 includes a second ferroelectric storage cell 161, a third ferroelectric storage cell 162, a second current mirror 163, a second voltage generation circuit 164, and a third node E. The circuit structures of the second ferroelectric storage cell 161 and the third ferroelectric storage cell 162 are the same as those of the first ferroelectric storage cell 11. The second current mirror 163 includes a third branch and a fourth branch.

[0197] The circuit structures of the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are the same as those of the first ferroelectric memory unit 11. This means that the number of transistors and ferroelectric capacitors in the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are the same as those in the first ferroelectric memory unit 11. Furthermore, the parameters of each film layer of the transistors in the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are the same as those of each film layer of the transistors in the first ferroelectric memory unit 11. The parameters of each film layer of the ferroelectric capacitors in the second ferroelectric memory unit 161 and the third ferroelectric memory unit 162 are also the same as those of each film layer of the ferroelectric capacitors in the first ferroelectric memory unit 11.

[0198] During the reading phase:

[0199] The second voltage generation circuit 164 is used to input a fourth voltage to the third node E, which is the same as the second voltage. The fifth voltage terminal Vss3 is used to input a low level to the second current mirror 163.

[0200] The second ferroelectric storage unit 161 is used to input a second current into the third branch, and the second current indicates that the second ferroelectric storage unit 161 reads a digital signal 1. The third ferroelectric storage unit 162 is used to input a third current into the fourth branch, and the third current indicates that the third ferroelectric storage unit 162 reads a digital signal 0. The third branch receives the second current and the third current, and copies the average value of the second current and the third current to the fourth branch.

[0201] The fourth branch is used to extract charge from the third node E based on the average of the second and third currents, the fourth voltage, and the low level on the fourth branch, so that the potential of the third node E drops from the fourth voltage to the fifth voltage, and the fifth voltage is input to the reference voltage terminal Vref. The fifth voltage is half of the fourth voltage.

[0202] Since the circuit structures of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 are the same as those of the first ferroelectric storage unit 11, the fourth voltage on the third node E is the same as the second voltage on the second node B, and the current of the fourth branch is the average of the second current when the second ferroelectric storage unit 161 reads the digital signal 1 and the third current when the third ferroelectric storage unit 162 reads the digital signal 0. The fourth branch will extract the average charge between the digital signal 0 and the digital signal 1 from the third node E. The remaining fifth voltage of the third node E is also between the third voltage when the first ferroelectric storage unit 11 reads the digital signal 1 and the third voltage when the first ferroelectric storage unit 11 reads the digital signal 0. Therefore, the fifth voltage can be used as a reference voltage to determine whether the data corresponding to the third voltage input from the second node B to the comparison circuit 14 is the digital signal 0 or the digital signal 1.

[0203] Furthermore, since the circuit structures of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 are the same as those of the first ferroelectric storage unit 11, when the performance of the first ferroelectric storage unit 11 changes due to external changes (such as temperature, voltage, etc.), the performance of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 also changes in the same way. Therefore, the reference voltage generation circuit 16 can also be used to realize automatic adjustment under different environments.

[0204] Furthermore, in order to ensure that when external changes (such as temperature, voltage, etc.) cause changes in the performance of the first ferroelectric storage unit 11, the performance of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 also change in the same way, the circuit structure of the second voltage generating circuit 164 can be the same as the circuit structure of the first voltage generating circuit 13. The second ferroelectric storage unit 161 is also electrically connected to the second bit line BL2, and the third ferroelectric storage unit 162 is also electrically connected to the third bit line BL3. Moreover, the parasitic capacitance Cbl2 on the second bit line BL2 and the parasitic capacitance Cbl3 on the third bit line BL3 are the same as the parasitic capacitance on the first bit line BL1.

[0205] However, those skilled in the art should know that although the circuit structure of the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 is the same as that of the first ferroelectric storage unit 11, the digital signals 1 and 0 output by the second ferroelectric storage unit 161 and the third ferroelectric storage unit 162 are not considered as data read out by the storage circuit.

[0206] In some possible implementations, the third branch can replicate the average value of the second and third currents to the fourth branch in the following two ways.

[0207] The first method, such as Figure 7a As shown, the third branch includes the fifth transistor T5 and the sixth transistor T6, and the fourth branch includes the seventh transistor; the channel widths of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all the same. The gates of the fifth transistor T5, the sixth transistor T6, the first terminal of the fifth transistor T5, the first terminal of the sixth transistor T6, and the gate of the seventh transistor T7 are all electrically connected to the output terminals of the second ferroelectric memory cell 161 and the third ferroelectric memory cell 162. The second terminals of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all electrically connected to the fifth voltage terminal Vss3, and the first terminal of the seventh transistor T7 is electrically connected to the third node E.

[0208] According to the transistor current formula, in the third branch, the fifth transistor T5 and the sixth transistor T6 are connected in parallel, and the channel width of the fifth transistor T5 is the same as that of the sixth transistor T6. Therefore, the total current flowing through the third branch is the sum of the second current flowing through the fifth transistor T5 and the third current flowing through the sixth transistor T6. Furthermore, since the channel widths of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all the same, the ratio of the total channel width of the third branch to the channel width of the fourth branch is 2:1. The third branch can replicate the average of the second and third currents to the fourth branch.

[0209] The second method, such as Figure 7b As shown, the third branch includes a fifth transistor T5, and the fourth branch includes a sixth transistor T6. The channel width of the fifth transistor T5 is twice the channel width of the sixth transistor T6. The gates of the fifth transistor T5 and the sixth transistor T6, as well as the first terminal of the fifth transistor T5, are electrically connected to the output terminals of the second ferroelectric memory cell 161 and the third ferroelectric memory cell 162. The second terminals of both the fifth transistor T5 and the sixth transistor T6 are electrically connected to the fifth voltage terminal Vss3, and the first terminal of the sixth transistor T6 is electrically connected to the third node E.

[0210] According to the transistor current formula, the channel width of the fifth transistor T5 is twice the channel width of the sixth transistor T6. Therefore, the current flowing through the sixth transistor T6 is twice the current flowing through the fifth transistor T5. The current in the third branch formed by the fifth transistor T5 is the sum of the second and third currents. Therefore, the third branch can replicate the average of the second and third currents to the fourth branch.

[0211] In some embodiments, after the read phase, a write-back operation can also be performed on the first ferroelectric memory cell. The memory circuit further includes a third switch WR electrically connected between the reference voltage terminal and the first node. During the read phase, the third switch WR is open; during the write-back phase, the third switch WR is open, used to input the write signal of the reference voltage terminal Vref to the first ferroelectric memory cell 11 through the first node A.

[0212] Taking the scenario where the first ferroelectric memory cell 11 reads digital signal 1 and the ferroelectric capacitor undergoes polarization reversal as an example, when reading digital signal 1, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 1. When reading digital signal 0, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 0.

[0213] Taking the scenario where the first ferroelectric memory cell 11 reads digital signal 0 and the ferroelectric capacitor undergoes polarization reversal as an example, when reading digital signal 0, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 0. When reading digital signal 1, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 1.

[0214] Furthermore, if the first ferroelectric memory cell 11 reads digital signal 1 during the read phase, and needs to write digital signal 0 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 during the read phase, and needs to write digital signal 1 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse.

[0215] In this case, instead of writing the signal back to the first ferroelectric storage cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparator circuit), and the signal is rewritten to the first ferroelectric storage cell 11 using the input terminal of the storage circuit.

[0216] The previous section introduced the operating principle of the storage circuit when the initial voltage of the first node A (first bit line BL1) is low and both the first transistor T1 and the second transistor T2 are N-type transistors. The following section, with reference to the accompanying drawings, will introduce the operating principle of the storage circuit when the initial voltage of the first node A (first bit line BL1) is low and both the first transistor T1 and the second transistor T2 are P-type transistors. Unlike when both the first transistor T1 and the second transistor T2 are N-type transistors, when both the first transistor T1 and the second transistor T2 are P-type transistors, the first node A (first bit line BL1) is high during both the pre-charge and read phases, and the board line PL connected to the other end of the first ferroelectric storage cell 11 is low (e.g., 0V). During the reading phase, the first ferroelectric storage cell 11 inputs a read signal to the first node A (first bit line BL1), causing the voltage of the first node A (first bit line BL1) to decrease instead of increase. This results in a decrease in the potential difference between the first bit line BL1 and the plate line PL, reducing the effective ferroelectric switching voltage used to control the switching of the ferroelectric capacitor FE-Cap. Consequently, the switching of the ferroelectric capacitor FE-Cap becomes slower and less complete. This phenomenon is the self-suppression phenomenon when the FeRAM reads the digital signal 1. This phenomenon will affect the uniformity and reliability of the ferroelectric circuit and will also reduce the storage window of the ferroelectric circuit.

[0217] Figure 5a and Figure 5b The circuit diagram and timing diagram of the storage circuit are shown respectively when both the first transistor T1 and the second transistor T2 are P-type transistors. In addition, Figure 5b The timing diagram shown is based on the example where all other transistors in the storage circuit are N-type transistors and the ferroelectric capacitor FE-Cap is flipped to read digital signal 1. The first voltage generation circuit 13 includes an inverter. The timing diagram corresponds to the potential of the gate of each transistor.

[0218] like Figure 5a As shown, the storage circuit includes a first ferroelectric storage unit 11, a first current mirror 12, a first voltage generation circuit 13, a comparison circuit 14, and a first voltage terminal Vdd. The first ferroelectric storage unit 11 and the first branch of the first current mirror 12 are electrically connected to the first node A, and the second branch of the first current mirror 12, the first voltage generation circuit 13, and the comparison circuit 14 are electrically connected to the second node B.

[0219] During the pre-charging phase, the potential of the first node A is the initial voltage, which is a high level.

[0220] During the reading phase, the operation of each module in the storage circuit is as follows:

[0221] The first voltage terminal Vdd is used to input a first voltage to the first current mirror 12, and the first voltage generating circuit 13 is used to input a second voltage to the second node B. Here, the first voltage input from the first voltage terminal Vdd to the first current mirror 12 is at a high level; the second voltage is at a low level, and the second voltage is less than the first voltage; furthermore, the initial voltage is less than the first voltage.

[0222] When the first ferroelectric storage cell 11 reads data, it inputs a charge (negative charge) to the first node A (first bit line BL1). Since the initial voltage is lower than the first voltage, there is a potential difference between the first node A and the first branch, and the first node A draws charge from the first branch. In this way, the first node A receives the charge input from the first ferroelectric storage cell 11 while simultaneously drawing charge from the first branch, thus maintaining the initial voltage at the first node A. That is, the charge input from the first ferroelectric storage cell 11 to the first node A does not accumulate at the first node A.

[0223] Furthermore, according to the working principle of the first current mirror 12, the first branch replicates the first current flowing through the first branch to the second branch. Then, the second branch will change the potential of the second node B from the second voltage to the third voltage based on the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0224] It should be understood that, when the first transistor T1 and the second transistor T2 are identical, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vdd simultaneously inputs a high level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is less than the first voltage, if the first node A draws charge from the first branch, then the second node B will also draw charge from the second branch, so that the potential of the second node B increases from the second voltage to the third voltage.

[0225] During the reading phase, when the polarization of the ferroelectric capacitor FE-Cap in the first ferroelectric storage unit 11 reverses, the first ferroelectric storage unit 11 outputs a polarization current; when the polarization of the ferroelectric capacitor FE-Cap does not reverse, the first ferroelectric storage unit 11 outputs a dielectric current. The amount of charge input to the first node A when the polarization of the ferroelectric capacitor FE-Cap reverses is greater than the amount of charge input to the first node A when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, the amount of charge drawn from the first branch by the first node A when the polarization of the ferroelectric capacitor FE-Cap reverses is greater than the amount of charge drawn from the first branch by the first node A when the polarization of the ferroelectric capacitor FE-Cap does not reverse.

[0226] It is known that when the polarization of a ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the first branch by node A is greater than the amount of charge drawn from the first branch by node A when the polarization of FE-Cap does not reverse. Therefore, when the polarization of FE-Cap reverses, the amount of charge drawn from the second branch by node B is also greater than the amount of charge drawn from the second branch by node B when the polarization of FE-Cap does not reverse. That is, whether the polarization of FE-Cap reverses or not, the third voltage after the second node B draws charge is different.

[0227] Furthermore, the second node B inputs the third voltage to the comparator circuit 14, which can then determine whether the data read from the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0228] In this application, due to whether or not the ferroelectric capacitor FE-Cap undergoes polarization reversal, the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11 is different, the amount of charge input to the first node A is different, the first current flowing through the first branch and the second branch is also different, the amount of charge drawn by the first node A from the first branch is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric storage unit 11 reads different data, the second node B can draw charge from the second branch according to the first current, the first voltage, and the second voltage, so that the potential of the second node B increases from the second voltage to the third voltage. It can be seen that the potential of the second node B, the third voltage, is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11. Therefore, the third voltage can be input to the comparison circuit 14 using the second node B, so that the comparison circuit 14 can determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0229] Meanwhile, whether reading digital signal 1 or digital signal 0, the first line BL1 draws charge from the first branch, keeping the potential on the first line BL1 at the initial voltage. On the one hand, the potential difference between the plate line PL and the first line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the first line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap will not become slower or even insufficient due to the decrease in the potential difference between the plate line PL and the first line BL1, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0230] In some possible implementations, the data read by the first ferroelectric storage unit 11 (digital signal 1 or digital signal 0) is different, and the magnitude of the third voltage is related to the data read when the polarization of the pre-set ferroelectric capacitor FE-Cap reverses.

[0231] For example, suppose that when the first ferroelectric storage unit 11 reads the digital signal 1, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads the digital signal 0, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads the digital signal 1, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second node B will draw a first charge from the second branch, and the potential of the second node B will increase significantly. When the first ferroelectric storage unit 11 reads the digital signal 0, it will output a small dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second node B will draw a second charge from the second branch, and the potential of the second node B will increase slightly. The first charge is greater than the second charge.

[0232] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0233] For example, suppose that when the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads digital signal 0, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second node B will draw a first charge from the second branch, and the potential of the second node B will increase significantly. When the first ferroelectric storage unit 11 reads digital signal 1, it will output a small dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second node B will draw a second charge from the second branch, and the potential of the second node B will increase slightly. The first charge is greater than the second charge.

[0234] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0235] In some embodiments, in the first current mirror 12, since the current input to the first branch and the current output from the second branch are always the same, when the first current mirror 12 is operating, in order to ensure that the first branch replicates the same polarization current or dielectric current to the second branch, the initial current flowing through the first branch should be the same as the initial current flowing through the second branch before the polarization current or dielectric current flows to the first branch. However, the current in the first branch is easily affected by the first node A, and the current in the second branch is easily affected by the second node B, which may cause the initial current in the first branch to be different from the initial current flowing through the second branch.

[0236] Based on this, the storage circuit in this embodiment further includes a third transistor T3 and a fourth transistor T4. The third transistor T3 is connected in series between the first node A and the first transistor T1 (the first terminal of the third transistor T3 is electrically connected to the first node A, and the second terminal of the third transistor T3 is electrically connected to the first terminal of the first transistor T1). The fourth transistor T4 is connected in series between the second node B and the second transistor T2 (the first terminal of the fourth transistor T4 is electrically connected to the second node B, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the second transistor T2). Furthermore, both the third transistor T3 and the fourth transistor T4 are P-type transistors.

[0237] During the reading phase, both the third transistor T3 and the fourth transistor T4 are turned on. The second terminal of the third transistor T3 inputs a clamping voltage to the first terminal of the first transistor T1, and the second terminal of the fourth transistor T4 inputs a clamping voltage to the first terminal of the second transistor T2. This makes the potential of the connection node C between the third transistor T3 and the first transistor T1 the same as the potential of the connection node D between the fourth transistor T4 and the second transistor T2. This ensures that, with the first transistor T1 and the second transistor T2 having the same resistance, the initial current flowing through the first branch is the same as the initial current flowing through the second branch.

[0238] Furthermore, due to the presence of a clamping voltage, the voltage of the first current mirror 12 stops increasing after reaching a certain value. Therefore, if the first node A draws charge from the first branch, causing the voltage of the first current mirror 12 to saturate, and the data reading phase continues, the first node A will no longer draw charge from the first branch. A small amount of charge will still be drawn from the first line BL1, resulting in a potential on the first line BL1 that is lower than the initial voltage, thus reducing the potential difference between the plate line PL and the first line BL1. Based on this, the storage circuit may not include the third transistor T3 and the fourth transistor T4.

[0239] Of course, it should be understood that even if the storage circuit includes the third transistor T3 and the fourth transistor T4, the first node A can still draw charge from the first branch. Therefore, compared with the prior art, it is still possible to increase the potential difference between the board line PL and the first line BL1, which can improve the self-suppression phenomenon.

[0240] In some embodiments, the first voltage generation circuit 13 includes a second voltage terminal V_boost, which is used to input voltage to the second node B during the reading phase. However, due to the presence of parasitic capacitance, the voltage value received by the second node B will not reach the voltage value output by the second voltage terminal V_boost. Therefore, the first voltage generation circuit 13 may further include a tank capacitor (TC), which is electrically connected between the second node B and the second voltage terminal V_boost. The second voltage terminal V_boost is electrically connected to the first electrode of the tank capacitor TC, and the second node B is electrically connected to the second electrode of the tank capacitor TC. In this way, the first voltage generation circuit 13 can first input a second voltage to the first electrode, which then couples the second voltage to the second electrode and the second node B. This improves the problem that the voltage output by the second voltage terminal V_boost is largely diverted by parasitic capacitance, causing the voltage value received by the second node B to not reach the voltage value output by the second voltage terminal V_boost.

[0241] Furthermore, since the first electrode and the second electrode of the energy storage capacitor TC are isolated by the insulating material between them, after the first electrode couples the second voltage to the second electrode and the second node B, even if the second voltage terminal V_boost still provides the second voltage to the first electrode, the potential of the second electrode and the second node B is no longer affected by the second voltage terminal V_boost and the first electrode. Therefore, after the second node B draws charge from the second branch, the potential on the second node B rises, instead of remaining at the initial voltage like the first node A, even if it draws charge from the first branch.

[0242] In some possible ways of implementation, such as Figure 8 As shown, signal loss usually occurs during transmission. Based on this, the first voltage generation circuit 13 may also include an inverter 131, which is electrically connected between the second voltage terminal V_boost and the storage capacitor TC to enhance the signal.

[0243] It should be noted here that the second voltage required by the second node B is a high level. If the first voltage generation circuit 13 does not include the inverter 131, the voltage output by the second voltage terminal V_boost is also a low level; if the first voltage generation circuit 13 includes the inverter 131, the voltage output by the second voltage terminal V_boost is a high level.

[0244] In some embodiments, such as Figure 8 As shown, the storage circuit also includes a third voltage terminal V3 and a pre-charge circuit 15, which is electrically connected between the third voltage terminal V3 and the first node A. During the pre-charge phase before the reading phase, the third voltage terminal V3 is used to input an initial voltage to the first bit line BL1 through the pre-charge circuit 15, preparing for the reading phase. Furthermore, during the reading phase, by controlling the voltage on the board line PL, the potential difference between the board line PL and the first bit line BL1 can be controlled, thereby controlling the first ferroelectric storage cell 11 to read data.

[0245] Optionally, the pre-charge circuit 15 includes a first switch ISO and a second switch PCH. The first switch ISO is electrically connected between the input terminal of the first branch and the output terminal of the second branch, and the second switch PCH is electrically connected between the third voltage terminal V3 and the second node B. During the pre-charge phase, both the first switch ISO and the second switch PCH are turned on, and the third voltage terminal V3 inputs an initial voltage to the first bit line BL1 through the second switch PCH and the first switch ISO.

[0246] In some possible implementations, during the pre-charging phase, after pre-charging the first line BL1 using the third voltage terminal V3, the second node B can also be pre-charged using the third voltage terminal V3. In this case, the second switch PCH is turned on, and the third voltage terminal V3 pre-charges the second node B to the charging voltage (low level) through the second switch PCH. Simultaneously, the first switch ISO is turned off; therefore, the charging voltage of the third voltage terminal V3 does not affect the potential on the first line BL1.

[0247] During the pre-charging phase, the third voltage terminal V3 inputs a charging voltage to the second node B; during the reading phase, the second voltage terminal V_boost inputs a second voltage to the second node B. Thus, before the second node B is charged by the second branch, the voltage on the second node B is the sum of the charging voltage and the second voltage. This embodiment of the application inputs voltage to the second node B multiple times to ensure that the voltage on the second node B is sufficiently small, thereby increasing the difference between the third voltage of the second node B when reading digital signal 1 and the third voltage of the second node B when reading digital signal 0, and increasing the MW of the storage circuit.

[0248] In other embodiments, as mentioned above, in the prior art, the comparator circuit 14 reads the digital signal 1 or digital signal 0 by acquiring the charge on the first bit line BL1. The first bit line BL1 is usually connected to multiple ferroelectric memory cells and is relatively long. In the memory chip, the first bit line BL1 inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures. The parasitic capacitance Cbl1 has a negative impact on the MW of the memory circuit.

[0249] According to the formula charge (Q) = voltage (U) × capacitance (C), the larger the parasitic capacitance Cbl1 on the first line BL1, the smaller the voltage U on the first line BL1, the larger the potential difference between the plate line PL and the first line BL1, the larger the effective switching voltage of the ferroelectric capacitor FE-Cap, and the more fully the ferroelectric capacitor FE-Cap switches.

[0250] As can be seen, the presence of parasitic capacitance Cbl1 causes a trade-off between the effective switching voltage of the storage circuit MW and the ferroelectric capacitor FE-Cap, thus limiting the design.

[0251] In the scheme of this application, the comparator circuit 14 no longer reads the digital signal 1 or digital signal 0 by acquiring the voltage on the first bit line BL1, but instead reads the digital signal 1 or digital signal 0 by acquiring the voltage on the second node B. In this way, even if the first bit line BL1 has a large parasitic capacitance Cbl1, it will not have a negative impact on the MW of the storage circuit. At the same time, according to the formula of charge (Q) = voltage (U) × capacitance (C), the parasitic capacitance Cbl1 of the first bit line BL1 can also increase the effective switching voltage, so that the ferroelectric capacitor FE-Cap can switch more fully.

[0252] Based on this, during the reading phase, the embodiments of this application can also disconnect the first switch ISO and the second switch PCH. In this way, the second node B is isolated (the second node B is isolated from the first node A through the first switch ISO, and the second node B is isolated from the third voltage terminal V3 through the second switch PCH). Therefore, the parasitic capacitance of the second node B is very small, and its impact on the MW of the storage circuit is also very small.

[0253] In some embodiments, such as Figure 6 As shown, the storage circuit also includes a reference voltage terminal Vref. During the reading phase, the reference voltage terminal Vref can input a reference voltage to the comparator circuit 14. The comparator circuit 14 determines whether the data read from the first ferroelectric storage cell 11 is a digital signal 0 or a digital signal 1 based on the received third voltage and the reference voltage.

[0254] The comparison circuit 14 of this application should combine the data read when the polarization of the set ferroelectric capacitor FE-Cap reverses, and determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the received third voltage and reference voltage.

[0255] The working principle of the comparator circuit 14 for reading data will be explained in detail below with reference to the circuit structure of the comparator circuit 14.

[0256] like Figure 6As shown, the comparator circuit 14 includes a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, and a ground terminal Vss1. The storage circuit also includes an output terminal OUT. During the read phase, the fourth voltage terminal V4 is at a high level, and the ground terminal Vss1 is at a low level.

[0257] The gates of the first P-type transistor P1 and the first N-type transistor N1 are electrically connected to the second terminal of the second P-type transistor, the first terminal of the second N-type transistor, and the reference voltage terminal Vref. The first terminal of the first P-type transistor P1 is electrically connected to the fourth voltage terminal V4. The second terminal of the first P-type transistor P1 is electrically connected to the first terminal of the first N-type transistor N1 and the output terminal OUT. The second terminal of the first N-type transistor N1 is electrically connected to the ground terminal Vss1. The gates of the second P-type transistor P2 and the second N-type transistor N2 are electrically connected to the second node B. The first terminal of the second P-type transistor P2 is electrically connected to the fourth voltage terminal V4. The second terminal of the second N-type transistor N2 is electrically connected to the ground terminal Vss1. The output terminal OUT is electrically connected between the second node B and the second terminal of the first P-type transistor P1 and the first terminal of the first N-type transistor N1.

[0258] For example, if the first ferroelectric storage unit 11 is set to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 1, the third voltage when reading digital signal 1 is greater than the third voltage when reading digital signal 0.

[0259] When reading digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss1 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0260] When reading digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage at the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss1 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0261] For example, if the first ferroelectric storage unit 11 is set to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 0, the third voltage when reading digital signal 0 is greater than the third voltage when reading digital signal 1.

[0262] When reading digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss1 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0263] When reading digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss1 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0264] In some embodiments, after the read phase, a write-back operation can also be performed on the first ferroelectric memory cell. The memory circuit further includes a third switch WR electrically connected between the reference voltage terminal and the first node. During the read phase, the third switch WR is open; during the write-back phase, the third switch WR is open, used to input the write signal of the reference voltage terminal Vref to the first ferroelectric memory cell 11 through the first node A.

[0265] Taking the first ferroelectric storage cell 11 reading digital signal 1 and the ferroelectric capacitor undergoing polarization reversal as an example, when reading digital signal 1, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first bit line BL1 through the third switch WR, and then inputs a high level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 1. When reading digital signal 0, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first bit line BL1 through the third switch WR, and then inputs a low level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 0.

[0266] Taking the first ferroelectric storage cell 11 reading digital signal 0 and the ferroelectric capacitor undergoing polarization reversal as an example, when reading digital signal 0, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first bit line BL1 through the third switch WR, and then inputs a high level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 0. When reading digital signal 1, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first bit line BL1 through the third switch WR, and then inputs a low level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 1.

[0267] Furthermore, when both the first transistor T1 and the second transistor T2 are P-type transistors, the memory chip may also include a reference voltage generation circuit 16, which provides a reference voltage to the comparator circuit 14. The circuit connection and operating principle of the reference voltage generation circuit 16 are the same as those in the previous embodiment when both the first transistor T1 and the second transistor T2 are N-type transistors, and will not be described again here.

[0268] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 during the read phase, and needs to write digital signal 0 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 during the read phase, and needs to write digital signal 1 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse.

[0269] In this case, instead of writing the signal back to the first ferroelectric storage cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparator circuit), and the signal is rewritten to the first ferroelectric storage cell 11 using the input terminal of the storage circuit.

[0270] In another embodiment, this application also provides a method for controlling a storage circuit, such as... Figures 4a-4b , Figure 6 , Figures 7a-7b As shown, the circuit structure of the storage circuit is the same as that of the storage circuit in the previous embodiment, and will not be described again here. Both the first transistor T1 and the second transistor T2 are N-type transistors.

[0271] During the pre-charge phase, the second switch PCH and the first switch ISO are turned on. The third voltage terminal V3 inputs an initial voltage of 0V to the first bit line BL1 through the second switch PCH and the first switch ISO, preparing for the reading phase. The initial voltage is low, for example, 0V. Then, the second switch PCH is turned on, the first switch ISO is turned off, and the third voltage terminal V3 can be used to pre-charge the second node B.

[0272] During the reading phase, the first transistor T1 of the first branch and the second transistor T2 of the second branch in the first current mirror 12 are both turned on. In the case that the storage circuit includes the third transistor T3 and the fourth transistor T4, the third transistor T3 and the fourth transistor T4 are also turned on.

[0273] Furthermore, the first voltage terminal Vss1 inputs a first voltage to the first current mirror 12, and the first voltage generating circuit 13 inputs a second voltage to the second node B. Here, the first voltage terminal Vss1 is grounded, and the first voltage input to the first current mirror 12 is at a low level; the second voltage is at a high level and is greater than the first voltage.

[0274] When the first ferroelectric storage cell 11 reads data, it inputs a charge (positive charge) to the first node A (first bit line BL1). Since the initial voltage is greater than the first voltage, a potential difference is generated between the first node A and the first branch, and the first branch draws charge from the first node A. Thus, while the first node A receives the charge input from the first ferroelectric storage cell 11, it is also having charge drawn from it by the first branch, thereby maintaining the initial voltage at the first node A. That is, the charge input from the first ferroelectric storage cell 11 to the first node A does not accumulate at the first node A.

[0275] During the reading phase, when the ferroelectric capacitor FE-Cap in the first ferroelectric storage unit 11 undergoes polarization reversal, the first ferroelectric storage unit 11 outputs a polarization current; when the ferroelectric capacitor FE-Cap does not undergo polarization reversal, the first ferroelectric storage unit 11 outputs a dielectric current. The amount of charge input to the first node A when the ferroelectric capacitor FE-Cap undergoes polarization reversal is greater than the amount of charge input to the first node A when the ferroelectric capacitor FE-Cap does not undergo polarization reversal. Therefore, the amount of charge extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap undergoes polarization reversal is greater than the amount of charge extracted from the first node A by the first branch when the ferroelectric capacitor FE-Cap does not undergo polarization reversal.

[0276] Furthermore, according to the working principle of the first current mirror 12, the first branch replicates the first current flowing through the first branch to the second branch. Then, the second branch will change the potential of the second node B from the second voltage to the third voltage based on the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0277] It should be understood that, when the first transistor T1 and the second transistor T2 are identical, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vss1 simultaneously inputs a low level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is greater than the first voltage, if the first branch draws charge from the first node A, the second branch will also draw charge from the second node B, so that the potential of the second node B decreases from the second voltage to the third voltage.

[0278] It is known that when the polarization of the ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the first node A by the first branch is greater than the amount of charge drawn from the first node A by the first branch when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, when the polarization of the ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the second node B by the second branch is also greater than the amount of charge drawn from the second node B by the second branch when the polarization of the ferroelectric capacitor FE-Cap does not reverse. That is, whether the polarization of the ferroelectric capacitor FE-Cap reverses or not, the remaining third voltage after the charge is drawn from the second node B is different.

[0279] Furthermore, the second node B inputs the remaining third voltage to the comparator circuit 14, which can then determine whether the data read from the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0280] In this application, due to whether or not the ferroelectric capacitor FE-Cap undergoes polarization reversal, the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11 is different, the amount of charge input to the first node A is different, the first current flowing through the first branch and the second branch is also different, the amount of charge drawn by the first branch from the first node A is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric storage unit 11 reads different data, the second branch can draw charge from the second node B according to the first current, the first voltage, and the second voltage, so that the potential of the second node B drops from the second voltage to the third voltage. It can be seen that the remaining potential third voltage on the second node B is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11. Therefore, the third voltage can be input to the comparison circuit 14 using the second node B, so that the comparison circuit 14 can determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0281] Meanwhile, whether reading digital signal 1 or digital signal 0, the charge on the first line BL1 is extracted by the first branch, keeping the potential on the first line BL1 at 0V (or close to 0V). On the one hand, the potential difference between the plate line PL and the first line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the first line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap will not become slower or even insufficient due to the decrease in the potential difference between the plate line PL and the first line BL1, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0282] In some possible implementations, the data read by the first ferroelectric storage unit 11 (digital signal 1 or digital signal 0) is different, and the magnitude of the third voltage is related to the data read when the polarization of the pre-set ferroelectric capacitor FE-Cap reverses.

[0283] For example, suppose that when the first ferroelectric storage unit 11 reads the digital signal 1, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads the digital signal 0, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads the digital signal 1, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second branch will draw a first charge from the second node B, and the potential of the second node B will decrease significantly. When the first ferroelectric storage unit 11 reads the digital signal 0, it will output a small amount of dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second branch will draw a second charge from the second node B, and the potential of the second node B will decrease slightly. The first charge is greater than the second charge.

[0284] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0285] For example, suppose that when the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads digital signal 0, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second branch will draw a first charge from the second node B, and the potential of the second node B will decrease significantly. When the first ferroelectric storage unit 11 reads digital signal 1, it will output a small amount of dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second branch will draw a second charge from the second node B, and the potential of the second node B will decrease slightly. The first charge is greater than the second charge.

[0286] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0287] Next, during the reading phase, the reference voltage terminal Vref can input a reference voltage to the comparator circuit 14. The comparator circuit 14 determines whether the data read from the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the received third voltage and the reference voltage.

[0288] Contrary to existing technologies, if the first ferroelectric memory cell 11 is configured to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 1, the third voltage in existing technologies when reading digital signal 1 is greater than the third voltage when reading digital signal 0; while in this application, the third voltage when reading digital signal 1 is less than the third voltage when reading digital signal 0. If the first ferroelectric memory cell 11 is configured to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 0, the third voltage in existing technologies when reading digital signal 0 is greater than the third voltage when reading digital signal 1; while in this application, the third voltage when reading digital signal 0 is less than the third voltage when reading digital signal 1.

[0289] Based on this, the comparison circuit 14 of this application should combine the data read when the polarization of the set ferroelectric capacitor FE-Cap reverses, and determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 according to the received third voltage and reference voltage.

[0290] The working principle of the comparator circuit 14 for reading data will be explained in detail below with reference to the circuit structure of the comparator circuit 14.

[0291] like Figure 6 As shown, the comparator circuit 14 includes a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, and a ground terminal Vss2. The storage circuit also includes an output terminal OUT. During the read phase, the fourth voltage terminal V4 is at a high level, and the ground terminal Vss2 is at a low level.

[0292] The gates of the first P-type transistor P1 and the first N-type transistor N1 are electrically connected to the second terminal of the second P-type transistor, the first terminal of the second N-type transistor, and the reference voltage terminal Vref. The first terminal of the first P-type transistor P1 is electrically connected to the fourth voltage terminal V4. The second terminal of the first P-type transistor P1 is electrically connected to the first terminal of the first N-type transistor N1 and the output terminal OUT. The second terminal of the first N-type transistor N1 is electrically connected to the ground terminal Vss2. The gates of the second P-type transistor P2 and the second N-type transistor N2 are electrically connected to the second node B. The first terminal of the second P-type transistor P2 is electrically connected to the fourth voltage terminal V4. The second terminal of the second N-type transistor N2 is electrically connected to the ground terminal Vss2. The output terminal OUT is electrically connected between the second node B and the second terminal of the first P-type transistor P1 and the first terminal of the first N-type transistor N1.

[0293] For example, if the first ferroelectric storage unit 11 is set to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 1, the third voltage when reading digital signal 1 is less than the third voltage when reading digital signal 0.

[0294] When reading digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss2 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0295] When reading digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss2 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0296] For example, if the first ferroelectric storage cell 11 is set to reverse polarization when reading digital signal 0, the third voltage when reading digital signal 0 is less than the third voltage when reading digital signal 1.

[0297] When reading digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss2 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0298] When reading digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss2 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0299] During the reverse writing phase, the third switch WR is turned on, and the write signal of the reference voltage terminal Vref is input to the first ferroelectric memory cell 11 through the first node A.

[0300] Taking the scenario where the first ferroelectric memory cell 11 reads digital signal 1 and the ferroelectric capacitor undergoes polarization reversal as an example, when reading digital signal 1, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 1. When reading digital signal 0, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 0.

[0301] Taking the scenario where the first ferroelectric memory cell 11 reads digital signal 0 and the ferroelectric capacitor undergoes polarization reversal as an example, when reading digital signal 0, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 0. When reading digital signal 1, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first ferroelectric memory cell 11 through the third switch WR, completing the reverse writing of digital signal 1.

[0302] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the previous embodiment when the initial voltage is low, and will not be repeated here.

[0303] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 during the read phase, and needs to write digital signal 0 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 during the read phase, and needs to write digital signal 1 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse.

[0304] In this case, instead of writing the signal back to the first ferroelectric storage cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparator circuit), and the signal is rewritten to the first ferroelectric storage cell 11 using the input terminal of the storage circuit.

[0305] The previous section introduced the operating principle of the storage circuit when the initial voltage of the first node A (first bit line BL1) is low and both the first transistor T1 and the second transistor T2 are N-type transistors. The following section, with reference to the accompanying drawings, will introduce the operating principle of the storage circuit when the initial voltage of the first node A (first bit line BL1) is low and both the first transistor T1 and the second transistor T2 are P-type transistors. Unlike when both the first transistor T1 and the second transistor T2 are N-type transistors, when both the first transistor T1 and the second transistor T2 are P-type transistors, the first node A (first bit line BL1) is high during both the pre-charge and read phases, and the board line PL connected to the other end of the first ferroelectric storage cell 11 is low (e.g., 0V). During the reading phase, the first ferroelectric storage cell 11 inputs a read signal to the first node A (first bit line BL1), causing the voltage of the first node A (first bit line BL1) to decrease instead of increase. This results in a decrease in the potential difference between the first bit line BL1 and the plate line PL, reducing the effective ferroelectric switching voltage used to control the switching of the ferroelectric capacitor FE-Cap. Consequently, the switching of the ferroelectric capacitor FE-Cap becomes slower and less complete. This phenomenon is the self-suppression phenomenon when the FeRAM reads the digital signal 1. This phenomenon will affect the uniformity and reliability of the ferroelectric circuit and will also reduce the storage window of the ferroelectric circuit.

[0306] like Figures 5a-5b , Figure 8 As shown, the circuit structure of the storage circuit is the same as that of the storage circuit in the previous embodiment, and will not be described again here. Both the first transistor T1 and the second transistor T2 are P-type transistors.

[0307] During the pre-charge phase, the second switch PCH and the first switch ISO are turned on, and the third voltage terminal V3 inputs an initial voltage to the first bit line BL1 through the second switch PCH and the first switch ISO, preparing for the reading phase. Then, the second switch PCH is turned on, the first switch ISO is turned off, and the third voltage terminal V3 can be used to pre-charge the second node B.

[0308] During the reading phase, the first transistor T1 of the first branch and the second transistor T2 of the second branch in the first current mirror 12 are both turned on. In the case that the storage circuit includes the third transistor T3 and the fourth transistor T4, the third transistor T3 and the fourth transistor T4 are also turned on.

[0309] Furthermore, the first voltage terminal Vdd inputs a first voltage to the first current mirror 12, and the first voltage generating circuit 13 is used to input a second voltage to the second node B. Here, the first voltage input from the first voltage terminal Vdd to the first current mirror 12 is at a high level; the second voltage is at a low level and is less than the first voltage.

[0310] When the first ferroelectric storage cell 11 reads data, it inputs a charge (negative charge) to the first node A (first bit line BL1). Since the initial voltage is lower than the first voltage, there is a potential difference between the first node A and the first branch, and the first node A draws charge from the first branch. In this way, the first node A receives the charge input from the first ferroelectric storage cell 11 while simultaneously drawing charge from the first branch, thus maintaining the initial voltage at the first node A. That is, the charge input from the first ferroelectric storage cell 11 to the first node A does not accumulate at the first node A.

[0311] During the reading phase, when the ferroelectric capacitor FE-Cap in the first ferroelectric storage unit 11 undergoes polarization reversal, the first ferroelectric storage unit 11 outputs a polarization current; when the ferroelectric capacitor FE-Cap does not undergo polarization reversal, the first ferroelectric storage unit 11 outputs a dielectric current. The amount of charge input to the first node A when the ferroelectric capacitor FE-Cap undergoes polarization reversal is greater than the amount of charge input to the first node A when the ferroelectric capacitor FE-Cap does not undergo polarization reversal. Therefore, the amount of charge drawn from the first branch by the first node A when the ferroelectric capacitor FE-Cap undergoes polarization reversal is greater than the amount of charge drawn from the first branch by the first node A when the ferroelectric capacitor FE-Cap does not undergo polarization reversal.

[0312] Furthermore, according to the working principle of the first current mirror 12, the first branch replicates the first current flowing through the first branch to the second branch. Then, the second branch will change the potential of the second node B from the second voltage to the third voltage based on the first current, the first voltage input to the first current mirror, and the second voltage of the second node B.

[0313] It should be understood that, when the first transistor T1 and the second transistor T2 are identical, the current flowing through the first transistor T1 and the second transistor T2 is the first current, the first voltage terminal Vdd simultaneously inputs a high level to the first transistor T1 and the second transistor T2, and the second voltage of the second node B is less than the first voltage, if the first node A draws charge from the first branch, then the second node B will also draw charge from the second branch, so that the potential of the second node B increases from the second voltage to the third voltage.

[0314] It is known that when the polarization of a ferroelectric capacitor FE-Cap reverses, the amount of charge drawn from the first branch by node A is greater than the amount of charge drawn from the first branch by node A when the polarization of FE-Cap does not reverse. Therefore, when the polarization of FE-Cap reverses, the amount of charge drawn from the second branch by node B is also greater than the amount of charge drawn from the second branch by node B when the polarization of FE-Cap does not reverse. That is, whether the polarization of FE-Cap reverses or not, the third voltage after the second node B draws charge is different.

[0315] Furthermore, the second node B inputs the third voltage to the comparator circuit 14, which can then determine whether the data read from the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0316] In this application, due to whether or not the ferroelectric capacitor FE-Cap undergoes polarization reversal, the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11 is different, the amount of charge input to the first node A is different, the first current flowing through the first branch and the second branch is also different, the amount of charge drawn by the first node A from the first branch is different, and the potential difference between the second node B and the second branch is different. Therefore, when the first ferroelectric storage unit 11 reads different data, the second node B can draw charge from the second branch according to the first current, the first voltage, and the second voltage, so that the potential of the second node B increases from the second voltage to the third voltage. It can be seen that the potential of the second node B, the third voltage, is related to the data (digital signal 1 or digital signal 0) read by the first ferroelectric storage unit 11. Therefore, the third voltage can be input to the comparison circuit 14 using the second node B, so that the comparison circuit 14 can determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the third voltage.

[0317] Meanwhile, whether reading digital signal 1 or digital signal 0, the first line BL1 draws charge from the first branch, keeping the potential on the first line BL1 at the initial voltage. On the one hand, the potential difference between the plate line PL and the first line BL1 is stabilized at a fixed value, which does not affect the polarization reversal of the ferroelectric capacitor FE-Cap. On the other hand, the potential difference between the plate line PL and the first line BL1 is always at a large value, so that the polarization reversal of the ferroelectric capacitor FE-Cap will not become slower or even insufficient due to the decrease in the potential difference between the plate line PL and the first line BL1, thus preventing the self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0318] In some possible implementations, the data read by the first ferroelectric storage unit 11 (digital signal 1 or digital signal 0) is different, and the magnitude of the third voltage is related to the data read when the polarization of the pre-set ferroelectric capacitor FE-Cap reverses.

[0319] For example, suppose that when the first ferroelectric storage unit 11 reads the digital signal 1, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads the digital signal 0, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads the digital signal 1, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second node B will draw a first charge from the second branch, and the potential of the second node B will increase significantly. When the first ferroelectric storage unit 11 reads the digital signal 0, it will output a small dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second node B will draw a second charge from the second branch, and the potential of the second node B will increase slightly. The first charge is greater than the second charge.

[0320] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0321] For example, suppose that when the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor does not undergo polarization reversal. Then, when the first ferroelectric storage unit 11 reads digital signal 0, it will output a polarization current. This polarization current flows through the first node A to the first branch. The first branch copies a polarization current of the same magnitude to the second branch. Influenced by the polarization current, the first voltage, and the second voltage, the second node B will draw a first charge from the second branch, and the potential of the second node B will increase significantly. When the first ferroelectric storage unit 11 reads digital signal 1, it will output a small dielectric current. This dielectric current flows through the first node A to the first branch. The first branch copies a dielectric current of the same magnitude to the second branch. Influenced by the dielectric current, the first voltage, and the second voltage, the second node B will draw a second charge from the second branch, and the potential of the second node B will increase slightly. The first charge is greater than the second charge.

[0322] In this case, the third voltage when the first ferroelectric storage unit 11 reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit 11 reads digital signal 0.

[0323] Next, during the reading phase, the reference voltage terminal Vref can input a reference voltage to the comparator circuit 14. The comparator circuit 14 determines whether the data read from the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the received third voltage and the reference voltage.

[0324] The comparison circuit 14 of this application should combine the data read when the polarization of the set ferroelectric capacitor FE-Cap reverses, and determine whether the data read by the first ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the received third voltage and reference voltage.

[0325] The working principle of the comparator circuit 14 for reading data will be explained in detail below with reference to the circuit structure of the comparator circuit 14.

[0326] like Figure 6 As shown, the comparator circuit 14 includes a fourth voltage terminal V4, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, a second N-type transistor N2, and a ground terminal Vss1. The storage circuit also includes an output terminal OUT. During the read phase, the fourth voltage terminal V4 is at a high level, and the ground terminal Vss1 is at a low level.

[0327] The gates of the first P-type transistor P1 and the first N-type transistor N1 are electrically connected to the second terminal of the second P-type transistor, the first terminal of the second N-type transistor, and the reference voltage terminal Vref. The first terminal of the first P-type transistor P1 is electrically connected to the fourth voltage terminal V4. The second terminal of the first P-type transistor P1 is electrically connected to the first terminal of the first N-type transistor N1 and the output terminal OUT. The second terminal of the first N-type transistor N1 is electrically connected to the ground terminal Vss1. The gates of the second P-type transistor P2 and the second N-type transistor N2 are electrically connected to the second node B. The first terminal of the second P-type transistor P2 is electrically connected to the fourth voltage terminal V4. The second terminal of the second N-type transistor N2 is electrically connected to the ground terminal Vss1. The output terminal OUT is electrically connected between the second node B and the second terminal of the first P-type transistor P1 and the first terminal of the first N-type transistor N1.

[0328] For example, if the first ferroelectric storage unit 11 is set to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 1, the third voltage when reading digital signal 1 is greater than the third voltage when reading digital signal 0.

[0329] When reading digital signal 0, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss1 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0330] When reading digital signal 1, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage at the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss1 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0331] For example, if the first ferroelectric storage unit 11 is set to reverse the polarization of the ferroelectric capacitor FE-Cap when reading digital signal 0, the third voltage when reading digital signal 0 is greater than the third voltage when reading digital signal 1.

[0332] When reading digital signal 1, the third voltage of the second node B is low, and the second P-type transistor P2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second P-type transistor P2. The second P-type transistor P2 can charge more quickly and transmit the high level of the fourth voltage terminal V4 to the gate of the first N-type transistor N1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref high. Further, the first N-type transistor N1 is turned on, and the ground terminal Vss1 transmits a low level to the output terminal OUT through the first N-type transistor N1. The output terminal OUT outputs a low level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 1.

[0333] When reading digital signal 0, the third voltage of the second node B is high, and the second N-type transistor N2 is turned on. The reference voltage of the reference voltage terminal Vref is greater than the third voltage when the first ferroelectric memory cell 11 reads digital signal 0, but less than the third voltage when the first ferroelectric memory cell 11 reads digital signal 1. Therefore, even though the reference voltage terminal Vref is electrically connected to the gates of the first P-type transistor P1 and the first N-type transistor N1, the conduction level of the first P-type transistor P1 and the first N-type transistor N1 is less than that of the second N-type transistor N2. The second N-type transistor N2 can charge more quickly and transmit the low level of the ground terminal Vss1 to the gate of the first P-type transistor P1 and the reference voltage terminal Vref, pulling the reference voltage terminal Vref low. Further, the first P-type transistor P1 is turned on, and the fourth voltage terminal V4 transmits a high level to the output terminal OUT through the first P-type transistor P1. The output terminal OUT outputs a high level, confirming that the data read by the first ferroelectric memory cell 11 is digital signal 0.

[0334] During the reverse writing phase, the third switch WR is turned on, and the write signal of the reference voltage terminal Vref is input to the first ferroelectric memory cell 11 through the first node A.

[0335] Taking the first ferroelectric storage cell 11 reading digital signal 1 and the ferroelectric capacitor undergoing polarization reversal as an example, when reading digital signal 1, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first bit line BL1 through the third switch WR, and then inputs a high level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 1. When reading digital signal 0, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first bit line BL1 through the third switch WR, and then inputs a low level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 0.

[0336] Taking the first ferroelectric storage cell 11 reading digital signal 0 and the ferroelectric capacitor undergoing polarization reversal as an example, when reading digital signal 0, the reference voltage terminal Vref is at a low level; during the reverse writing stage, the reference voltage terminal Vref inputs a low level to the first bit line BL1 through the third switch WR, and then inputs a high level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 0. When reading digital signal 1, the reference voltage terminal Vref is at a high level; during the reverse writing stage, the reference voltage terminal Vref inputs a high level to the first bit line BL1 through the third switch WR, and then inputs a low level to the board line PL. The first bit line BL1 and the board line PL form a potential difference across the two ends of the first ferroelectric storage cell 11, completing the reverse writing of digital signal 1.

[0337] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the previous embodiment when the initial voltage is high, and will not be repeated here.

[0338] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 during the read phase, and needs to write digital signal 0 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 during the read phase, and needs to write digital signal 1 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse.

[0339] In this case, instead of writing the signal back to the first ferroelectric storage cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparator circuit), and the signal is rewritten to the first ferroelectric storage cell 11 using the input terminal of the storage circuit.

[0340] In yet another embodiment, this application also provides a storage circuit, such as Figure 9a and Figure 9b As shown, the storage circuit includes a ferroelectric storage cell 11, a clamping circuit 12, a voltage generating circuit 13, and a comparator circuit 14. The output terminal of the ferroelectric storage cell 11 is electrically connected to one end of the clamping circuit 12 at a first node A. The other end of the clamping circuit 12, the voltage generating circuit 13, and the output terminal of the comparator circuit 14 are electrically connected to a second node B. The output terminal of the comparator circuit 14 is electrically connected to the output terminal OUT of the storage circuit.

[0341] The working process of the storage circuit includes:

[0342] During the pre-charging phase, the voltage of the first node is charged to 0V. The voltage generation circuit 13 is used to provide a first voltage to the second node B, which is less than 0V. That is, the potential of the first node A is higher than the potential of the second node B.

[0343] During the reading phase:

[0344] Ferroelectric storage cell 11 is used to input a second voltage to the first node A. Since the potential of the first node A is higher than that of the second node B, the ferroelectric storage cell 11 is used to input a second voltage to the second node B through the first node A and the clamping circuit 12. The second voltage is greater than 0V. Although the ferroelectric storage cell 11 inputs a second voltage to the first node A, the clamping circuit 12 clamps the potential of the first node A at the initial voltage. Therefore, the second voltage output by the ferroelectric storage cell 11 passes through the first node A but does not accumulate at the first node A, and the voltage of the first node A remains the initial voltage.

[0345] During the reading phase, when the polarization of the ferroelectric capacitor FE-Cap in the ferroelectric storage cell 11 reverses, the first ferroelectric storage cell 11 outputs a polarization current; when the polarization of the ferroelectric capacitor FE-Cap does not reverse, the ferroelectric storage cell 11 outputs a dielectric current. The second voltage output when the polarization of the ferroelectric capacitor FE-Cap reverses is greater than the second voltage output when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, when the polarization of the ferroelectric capacitor FE-Cap reverses, the ferroelectric storage cell 11 inputs a second voltage to the second node B through the first node A and the clamping circuit 12, which is greater than the second voltage input to the second node B through the first node A and the clamping circuit 12 when the polarization of the ferroelectric capacitor FE-Cap does not reverse.

[0346] Regardless of whether the polarization of the ferroelectric capacitor FE-Cap reverses, the voltage at the second node B increases, from the original first voltage to the sum of the first and second voltages.

[0347] The voltage generating circuit 13 is also used to input a third voltage to the second node B, changing the potential of the second node B to a fourth voltage. The voltage generating circuit 13 is also used to input the fourth voltage to the comparator circuit 14. The fourth voltage is the sum of the first, second, and third voltages.

[0348] The comparator circuit 14 receives the fourth voltage input from the second node B and determines whether the data read from the ferroelectric storage cell 11 is digital signal 0 or digital signal 1 based on the fourth voltage. The fourth voltage is within the operating voltage range of the comparator voltage 14.

[0349] It should be understood that the fourth voltage when the ferroelectric storage cell 11 reads digital signal 1 is different from the fourth voltage when reading digital signal 0. Only when both the fourth voltage when reading digital signal 1 and the fourth voltage when reading digital signal 0 are within the operating voltage range of the comparison circuit 14 can the comparison circuit 14 compare the fourth voltage to determine whether the data indicated by the fourth voltage it receives is digital signal 1 or digital signal 0.

[0350] Optionally, the operating voltage of the comparator circuit 14 is typically positive, ranging from 0V to 3.3V or 0V to 2.5V. After the ferroelectric storage cell 11 inputs the second voltage to the first node A, although the potential of the second node B becomes the sum of the first and second voltages, the potential of the second node B may still be negative. Alternatively, if the ferroelectric capacitor FE-Cap undergoes polarization reversal, the potential of the second node B (the sum of the first and second voltages) will be positive; if the ferroelectric capacitor FE-Cap does not undergo polarization reversal, the potential of the second node B (the sum of the first and second voltages) will still be negative. Therefore, a third voltage can also be input to the second node B using the voltage generation circuit 13. This third voltage is positive, and the voltage of the second node B is then a fourth voltage (the sum of the first, second, and third voltages). This embodiment does not limit the specific value of the third voltage; it can be adjusted based on the sum of the first and second voltages and the operating voltage of the comparator circuit 14.

[0351] In some possible implementations, the third voltage can be the absolute value of the first voltage. For example, the voltage generation circuit 13 is used to pull the second node B down by 5V (the first voltage is -5V). After the second node B receives the second voltage, the voltage generation circuit 13 is used to pull the second node B up by 5V (the third voltage is 5V). The resulting fourth voltage is the second voltage input from the ferroelectric storage unit 11 to the second node B.

[0352] Of course, in other possible implementations, if after the ferroelectric storage cell 11 inputs the second voltage to the first node A, the potential of the second node B becomes the sum of the first and second voltages, which is already positive and within the operating voltage range of the comparator circuit 14, then the third voltage can also be 0V, and the voltage generation circuit 13 may no longer provide the third voltage to the second node B. Alternatively, if after the ferroelectric storage cell 11 inputs the second voltage to the first node A, the potential of the second node B becomes the sum of the first and second voltages, which is already positive, and the fourth voltage is greater than the upper limit of the operating voltage of the comparator circuit 14 (e.g., 3.3V or 2.5V), then the third voltage can also be negative. Unless otherwise stated, the following description assumes the third voltage is positive.

[0353] In this application, when reading data, the second voltage of the ferroelectric storage cell 11 is first input to the first node A. Since the potential of the first node A is higher than that of the second node B, the ferroelectric storage cell 11 inputs the second voltage to the second node B through the first node A. Whether the polarization of the ferroelectric capacitor FE-Cap reverses or not, the data (digital signal 1 or digital signal 0) read by the ferroelectric storage cell 11 is different, and the second voltage input to the second node B by the ferroelectric storage cell 11 is different. In addition to the second voltage, the first voltage when the ferroelectric storage cell 11 reads digital signal 1 is the same as the first voltage when reading digital signal 0, and the third voltage when the ferroelectric storage cell 11 reads digital signal 1 is the same as the third voltage when reading digital signal 0. Therefore, after receiving the fourth voltage input to the second node B, the comparison circuit 14 can determine whether the data read by the ferroelectric storage cell 11 is digital signal 1 or digital signal 0 based on the fourth voltage.

[0354] Meanwhile, whether reading digital signal 1 or digital signal 0, the voltage on bit line BL (first node A) is clamped at the initial voltage by clamping circuit 12. On the one hand, the potential difference between plate line PL and bit line BL is stabilized at a fixed value, which does not affect the polarization reversal of ferroelectric capacitor FE-Cap. On the other hand, the potential difference between plate line PL and bit line BL is always at a large value, so that the polarization reversal of ferroelectric capacitor FE-Cap will not become slower or even insufficient due to the decrease in the potential difference between plate line PL and bit line BL, thus preventing self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0355] Furthermore, as mentioned earlier, in the prior art, the comparator circuit 14 reads the digital signal 1 or digital signal 0 by acquiring the charge on the bit line BL. The bit line BL is usually connected to multiple ferroelectric memory cells and is relatively long. In the memory chip, the bit line BL inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures. The parasitic capacitance Cbl has a negative impact on the MW of the memory circuit.

[0356] In this application, the voltage on the bit line BL (first node A) is clamped at the initial voltage by the clamping circuit 12, and the parasitic capacitance Cbl cannot be transmitted to the second node B through the bit line BL. The comparison circuit 14 of this application confirms whether the data is digital signal 0 or digital signal 1 based on the fourth voltage transmitted by the second node B. Therefore, the parasitic capacitance Cbl will not have a negative impact on the MW of the storage circuit.

[0357] In some embodiments, such as Figure 9a As shown, the clamping circuit 12 includes a first transistor T1 and a second transistor T2. The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor. The first transistor T1 is electrically connected between the first node A and the second transistor T2.

[0358] While the ferroelectric storage cell 11 inputs the second voltage to the second node B through the first node A and the clamping circuit 12, the first transistor T1 and the second transistor T2 are turned on. The second transistor T2 is a P-type transistor, so it can clamp the node connected to the first transistor T1. The potential of the node connected to the first transistor T1 is the same as the potential of the first node A. Therefore, the potential of the first node A can be clamped at 0V by the second transistor T2 through the first transistor T1.

[0359] While the voltage generation circuit 13 inputs the third voltage to the second node B, the first transistor T1 is turned off to prevent the potential of the first node A from being affected by the second transistor T2 and the first transistor T1 when the potential of the second node B rises, thus causing the potential of the first node A to increase.

[0360] Similarly, in some possible implementations, the storage circuit may also include a P-type transistor P1 electrically connected between the second node B and the comparator circuit 14. When the voltage generation circuit 13 inputs a third voltage to the second node B, the P-type transistor P1 is turned off to prevent the potential of the second node B from rising and affecting the potential of the comparator circuit 14 through the second transistor T2 and the first transistor T1. Afterwards, the P-type transistor P1 is turned on, and the second node B inputs a fourth voltage to the comparator circuit 14 through the P-type transistor P1.

[0361] In some embodiments, such as Figure 9a As shown, the voltage generation circuit includes a first voltage terminal V_boost. During the reading phase, the first voltage terminal V_boost is used to input a third voltage to the second node B. However, due to the presence of parasitic capacitance, the voltage value received by the second node B will not reach the voltage value output by the first voltage terminal V_boost. Therefore, the voltage generation circuit 13 can also include a storage capacitor TC, which is electrically connected between the second node B and the first voltage terminal V_boost. The first voltage terminal V_boost is electrically connected to the first electrode of the storage capacitor TC, and the second node B is electrically connected to the second electrode of the storage capacitor TC. In this way, the voltage generation circuit 13 can first input the third voltage to the first electrode, and the first electrode couples the third voltage to the second electrode and the second node B, thereby improving the problem that the voltage output by the first voltage terminal V_boost is largely diverted by the parasitic capacitance, causing the voltage value received by the second node B to not reach the voltage value output by the first voltage terminal V_boost.

[0362] In some possible ways of implementation, such as Figure 10As shown, signal loss usually occurs during transmission. Based on this, the voltage generation circuit 13 may also include an inverter 131, which is electrically connected between the first voltage terminal V_boost and the storage capacitor TC to enhance the signal.

[0363] It should be noted here that if the third voltage required by the second node B is high, the voltage output by the first voltage terminal V_boost is also high when the first voltage generation circuit 13 does not include the inverter 131; and the voltage output by the first voltage terminal V_boost is low when the third voltage generation circuit 13 includes the inverter 131.

[0364] In some embodiments, the storage circuit further includes a third transistor T3 and a second voltage terminal V2. During the pre-charging phase, the third transistor T3 is turned on, and the second voltage terminal V2 pre-charges the first node A to 0V through the third transistor T3 in preparation for the reading phase.

[0365] Optional, such as Figure 10 As shown, the third transistor T3 is electrically connected between the second node B and the second voltage terminal V2. The second voltage terminal V2 precharges the first node A to 0V through the third transistor T3, the second node B, the second transistor T2, and the first transistor T1.

[0366] Optional, such as Figure 11 As shown, the third transistor T3 is electrically connected between the third node C and the second voltage terminal V2. The third node C is the connection node between the first transistor T1 and the second transistor T2. The second voltage terminal V2 precharges the first node A to 0V through the third transistor T3, the third node C, and the first transistor T1.

[0367] In some possible ways of implementation, such as Figure 9b As shown, during the pre-charging phase, the voltage generation circuit 13 provides a first voltage less than 0V to the second node B, which can be achieved in the following way:

[0368] The first voltage terminal V_boost is low, and after passing through inverter 131, it inputs a high level to the first electrode of the storage capacitor TC. The third transistor T3 is turned on, and the second voltage terminal V2 provides a 0V voltage to the second node B and the second electrode of the storage capacitor TC through the third transistor T3. Then, the first voltage terminal V_boost is high, and after passing through inverter 131, it inputs a 0V voltage to the first electrode of the storage capacitor TC. The voltage on the first electrode decreases, and the voltage on the second electrode also decreases due to coupling with the first electrode, changing the voltage of the second electrode from 0V to a negative value.

[0369] In some embodiments, such as Figure 12As shown, the storage circuit also includes a third voltage terminal V3 and a fourth transistor T4. The fourth transistor T4 is an N-type transistor, with its gate electrically connected to the second node B, its first terminal electrically connected to the third voltage terminal V3, and its second terminal electrically connected to the input terminal of the comparator circuit 14. Furthermore, the storage circuit may also include a fifth transistor T5, which is a P-type transistor and is electrically connected between the fourth transistor T4 and the third voltage terminal V3.

[0370] As mentioned earlier, the fourth voltage is positive regardless of whether the digital signal is 1 or 0, but the fourth voltage when reading digital signal 1 is different from the fourth voltage when reading digital signal 0.

[0371] like Figure 9b As shown, when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor does not undergo polarization reversal. Therefore, the fourth voltage when reading digital signal 1 is greater than the fourth voltage when reading digital signal 0, the conduction degree of the fourth transistor T4 when reading digital signal 1 is greater than the conduction degree of the fourth transistor T4 when reading digital signal 0, and more current flows through the fourth transistor T4 when reading digital signal 1. Consequently, more charge accumulates at the input terminal of the comparator circuit 14 within a certain period of time, and the comparator circuit 14 receives more voltage. The comparator circuit 14 determines whether the data read by the ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the magnitude of the received voltage.

[0372] When the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor does not undergo polarization reversal. Therefore, the fourth voltage when reading digital signal 0 is greater than the fourth voltage when reading digital signal 1, the conduction degree of the fourth transistor T4 when reading digital signal 0 is greater than the conduction degree of the fourth transistor T4 when reading digital signal 1, and more current flows through the fourth transistor T4 when reading digital signal 0. Consequently, more charge accumulates at the input terminal of the comparator circuit 14 within a certain period of time, and the comparator circuit 14 receives more voltage. The comparator circuit 14 determines whether the data read by the ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the magnitude of the received voltage.

[0373] In this case, since the gate of the fourth transistor T4 is electrically connected to the second node B, the fourth voltage controls the conduction level of the fourth transistor T4 and the magnitude of the current flowing through it. Therefore, the comparator circuit 14 still indirectly determines whether the data read by the ferroelectric memory cell 11 is digital signal 0 or digital signal 1 based on the fourth voltage. Furthermore, the fourth voltage can be amplified through charge accumulation to improve the read quality and resolution of the memory circuit.

[0374] In some embodiments, after the read phase, the ferroelectric memory cell 11 can also be reverse-written. During the reverse-writing phase, P-type transistor P1, second transistor T2, and first transistor T1 are all turned on, and the comparator circuit 14 inputs a write signal to the ferroelectric memory cell 11 through P-type transistor P1, second transistor T2, and first transistor T1.

[0375] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 during the read phase, and needs to write digital signal 0 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 during the read phase, and needs to write digital signal 1 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse.

[0376] In this case, instead of writing the signal back to the first ferroelectric storage cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparator circuit), and the signal is rewritten to the first ferroelectric storage cell 11 using the input terminal of the storage circuit.

[0377] In yet another embodiment, this application also provides a method for controlling a storage circuit, such as... Figures 9a-12 As shown, the circuit structure of the storage circuit is the same as that of the storage circuit in the previous embodiment, and will not be described again here.

[0378] In step S110, transistors T1, T2, and T3 are turned on. The second voltage terminal V2, through transistors T3, T2, and T1, charges 0V to node A. V2 also charges 0V to node B and the second electrode of capacitor TC through transistor T3. The first voltage terminal V_boost is low, and after passing through inverter 131, it inputs a high level to the first electrode of capacitor TC. Then, V_boost is high again, and after passing through inverter 131, it inputs 0V to the first electrode of capacitor TC. The voltage on the first electrode decreases, and due to coupling with the first electrode, the voltage on the second electrode also decreases, changing from 0V to a negative value. At this point, the potential of node A is 0V, and the voltage of node B is a first voltage less than 0V.

[0379] S120, the ferroelectric storage cell 11 inputs a second voltage to the first node A. Since the potential of the first node A is higher than that of the second node B, the ferroelectric storage cell 11 is used to input a second voltage to the second node B through the first node A and the clamping circuit 12. The second voltage is greater than 0V. Although the ferroelectric storage cell 11 inputs a second voltage to the first node A, the clamping circuit 12 clamps the potential of the first node A at the initial voltage. Therefore, the second voltage output by the ferroelectric storage cell 11 passes through the first node A but does not accumulate at the first node A, and the voltage of the first node A remains the initial voltage.

[0380] The voltage generating circuit 13 is also used to input a third voltage to the second node B, changing the potential of the second node B to a fourth voltage. The voltage generating circuit 13 is also used to input the fourth voltage to the comparator circuit 14. The fourth voltage is the sum of the first, second, and third voltages.

[0381] During the reading phase, when the polarization of the ferroelectric capacitor FE-Cap in the ferroelectric storage cell 11 reverses, the first ferroelectric storage cell 11 outputs a polarization current; when the polarization of the ferroelectric capacitor FE-Cap does not reverse, the ferroelectric storage cell 11 outputs a dielectric current. The second voltage output when the polarization of the ferroelectric capacitor FE-Cap reverses is greater than the second voltage output when the polarization of the ferroelectric capacitor FE-Cap does not reverse. Therefore, when the polarization of the ferroelectric capacitor FE-Cap reverses, the ferroelectric storage cell 11 inputs a second voltage to the second node B through the first node A and the clamping circuit 12, which is greater than the second voltage input to the second node B through the first node A and the clamping circuit 12 when the polarization of the ferroelectric capacitor FE-Cap does not reverse.

[0382] S130, the comparator circuit 14 receives the fourth voltage input from the second node B, and determines whether the data read by the ferroelectric storage cell 11 is digital signal 0 or digital signal 1 based on the fourth voltage. The fourth voltage is within the operating voltage range of the comparator voltage 14.

[0383] It should be understood that the fourth voltage when the ferroelectric storage cell 11 reads digital signal 1 is different from the fourth voltage when reading digital signal 0. Only when both the fourth voltage when reading digital signal 1 and the fourth voltage when reading digital signal 0 are within the operating voltage range of the comparison circuit 14 can the comparison circuit 14 compare the fourth voltage to determine whether the data indicated by the fourth voltage it receives is digital signal 1 or digital signal 0.

[0384] Optionally, the operating voltage of the comparator circuit 14 is typically positive, ranging from 0V to 3.3V or 0V to 2.5V. After the ferroelectric storage cell 11 inputs the second voltage to the first node A, although the potential of the second node B becomes the sum of the first and second voltages, the potential of the second node B may still be negative. Alternatively, if the ferroelectric capacitor FE-Cap undergoes polarization reversal, the potential of the second node B (the sum of the first and second voltages) will be positive; if the ferroelectric capacitor FE-Cap does not undergo polarization reversal, the potential of the second node B (the sum of the first and second voltages) will still be negative. Therefore, a third voltage can also be input to the second node B using the voltage generation circuit 13. This third voltage is positive, and the voltage of the second node B is then a fourth voltage (the sum of the first, second, and third voltages). This embodiment does not limit the specific value of the third voltage; it can be adjusted based on the sum of the first and second voltages and the operating voltage of the comparator circuit 14.

[0385] In some possible implementations, the third voltage can be the absolute value of the first voltage. For example, the voltage generation circuit 13 is used to pull the second node B down by 5V (the first voltage is -5V). After the second node B receives the second voltage, the voltage generation circuit 13 is used to pull the second node B up by 5V (the third voltage is 5V). The resulting fourth voltage is the second voltage input from the ferroelectric storage unit 11 to the second node B.

[0386] Of course, in other possible implementations, if after the ferroelectric storage cell 11 inputs the second voltage to the first node A, the potential of the second node B becomes the sum of the first and second voltages, which is already positive and within the operating voltage range of the comparator circuit 14, then the third voltage can also be 0V, and the voltage generation circuit 13 may no longer provide the third voltage to the second node B. Alternatively, if after the ferroelectric storage cell 11 inputs the second voltage to the first node A, the potential of the second node B becomes the sum of the first and second voltages, which is already positive, and the fourth voltage is greater than the upper limit of the operating voltage of the comparator circuit 14 (e.g., 3.3V or 2.5V), then the third voltage can also be negative.

[0387] In this application, when reading data, the second voltage of the ferroelectric storage cell 11 is first input to the first node A. Since the potential of the first node A is higher than that of the second node B, the ferroelectric storage cell 11 inputs the second voltage to the second node B through the first node A. Whether the polarization of the ferroelectric capacitor FE-Cap reverses or not, the data (digital signal 1 or digital signal 0) read by the ferroelectric storage cell 11 is different, and the second voltage input to the second node B by the ferroelectric storage cell 11 is different. In addition to the second voltage, the first voltage when the ferroelectric storage cell 11 reads digital signal 1 is the same as the first voltage when reading digital signal 0, and the third voltage when the ferroelectric storage cell 11 reads digital signal 1 is the same as the third voltage when reading digital signal 0. Therefore, after receiving the fourth voltage input to the second node B, the comparison circuit 14 can determine whether the data read by the ferroelectric storage cell 11 is digital signal 1 or digital signal 0 based on the fourth voltage.

[0388] Meanwhile, whether reading digital signal 1 or digital signal 0, the voltage on bit line BL (first node A) is clamped at the initial voltage by clamping circuit 12. On the one hand, the potential difference between plate line PL and bit line BL is stabilized at a fixed value, which does not affect the polarization reversal of ferroelectric capacitor FE-Cap. On the other hand, the potential difference between plate line PL and bit line BL is always at a large value, so that the polarization reversal of ferroelectric capacitor FE-Cap will not become slower or even insufficient due to the decrease in the potential difference between plate line PL and bit line BL, thus preventing self-suppression phenomenon. This improves the uniformity and reliability of the storage circuit and also increases the storage window of the ferroelectric circuit.

[0389] Furthermore, as mentioned earlier, in the prior art, the comparator circuit 14 reads the digital signal 1 or digital signal 0 by acquiring the charge on the bit line BL. The bit line BL is usually connected to multiple ferroelectric memory cells and is relatively long. In the memory chip, the bit line BL inevitably forms a parasitic capacitance Cbl1 with multiple conductive structures. The parasitic capacitance Cbl has a negative impact on the MW of the memory circuit.

[0390] In this application, the voltage on the bit line BL (first node A) is clamped at the initial voltage by the clamping circuit 12, and the parasitic capacitance Cbl cannot be transmitted to the second node B through the bit line BL. The comparison circuit 14 of this application confirms whether the data is digital signal 0 or digital signal 1 based on the fourth voltage transmitted by the second node B. Therefore, the parasitic capacitance Cbl will not have a negative impact on the MW of the storage circuit.

[0391] In some embodiments, such as Figure 12 As shown, the storage circuit also includes a third voltage terminal V3 and a fourth transistor T4. The fourth transistor T4 is an N-type transistor, with its gate electrically connected to the second node B, its first terminal electrically connected to the third voltage terminal V3, and its second terminal electrically connected to the input terminal of the comparator circuit 14. Furthermore, the storage circuit may also include a fifth transistor T5, which is a P-type transistor and is electrically connected between the fourth transistor T4 and the third voltage terminal V3.

[0392] As mentioned earlier, the fourth voltage is positive regardless of whether the digital signal is 1 or 0, but the fourth voltage when reading digital signal 1 is different from the fourth voltage when reading digital signal 0.

[0393] like Figure 9b As shown, when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor does not undergo polarization reversal. Therefore, the fourth voltage when reading digital signal 1 is greater than the fourth voltage when reading digital signal 0, the conduction degree of the fourth transistor T4 when reading digital signal 1 is greater than the conduction degree of the fourth transistor T4 when reading digital signal 0, and more current flows through the fourth transistor T4 when reading digital signal 1. Consequently, more charge accumulates at the input terminal of the comparator circuit 14 within a certain period of time, and the comparator circuit 14 receives more voltage. The comparator circuit 14 determines whether the data read by the ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the magnitude of the received voltage.

[0394] When the first ferroelectric storage unit 11 reads digital signal 0, the ferroelectric capacitor FE-Cap undergoes polarization reversal; when the first ferroelectric storage unit 11 reads digital signal 1, the ferroelectric capacitor does not undergo polarization reversal. Therefore, the fourth voltage when reading digital signal 0 is greater than the fourth voltage when reading digital signal 1, the conduction degree of the fourth transistor T4 when reading digital signal 0 is greater than the conduction degree of the fourth transistor T4 when reading digital signal 1, and more current flows through the fourth transistor T4 when reading digital signal 0. Consequently, more charge accumulates at the input terminal of the comparator circuit 14 within a certain period of time, and the comparator circuit 14 receives more voltage. The comparator circuit 14 determines whether the data read by the ferroelectric storage unit 11 is digital signal 0 or digital signal 1 based on the magnitude of the received voltage.

[0395] In this case, since the gate of the fourth transistor T4 is electrically connected to the second node B, the fourth voltage controls the conduction level of the fourth transistor T4 and the magnitude of the current flowing through it. Therefore, the comparator circuit 14 still indirectly determines whether the data read by the ferroelectric memory cell 11 is digital signal 0 or digital signal 1 based on the fourth voltage. Furthermore, the fourth voltage can be amplified through charge accumulation to improve the read quality and resolution of the memory circuit.

[0396] S130, during the reverse writing stage, P-type transistor P1, second transistor T2, and first transistor T1 are all turned on, and the comparator circuit 14 inputs a write signal to the ferroelectric memory cell 11 through P-type transistor P1, second transistor T2, and first transistor T1.

[0397] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the previous embodiment, and will not be repeated here.

[0398] In other embodiments, if the first ferroelectric memory cell 11 reads digital signal 1 during the read phase, and needs to write digital signal 0 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse. Alternatively, if the first ferroelectric memory cell 11 reads digital signal 0 during the read phase, and needs to write digital signal 1 to the first ferroelectric memory cell 11 during the write phase, then the first ferroelectric memory cell 11 can be rewritten instead of written in reverse.

[0399] In this case, instead of writing the signal back to the first ferroelectric storage cell 11 through the reference voltage terminal Vref, the output terminal OUT of the storage circuit is multiplexed as the input terminal of the storage circuit (or the comparator circuit), and the signal is rewritten to the first ferroelectric storage cell 11 using the input terminal of the storage circuit.

[0400] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A storage circuit, characterized by comprising: The first ferroelectric memory cell, a first current mirror, a first voltage generating circuit, a comparison circuit, and a first voltage terminal are included. The first current mirror includes a first branch and a second branch, one end of the first branch and one end of the second branch are electrically connected to the first voltage terminal, and the current of the first branch is the same as the current of the second branch. The output end of the first ferroelectric memory cell is electrically connected to the other end of the first branch at a first node, the other end of the second branch is electrically connected to the output end of the first voltage generating circuit and the input end of the comparison circuit at a second node, and the output end of the comparison circuit is electrically connected to the output end of the memory circuit.

2. The storage circuit according to claim 1, characterized by, The first branch includes a first transistor, and the second branch includes a second transistor, and the first transistor is the same as the second transistor. The first pole of the first transistor is electrically connected to the first node, the gate of the first transistor, and the gate of the second transistor, the second pole of the first transistor and the second pole of the second transistor are both electrically connected to the first voltage terminal, and the first pole of the second transistor is electrically connected to the second node. In the read stage, the first voltage terminal is used to input a first voltage to the second pole of the first transistor and the second pole of the second transistor.

3. The storage circuit according to claim 2, characterized by The memory chip further includes a third transistor and a fourth transistor, the third transistor is connected in series between the first node and the first transistor, and the fourth transistor is connected in series between the second node and the second transistor. In the read stage, the third transistor is used to input a clamping voltage to the first pole of the first transistor, and the fourth transistor is used to input a clamping voltage to the first pole of the second transistor.

4. The storage circuit according to claim 2 or 3, characterized by The first voltage generating circuit includes a second voltage terminal and a storage capacitor, and the storage capacitor is electrically connected between the second node and the second voltage terminal. In the read stage, the second voltage terminal is used to input a second voltage to the second node through the storage capacitor.

5. The storage circuit according to claim 4, characterized by The first voltage generating circuit further includes an inverter electrically connected between the second voltage terminal and the storage capacitor.

6. The storage circuit according to claim 4 or 5, characterized by The memory circuit further includes a third voltage terminal and a pre-charge circuit electrically connected between the third voltage terminal and the first node. The memory circuit further includes a plate line and a bit line, the first ferroelectric memory cell is electrically connected between the bit line and the plate line, the bit line, the output end of the first ferroelectric memory cell, and one end of the first branch are electrically connected to the first node; in the pre-charge stage, the third voltage terminal is used to charge an initial voltage to the bit line through the pre-charge circuit.

7. The storage circuit according to claim 6, characterized by The pre-charge circuit includes a first switch and a second switch, the first switch is electrically connected between the input end of the first branch and the output end of the second branch, and the second switch is electrically connected between the third voltage terminal and the second node.

8. The memory circuit of claim 7, wherein In the pre-charge stage, the third voltage terminal is also used to pre-charge the second node through the second switch. In the reading phase, the first switch and the second switch are both open.

9. The memory circuit of any one of claims 6-8, wherein, in the reading phase: the ferroelectric memory cell is configured to input a charge to the first node; the first branch is configured to copy a first current of the first branch to the second branch, and to maintain a potential of the first node at an initial voltage according to the first voltage and the initial voltage; the second branch is configured to change a potential of the second node from a second voltage to a third voltage according to the first current, the first voltage, and the second voltage; the comparison circuit is configured to receive the third voltage input from the second node, and to determine whether data read by the first ferroelectric memory cell is a digital signal 0 or 1 according to the third voltage.

10. The storage circuit according to claim 9, characterized by the first transistor and the second transistor are both N-type transistors, the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low voltage; the first branch is configured to extract a charge from the first node according to the first voltage and the initial voltage, so as to maintain the potential of the first node at the initial voltage; the second branch is configured to extract a charge from the second node according to the first current, the first voltage, and the second voltage, so as to decrease the potential of the second node from the second voltage to a third voltage.

11. The memory circuit of claim 10, wherein: if the first ferroelectric memory cell reads a digital signal 1 and a polarization of a ferroelectric capacitor in the first ferroelectric memory cell flips, the third voltage when the first ferroelectric memory cell reads the digital signal 1 is less than the third voltage when the first ferroelectric memory cell reads a digital signal 0; if the first ferroelectric memory cell reads a digital signal 0 and the polarization of the ferroelectric capacitor in the first ferroelectric memory cell flips, the third voltage when the first ferroelectric memory cell reads the digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads the digital signal 0.

12. The storage circuit of claim 9, wherein, the first transistor and the second transistor are both P-type transistors, the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high voltage; the first node is configured to extract a charge from the first branch according to the first voltage and the initial voltage, so as to maintain the potential of the first node at the initial voltage; the second node is configured to extract a charge from the second branch according to the first current, the first voltage, and the second voltage, so as to increase the potential of the second node from the second voltage to a third voltage.

13. The memory circuit of claim 12, wherein: if the first ferroelectric memory cell reads a digital signal 1 and a polarization of a ferroelectric capacitor in the first ferroelectric memory cell flips, the third voltage when the first ferroelectric memory cell reads the digital signal 1 is greater than the third voltage when the first ferroelectric memory cell reads a digital signal 0. If the first ferroelectric memory cell reads a digital signal 0, and the ferroelectric capacitor in the first ferroelectric memory cell is polarized to flip, then the third voltage when the first ferroelectric memory cell reads a digital signal 0 is greater than the third voltage when the first ferroelectric memory cell reads a digital signal 1.

14. The storage circuit according to any one of claims 1 to 13, characterized by, The storage circuit further comprises a reference voltage terminal; In the reading stage: The reference voltage terminal is configured to input a reference voltage to the comparison circuit, the reference voltage having a voltage value between the third voltage when the first ferroelectric memory cell reads a digital signal 0 and the third voltage when the first ferroelectric memory cell reads a digital signal 1. The comparison circuit is configured to determine whether the data read by the first ferroelectric memory cell is a digital signal 0 or a digital signal 1 according to the third voltage and the reference voltage.

15. The storage circuit of claim 14, wherein, The comparison circuit comprises a fourth voltage terminal, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a ground terminal; the storage circuit further comprises an output terminal; in the reading stage, the fourth voltage terminal is at a high level, and the ground terminal is at a low level. The gate of the first P-type transistor and the gate of the first N-type transistor are electrically connected to the second electrode of the second P-type transistor, the first electrode of the second N-type transistor, and the reference voltage terminal; the first electrode of the first P-type transistor is electrically connected to the fourth voltage terminal; the second electrode of the first P-type transistor is electrically connected to the first electrode of the first N-type transistor and the output terminal; and the second electrode of the first N-type transistor is electrically connected to the ground terminal. The gate of the second P-type transistor and the gate of the second N-type transistor are electrically connected to the second node; the first electrode of the second P-type transistor is electrically connected to the fourth voltage terminal; and the second electrode of the second N-type transistor is electrically connected to the ground terminal.

16. The storage circuit according to claim 14 or 15, characterized by The storage circuit further comprises a reference voltage generation circuit, the reference voltage generation circuit comprising a second ferroelectric memory cell, a third ferroelectric memory cell, a second current mirror, a second voltage generation circuit, and a third node; the circuit structure of the second ferroelectric memory cell and the third ferroelectric memory cell is the same as that of the first ferroelectric memory cell; and the second current mirror comprises a third branch and a fourth branch. In the reading stage: The second voltage generation circuit is configured to input a fourth voltage to the third node, the fourth voltage being the same as the second voltage; The second ferroelectric memory cell is configured to input a second current to the third branch, the second current representing that the second ferroelectric memory cell reads a digital signal 1; The third ferroelectric memory cell is configured to input a third current to the fourth branch, the third current representing that the third ferroelectric memory cell reads a digital signal 0; The third branch is configured to receive the second current and the third current, and copy an average value of the second current and the third current to the fourth branch. The third node is configured to transmit electric charges to the fourth branch according to an average value of the second current and the third current, so that the potential of the third node decreases from the second voltage to a fifth voltage, and the fifth voltage is input to the reference voltage terminal; and the fifth voltage is half of the fourth voltage.

17. The storage circuit of claim 16, wherein, The third branch includes a fifth transistor and a sixth transistor, and the fourth branch includes a seventh transistor; the channel width of the fifth transistor, the sixth transistor and the seventh transistor is the same; the gate of the fifth transistor, the gate of the sixth transistor, the first electrode of the fifth transistor, the first electrode of the sixth transistor and the gate of the seventh transistor are electrically connected to the output terminals of the second ferroelectric storage unit and the third ferroelectric storage unit; the second electrode of the fifth transistor, the second electrode of the sixth transistor and the second electrode of the seventh transistor are electrically connected to the fifth voltage terminal, and the first electrode of the seventh transistor is electrically connected to the third node; or, The third branch includes a fifth transistor, and the fourth branch includes a sixth transistor; the channel width of the fifth transistor is twice the channel width of the sixth transistor; the gate of the fifth transistor, the gate of the sixth transistor and the first electrode of the fifth transistor are electrically connected to the output terminals of the second ferroelectric storage unit and the third ferroelectric storage unit; the second electrode of the fifth transistor and the second electrode of the sixth transistor are electrically connected to the fifth voltage terminal; and the first electrode of the sixth transistor is electrically connected to the third node.

18. The storage circuit according to any one of claims 14 to 17, characterized by The storage circuit further includes a third switch electrically connected between the reference voltage terminal and the first node; In the reading stage, the third switch is turned off; and in the anti-writing stage, the third switch is turned on to input a write signal of the reference voltage terminal to the first ferroelectric storage unit through the first node.

19. A control method of a storage circuit, characterized by, The storage circuit includes a first ferroelectric storage unit, a first current mirror, a first voltage generation circuit, a comparison circuit and a first voltage terminal; the first ferroelectric storage unit and a first branch of the first current mirror are electrically connected to a first node; a second branch of the first current mirror, the first voltage generation circuit and the comparison circuit are electrically connected to a second node. The control method of the storage circuit includes: In a pre-charging stage, the first node is pre-charged so that the potential of the first node is an initial voltage; In a reading stage: a first voltage is input to the first current mirror through the first voltage terminal; electric charges are input to the first node by the first ferroelectric storage unit; a second voltage is input to the second node by the first voltage generation circuit; the initial voltage and the second voltage are both greater than the first voltage, and the initial voltage is a low level; or the initial voltage and the second voltage are both less than the first voltage, and the initial voltage is a high level; and In an anti-writing stage: the third switch is turned on to input a write signal of the reference voltage terminal to the first ferroelectric storage unit through the first node; and the first voltage is input to the first current mirror through the first voltage terminal. The first branch is used to keep the potential of the first node at the initial voltage and copy the first current of the first branch to the second branch according to the first voltage and the initial voltage; The second branch is used to change the potential of the second node from the second voltage to a third voltage according to the first current, the first voltage and the second voltage; The third voltage is received by the comparison circuit, and the data read by the first ferroelectric storage unit is determined as digital signal 0 or 1 according to the third voltage.

20. The control method of a memory circuit according to claim 19, wherein The first transistor and the second transistor are both N-type transistors, and the initial voltage and the second voltage are both greater than the first voltage; The first branch is used to extract charges from the first node according to the first voltage and the initial voltage, so that the potential of the first node is kept at the initial voltage; The second branch is used to extract charges from the second node according to the first current, the first voltage and the second voltage, so that the potential of the second node is reduced from the second voltage to a third voltage.

21. The control method of the storage circuit according to claim 20, wherein If the first ferroelectric storage unit reads digital signal 1 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 1 is less than the third voltage when the first ferroelectric storage unit reads digital signal 0; If the first ferroelectric storage unit reads digital signal 0 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0.

22. The control method of a memory circuit according to claim 19, wherein The first transistor and the second transistor are both P-type transistors, and the initial voltage and the second voltage are both less than the first voltage; The first node is used to extract charges from the first branch according to the first voltage and the initial voltage, so that the potential of the first node is kept at the initial voltage; The second node is used to extract charges from the second branch according to the first current, the first voltage and the second voltage, so that the potential of the second node is increased from the second voltage to a third voltage.

23. The control method of the storage circuit according to claim 22, wherein If the first ferroelectric storage unit reads digital signal 1 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 1 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 0; If the first ferroelectric storage unit reads digital signal 0 and the ferroelectric capacitor in the first ferroelectric storage unit is polarized to flip, the third voltage when the first ferroelectric storage unit reads digital signal 0 is greater than the third voltage when the first ferroelectric storage unit reads digital signal 1.

24. The control method of a memory circuit according to any one of claims 19 to 23, characterized by, The control method of the storage circuit further comprises: In the pre-charging phase, the second node is pre-charged.

25. The control method of a memory circuit according to any one of claims 19 to 24, characterized by, The storage circuit further comprises a reference voltage terminal; In the reading phase: The reference voltage terminal inputs a reference voltage to the comparison circuit, the voltage value of the reference voltage is between the third voltage when the first ferroelectric memory unit reads digital signal 0 and the third voltage when the first ferroelectric memory unit reads digital signal 1; The comparison circuit determines the data read by the first ferroelectric memory unit as digital signal 0 or digital signal 1 according to the third voltage and the reference voltage.

26. The control method of a memory circuit according to any one of claims 19 to 25, wherein The storage circuit further comprises a third switch electrically connected between the reference voltage terminal and the first node; In the reading phase, the third switch is turned off; In the writing phase, the third switch is turned on, and the writing signal of the reference voltage terminal is input to the first ferroelectric memory unit through the first node.

27. A storage circuit, comprising: The storage circuit comprises a ferroelectric memory unit, a clamping circuit, a voltage generating circuit, and a comparison circuit. The output terminal of the ferroelectric memory unit and one end of the clamping circuit are electrically connected to the first node; the other end of the clamping circuit, the voltage generating circuit, and the input terminal of the comparison circuit are electrically connected to the second node, and the output terminal of the comparison circuit is electrically connected to the output terminal of the storage circuit.

28. The storage circuit of claim 27, wherein, The voltage generating circuit comprises a first voltage terminal and a storage capacitor, and the storage capacitor is electrically connected between the second node and the first voltage terminal; In the pre-charging phase, the first voltage terminal is used to input the first voltage to the second node through the storage capacitor; In the reading phase, the ferroelectric memory unit is used to input the second voltage to the second node through the first node and the clamping circuit; In the reading phase, the first voltage terminal is used to input the third voltage to the second node through the storage capacitor.

29. The storage circuit of claim 28, wherein, The voltage generating circuit further comprises an inverter electrically connected between the first voltage terminal and the storage capacitor.

30. The storage circuit of claim 28 or 29, wherein, The clamping circuit comprises a first transistor and a second transistor, the first transistor is an N-type transistor, and the second transistor is a P-type transistor; the first transistor is electrically connected between the first node and the second transistor; In the reading phase, while the ferroelectric memory unit inputs the second voltage to the second node through the first node and the clamping circuit, the first transistor and the second transistor are turned on, and the second transistor is used to clamp the potential of the first node at 0V through the first transistor; While the voltage generating circuit inputs the third voltage to the second node, the first transistor is turned off.

31. The storage circuit of claim 30, wherein, The storage circuit further comprises a third transistor and a second voltage terminal; In the pre-charge phase, the second voltage terminal is configured to pre-charge the first node to 0V through the third transistor; wherein in the read phase, the first voltage is less than 0V, the second voltage is greater than 0V, and the voltage of the first node is greater than the sum of the first voltage and the second voltage.

32. The memory circuit of claim 31, wherein, the third transistor is electrically connected between the second node and the second voltage terminal; or, the third transistor is electrically connected between the third node and the second voltage terminal, and the third node is a connection node of the first transistor and the second transistor.

33. The memory circuit of any one of claims 28-32, wherein, in the read phase, the second node is configured to input a fourth voltage to the comparison circuit, and the fourth voltage is the sum of the first voltage, the second voltage, and the third voltage; the comparison circuit is configured to receive the fourth voltage input by the second node, and determine the data read by the ferroelectric memory cell as digital signal 0 or 1 according to the fourth voltage; wherein the fourth voltage is within the working voltage range of the comparison voltage.

34. The storage circuit of claim 30, wherein, the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage.

35. The storage circuit of any of claims 27-34, wherein, The memory circuit further comprises a third voltage terminal and a fourth transistor, and the fourth transistor is an N-type transistor. the gate of the fourth transistor is electrically connected to the second node, the first pole of the fourth transistor is electrically connected to the third voltage terminal, and the second pole of the fourth transistor is electrically connected to the input terminal of the comparison circuit.

36. A control method of a storage circuit, characterized by, The memory circuit comprises a ferroelectric memory cell, a clamping circuit, a voltage generation circuit, and a comparison circuit; the ferroelectric memory cell and the clamping circuit are electrically connected to a first node; the clamping circuit, the voltage generation circuit, and the comparison circuit are electrically connected to a second node; in the pre-charge phase, the first node is pre-charged to 0V, and the second node is pre-charged to a first voltage by the voltage generation circuit, and the first voltage is less than 0V; in the read phase: the ferroelectric memory cell inputs a second voltage to the second node through the first node and the clamping circuit, and the second voltage is greater than 0V; the clamping circuit clamps the potential of the first node to 0V; the voltage generation circuit inputs a third voltage to the second node, and the potential of the second node is a fourth voltage; the comparison circuit receives the fourth voltage input by the second node, and determines the data read by the ferroelectric memory cell as digital signal 0 or 1 according to the fourth voltage; wherein the fourth voltage is within the working voltage range of the comparison voltage.

37. The control method of a storage circuit according to claim 36, wherein the third voltage is the absolute value of the first voltage, and the fourth voltage is equal to the second voltage.

38. The control method of a storage circuit according to claim 36 or 37, wherein The memory circuit further comprises a third transistor and a second voltage terminal; and in the pre-charge phase, the first node is pre-charged to 0V, which comprises: In the pre-charge phase, the third transistor is turned on, and the second voltage terminal pre-charges the first node to 0V through the third transistor.

39. A memory, comprising: The memory circuit comprises a controller, and the memory circuit of any one of claims 1-18 or any one of claims 27-35, wherein the controller is configured to control the memory circuit to read and write data.

40. An electronic device, comprising: The memory circuit comprises a circuit board, and the memory circuit of claim 39, wherein the memory circuit is disposed on the circuit board.

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