High-speed level shifter

Abstract

The invention relates to a high-speed level shifter. A semiconductor device (100) includes a low voltage to high voltage level shifter (102) configured to receive a low voltage input signal and output a high voltage signal. The level shifter (102) includes a buffer (104) configured to receive the low voltage input signal. The buffer (104) includes a pull-up transconductance (106) having a negative transconductance, a pull-down transconductance (108) having a positive transconductance, and a cut-off transconductance (110) having a positive transconductance coupled in series. The pull-up transconductor (106) and the pull-down transconductor (108) are configured to be controlled by the low voltage input signal. The cut-off transconductance (110) is configured to be controlled by a delayed cut-off signal that reversely corresponds to the low voltage input signal. A pull-up auxiliary transconductance (114) having a negative transconductance is connected to an output of the buffer (104).

Description

[0001] Cross-reference to related applications

[0002] This application is a partial continuation of U.S. Application No. 18 / 902,747 (Texas Instruments File No. T102627US01), filed on September 30, 2024. Technical Field

[0003] This disclosure relates to the field of semiconductor devices. More specifically, but not exclusively, this disclosure relates to level shifters in semiconductor devices. Background Technology

[0004] A semiconductor device may include a level shifter that accepts a digital input signal at a relatively low voltage and outputs a corresponding digital output signal at a higher voltage. The digital input signal may be generated by low-voltage circuitry within the semiconductor device. The digital output signal may be provided to an output terminal of the semiconductor device. Summary of the Invention

[0005] A semiconductor device includes a low-to-high voltage level shifter, hereinafter referred to as a level shifter. The level shifter is configured to receive a low-voltage input signal and provide a high-voltage output signal. The level shifter includes a buffer configured to receive the low-voltage input signal. The buffer includes a series-coupled pull-up transconductor, a pull-down transconductor, and a cutoff transconductor. The pull-up transconductor is configured to be controlled by the low-voltage input signal. The pull-down transconductor is configured to be controlled by the low-voltage input signal. The cutoff transconductor is configured to be controlled by a delayed high-voltage cutoff signal that corresponds inversely to the low-voltage input signal. Attached Figure Description

[0006] Figure 1 This is a diagram of a semiconductor device with an example level shifter.

[0007] Figure 2A and Figure 2B This is a schematic diagram of another semiconductor device with an example level shifter.

[0008] Figure 3 This is a flowchart of a method for forming a semiconductor device having an example level shifter. Detailed Implementation

[0009] This disclosure is described with reference to the accompanying drawings. The drawings are not to scale and are provided merely for illustrative purposes. Several aspects of this disclosure are described below with reference to example applications used for illustration. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the described order of actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all described actions or events are necessary to implement the methods according to this disclosure.

[0010] A semiconductor device includes a level shifter configured to receive a low-voltage input signal and provide a high-voltage output signal corresponding to the low-voltage input signal. The low-voltage input signal ranges from a reference potential (referred to herein as reference potential VSS) to a low operating potential (referred to herein as low operating potential VDD LO). The semiconductor device may include low-voltage digital logic circuitry that operates from the reference potential VSS to the low operating potential VDD LO, thereby providing the low-voltage input signal.

[0011] The high-voltage output signal ranges from the reference potential VSS to the high operating potential, referred to herein as the high operating potential VDD HI. The high operating potential VDD HI is provided by the first power rail during operation of the semiconductor device. The low operating potential VDD LO is provided by the second power rail during operation of the semiconductor device. The reference potential VSS is provided by the reference power rail during operation of the semiconductor device. In some cases, the high-voltage output signal may be provided to the output terminals of the semiconductor device for communication with external circuitry. In other cases, the high-voltage output signal may be provided to high-voltage digital logic circuitry that operates from the reference potential VSS to the high operating potential VDD HI. The ratio of the high operating potential VDD HI to the low operating potential VDD LO can range from 1.3 to 4.0. Common nominal values ​​for the high operating potential VDD HI are 5.0 volts and 3.3 volts. The tolerance range for the high operating potential VDD HI in many devices is + / - 10% of the nominal value. The commonly used nominal values ​​for high operating potential VDD HI range from 3.3 volts to 1.0 volts, with a tolerance of + / -10%.

[0012] In this disclosure, a first signal may be disclosed as corresponding to a second signal. The first signal has a similar polarity to the second signal, i.e., the first signal is high when the second signal is high, and low when the second signal is low. Similarly, a third signal may be disclosed as corresponding inversely to a fourth signal. The third signal has the opposite polarity to the fourth signal, i.e., the third signal is low when the fourth signal is high, and high when the fourth signal is low. In both cases, the transitions of the first and third signals from low to high and from high to low, respectively, are delayed relative to the transitions of the second and fourth signals, through signal propagation via circuit elements that generate the first and third signals.

[0013] The high-voltage output signal corresponds to the low-voltage input signal. During the operation of the semiconductor device, when the low-voltage input signal changes from the reference potential VSS to the low operating potential VDD LO, the level shifter causes the high-voltage output signal to change from the reference potential VSS to the high operating potential VDD HI, and when the low-voltage input signal changes from the low operating potential VDD LO to the reference potential VSS, the level shifter causes the high-voltage output signal to change from the high operating potential VDD HI to the reference potential VSS.

[0014] A component disclosed as "configured to be signal-controlled" (e.g., a transconductor or transistor) has a control node connected to one or more circuits that provide signals during operation of the corresponding semiconductor device. The control node may comprise the gate of a field-effect transistor or the base of a bipolar junction transistor. Similarly, a component disclosed as "configured to receive" a signal has a control node connected to one or more circuits that provide signals during operation of the corresponding semiconductor device. A component disclosed as "configured to provide" a signal is connected to one or more receiving elements at the current node of the component. The receiving element may be a control node of a transistor, such as the gate or base. A component disclosed as "configured to operate between a first potential (e.g., a high operating potential VDD HI or a low operating potential VDD LO) and a second potential (e.g., a reference potential VSS)" has a composition and architecture that enables the component to operate at a first potential applied to the first current node of the component and a second potential applied to the second current node of the component. The first and second current nodes can be the source and drain of a field-effect transistor, or the emitter and collector of a bipolar junction transistor. Transistors described as "high voltage" are configured to operate between a high operating potential VDD HI and a reference potential VSS, and transistors described as "low voltage" are configured to operate between a low operating potential VDD LO and a reference potential VSS. High-voltage transistors may have a longer channel length than low-voltage transistors. High-voltage transistors may have a thicker dielectric layer than low-voltage transistors. High-voltage transistors may have a drift region, while low-voltage transistors do not. High-voltage transistors may have other structural differences relative to low-voltage transistors. Due to their shorter channel length, low-voltage transistors can advantageously have higher switching speeds than high-voltage transistors.

[0015] The transducer and transistor are disclosed to be in an on-state or an off-state. The transducer and transistor in the on-state have lower impedance than in the off-state, and therefore can conduct more current than in the off-state.

[0016] Components disclosed as being coupled to or connected to another component or potential (e.g., a high operating potential VDD HI) are configured to support direct current (DC) through the connection between said component and the other component or potential. The aspects of this disclosure describing current flow and signal voltage transitions relate to the operation of a semiconductor device. Explaining current flow and signal voltage transitions aids in understanding the semiconductor device. When the semiconductor device is not powered, there may be no current flow and signal voltage transitions in the semiconductor device. Components disclosed as being connected to an operating potential or a reference potential, or connected between the operating potential and the reference potential, are connected to one or more conductive elements of the semiconductor device, said conductive elements being configured to provide a potential during operation of the semiconductor device.

[0017] The following describes one or more operational characteristics of various circuits, systems, and / or components in the context of functionality, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is powered and operated. The various structures and methods disclosed herein can be advantageously applied to manufactured electronic devices, such as integrated circuits. While various improvements are contemplated from such examples, this disclosure does not claim a particular outcome unless expressly stated in the specific claims.

[0018] Figure 1 This is a diagram of a semiconductor device having an example level shifter. As an example, semiconductor device 100 may be an integrated circuit, a microelectromechanical system (MEMS) device, an electro-optical device, a microfluidic device, or a micro-optical-mechanical device. Semiconductor device 100 includes a level shifter 102. Level shifter 102 is configured to receive a low-voltage input signal VSIG LV (in... Figure 1 The value marked "VSIG LV" is within the range of the reference potential VSS provided by the reference power rail of the semiconductor device 100. Figure 1 (marked as "VSS") to the low operating potential VDD LO provided by the second power rail of semiconductor device 100. Figure 1 (marked as "VDD LO" in the middle). Level shifter 102 is configured to provide a high-voltage output signal VSIG HV (in Figure 1 The value is marked as "VSIGHV" and ranges from the reference potential VSS to the high operating potential VDD HI provided by the first power rail of the semiconductor device 100. Figure 1 (marked as "VDD HI"). The high operating potential VDD HI is higher than the low operating potential VDD LO. The high-voltage output signal VSIGHV corresponds to the low-voltage input signal VSIG LV after a delay in signal propagation through level shifter 102.

[0019] Level shifter 102 includes a first buffer 104. The first buffer 104 is configured to receive a low-voltage input signal VSIG LV as input. The first buffer 104 includes a first pull-up transconductance 106 configured to be controlled by the low-voltage input signal VSIG LV. In this example, the first pull-up transconductance 106 is connected to a high operating potential VDD HI, such as... Figure 1As shown. The first pull-up transconductance 106 can be manifested as a single high-voltage transistor configured to operate between a high operating potential VDD HI and a reference potential VSS, such as a metal-oxide-semiconductor (MOS) transistor, a drain-extended MOS (DEMOS) transistor, a junction field-effect transistor (JFET), or a bipolar junction transistor (BJT). The first pull-up transconductance 106 can be manifested by two or more transistors configured, for example, to operate between the high operating potential VDD HI and the reference potential VSS in a cascode configuration. The current from the high operating potential VDD HI through the first pull-up transconductance 106 is controlled, i.e., modulated, by the low-voltage input signal VSIG LV. In this example, the first pull-up transconductance 106 has negative transconductance; the current through the first pull-up transconductance 106 decreases when the amplitude of the low-voltage input signal VSIG LV increases, and increases when the amplitude of the low-voltage input signal VSIG LV decreases.

[0020] The first buffer 104 includes a first pull-down transconductor 108 configured to be controlled by a low-voltage input signal VSIG LV. In this example, the first pull-down transconductor 108 is connected to a first pull-up transconductor 106, as shown below. Figure 1 As shown. The first pull-down transconductor 108 may be represented by a single high-voltage transistor, or by two or more transistors configured to operate between a high operating potential VDD HI and a reference potential VSS. The current from the first pull-up transconductor 106 through the first pull-down transconductor 108 is controlled by the low-voltage input signal VSIG LV. In this example, the first pull-down transconductor 108 has positive transconductance; the current through the first pull-down transconductor 108 increases when the amplitude of the low-voltage input signal VSIG LV increases, and the current through the first pull-down transconductor decreases when the amplitude of the low-voltage input signal VSIG LV decreases.

[0021] The first buffer 104 includes a first cutoff transconductor 110. The first cutoff transconductor 110 is configured to be cut off by a first delayed high-voltage cutoff signal 1st VCO DEL HV (in Figure 1The first delayed high-voltage cutoff signal 1st VCO DEL HV is controlled by the following: The first delayed high-voltage cutoff signal 1st VCO DEL HV corresponds inversely to the low-voltage input signal. That is, when the low-voltage input signal VSIG LV transitions from the reference potential VSS to the low operating potential VDD LO, the semiconductor device 100 causes the first delayed high-voltage cutoff signal 1st VCO DEL HV to transition from the high operating potential VDD HI to the reference potential VSS after at least a signal propagation delay through the level shifter 102. And when the low-voltage input signal VSIG LV transitions from the low operating potential VDD LO to the reference potential VSS, the semiconductor device 100 causes the first delayed high-voltage cutoff signal 1st VCO DEL HV to transition from the reference potential VSS to the high operating potential VDD HI after a delay of one or more logic gates. In this example, the first cutoff transconductor 110 is connected to the first pull-down transconductor 108, as shown below. Figure 1 As shown. The first cutoff transconductor 110 is connected to the reference potential VSS, as... Figure 1 As shown. The first cutoff transconductor 110 may be represented by a single high-voltage transistor, or by two or more transistors configured to operate between a high operating potential VDD HI and a reference potential VSS. The current from the first pull-down transconductor 108 through the first cutoff transconductor 110 is controlled by a first delayed high-voltage cutoff signal 1st VCO DEL HV. In this example, the first cutoff transconductor 110 has positive transconductance. By configuring the first cutoff transconductor 110 to be controlled by a first delayed high-voltage cutoff signal 1st VCO DEL HV, which ranges from the reference potential VSS to the high operating potential VDD HI, the transition from the delayed high-voltage signal to the low-voltage range can be advantageously eliminated, thereby enabling faster operation of the level shifter 102.

[0022] The first pull-up transconductor 106 is connected to the output VOUT 1st BFR of the first buffer 104. Figure 1 The output VOUT 1st BFR is marked as “VOUT 1st BFR”. The output VOUT 1st BFR provides voltage to other circuit elements of the semiconductor device 100, and the current through the output VOUT 1st BFR is less than the current from the first pull-up transconductor 106 to the first pull-down transconductor 108.

[0023] Level shifter 102 includes a rising-edge pull-up transconductance 112 connected to a high operating potential VDD HI. The output VOUT 1st BFR of first buffer 104 is connected to the input of rising-edge pull-up transconductance 112. Rising-edge pull-up transconductance 112 is configured to be controlled by the output of first buffer 104. Rising-edge pull-up transconductance 112 is connected to the high-voltage output signal VSIG HV of level shifter 102. In this example, rising-edge pull-up transconductance 112 has negative transconductance.

[0024] Level shifter 102 includes a pull-up auxiliary transconductance 114 connected to a high operating potential VDD HI. The pull-up auxiliary transconductance 114 is configured to be switched off by a second delayed high-voltage cutoff signal 2nd VCO DEL HV (in...). Figure 1 The second delayed high-voltage cutoff signal, 2nd VCO DEL HV, is controlled by a gate labeled "2nd VCO DEL HV". The range of 2nd VCO DEL HV is between the reference potential VSS and the high operating potential VDD HI, and corresponds inversely to the low-voltage input signal VSIG LV after a delay of one or more logic gates. A pull-up auxiliary transconductance 114 is connected to the output VOUT 1st BFR of the first buffer 104. In this example, the pull-up auxiliary transconductance 114 has negative transconductance.

[0025] Level shifter 102 includes a second buffer 116. The second buffer 116 is configured to receive an inverted low-voltage signal VSIGINV LV as input. The inverted low-voltage signal VSIGINV LV... Figure 1 The inverted low-voltage signal VSIGINV LV is marked as "VSIGINV LV" and corresponds to the low-voltage input signal VSIG LV inversely after a delay of one or more logic gates. The range of the inverted low-voltage signal VSIGINV LV is between the reference potential VSS and the low operating potential VDD LO.

[0026] The second buffer 116 includes a latched pull-up transconductor 122. The latched pull-up transconductor 122 is configured to receive a third delayed high-voltage cutoff signal 3rd VCO DEL HV (in... Figure 1 The third delayed high-voltage cutoff signal (3rd VCO DEL HV) is controlled by a gate labeled "3rd VCO DEL HV". The range of the third delayed high-voltage cutoff signal 3rd VCO DEL HV is between the reference potential VSS and the high operating potential VDD HI, and corresponds inversely to the low-voltage input signal VSIG LV after a delay of one or more logic gates. The latched pull-up transconductance 122 may be represented as a single high-voltage transistor, or by two or more transistors configured to operate between the high operating potential VDD HI and the reference potential VSS. In this example, the latched pull-up transconductance 122 has negative transconductance.

[0027] The second buffer 116 includes a second pull-up transconductor 118, which is configured to be controlled by an inverted low-voltage signal VSIG INV LV. In this example, the second pull-up transconductor 118 is connected to a latched pull-up transconductor 122, as... Figure 1 As shown. The second pull-up transconductor 118 may be any of the examples disclosed for the first pull-up transconductor 106. In this example, the second pull-up transconductor 118 has negative transconductance.

[0028] The second buffer 116 includes a second pull-down transconductor 120, which is configured to be controlled by an inverted low-voltage signal VSIG INV LV. In this example, the second pull-down transconductor 120 is coupled between the second pull-up transconductor 118 and the reference potential VSS, as shown below. Figure 1 As shown. The second pull-down transconductance 120 may be represented as a single high-voltage transistor, or by two or more transistors configured to operate between a high operating potential VDD HI and a reference potential VSS. In this example, the second pull-down transconductance 120 has positive transconductance.

[0029] The second pull-up transconductor 118 is connected to the output VOUT 2nd BFR of the second buffer 116. Figure 1 The output VOUT 2nd BFR is labeled "VOUT 2nd BFR". The output VOUT 2nd BFR is connected to the high-voltage output signal VSIG HV of the level shifter 102. The output VOUT 2nd BFR provides voltage to other circuit elements of the semiconductor device 100, and the current through the output VOUT 2nd BFR is less than the current from the second pull-up transconductor 118 to the second pull-down transconductor 120.

[0030] The semiconductor device 100 in this example further includes a low-voltage inverter 124. The low-voltage inverter 124 is connected between a low operating potential VDD LO and a reference potential VSS. The low-voltage inverter 124 is configured to be controlled by a low-voltage input signal VSIG LV. The low-voltage inverter 124 is configured to provide an inverted low-voltage signal VSIG INV LV, in Figure 1 The inverted low-voltage signal VSIG INV LV is marked as "VSIG INV LV". The range of the inverted low-voltage signal VSIG INV LV is between the reference potential VSS and the low operating potential VDD LO, and it corresponds inversely to the low-voltage input signal VSIG LV after a delay in signal propagation through the low-voltage inverter 124. The low-voltage inverter 124 may include a low-voltage transistor. The low-voltage inverter 124 may not have a high-voltage transistor, which advantageously reduces the signal propagation delay through the low-voltage inverter 124 compared to an inverter with a high-voltage transistor.

[0031] The semiconductor device 100 in this example further includes a high-voltage inverter 126. The high-voltage inverter 126 is connected between a high operating potential VDD HI and a reference potential VSS. The high-voltage inverter 126 is configured to be controlled by a high-voltage output signal VSIG HV. The high-voltage inverter 126 is configured to provide an inverted high-voltage signal VSIG INV HV, in Figure 1 The inverted high-voltage signal VSIGINV HV is labeled "VSIGINV HV". The range of the inverted high-voltage signal VSIGINV HV is between the reference potential VSS and the high operating potential VDD HI, and it corresponds inversely to the high-voltage output signal VSIG HV after a delay in signal propagation through the high-voltage inverter 126. The high-voltage inverter 126 may include a high-voltage transistor configured to operate between the high operating potential VDD HI and the reference potential VSS.

[0032] The semiconductor device 100 in this example further includes a high-voltage delay buffer 128, which is configured to receive an inverted high-voltage signal VSIGINV HV and provide a first delayed high-voltage cutoff signal 1stVCO DEL HV and a second delayed high-voltage cutoff signal 2ndVCO DEL HV, as shown below. Figure 1 As shown. The high-voltage delay buffer 128 may contain two delay stages. As an example, the high-voltage delay buffer 128 may contain a first high-voltage inverter 128a and a second high-voltage inverter 128b, both of which operate between the high operating potential VDD HI and the reference potential VSS, as shown. Figure 1 As shown. The first high-voltage inverter 128a can be configured to be controlled by an inverted high-voltage signal VSIGINV HV. The second high-voltage inverter 128b can be configured to be controlled by the output of the first high-voltage inverter 128a. The output of the second high-voltage inverter 128b can provide a first delayed high-voltage cutoff signal 1stVCO DELHV and a second delayed high-voltage cutoff signal 2ndVCO DELHV. Other circuitry of the high-voltage delay buffer 128 is configured within the scope of this example. In other versions of this example, the high-voltage delay buffer 128 can be configured to receive a high-voltage output signal VSIG HV. In such versions, the high-voltage delay buffer 128 can include one or three high-voltage inverters connected in sequence. The high-voltage delay buffer 128 can include a high-voltage transistor configured to operate between a high operating potential VDD HI and a reference potential VSS.

[0033] The operation of semiconductor device 100 includes a rising edge transition of the low-voltage input signal VSIG LV, that is, a transition of the low-voltage input signal VSIG LV from the reference potential VSS to the low operating potential VDD LO. The operation of semiconductor device 100 also includes a falling edge transition of the low-voltage input signal VSIG LV, that is, a transition of the low-voltage input signal VSIG LV from the low operating potential VDD LO to the reference potential VSS. (Reference) Figure 1 The operation of the semiconductor device 100 via rising edge transition and falling edge transition is disclosed.

[0034] Immediately before the rising edge transition, the low-voltage input signal VSIG LV is at the reference potential VSS, causing the first pull-up transconductor 106 to be turned on and the first pull-down transconductor 108 to be turned off. The first pull-up transconductor 106 being on and the first pull-down transconductor 108 being off causes the output VOUT 1stBFR of the first buffer 104 to be at a high operating potential VDD HI. The high operating potential VDD HI of the output VOUT 1stBFR of the first buffer 104 causes the rising edge pull-up transconductor 112 to be turned off.

[0035] Immediately before the rising edge transition, the inverted low-voltage signal VSIG INV LV is at a low operating potential VDD LO through the operation of the low-voltage inverter 124. The inverted low-voltage signal VSIG INV LV at the low operating potential VDD LO causes the second pull-up transconductor 118 to be off or near off, and causes the second pull-down transconductor 120 to be on or partially on, causing the output VOUT 2nd BFR of the second buffer 116 to be at the reference potential VSS. In the near off state, the second pull-up transconductor 118 has a lower impedance than in the off state, but a higher impedance than in the on state. In the partially on state, the second pull-down transconductor 120 has a higher impedance than in the on state, but a lower impedance than in the off state.

[0036] Immediately before the rising edge transition, the rising edge pull-up transconductor 112 is in the off state, and the output VOUT 2nd BFR of the second buffer 116 is at the reference potential VSS, causing the high-voltage output signal VSIG HV to be at the reference potential VSS. The high-voltage output signal VSIG HV being at the reference potential VSS causes the inverted high-voltage signal VSIGINV HV and the third delayed high-voltage cutoff signal 3rd VCO DEL HV to be at a high operating potential VDD HI through the operation of the high-voltage inverter 126. The inverted high-voltage signal VSIGINV HV being at a high operating potential VDD HI causes the first delayed high-voltage cutoff signal 1st VCO DEL HV and the second delayed high-voltage cutoff signal 2nd VCO DEL HV to be at a high operating potential VDD HI through the operation of the high-voltage delay buffer 128. The first delayed high-voltage cutoff signal 1st VCO DEL HV being at a high operating potential VDD HI causes the first cutoff transconductor 110 to be in the on state. The second delayed high-voltage cutoff signal 2nd VCO DEL HV, at a high operating potential VDD HI, causes the pull-up auxiliary transconductor 114 to be in the off state. The third delayed high-voltage cutoff signal 3rd VCO DEL HV, at a high operating potential VDD HI, causes the latched pull-up transconductor 122 to be in the off state, thereby increasing the total impedance between the output VOUT 2ndBFR of the second buffer 116 and the high operating potential VDD HI.

[0037] When the low-voltage input signal VSIG LV undergoes a rising edge transition, it changes from the reference potential VSS to the low operating potential VDD LO. This rising edge transition causes the low-voltage inverter 124 to invert the low-voltage signal VSIG INVLV from the low operating potential VDD LO back to the reference potential VSS.

[0038] In the first buffer 104, the low-voltage input signal VSIG LV transitions to a low operating potential VDD LO, causing the first pull-up transconductor 106 to turn off or near-off, and the first pull-down transconductor 108 to turn on or partially on. The first cut-off transconductor 110 being on, the first pull-up transconductor 106 being off or near-off, and the first pull-down transconductor 108 being on or partially on cause the output VOUT 1st BFR of the first buffer 104 to transition to the reference potential VSS. The first pull-down transconductor 108 can be configured to provide more current than the first pull-up transconductor 106 in its respective on state, which advantageously reduces the transition time of the output VOUT 1st BFR of the first buffer 104 to the reference potential VSS. Furthermore, having the first pull-up transconductor 106 in an off or near-off state reduces the current through the first pull-down transconductor 108 required for the output VOUT 1st BFR of the first buffer 104 to reach the reference potential VSS, thereby further advantageously reducing the transition time.

[0039] The second pull-down transconductor 120 turns off, thereby isolating the output VOUT 1st BFR of the first buffer 104 from the reference potential VSS. The transition of output VOUT 1st BFR to the reference potential VSS causes the rising-edge pull-up transconductor 112 to turn on, causing its output to transition from the reference potential VSS to the high operating potential VDD HI. The rising-edge pull-up transconductor 112 can be configured to provide sufficient current in the on-state to achieve the required speed at which its output transitions to the high operating potential VDD HI.

[0040] In the second buffer 116, the inverted low-voltage signal VSIG INV LV transitions to the reference potential VSS, causing the second pull-up transconductor 118 to turn on and the second pull-down transconductor 120 to turn off. With the latched pull-up transconductor 122 off and the second pull-down transconductor 120 off, the second buffer 116 presents a high impedance at its output VOUT 2nd BFR. Therefore, the high-voltage output signal VSIGHV of the level shifter 102 is driven by the rising edge of the pull-up transconductor 112 to transition from the reference potential VSS to the high operating potential VDD HI.

[0041] The high-voltage output signal VSIG HV transitions to a high operating potential VDD HI, causing the inverted high-voltage signal VSIG INV HV and the third delayed high-voltage cutoff signal 3rd VCO DEL HV to be converted to the reference potential VSS through the operation of the high-voltage inverter 126. The conversion of the third delayed high-voltage cutoff signal 3rd VCO DEL HV to the reference potential VSS causes the latched pull-up transconductor 122 to turn on. With both the latched pull-up transconductor 122 and the second pull-up transconductor 118 on and the second pull-down transconductor 120 off, the output VOUT 2nd BFR of the second buffer 116 transitions to a high operating potential VDDHI, thereby strengthening the output of the rising edge pull-up transconductor 112.

[0042] The inverted high-voltage signal VSIG INV HV transforms into the reference potential VSS, causing the first delayed high-voltage cutoff signal 1stVCO DEL HV and the second delayed high-voltage cutoff signal 2ndVCO DEL HV to transform into the reference potential VSS through the operation of the high-voltage delay buffer 128 after the signal propagation delay. The transformation of the second delayed high-voltage cutoff signal 2ndVCO DEL HV into the reference potential VSS causes the pull-up auxiliary transconductor 114 to turn on, which causes the output of the pull-up auxiliary transconductor 114 to turn into a high operating potential VDD HI. This, in turn, causes the rising edge pull-up transconductor 112 to turn off, thereby isolating the high-voltage output signal VSIG HV of the level shifter 102 from the high operating potential VDD HI through the rising edge pull-up transconductor 112.

[0043] The first delayed high-voltage cutoff signal 1st VCO DEL HV transitions to the reference potential VSS, causing the first cutoff transconductor 110 to turn off. This advantageously reduces the current flowing through the first pull-down transconductor 108. The output of the pull-up auxiliary transconductor 114 transitions to a high operating potential VDD HI, which, combined with the first cutoff transconductor 110 turning off, advantageously resets the output VOUT 1st BFR of the first buffer 104 to a high operating potential VDD HI, thereby preparing for the subsequent falling edge transition of the low-voltage input signal VSIGLV. The pull-up auxiliary transconductor 114 can be configured to provide sufficient current to reset the output VOUT 1st BFR of the first buffer 104 to a high operating potential VDD HI within the required reset time. Therefore, the pull-up auxiliary transconductor 114 enables the first pull-up transconductor 106 to provide sufficient current to keep the output VOUT 1st BFR of the first buffer 104 at a high operating potential VDD HI when both the first pull-down transconductor 108 and the pull-up auxiliary transconductor 114 are in the off state, but the current is less than that of the first pull-down transconductor 108.

[0044] When the low-voltage input signal VSIG LV undergoes a falling edge transition, it changes from the low operating potential VDD LO to the reference potential VSS. This falling edge transition causes the low-voltage inverter 124 to invert the low-voltage signal VSIG INV LV from the reference potential VSS to the low operating potential VDD LO.

[0045] In the first buffer 104, the low-voltage input signal VSIG LV transitions to the reference potential VSS, causing the first pull-up transconductor 106 to turn on and the first pull-down transconductor 108 to turn off. With the first cutoff transconductor 110 off, the first pull-up transconductor 106 on, and the first pull-down transconductor 108 off, the output VOUT 1st BFR of the first buffer 104 is maintained at a high operating potential VDD HI.

[0046] In the second buffer 116, the inverted low-voltage signal VSIG INV LV transitions to a low operating potential VDD LO, causing the second pull-up transconductor 118 to turn off or near turn off, and causing the second pull-down transconductor 120 to turn on or partially turn on. The latched pull-up transconductor 122 is on because the third delayed high-voltage cutoff signal 3rdVCO DEL HV is at the reference potential VSS through the operation of the high-voltage inverter 126. The latched pull-up transconductor 122 being on, the second pull-up transconductor 118 transitions to a turn off or near turn off, and the second pull-down transconductor 120 transitions to a turn on or partially turn on, causes the output VOUT 2nd BFR of the second buffer 116 to transition to the reference potential VSS. The second pull-down transconductor 120 can be configured to provide more current than the second pull-up transconductor 118 and more current than the latched pull-up transconductor 122 in the corresponding on state, which can advantageously reduce the transition time of the output VOUT 2ndBFR of the second buffer 116 to the reference potential VSS.

[0047] The output VOUT 1st BFR of the first buffer 104 is at a high operating potential VDD HI, which keeps the rising edge pull-up transconductor 112 in the off state, thereby maintaining the isolation of the high-voltage output signal VSIG HV of the level shifter 102 through the rising edge pull-up transconductor 112. Therefore, the high-voltage output signal VSIG HV of the level shifter 102 is driven by the output VOUT 2nd BFR of the second buffer 116 to become the reference potential VSS.

[0048] The high-voltage output signal VSIG HV transitions to the reference potential VSS, causing the inverted high-voltage signal VSIGINV HV and the third delayed high-voltage cutoff signal 3rd VCO DEL HV to transition to the high operating potential VDDHI through the operation of the high-voltage inverter 126. The transition of the third delayed high-voltage cutoff signal 3rd VCO DEL HV to the high operating potential VDDHI causes the latched pull-up transconductor 122 to turn off. With the latched pull-up transconductor 122 off, the second pull-up transconductor 118 off or near-off, and the second pull-down transconductor 120 on, the output VOUT 2ndBFR of the second buffer 116 is stabilized at the reference potential VSS.

[0049] The inverted high-voltage signal VSIG INV HV transitions to a high operating potential VDD HI, causing the first delayed high-voltage cutoff signal 1st VCO DEL HV and the second delayed high-voltage cutoff signal 2nd VCO DEL HV to transition to a high operating potential VDD HI through the operation of the high-voltage delay buffer 128 after the signal propagation delay through the high-voltage delay buffer 128. The transition of the second delayed high-voltage cutoff signal 2nd VCO DEL HV to a high operating potential VDD HI causes the pull-up auxiliary transconductor 114 to turn off, which provides high impedance to the output VOUT 1st BFR of the first buffer 104, thereby enabling the subsequent rising edge transition of the low-voltage input signal VSIGLV. Connecting the first pull-down transconductor 108 between the first pull-up transconductor 106 and the first cutoff transconductor 110 advantageously prevents the potential interruption at the output VOUT 1st BFR of the first buffer 104 when the first delayed high-voltage cutoff signal 1st VCO DEL HV transitions to a high operating potential VDD HI.

[0050] The first delayed high-voltage cutoff signal 1st VCO DEL HV transitions to a high operating potential VDD HI, causing the first cutoff transconductor 110 to turn on, thereby enabling the subsequent rising edge transition of the low-voltage input signal VSIG LV.

[0051] In an alternative version of this example, the high-voltage delay buffer 128 may contain more than two logic gates in its signal propagation path. In an alternative version of this example, the first cutoff transconductor 110 may be connected between the first pull-up transconductor 106 and the first pull-down transconductor 108. In an alternative version of this example, the latched pull-up transconductor 122 may be connected between the second pull-up transconductor 118 and the second pull-down transconductor 120.

[0052] Figure 2A and Figure 2B This is a schematic diagram of another semiconductor device having an example level shifter. Semiconductor device 200 may be represented as a reference. Figure 1 The semiconductor device 100 may be any type of device disclosed therein. The semiconductor device 200 includes a level shifter 202. The level shifter 202 is configured to receive a low-voltage input signal VSIG LV, in... Figure 2A The value marked "VSIG LV" ranges from the reference potential VSS to the low operating potential VDD LO. Figure 2A These are labeled "VSS" and "VDD LO" respectively. Level shifter 202 is configured to provide a high-voltage output signal VSIG HV, in... Figure 2A and Figure 2B The value marked "VSIG HV" ranges from the reference potential VSS to the high operating potential VDD HI. Figure 2A and Figure 2B The high operating potential VDDHI is marked as "VDD HI". The high operating potential VDDHI is higher than the low operating potential VDD LO. The high-voltage output signal VSIG HV corresponds to the low-voltage input signal VSIG LV after the signal propagation delay through the level shifter 202.

[0053] The transistors in semiconductor device 200 are disclosed as p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors. In this example, the PMOS and NMOS transistors are enhancement-mode transistors.

[0054] Level shifter 202 includes a first buffer 204 configured to receive a low-voltage input signal VSIG LV as input. The first buffer 204 includes a first pull-up PMOS transistor 206, a first pull-down NMOS transistor 208, and a first cutoff NMOS transistor 210 connected in series between a high operating potential VDD HI and a reference potential VSS. The first pull-up PMOS transistor 206 and the first pull-down NMOS transistor 208 are configured to be controlled by the low-voltage input signal VSIG LV; that is, the gates of the first pull-up PMOS transistor 206 and the first pull-down NMOS transistor 208 are connected to a circuit (not shown) configured to provide the low-voltage input signal VSIG LV. The first cutoff NMOS transistor 210 is configured to be controlled by a delayed high-voltage cutoff signal VCO DEL HV (in...). Figure 2A and Figure 2BThe high-voltage cutoff signal VCO DEL HV is controlled by a delay signal (marked as "VCO DEL HV"). The high-voltage cutoff signal VCO DEL HV corresponds inversely to the low-voltage input signal VSIG LV after a delay in signal propagation through level shifter 202, high-voltage inverter 226, and high-voltage delay buffer 228. The gate of the first cutoff NMOS transistor 210 is connected to the output of the high-voltage delay buffer 228. The drain of the first pull-up PMOS transistor 206 is connected to the drain of the first pull-down NMOS transistor 208; the drains of the first pull-up PMOS transistor 206 and the first pull-down NMOS transistor 208 provide the output of the first buffer 204. The output of the first buffer 204 provides voltage to other circuit elements of the semiconductor device 200, while the current through the output of the first buffer 204 is less than the current from the first pull-up PMOS transistor 206 to the first pull-down NMOS transistor 208.

[0055] Level shifter 202 includes a rising-edge pull-up PMOS transistor 212 connected to a high operating potential VDD HI. The rising-edge pull-up PMOS transistor 212 is configured to be controlled by the output of the first buffer 204, i.e., the gate of the rising-edge pull-up PMOS transistor 212 is connected to the drains of a first pull-up PMOS transistor 206 and a first pull-down NMOS transistor 208. The drain of the rising-edge pull-up PMOS transistor 212 is connected to the high-voltage output signal VSIG HV of level shifter 202.

[0056] Level shifter 202 includes a pull-up auxiliary PMOS transistor 214 connected to a high operating potential VDD HI. The pull-up auxiliary PMOS transistor 214 is configured to be controlled by a delayed high-voltage cutoff signal VCO DEL HV. The drain of the pull-up auxiliary PMOS transistor 214 is connected to the drain of a first pull-up PMOS transistor 206.

[0057] The semiconductor device 200 in this example includes a low-voltage inverter 224. The low-voltage inverter 224 is configured to receive a low-voltage input signal VSIG LV and provide an inverted low-voltage signal VSIG INV LV. Figure 2A The inverted low-voltage signal VSIG INV LV corresponds to the low-voltage input signal VSIG LV in reverse after a delay in signal propagation through the low-voltage inverter 224. The range of the inverted low-voltage signal VSIG INV LV is between the reference potential VSS and the low operating potential VDD LO.

[0058] The low-voltage inverter 224 may include a low-voltage pull-up PMOS transistor 224a and a low-voltage pull-down NMOS transistor 224b connected in series between the low operating potential VDD LO and the reference potential VSS, such as Figure 2AAs shown. The low-voltage pull-up PMOS transistor 224a and the low-voltage pull-down NMOS transistor 224b can each be controlled by a low-voltage input signal VSIG LV. The low-voltage pull-up PMOS transistor 224a has negative transconductance, and the low-voltage pull-down NMOS transistor 224b has positive transconductance. The low-voltage pull-up PMOS transistor 224a and the low-voltage pull-down NMOS transistor 224b can be configured to operate between a low operating potential VDD LO and a reference potential VSS. The low-voltage pull-up PMOS transistor and the low-voltage pull-down NMOS transistor can have a shorter channel length and a thinner gate dielectric layer than high-voltage transistors (i.e., transistors configured to operate between a high operating potential VDD HI and a reference potential VSS). Due to the shorter channel length, the low-voltage transistor can advantageously have a higher switching speed than the high-voltage transistor. The drain of the low-voltage pull-up PMOS transistor 224a is connected to the drain of the low-voltage pull-down NMOS transistor 224b. The drains of the low-voltage pull-up PMOS transistor 224a and the low-voltage pull-down NMOS transistor 224b can provide an inverted low-voltage signal VSIG INV LV, such as... Figure 2A As shown.

[0059] Level shifter 202 includes a second buffer 216 configured to receive an inverted low-voltage signal VSIGINV LV as input. The second buffer 216 includes a latching pull-up PMOS transistor 222, a second pull-up PMOS transistor 218, a second pull-down NMOS transistor 220, and a buffer enable NMOS transistor 234 connected in series between a high operating potential VDD HI and a reference potential VSS. The second pull-up PMOS transistor 218 and the second pull-down NMOS transistor 220 are configured to be controlled by the inverted low-voltage signal VSIG INV LV. The latching pull-up PMOS transistor 222 is configured to be controlled by the inverted high-voltage signal VSIG INVHV (in...). Figure 2A and Figure 2B The inverted high-voltage signal VSIGINV HV ranges from the reference potential VSS to the high operating potential VDD HI, and corresponds inversely to the high-voltage output signal VSIG HV after a delay in signal propagation through the high-voltage inverter 226. The buffer-enabled NMOS transistor 234 is configured to be enabled by the enable signal ENABLE (in...). Figure 2A and Figure 2BThe enable signal (marked "ENABLE") is controlled by a voltage. The ENABLE signal ranges from the reference potential VSS to the high operating potential VDD HI, and is set to the high operating potential VDD HI for normal operation of the level shifter 202. The ENABLE signal can be set to the reference potential VSS during startup of the semiconductor device 200, during an assertion of a sleep condition, or at other times. The drain of the second pull-up PMOS transistor 218 is connected to the drain of the second pull-down NMOS transistor 220; the drains of the second pull-up PMOS transistor 218 and the second pull-down NMOS transistor 220 are connected to the high-voltage output signal VSIG HV of the level shifter 202.

[0060] The semiconductor device 200 in this example further includes a reset pull-up PMOS transistor 236 connected between the high operating potential VDD HI and the high-voltage output signal VSIG HV of the level shifter 202. The reset pull-up PMOS transistor 236 is configured to respond to a reset signal RESET (in... Figure 2A The reset signal (referred to as "RESET") is controlled by a reference potential VSS to a high operating potential VDD HI, and is set to a high operating potential VDD HI for normal operation of the level shifter 202 and during sleep mode. The reset signal RESET can be set to the reference potential VSS during startup of the semiconductor device 200 or at other times.

[0061] In some implementations, it may be advantageous to arrange the first pull-up PMOS transistor 206, the first pull-down NMOS transistor 208, and the first cutoff NMOS transistor 210 as shown in the figure, wherein the first cutoff NMOS transistor 210 is connected between the first pull-down NMOS transistor 208 and the reference potential VSS. In an alternative configuration where the first pull-down NMOS transistor 208 is connected between the first cutoff NMOS transistor 210 and the reference potential VSS, in some cases, the transition of VCO DEV HV from a low state to a high state may cause charge sharing on the circuit node to which the gate of the rising edge pull-up PMOS transistor 212 is connected.

[0062] The semiconductor device 200 in this example also includes a high-voltage inverter 226. The high-voltage inverter 226 is configured to provide an inverted high-voltage signal VSIGINVHV. The high-voltage inverter 226 may include a high-voltage inverter pull-up PMOS transistor 226a and a high-voltage inverter pull-down NMOS transistor 226b connected in series between the high operating potential VDDHI and the reference potential VSS, as shown below. Figure 2AAs shown. The high-voltage inverter pull-up PMOS transistor 226a and the high-voltage inverter pull-down NMOS transistor 226b can each be controlled by a high-voltage output signal VSIG HV. The high-voltage inverter pull-up PMOS transistor 226a has negative transconductance, and the high-voltage inverter pull-down NMOS transistor 226b has positive transconductance. The high-voltage inverter pull-up PMOS transistor 226a and the high-voltage inverter pull-down NMOS transistor 226b can be configured to operate between a high operating potential VDD HI and a reference potential VSS to provide an inverted high-voltage signal VSIGINV HV with a desired range between the high operating potential VDD HI and the reference potential VSS. The drain of the high-voltage inverter pull-up PMOS transistor 226a is connected to the drain of the high-voltage inverter pull-down NMOS transistor 226b; the drains of the high-voltage inverter pull-up PMOS transistor 226a and the high-voltage inverter pull-down NMOS transistor 226b can provide the inverted high-voltage signal VSIGINVHV, as... Figure 2A As shown.

[0063] The semiconductor device 200 in this example further includes a high-voltage delay buffer 228 configured to provide a delayed high-voltage cutoff signal VCO DEL HV. The high-voltage delay buffer 228 may include two delay stages. The high-voltage delay buffer 228 may include a high-voltage NAND gate 228a and a high-voltage delayed inverter 228b. The high-voltage NAND gate 228a includes a signal-controlled pull-up PMOS transistor 228c and an enable-controlled pull-up PMOS transistor 228d connected in parallel to a high operating potential VDD HI. The signal-controlled pull-up PMOS transistor 228c is configured to be controlled by an inverted high-voltage signal VSIGINV HV, and the enable-controlled pull-up PMOS transistor 228d is configured to be controlled by an enable signal ENABLE. The high-voltage NAND gate 228a also includes a signal-controlled pull-down NMOS transistor 228e and an enable-controlled pull-down NMOS transistor 228f connected in series between the reference potential VSS and the drains of the signal-controlled pull-up PMOS transistor 228c and the enable-controlled pull-up PMOS transistor 228d, as shown below. Figure 2B As shown. The signal-controlled pull-down NMOS transistor 228e is configured to be controlled by an inverted high-voltage signal VSIGINV HV, and the enable-controlled pull-down NMOS transistor 228f is configured to be controlled by an enable signal ENABLE. The drain of the signal-controlled pull-down NMOS transistor 228e can be connected to the drain of the signal-controlled pull-up PMOS transistor 228c and the enable-controlled pull-up PMOS transistor 228d, and the source of the enable-controlled pull-down NMOS transistor 228f can be connected to a reference potential VSS, as shown. Figure 2BAs shown. Alternatively, the signal-controlled pull-down NMOS transistor 228e and the enable-controlled pull-down NMOS transistor 228f can be interchanged, such that the drain of the enable-controlled pull-down NMOS transistor 228f can be connected to the drain of the signal-controlled pull-up PMOS transistor 228c and the enable-controlled pull-up PMOS transistor 228d, and the source of the signal-controlled pull-down NMOS transistor 228e can be connected to the reference potential VSS.

[0064] The high-voltage delayed inverter 228b may include a delayed pull-up transistor 228g and a delayed pull-down transistor 228h connected in series between the high operating potential VDD HI and the reference potential VSS, such as Figure 2B As shown. The delayed pull-up transistor 228g and delayed pull-down transistor 228h can be controlled by the drains of the signal-controlled pull-up PMOS transistor 228c and the enable-controlled pull-up PMOS transistor 228d, as well as the signal-controlled pull-down NMOS transistor 228e and the enable-controlled pull-down NMOS transistor 228f. The drains of the delayed pull-up transistor 228g and the delayed pull-down transistor 228h can be connected to each other; the drains of the delayed pull-up transistor 228g and the delayed pull-down transistor 228h can provide a delayed high-voltage cutoff signal VCO DEL HV. The signal-controlled pull-up PMOS transistor 228c, the enable-controlled pull-up PMOS transistor 228d, the signal-controlled pull-down NMOS transistor 228e, the enable-controlled pull-down NMOS transistor 228f, the delayed pull-up transistor 228g, and the delayed pull-down transistor 228h can be configured to operate between a high operating potential VDD HI and a reference potential VSS to provide a delayed high-voltage cutoff signal VCO DEL HV with a desired range between the high operating potential VDD HI and the reference potential VSS. Other circuitry configurations for the high-voltage delay buffer 228 are within the scope of this example.

[0065] The semiconductor device 200 in this example also includes a sleep signal inverter 230, which is configured to receive a sleep signal SLEEP (in the context of sleep signal inverters). Figure 2B Marked as "SLEEP" in the middle, and configured to provide the inverted sleep signal INVSLEEP (in Figure 2B (Identified as "INV SLEEP"). The range of the sleep signal SLEEP and the inverted sleep signal INV SLEEP can be between the reference potential VSS and the high operating potential VDD HI. The inverted sleep signal INV SLEEP corresponds to the sleep signal SLEEP in reverse after a delay in signal propagation through the sleep signal inverter 230. The sleep signal inverter 230 may include a sleep pull-up PMOS transistor 230a and a sleep pull-down NMOS transistor 230b connected in series between the high operating potential VDD HI and the reference potential VSS, as shown below. Figure 2B As shown. The sleep pull-up PMOS transistor 230a and the sleep pull-down NMOS transistor 230b can each be controlled by a sleep signal SLEEP. The sleep pull-up PMOS transistor 230a and the sleep pull-down NMOS transistor 230b can be configured to operate between a high operating potential VDD HI and a reference potential VSS to provide an inverted sleep signal INV SLEEP with a desired range between the high operating potential VDD HI and the reference potential VSS. The drain of the sleep pull-up PMOS transistor 230a is connected to the drain of the sleep pull-down NMOS transistor 230b; the drains of the sleep pull-up PMOS transistor 230a and the sleep pull-down NMOS transistor 230b can provide an inverted sleep signal INV SLEEP, as shown. Figure 2B As shown.

[0066] The semiconductor device 200 in this example further includes a sleep latch 232. The sleep latch 232 in this example includes a sleep pull-up leg 232a connected between the high operating potential VDD HI and the high-voltage output signal VSIG HV. The sleep latch 232 in this example includes a sleep pull-down leg 232b connected between the high-voltage output signal VSIG HV and the reference potential VSS.

[0067] The sleep pull-up branch 232a includes a latched pull-up PMOS transistor 222 connected in series with the sleep isolation PMOS transistor 232c. The latched pull-up PMOS transistor 222 is configured to be controlled by an inverted high-voltage signal VSIGINVHV, as disclosed in reference second buffer 216. The sleep isolation PMOS transistor 232c is configured to be controlled by an inverted sleep signal INVSLEEP. The sleep isolation PMOS transistor 232c may be a high-voltage transistor configured to operate between a high operating potential VDDHI and a reference potential VSS. The drain of the sleep isolation PMOS transistor 232c may be connected to the high-voltage output signal VSIGHV, as disclosed in reference second buffer 216. Figure 2B As shown.

[0068] The sleep pull-down branch 232b includes a sleep pull-down NMOS transistor 232d connected in series with the sleep isolation NMOS transistor 232e. The sleep pull-down NMOS transistor 232d is configured to be controlled by an inverted high-voltage signal VSIG INV HV. The sleep isolation NMOS transistor 232e is configured to be controlled by a sleep signal SLEEP. Both the sleep pull-down NMOS transistor 232d and the sleep isolation NMOS transistor 232e can be high-voltage transistors. The drain of the sleep isolation NMOS transistor 232e can be connected to the high-voltage output signal VSIG HV, and the source of the sleep pull-down NMOS transistor 232d can be connected to a reference potential VSS, such as... Figure 2B As shown.

[0069] The operation of the semiconductor device 200 in this example includes the rising edge transition of the low-voltage input signal VSIG LV, the falling edge transition of the low-voltage input signal VSIG LV, sleep mode, and reset mode. The operation of the semiconductor device 200 with respect to the enable signal ENABLE, the sleep signal SLEEP, and the reset signal RESET is disclosed. (Reference) Figure 2A and Figure 2B The operation of the semiconductor device 200 is disclosed. During rising-edge transitions and falling-edge transitions, the enable signal ENABLE and the reset signal RESET are at high operating potentials VDD HI, and the sleep signal SLEEP is at a reference potential VSS. During sleep mode, the sleep signal SLEEP and the reset signal RESET are at high operating potentials VDD HI, and the enable signal ENABLE is at the reference potential VSS. During reset mode, the enable signal ENABLE, the reset signal RESET, and the sleep signal SLEEP are all at the reference potential VSS.

[0070] Regarding the rising edge, immediately before the rising edge transition, in the first buffer 204, the low-voltage input signal VSIG LV is at the reference potential VSS, which turns on the first pull-up PMOS transistor 206 and turns off the first pull-down NMOS transistor 208, thereby causing the drain of the first pull-up PMOS transistor 206 to be at a high operating potential VDD HI. The high operating potential VDD HI of the drain of the first pull-up PMOS transistor 206 causes the rising edge pull-up PMOS transistor 212 to be turned off.

[0071] Immediately before the rising edge transition, the inverted low-voltage signal VSIG INV LV is at a low operating potential VDD LO through the operation of the low-voltage inverter 224. In the second buffer 216, the inverted low-voltage signal VSIGINV LV at the low operating potential VDD LO causes the second pull-up PMOS transistor 218 to be off or near off, and causes the second pull-down NMOS transistor 220 to be on or partially on. The enable signal ENABLE at the high operating potential VDD HI causes the buffer enable NMOS transistor 234 to be on. The rising edge pull-up PMOS transistor 212 being off, the second pull-up PMOS transistor 218 being off or near off, the second pull-down NMOS transistor 220 being on or partially on, and the buffer enable NMOS transistor 234 being on, causes the high-voltage output signal VSIG HV of the level shifter 202 to be at the reference potential VSS. The reset signal RESET being at a high operating potential VDD HI causes the reset pull-up PMOS transistor 236 to be in the off state.

[0072] Immediately before the rising edge transition, the high-voltage output signal VSIG HV at the reference potential VSS, through the operation of the high-voltage inverter 226, causes the inverted high-voltage signal VSIG INV HV to reach a high operating potential VDD HI. The inverted high-voltage signal VSIG INV HV and the enable signal ENABLE, both at a high operating potential VDD HI, through the operation of the high-voltage delay buffer 228, cause the delayed high-voltage cutoff signal VCO DEL HV to reach a high operating potential VDD HI. The delayed high-voltage cutoff signal VCO DEL HV at a high operating potential VDD HI causes the first cutoff NMOS transistor 210 to be turned on and the pull-up auxiliary PMOS transistor 214 to be turned off. The inverted high-voltage signal VSIG INV HV at a high operating potential VDD HI causes the latching pull-up PMOS transistor 222 to be turned off.

[0073] Immediately before the rising edge transition, the sleep signal SLEEP, at the reference potential VSS, causes the inverted sleep signal INV SLEEP to reach a high operating potential VDD HI through the operation of the sleep signal inverter 230. In the sleep latch 232, the sleep signal SLEEP at the reference potential VSS turns off the sleep isolation NMOS transistor 232e, and the inverted sleep signal INV SLEEP at the high operating potential VDD HI turns off the sleep isolation PMOS transistor 232c. This isolates the high voltage output signal VSIG HV of the level shifter 202 from the high operating potential VDD HI through the sleep pull-up branch 232a, and isolates the high voltage output signal VSIG HV from the reference potential VSS through the sleep pull-down branch 232b.

[0074] When the low-voltage input signal VSIG LV undergoes a rising edge transition, it changes from the reference potential VSS to the low operating potential VDD LO, causing the first pull-up PMOS transistor 206 to turn off or near turn off, and the first pull-down NMOS transistor 208 to turn on or partially turn on. The first cutoff NMOS transistor 210 remains on. Therefore, the first pull-up PMOS transistor 206 turning off or near turn off and the first pull-down NMOS transistor 208 turning on or partially turn on cause the drain of the first pull-down NMOS transistor 208 to return to the reference potential VSS. This causes the rising edge pull-up PMOS transistor 212 to turn on, and consequently, the drain of the rising edge pull-up PMOS transistor 212 to transition from the reference potential VSS to the high operating potential VDD HI. The rising edge pull-up PMOS transistor 212 can be configured to provide sufficient current in the on state to achieve the required speed at which its output transitions to the high operating potential VDD HI.

[0075] The rising edge transition causes the low-voltage inverter 224 to change the inverted low-voltage signal VSIG INV LV from the low operating potential VDDLO to the reference potential VSS, thereby turning on the second pull-up PMOS transistor 218 and turning off the second pull-down NMOS transistor 220. The buffer enable NMOS transistor 234 remains on. The latch pull-up PMOS transistor 222 remains off and the second pull-down NMOS transistor 220 turns off, causing the drains of the second pull-down NMOS transistor 220 and the second pull-up PMOS transistor 218 to present high impedance, so that the high-voltage output signal VSIG HV of the level shifter 202 is driven by the drain of the rising edge pull-up PMOS transistor 212 to change from the reference potential VSS to the high operating potential VDD HI.

[0076] The high-voltage output signal VSIG HV transitions to a high operating potential VDD HI. Through the operation of the high-voltage inverter 226, the inverted high-voltage signal VSIGINV HV transitions to a reference potential VSS. This transition causes the latching pull-up PMOS transistor 222 to turn on. With both the latching pull-up PMOS transistor 222 and the second pull-up PMOS transistor 218 on, and the second pull-down NMOS transistor 220 off, the drain of the second pull-up PMOS transistor 218 transitions to a high operating potential VDD HI, thereby strengthening the high operating potential VDD HI at the drain of the rising-edge pull-up PMOS transistor 212.

[0077] The inverted high-voltage signal VSIGINV HV transitions to the reference potential VSS, causing the delayed high-voltage cutoff signal VCO DEL HV, after signal propagation delay through the high-voltage NAND gate 228a and the high-voltage delay inverter 228b, to transition to the reference potential VSS through the operation of the high-voltage delay buffer 228. The transition of the delayed high-voltage cutoff signal VCO DEL HV to the reference potential VSS causes the pull-up auxiliary PMOS transistor 214 to turn on, which in turn causes the drain of the pull-up auxiliary PMOS transistor 214 to turn on to a high operating potential VDD HI. This, in turn, causes the rising-edge pull-up PMOS transistor 212 to turn off, thereby isolating the high-voltage output signal VSIG HV of the level shifter 202 from the high operating potential VDD HI through the rising-edge pull-up PMOS transistor 212.

[0078] The delayed transition of the high-voltage cutoff signal VCO DEL HV to the reference potential VSS also causes the first cutoff NMOS transistor 210 to turn off, which advantageously reduces the current flowing through the first pull-down NMOS transistor 208. The transition of the drain of the pull-up auxiliary PMOS transistor 214 to a high operating potential VDD HI, combined with the turn-off of the first cutoff NMOS transistor 210, advantageously resets the drain of the first pull-down NMOS transistor 208 to a high operating potential VDD HI, thereby preparing for the subsequent falling edge transition of the low-voltage input signal VSIG LV.

[0079] Regarding the falling edge transition, the low-voltage input signal VSIG LV changes from the low operating potential VDD LO to the reference potential VSS, causing the first pull-up PMOS transistor 206 to turn on and the first pull-down NMOS transistor 208 to turn off. The first cutoff NMOS transistor 210 remains off, the first pull-up PMOS transistor 206 turns on, and the first pull-down NMOS transistor 208 turns off, keeping the drain of the first pull-up PMOS transistor 206 at the high operating potential VDD HI.

[0080] A falling edge transition causes the low-voltage inverter 224 to change the inverted low-voltage signal VSIG INV LV from the reference potential VSS to the low operating potential VDD LO, thereby causing the second pull-up PMOS transistor 218 to turn off or near turn off, and causing the second pull-down NMOS transistor 220 to turn on or partially turn on. The latched pull-up PMOS transistor 222 is in the on state because the delayed high-voltage cutoff signal VCO DEL HV is still at the reference potential VSS. The buffer-enabled NMOS transistor 234 remains in the on state. With the latched pull-up PMOS transistor 222 in the on state, the second pull-up PMOS transistor 218 in the off or near turn off state, the second pull-down NMOS transistor 220 in the on or partially turn on state, and the buffer-enabled NMOS transistor 234 in the on state, the drain node of the second pull-down NMOS transistor 220 turns to near the reference potential VSS.

[0081] The drain of the first pull-up PMOS transistor 206 is at a high operating potential VDD HI, keeping the rising edge pull-up PMOS transistor 212 in the off state. Therefore, the rising edge pull-up PMOS transistor 212 maintains the isolation of the high-voltage output signal VSIG HV of the level shifter 202. Thus, the high-voltage output signal VSIG HV of the level shifter 202 is driven by the drain node of the second pull-down NMOS transistor 220 to become the reference potential VSS. The reset signal RESET remains at a high operating potential VDD HI, keeping the reset pull-up PMOS transistor 236 in the off state, thereby isolating the high-voltage output signal VSIG HV of the level shifter 202 from the high operating potential VDD HI through the reset pull-up PMOS transistor 236.

[0082] The high-voltage output signal VSIG HV is transformed into a reference potential VSS. Through the operation of the high-voltage inverter 226, the inverted high-voltage signal VSIG INV HV is transformed into a high operating potential VDD HI, thereby causing the latching pull-up PMOS transistor 222 to turn off. With the latching pull-up PMOS transistor 222 in the off state, the second pull-up PMOS transistor 218 in the off state or near-off state, and the second pull-down NMOS transistor 220 and the buffer enable NMOS transistor 234 both in the on state, the drain node of the second pull-down NMOS transistor 220 is stabilized at the reference potential VSS.

[0083] The inverted high-voltage signal VSIG INV HV transitions to a high operating potential VDD HI, and the enable signal ENABLE is also at a high operating potential VDD HI. This causes the delayed high-voltage cutoff signal VCO DEL HV to transition to a high operating potential VDD HI after the signal propagation delay through the high-voltage delay buffer 228. The transition of the delayed high-voltage cutoff signal VCO DEL HV to a high operating potential VDD HI causes the pull-up auxiliary PMOS transistor 214 to turn off, which provides high impedance to the drain of the first pull-down NMOS transistor 208, thereby enabling the subsequent rising edge transition of the low-voltage input signal VSIG LV. The transition of the delayed high-voltage cutoff signal VCO DEL HV to a high operating potential VDD HI also causes the first cutoff NMOS transistor 210 to turn on, thereby enabling the subsequent rising edge transition of the low-voltage input signal VSIG LV.

[0084] In sleep mode, the sleep signal SLEEP transitions from the reference potential VSS to the high operating potential VDD HI, and the enable signal ENABLE transitions from the high operating potential VDD HI to the reference potential VSS. During sleep mode, the reset signal RESET remains at the high operating potential VDD HI. The transition of the sleep signal SLEEP to the high operating potential VDD HI causes the inverted sleep signal INV SLEEP to transition from the high operating potential VDD HI to the reference potential VSS through the operation of the sleep signal inverter 230. The transition of the sleep signal SLEEP to the high operating potential VDD HI turns on the sleep isolation NMOS transistor 232e, and the transition of the inverted sleep signal INV SLEEP to the reference potential VSS causes the sleep isolation PMOS transistor 232c to also turn on. The transition of the enable signal ENABLE to the reference potential VSS causes the delayed high-voltage cutoff signal VCO DEL HV to transition to the reference potential VSS through the operation of the high-voltage delay buffer 228.

[0085] With the low-voltage input signal VSIG LV at the reference potential VSS and therefore the high-voltage output signal VSIG HV at the reference potential VSS, when the sleep signal SLEEP is at the high operating potential VDD HI, the inverted high-voltage signal VSIG INVHV is also at the high operating potential VDD HI. This causes the latching pull-up PMOS transistor 222 to be turned off and the sleep pull-down NMOS transistor 232d to be turned on. The latching pull-up PMOS transistor 222, which is in the off state, isolates the high-voltage output signal VSIG HV from the high operating potential VDD HI through the sleep pull-up branch 232a. The sleep pull-down NMOS transistor 232d is in the on state, and the sleep isolation NMOS transistor 232e is in the on state, connecting the high-voltage output signal VSIG HV to the reference potential VSS through the sleep pull-down branch 232b, so that the high-voltage output signal VSIG HV is latched at the reference potential VSS. If the low-voltage input signal VSIG LV subsequently transitions to a low operating potential VDD LO, while the sleep signal SLEEP remains at a high operating potential VDD HI, the high-voltage output signal VSIG HV remains at the reference potential VSS. This is because the delayed high-voltage cutoff signal VCODEL HV at the reference potential VSS causes the first cutoff NMOS transistor 210 to be turned off, thereby stopping the operation of the first buffer 204. The enable signal ENABLE at the reference potential VSS causes both the buffer enable NMOS transistor 234 and the rising-edge pull-up PMOS transistor 212 to be turned off, thus isolating the high-voltage output signal VSIG HV from the high operating potential VDD HI through the rising-edge pull-up PMOS transistor 212. The enable signal ENABLE at the reference potential VSS causes the buffer enable NMOS transistor 234 to be turned off, and the inverted high-voltage signal VSIG INV HV at the high operating potential VDD HI causes the latch pull-up PMOS transistor 222 to be turned off, thereby stopping the operation of the second buffer 216. Therefore, the sleep pull-down branch 232b and the sleep pull-up branch 232a are configured to maintain the high voltage output signal VSIG HV at the reference potential VSS, while the sleep signal SLEEP is asserted to be at the high operating potential VDD HI when the low voltage input signal VSIG LV is at the reference potential VSS.

[0086] When the low-voltage input signal VSIG LV is at a low operating potential VDD LO and therefore the high-voltage output signal VSIG HV is at a high operating potential VDD HI, when the sleep signal SLEEP is at a high operating potential VDD HI, the inverted high-voltage signal VSIG INV HV is at the reference potential VSS, causing the latching pull-up PMOS transistor 222 to be turned on and the sleep pull-down NMOS transistor 232d to be turned off. The sleep pull-down NMOS transistor 232d, which is in the off state, isolates the high-voltage output signal VSIG HV from the reference potential VSS through the sleep pull-down branch 232b. The latching pull-up PMOS transistor 222 is turned on and the sleep isolation PMOS transistor 232c is turned on, connecting the high-voltage output signal VSIG HV to the high operating potential VDD HI through the sleep pull-up branch 232a, thereby latching the high-voltage output signal VSIG HV at the high operating potential VDD HI. If the low-voltage input signal VSIG LV subsequently transitions to the reference potential VSS, while the sleep signal SLEEP remains at the high operating potential VDD HI, then the high-voltage output signal VSIG HV remains at the high operating potential VDD HI because the buffer-enabling NMOS transistor 234 is off, stopping the operation of the second buffer 216. Therefore, the sleep pull-down branch 232b and the sleep pull-up branch 232a are configured to maintain the high-voltage output signal VSIG HV at the high operating potential VDD HI, while the sleep signal SLEEP is asserted to be at the high operating potential VDD HI when the low-voltage input signal VSIG LV is at the low operating potential VDD LO.

[0087] Regarding the reset mode, the ENABLE signal at the reference potential VSS turns off the buffer enable NMOS transistor 234. The SLEEP signal at the reference potential VSS disables the sleep latch 232. The RESET signal at the reference potential VSS turns on the reset pull-up PMOS transistor 236, which keeps the high voltage output signal VSIG HV at the high operating potential VDD HI, regardless of the value of the low voltage input signal VSIG LV.

[0088] In an alternative version of this example, the high-voltage delay buffer 228 may include more than two logic gates in its signal propagation path. In an alternative version of this example, the first cutoff NMOS transistor 210 may be connected between the first pull-up PMOS transistor 206 and the first pull-down NMOS transistor 208. In an alternative version of this example, the latching pull-up PMOS transistor 222 may be connected between the second pull-up PMOS transistor 218 and the second pull-down NMOS transistor 220.

[0089] Figure 3This is a flowchart of a method for forming a semiconductor device having an example low-to-high voltage level shifter. The level shifter is configured to receive a low-voltage (LV) input signal and output a high-voltage (HV) output signal corresponding to the LV input signal. The level shifter includes a first buffer configured to generate an inverted HV signal corresponding to the LV input signal.

[0090] Method 300 includes step 302: configuring a first NMOS HV pull-down transistor of a first buffer to receive an LV input signal. Step 302 may include forming one or more interconnects, vias, and / or contacts to connect the gate of the first NMOS HV pull-down transistor to a circuit configured to provide the LV input signal.

[0091] Method 300 includes step 304: connecting a first PMOS HV pull-up transistor of the first buffer in series between the HV rail and a first NMOS HV pull-down transistor. Step 304 may include forming one or more interconnects, vias, and / or contacts to connect the source of the first PMOS HV pull-up transistor to the HV rail. Step 304 may include forming one or more interconnects, vias, and / or contacts to connect the drain of the first PMOS HV pull-up transistor to the drain of the first NMOS HV pull-down transistor. The first PMOS HV pull-up transistor is configured to receive an LV input signal and cooperate with the pull-down transistor to generate an inverted HV signal. Step 304 may include forming one or more interconnects, vias, and / or contacts to connect the gate of the first PMOS HV pull-up transistor to a circuit configured to provide the LV input signal.

[0092] Method 300 includes step 306: connecting a first MOS HV cutoff transistor of the first buffer in series with a first NMOS HV pull-down transistor and a first PMOS HV pull-up transistor between the first NMOS HV pull-down transistor and a reference voltage rail. The first MOS HV cutoff transistor has positive transconductance. Step 306 may include forming one or more interconnects, vias, and / or contacts to connect the source of the first MOS HV cutoff transistor to the reference voltage rail. Step 306 may include forming one or more interconnects, vias, and / or contacts to connect the drain of the first MOS HV cutoff transistor to the source of the first NMOS HV pull-down transistor.

[0093] Method 300 includes step 308: configuring a first MOS HV cutoff transistor to receive a delayed HV cutoff signal corresponding to the inverse of the LV input signal. Step 308 may include forming one or more interconnects, vias, and / or contacts to connect the gate of the first MOS HV cutoff transistor to a circuit configured to provide the delayed HV cutoff signal.

[0094] The level shifter may include a second buffer. Method 300 may include step 310: configuring a second HV NMOS pull-down transistor of the second buffer to receive an inverted LV signal. The inverted LV signal corresponds inversely to the LV input signal. Step 310 may include forming one or more interconnects, vias, and / or contacts to connect the gate of the second HV NMOS pull-down transistor to a circuit configured to provide the inverted LV signal.

[0095] Method 300 may include step 312: configuring a second HV PMOS pull-up transistor of the second buffer to receive an inverted LV signal. Step 312 may include forming one or more interconnects, vias, and / or contacts to connect the gate of the second HV PMOS pull-up transistor to a circuit configured to provide an inverted LV signal.

[0096] Method 300 may include step 314: connecting a second HV MOS cutoff transistor of the second buffer in series with a second HV NMOS pull-down transistor and a second HV PMOS pull-up transistor. The second HV MOS cutoff transistor is connected between the second HV PMOS pull-up transistor and the HV rail. The second HV MOS cutoff transistor is configured to receive a delayed HV cutoff signal. Step 314 may include forming one or more interconnects, vias, and / or contacts to connect the source of the second HV MOS cutoff transistor to the HV rail. Step 314 may include forming one or more interconnects, vias, and / or contacts to connect the drain of the second HV MOS cutoff transistor to the source of the second HV PMOS pull-up transistor. Step 314 may include forming one or more interconnects, vias, and / or contacts to connect the gate of the second HV MOS cutoff transistor to a circuit configured to provide a delayed HV cutoff signal.

[0097] The semiconductor device may include a low-voltage inverter. The low-voltage inverter is configured to receive an LV input signal and provide an inverted LV signal. Method 300 may include step 316: configuring the LV PMOS pull-up transistor of the low-voltage inverter and the LV NMOS pull-down transistor of the low-voltage inverter to generate an inverted LV signal. Step 316 may include forming the LV PMOS pull-up transistor to have a thinner gate dielectric layer than either the first PMOS HV pull-up transistor or the second PMOS HV pull-up transistor. Step 316 may include forming the LV NMOS pull-down transistor to have a thinner gate dielectric layer than either the first NMOS HV pull-down transistor or the second NMOS HV pull-down transistor.

[0098] The various features of the examples disclosed herein can be combined in other manifestations of the example semiconductor devices. For example, Figure 1 The semiconductor device 100 may include and Figure 2B The hibernation latch 232 is similar to the hibernation latch. Figure 1 The semiconductor device 100 may include a reset pull-up transconductor coupled between a high operating potential VDD HI and a high-voltage output signal VSIG HV of the level shifter 102, which is similar to Figure 2A The reset pull-up PMOS transistor 236.

[0099] While various examples of this disclosure have been described above, it should be understood that they are presented as examples only and not as limitations. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined according to the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a low-to-high voltage level shifter configured to receive a low voltage input signal and provide a high voltage output signal, the low-to-high voltage level shifter including a buffer, the buffer including: a pull-up transconductor configured to be controlled by the low voltage input signal; a pull-down transconductor configured to be controlled by the low voltage input signal; and an off transconductor configured to be controlled by a delayed off signal; wherein: the delayed off signal inversely corresponds to the low voltage input signal; and the pull-up transconductor, the pull-down transconductor, and the off transconductor are connected in series.

2. The semiconductor device of claim 1, wherein the off transconductor is connected between the pull-down transconductor and a reference supply rail.

3. The semiconductor device of claim 1, wherein: the buffer is a first buffer; the pull-up transconductor is a first pull-up transconductor; the pull-down transconductor is a first pull-down transconductor; the off transconductor is a first off transconductor; and the delayed off signal is a first delayed off signal; and the semiconductor device further includes: a second buffer, the second buffer including: a second pull-up transconductor configured to be controlled by an inverted low voltage signal, wherein the inverted low voltage signal inversely corresponds to the low voltage input signal; a second pull-down transconductor configured to be controlled by the inverted low voltage signal; and a second off transconductor configured to be controlled by a second delayed off signal; wherein: the second delayed off signal inversely corresponds to the low voltage input signal; and the second pull-up transconductor, the second pull-down transconductor, and the second off transconductor are connected in series.

4. The semiconductor device of claim 1, further including a reset transconductor connected to an output of the buffer, the reset transconductor having a transconductance opposite that of the off transconductor, the reset transconductor configured to be controlled by a delayed reset signal corresponding to the delayed off signal.

5. The semiconductor device of claim 3, further including a rising edge pull-up transconductor connected to an output of the low-to-high voltage level shifter, the rising edge pull-up transconductor configured to be controlled by an output of the first buffer.

6. The semiconductor device of claim 3, further including a first supply rail and a reference supply rail, wherein the first off transconductor is connected to the reference supply rail and the second off transconductor is connected to the first supply rail.

7. The semiconductor device of claim 3, further including a low voltage inverter configured to receive the low voltage input signal and configured to provide the inverted low voltage signal, the low voltage inverter configured to operate at a lower potential than the first buffer and the second buffer.

8. The semiconductor device of claim 1, further including a high voltage inverter configured to receive the high voltage output signal and output an inverted high voltage signal, the inverted high voltage signal inversely corresponding to the high voltage output signal.

9. The semiconductor device of claim 1, further comprising a delay buffer configured to receive an inverted sense signal and provide a delayed output signal, wherein the inverted sense signal inversely corresponds to the high voltage output signal.

10. The semiconductor device of claim 3, wherein: the first pull-up transconductor has a negative transconductance; the first pull-down transconductor has a positive transconductance; the first cutoff transconductor has a positive transconductance; the second pull-up transconductor has a negative transconductance; the second pull-down transconductor has a positive transconductance; and the second cutoff transconductor has a negative transconductance.

11. The semiconductor device of claim 3, wherein the low voltage to high voltage level shifter further comprises a sleep pull-down leg in series with a sleep pull-up leg; wherein: the sleep pull-down leg is configured to receive a sleep signal; the sleep pull-down leg is configured to receive an inverted input signal, the inverted input signal inversely corresponding to the high voltage output signal; the sleep pull-up leg is configured to receive an inverted sleep signal, the inverted sleep signal inversely corresponding to the sleep signal; the sleep pull-up leg is configured to receive the inverted input signal; and the sleep pull-down leg and the sleep pull-up leg are configured to maintain the high voltage output signal when the sleep signal is asserted.

12. The semiconductor device of claim 3, wherein: the first pull-up transconductor is a first pull-up p-channel metal-oxide-semiconductor (PMOS) transistor; the first pull-down transconductor is a first pull-down n-channel metal-oxide-semiconductor (NMOS) transistor; the first cutoff transconductor is a first cutoff NMOS transistor; the second pull-up transconductor is a second pull-up PMOS transistor; the second pull-down transconductor is a second pull-down NMOS transistor; and the second cutoff transconductor is a second cutoff PMOS transistor.

13. A semiconductor device, comprising: a low voltage to high voltage level shifter configured to receive a low voltage input signal and provide a high voltage output signal, the low voltage to high voltage level shifter comprising a first buffer, the first buffer comprising: a pull-down n-channel metal-oxide-semiconductor (NMOS) transistor configured to receive the low voltage input signal; a pull-up p-channel metal-oxide-semiconductor (PMOS) transistor configured to receive the low voltage input signal; and a cutoff metal-oxide-semiconductor (MOS) transistor configured to receive a delayed cutoff signal; wherein: the delayed cutoff signal inversely corresponds to the low voltage input signal; and the pull-up PMOS transistor, the pull-down NMOS transistor, and the cutoff MOS transistor are connected in series between a first power rail and a reference voltage rail.

14. The semiconductor device of claim 13, wherein: the pull-up PMOS transistor is a first pull-up PMOS transistor; the pull-down NMOS transistor is a first pull-down NMOS transistor; the cutoff MOS transistor is a first cutoff MOS transistor; and the delayed cutoff signal is a first delayed cutoff signal; and the semiconductor device further comprises: ​ a second buffer comprising: a second pull-up PMOS transistor configured to receive an inverted low voltage signal, the inverted low voltage signal inversely corresponding to the low voltage input signal; a second pull-down NMOS transistor configured to receive the inverted low voltage signal; and a second off MOS transistor configured to receive a second delayed off signal; wherein: the second delayed off signal inversely corresponds to the low voltage input signal; and the second pull-up PMOS transistor, the second pull-down NMOS transistor, and the second off MOS transistor are connected in series between the first power rail and the reference voltage rail.

15. The semiconductor device of claim 13, further comprising a reset PMOS transistor connected to an output of the first buffer, the reset PMOS transistor configured to receive a delayed reset signal corresponding to the delayed off signal.

16. The semiconductor device of claim 13, further comprising a rising edge pull-up PMOS transistor connected to an output of the low voltage to high voltage level shifter, the rising edge pull-up PMOS transistor configured to be controlled by an output of the first buffer.

17. The semiconductor device of claim 13, wherein the low voltage to high voltage level shifter further comprises a sleep pull-down branch in series with a sleep pull-up branch; wherein: the sleep pull-down branch comprises a sleep isolation NMOS transistor configured to receive a sleep signal; the sleep pull-down branch comprises a sleep pull-down NMOS transistor configured to receive an inverted input signal, the inverted input signal inversely corresponding to the high voltage output signal; the sleep pull-up branch comprises a sleep isolation PMOS transistor configured to receive an inverted sleep signal, the inverted sleep signal inversely corresponding to the sleep signal; the sleep pull-up branch comprises a sleep pull-up PMOS transistor configured to receive the inverted input signal; and the sleep pull-down branch and the sleep pull-up branch are configured to maintain the high voltage output signal when the sleep signal is asserted.

18. An integrated circuit comprising: a first power rail and a second power rail, the first power rail configured to provide a first operating voltage and the second power rail configured to provide a reference voltage; a PMOS transistor connected to the first power rail and configured to operate at a first gate voltage and receive an input signal at its gate having a maximum voltage less than the gate voltage; a first NMOS transistor connected between the PMOS transistor and the second power rail, the first NMOS transistor configured to operate at the first gate voltage and receive the input signal at its gate; and a second NMOS transistor connected between the first NMOS transistor and the second power rail, the second NMOS transistor configured to operate at the first gate voltage and receive the input signal at its gate. a second NMOS transistor connected between the first NMOS transistor and the second power rail, the second NMOS transistor configured to operate at the gate voltage and receive an input signal at its gate having a maximum voltage equal to the gate voltage.

19. A method of forming a semiconductor device, comprising: forming a low-to-high voltage level shifter to receive a low voltage (LV) input signal and output a high voltage (HV) output signal corresponding to the LV input signal, the low-to-high voltage level shifter including a first buffer configured to generate an inverted HV signal inversely corresponding to the LV input signal, the low-to-high voltage level shifter formed by: configuring an n-channel metal-oxide-semiconductor (NMOS) HV pull-down transistor to receive the LV input signal; connecting a p-channel metal-oxide-semiconductor (PMOS) HV pull-up transistor in series between an HV rail and the pull-down transistor, the pull-up transistor configured to receive the LV input signal and cooperate with the pull-down transistor to generate the inverted HV signal; connecting a metal-oxide-semiconductor (MOS) HV cutoff transistor in series with the pull-down transistor and the pull-up transistor between the pull-down transistor and a reference voltage rail; and configuring the cutoff transistor to receive a delayed HV cutoff signal inversely corresponding to the LV input signal.

20. The method of claim 19, wherein: the pull-up transistor is a first pull-up transistor; the pull-down transistor is a first pull-down transistor; the cutoff HV MOS transistor is a first cutoff HV MOS transistor; and the delayed HV cutoff signal is a first delayed HV cutoff signal, and the method further comprises forming a second buffer by: configuring a second HV NMOS pull-down transistor to receive an inverted LV signal inversely corresponding to the LV input signal; configuring a second HV PMOS pull-up transistor to receive the inverted HV signal; and connecting a second HV MOS cutoff transistor in series with the second pull-down transistor and the second pull-up transistor between the second pull-up transistor and the reference voltage rail, the second cutoff transistor configured to receive the delayed HV cutoff signal.

21. The method of claim 19, further comprising: configuring an LV PMOS pull-up transistor and an LV NMOS pull-down transistor to generate the inverted LV signal; wherein: the LV pull-up transistor and the HV pull-down transistor have a first gate dielectric thickness; and the HV pull-up transistor, the HV pull-down transistor, and the HV cutoff transistor have a second, greater gate dielectric thickness.

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