Device and method capable of quickly establishing delay-locked loop

Abstract

The invention relates to the technical field of Internet of Things, in particular to a device and method capable of quickly establishing a delay-locked loop. The circuit comprises a phase discriminator, a charge pump, a voltage control delay line VCDL, a locking detector, a setting charge pump and a reset switch. When the locking detector outputs a low level, the set charge pump is started, the Vctrl voltage is increased, the VCDL delay is shortened, and the internal clock quickly catches the external clock. According to the invention, the delay control voltage Vctrl is directly pulled away from the reset state quickly by using a large current at the initial establishment time, and the delay phase-locked loop circuit is automatically switched to the normal working state through the locking detection device to complete locking, so that the establishment time of the delay phase-locked loop circuit is greatly shortened. In the reset state, the delay time of the voltage-controlled delay line is longest; after resetting is finished, the control voltage Vctrl of the voltage-controlled delay line is quickly pulled to be close to a normal locking value through large current to accelerate establishment.

Description

Technical Field

[0001] This disclosure relates to the field of Internet of Things (IoT) technology, and in particular to an apparatus and method for rapidly establishing a delay-locked loop (PLL). Background Technology

[0002] With the rapid development of IoT technology, low-power wireless sensor nodes and wearable devices are widely used in various fields such as military and biomedicine. These wearable devices and sensor nodes are typically small in size and easy to carry, usually powered by batteries and capable of long-term operation, which places extremely stringent requirements on the low power consumption of the chips. In order to reduce chip power consumption, the chips not only need to consume as little power as possible during operation, but also need to be in an extremely low-power sleep mode when idle.

[0003] In existing technologies, the clock and phase-locked loop are often not in operation during sleep mode. After the sleep mode ends, without the drive of an auxiliary startup circuit, the delay phase-locked loop circuit needs to go through hundreds of clock edges before it can output a stable frequency signal, which will greatly slow down the recovery speed of the overall circuit.

[0004] In summary, a fast setup circuit for a delay phase-locked loop (PLL) circuit is needed. Summary of the Invention

[0005] To address the aforementioned problems, this disclosure provides an apparatus and method for rapidly establishing a delay phase-locked loop (PLL), thereby solving the problem of slow establishment of PLL circuits in the prior art.

[0006] In a first aspect, an apparatus for rapidly establishing a delayed phase-locked loop includes: Phase detector (PFD), charge pump (CP), voltage-controlled delay line (VCDL), latch detector, set charge pump, and reset switch (Reset); The phase detector (PFD) is used to compare the external input clock (CLK) and the internal feedback clock (CLK_FB) and output a pulse signal. The charge pump CP is used to convert the pulse signal output by the PFD into a voltage signal V_ctrl, and to change the level of V_ctrl by charging or discharging. The voltage-controlled delay line (VCDL) consists of four identical delay units connected in series, which sequentially generate four signals: CLK_1, CLK_2, CLK_3, and CLK_FB. CLK_FB is fed back to the phase detector (PFD). The lock detector is used to monitor the phase relationship between CLK and CLK_1, CLK_2, and CLK_3 at all times, determine whether the circuit has been locked, and output the signal V_switch, with a low level indicating that it is not locked and a high level indicating that it is locked. When the lock detector output V_switch is low, the set charge pump is activated, pulling the V_ctrl voltage high, shortening the VCDL delay, and allowing the internal clock to quickly catch up with the external clock. When the lock detector outputs V_switch at a high level, the set charge pump is turned off, and control is returned to the phase detector PFD and the main charge pump CP path. The system then enters negative feedback regulation, fine-tunes V_ctrl, eliminates phase error, and maintains stable lock. The reset switch Reset controls whether the voltage signal V_ctrl is grounded. When in sleep mode, Reset is high and V_ctrl is forced to be grounded; when in non-sleep mode, Reset is low and V_ctrl is not forced to be grounded.

[0007] Furthermore, the voltage-controlled delay line (VCDL) includes: It consists of four cascaded voltage-controlled delay units, each of which can adjust its delay to the input clock signal according to the magnitude of the control voltage; The delay of the voltage-controlled delay unit is controlled by the control voltage V_ctrl; CLK_1, CLK_2, CLK_3, and CLK_FB are the output clock signals of the first, second, third, and fourth voltage-controlled delay units, respectively.

[0008] Furthermore, in the voltage-controlled delay line (VCDL), the circuit structure and size of each voltage-controlled delay unit are identical. Under the same control voltage, each voltage-controlled delay unit has the same delay time for the input clock signal, and CLK_1, CLK_2, CLK_3, and CLK_FB have the same phase interval.

[0009] Furthermore, the lock detector determines whether the DLL is in a locked state by detecting the phase difference between the external clock signal CLK and the signals CLK_1, CLK_2 and CLK_3 generated by the voltage control delay line.

[0010] Furthermore, the lock detector includes: D flip-flops D3, D4, D5, D6 and D7, inverters INV1 and INV2, and AND gate AND2; The input signal CLK is connected to the data terminals of D flip-flops D3, D4, and D5; the input signal CLK_1 is connected to the clock signal terminal of D flip-flop D3; the input signal CLK_2 is connected to the clock signal terminal of D flip-flop D4; and the input signal CLK_3 is connected to the clock signal terminal of D flip-flop D5. The output of D flip-flop D3 is connected to the data terminal of D flip-flop D6, the output of D flip-flop D4 is connected to the input terminal of inverter INV1, the output of D flip-flop D4 is connected to the input terminal of inverter INV2, the output terminal of inverter INV1 is connected to the clock signal terminal of D flip-flop D6 and the data terminal of D flip-flop D7, and the output terminal of inverter INV2 is connected to the clock signal terminal of D flip-flop D7. The outputs of D flip-flops D6 and D7 are connected to the input of AND gate AND2, which generates the output control signal V_switch.

[0011] Furthermore, the lock detector also includes: The input signal Reset is connected to the reset control terminals of D flip-flops D3, D4, D5, D6, and D7. When the input signal Reset is high, D flip-flops D3, D4, D5, D6, and D7 are reset and output a low level, causing the output control signal V_switch to be low. When the input signal Reset is low, the reset control does not work.

[0012] Furthermore, the set charge pump includes: NMOS transistors M_5 and M_6, PMOS transistors M_3 and M_4, with the source of PMOS transistor M_3 connected to a high level and its drain connected to the source of PMOS transistor M_4, and the source of NMOS transistor M_6 connected to a low level and its drain connected to the source of NMOS transistor M_5. The gate of PMOS transistor M_3 is connected to the control voltage V_switch, the gate of PMOS transistor M_4 is connected to V_bias_P, the gate of NMOS transistor M_5 is connected to V_bias_N, the gate of NMOS transistor M_6 is connected to a low level and is always in the off state; the drains of PMOS transistor M_4 and NMOS transistor M_5 are both connected to the output voltage V_ctrl.

[0013] Furthermore, the position charge pump also includes: In the reset state, V_bias_P is connected to a high level, PMOS transistor M_4 is turned off, V_bias_N is connected to a low level, NMOS transistor M_5 is turned off, and the charge pump is set to not work. Under normal operating conditions, when V_bias_P is low, PMOS transistor M_4 is turned on, and when V_bias_N is high, NMOS transistor M_5 is turned on. When the control voltage V_switch is low, PMOS transistor M_3 is turned on, charging the output voltage V_ctrl. When the control voltage V_switch is high, PMOS transistor M_3 is turned off, and the charge pump is disabled.

[0014] Furthermore, the reset switch Reset includes: an NMOS transistor M_1, whose gate is connected to the reset signal Reset, its source is connected to a low level, and its drain is connected to the delayed control voltage V_ctrl; When the input signal Reset is high, the NMOS transistor M_1 is turned on, pulling the voltage V_ctrl low; when the input signal Reset is low, the NMOS transistor M_1 is turned off, and the reset switch does not work.

[0015] Secondly, a method for quickly establishing a delay-locked loop (PLL) is proposed. Based on the above, a device for quickly establishing a delay phase-locked loop is provided; When the sleep state ends, the Reset signal goes low, the reset transistor of V_ctrl is turned off, and it is no longer forcibly grounded; the set charge pump starts to work, and the bias voltage returns to normal. At this time, V_switch is low, and the charge pump starts charging V_ctrl, causing V_ctrl to rise from low. Until V_switch goes high, the charge pump is turned off, and the main loop of the phase detector PFD and the main charge pump CP takes over the control; the circuit enters closed-loop control and gradually adjusts V_ctrl to achieve phase alignment.

[0016] This disclosure includes at least the following beneficial effects: This disclosure directly uses a large current to quickly pull the delay control voltage V_ctrl away from the reset state during the initial setup time, and automatically switches the delay phase-locked loop circuit to the normal operating state through a lock detection device to complete the lockout, greatly shortening the setup time of the delay phase-locked loop circuit. In the reset state, the voltage-controlled delay line has the longest delay time; after the reset is completed, a large current is used to quickly pull the control voltage V_ctrl of the voltage-controlled delay line to near the normal lockout value to accelerate setup.

[0017] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic diagram of the device structure for rapidly establishing a delayed phase-locked loop according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the phase detector PFD structure according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the charge pump CP structure according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the voltage control delay line structure according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the lock detector structure according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the charge pump circuit structure according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the input-output timing of the DLL initial state voltage control delay chain in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the input-output timing of the DLL set state end voltage control delay chain in an embodiment of this disclosure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] like Figure 1 As shown, an apparatus for rapidly establishing a delay-locked loop includes: Phase detector (PFD), charge pump (CP), voltage-controlled delay line (VCDL), latch detector, set charge pump, and reset switch (Reset); The phase detector (PFD) is used to compare the external input clock (CLK) and the internal feedback clock (CLK_FB) and output a pulse signal. The charge pump CP is used to convert the pulse signal output by the PFD into a voltage signal V_ctrl, and to change the level of V_ctrl by charging or discharging. The voltage-controlled delay line (VCDL) consists of four identical delay units connected in series, which sequentially generate four signals: CLK_1, CLK_2, CLK_3, and CLK_FB. CLK_FB is fed back to the phase detector (PFD). The lock detector is used to monitor the phase relationship between CLK and CLK_1, CLK_2, and CLK_3 at all times, determine whether the circuit has been locked, and output the signal V_switch, with a low level indicating that it is not locked and a high level indicating that it is locked. When the lock detector output V_switch is low, the set charge pump is activated, pulling the V_ctrl voltage high, shortening the VCDL delay, and allowing the internal clock to quickly catch up with the external clock. When the lock detector outputs V_switch at a high level, the set charge pump is turned off, and control is returned to the phase detector PFD and the main charge pump CP path. The system then enters negative feedback regulation, fine-tunes V_ctrl, eliminates phase error, and maintains stable lock. The reset switch Reset controls whether the voltage signal V_ctrl is grounded. When in sleep mode, Reset is high and V_ctrl is forced to be grounded; when in non-sleep mode, Reset is low and V_ctrl is not forced to be grounded.

[0022] The specific implementation details are as follows: Figure 1 The circuit diagram for a fast-establishing delay phase-locked loop includes: an input clock CLK connected to a phase detector (PFD), a latch detector, and a voltage-controlled delay line (VCDL). The phase detector compares the input clock CLK with the feedback clock CLK_FB output from the voltage-controlled delay line, generating output signals V_P and V_N to the charge pump. This causes the charge pump to charge and discharge the control signal V_ctrl when V_switch is high, thereby controlling the delay of the voltage-controlled delay line. The latch detector receives the input signal CLK and the outputs CLK_1, CLK_2, and CLK_3 from the voltage-controlled delay line, generating an output signal V_switch to set the charge pump and controlling whether the charge pump charges the control signal V_ctrl or controls it directly.

[0023] A phase detector (PFD) is used to compare the phase difference between the external clock signal CLK and the feedback internal clock signal CLK_FB, and outputs a pulse signal based on the comparison result. For example... Figure 2 As shown, the phase detector includes: two D flip-flops D1 and D2 and an AND gate AND1. The input clock CLK is connected to the clock input of D flip-flop D1. When the input clock CLK goes from low to high, the output signal V_P is high. The input clock CLK_FB is connected to the clock input of D flip-flop D2. When the feedback clock CLK_FB goes from low to high, the output signal V_N is high. When the output signals V_P and V_N are high, the AND gate AND1 generates a high level, resetting D flip-flops D1 and D2, thereby resetting the output signals V_P and V_N to low.

[0024] The charge pump (CP) converts the pulse signal received from the phase detector into a current signal that charges and discharges the V_ctrl voltage, thereby generating a control signal voltage value V_ctrl to change the delay time. For example... Figure 3 As shown, the charge pump includes: NMOS transistors M_2 and M_7, constant current sources I_1 and I_2. When the input signal V_P is high, NMOS transistor M_2 is turned on, and constant current source I_1 charges the output voltage V_ctrl, causing the output voltage V_ctrl to increase; when the input signal V_N is high, NMOS transistor M_7 is turned on, and constant current source I_2 discharges the output voltage V_ctrl, causing the output voltage V_ctrl to decrease.

[0025] The Voltage Controlled Delay Line (VCDL) consists of four cascaded voltage-controlled delay units (VCDs). Each VCD adjusts its delay relative to the input clock signal according to the magnitude of the control voltage. The delay of each VCD is controlled by the control voltage V_ctrl. CLK_1, CLK_2, CLK_3, and CLK_FB are the output clock signals of the first, second, third, and fourth VCDs, respectively. Because each VCD has the same circuit structure and size, under the same control voltage, each VCD has the same delay time relative to the input clock signal. Therefore, CLK_1, CLK_2, CLK_3, and CLK_FB have the same phase interval. Its structure is as follows: Figure 4 As shown.

[0026] In this embodiment, it is assumed that the voltage control delay line has the longest delay time when the V_ctrl voltage is low and the shortest delay time when the V_ctrl voltage is high. The lock detector detects the phase difference between the external clock signal CLK and the signals CLK_1, CLK_2, and CLK_3 generated by the voltage control delay line to determine whether the DLL is in a locked state. Its structure is as follows: Figure 5 As shown.

[0027] If the lock detector is not in a locked state, V_switch is low, and only the charge pump charges the V_ctrl voltage, reducing the delay of the voltage control delay line until the delay of the voltage control delay line matches the delay of the input clock. If the lock detector is in a locked state, V_switch is high, and only the phase detector and charge pump fine-tune V_ctrl until the phase difference between the reference clock signal and the output clock signal is aligned, thus achieving the locking of the delay phase-locked loop.

[0028] The circuit of the set charge pump is as follows Figure 6As shown, in sleep mode, V_bias_N is low and V_bias_P is high, thus turning off the set charge pump. In normal operation, V_bias_N and V_bias_P are normally biased by the current source. When the output voltage V_switch of the lock detector is low, the P transistor is turned on, pulling up the V_ctrl voltage, thereby reducing the delay of the voltage-controlled delay line. When the output voltage V_switch of the lock detector is high, the P transistor is turned off, and the set charge pump does not work.

[0029] Specifically, in sleep mode, the reset control voltage Reset is high, the reset transistor of the V_ctrl voltage is turned on, and V_ctrl is pulled low; the bias voltages V_bias_N and V_bias_P inside the set charge pump are at low and high levels respectively, and the set charge pump is turned off; the D flip-flop in the latch detector is also reset, outputting a low level, so the output voltage V_switch is also low. Since the input voltage V_ctrl is low, the voltage control delay line is in the state of longest delay, and the generated output voltage remains low.

[0030] When the sleep state ends, the Reset voltage is low, the D flip-flop is not in the reset state, the reset transistor of the V_ctrl voltage is turned off, and the phase relationship between the output voltages of the voltage control delay line remains at a low level, thus locking the output voltage of the detector to remain 0. The bias voltages V_bias_N and V_bias_P of the set charge pump are normally biased, so the V_ctrl voltage is continuously pulled up, causing the output clock delay of the voltage control delay line to continuously shorten, and thus gradually generating an output square wave voltage.

[0031] like Figure 7 As shown, in this case, the lockout detector remains at a low level until the output voltages CLK_1, CLK_2, and CLK_3 of the voltage control delay line and the input voltage CLK appear as shown. Figure 8 The phase relationship is such that, in this case, the rising edge of CLK_1 samples the output as high, the rising edge of CLK_2 samples the output as low, and the rising edge of CLK_3 samples the output as low, thus making the output V_switch voltage high, setting the charge pump to turn off, and the V_ctrl voltage is controlled by a loop consisting of the phase detector, the charge pump, and the voltage control delay line, slowly building up to the locked state.

[0032] A method for quickly establishing a delay phase-locked loop. Based on the above, a device for quickly establishing a delay phase-locked loop is provided; When the sleep state ends, the Reset signal goes low, the reset transistor of V_ctrl is turned off, and it is no longer forcibly grounded; the set charge pump starts to work, and the bias voltage returns to normal. At this time, V_switch is low, and the charge pump starts charging V_ctrl, causing V_ctrl to rise from low. Until V_switch goes high, the charge pump is turned off, and the main loop of the phase detector PFD and the main charge pump CP takes over the control; the circuit enters closed-loop control and gradually adjusts V_ctrl to achieve phase alignment.

[0033] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A device for rapidly establishing a delay-locked loop, characterized in that, Comprise: a phase detector PFD, a charge pump CP, a voltage controlled delay line VCDL, a lock detector, a set charge pump and a reset switch Reset; a phase detector PFD, for comparing the external input clock CLK and the internal feedback clock CLK_FB, and outputting pulse signals; a charge pump CP, for converting the pulse signals output by the PFD into voltage signals V_ctrl, and changing the high and low of V_ctrl through charging or discharging; a voltage controlled delay line VCDL, which is composed of four identical delay units in series, and generates CLK_1, CLK_2, CLK_3 and CLK_FB in turn; CLK_FB is fed back to the phase detector PFD; a lock detector, for monitoring the phase relationship between CLK and CLK_1, CLK_2 and CLK_3 at all times, judging whether the circuit has been locked, and outputting a signal V_switch, low level indicating that it is not locked, and high level indicating that it is locked; when the lock detector outputs V_switch as low level, the set charge pump is started to pull up the V_ctrl voltage, the VCDL delay becomes shorter, and the internal clock quickly catches up with the external clock; when the lock detector outputs V_switch as high level, the set charge pump is closed, and the control is returned to the phase detector PFD and the main charge pump CP path, entering negative feedback regulation, fine tuning V_ctrl, eliminating phase error, and maintaining stable locking; a reset switch Reset, for controlling whether the voltage signal V_ctrl is grounded; when in sleep mode, Reset is high level, and V_ctrl is forced to ground; when in non-sleep mode, Reset is low level, and V_ctrl is not forced to ground.

2. The device of claim 1, wherein the voltage controlled delay line VCDL comprises: four voltage controlled delay units connected in series, each of which can adjust its delay to the input clock signal according to the size of the control voltage; the delay of the voltage controlled delay unit is controlled by the control voltage V_ctrl; CLK_1, CLK_2, CLK_3 and CLK_FB are the output clock signals of the first, second, third and fourth voltage controlled delay units respectively.

3. The device of claim 2, wherein in the voltage controlled delay line VCDL, the circuit structure and size of each voltage controlled delay unit are the same; under the same size of control voltage, each voltage controlled delay unit has the same delay time to the input clock signal, and CLK_1, CLK_2, CLK_3 and CLK_FB have the same phase interval.

4. The device of claim 1, wherein the lock detector determines whether the DLL is in a locked state by detecting the phase difference between the external clock signal CLK and the signals CLK_1, CLK_2 and CLK_3 generated by the voltage controlled delay line. ​ ​ ​ 5. The device of claim 1, wherein the lock detector comprises D flip-flops D3, D4, D5, D6 and D7, inverters INV1 and INV2, and an AND gate AND2. The input signal CLK is connected to the data terminals of the D flip-flops D3, D4 and D5, the input signal CLK_1 is connected to the clock signal terminal of the D flip-flop D3, the input signal CLK_2 is connected to the clock signal terminal of the D flip-flop D4, and the input signal CLK_3 is connected to the clock signal terminal of the D flip-flop D5. The output of the D flip-flop D3 is connected to the data terminal of the D flip-flop D6, the output of the D flip-flop D4 is connected to the input terminal of the inverter INV1, the output of the D flip-flop D4 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV1 is connected to the clock signal terminal of the D flip-flop D6 and the data terminal of the D flip-flop D7, and the output terminal of the inverter INV2 is connected to the clock signal terminal of the D flip-flop D7. The outputs of the D flip-flops D6 and D7 are connected to the input terminals of the AND gate AND2, and the output control signal V_switch is generated via the AND gate AND2.

6. The device of claim 5, wherein the lock detector further comprises: The input signal Reset is connected to the reset control terminals of the D flip-flops D3, D4, D5, D6 and D7, when the input signal Reset is high, the D flip-flops D3, D4, D5, D6 and D7 are reset, and low level is outputted, so that the output control signal V_switch is low; when the input signal Reset is low, the reset control is not in operation.

7. The device of claim 1, wherein the set charge pump comprises NMOS transistors M_5 and M_6, and PMOS transistors M_3 and M_4, the source of the PMOS transistor M_3 is connected to high level, the drain of the PMOS transistor M_3 is connected to the source of the PMOS transistor M_4, the source of the NMOS transistor M_6 is connected to low level, and the drain of the NMOS transistor M_6 is connected to the source of the NMOS transistor M_5. The gate of the PMOS transistor M_3 is connected to the control voltage V_switch, the gate of the PMOS transistor M_4 is connected to V_bias_P, the gate of the NMOS transistor M_5 is connected to V_bias_N, the gate of the NMOS transistor M_6 is connected to low level, and the NMOS transistor M_6 is always kept in off state; the drain of the PMOS transistor M_4 and the drain of the NMOS transistor M_5 are both connected to the output voltage V_ctrl.

8. The device of claim 7, wherein the set charge pump further comprises: In the reset state, V_bias_P is connected to high level, the PMOS transistor M_4 is off, V_bias_N is connected to low level, the NMOS transistor M_5 is off, and the set charge pump is not in operation. ​ ​ ​ ​ In normal working state, V_bias_P is low, PMOS M_4 is on, V_bias_N is high, NMOS M_5 is on; when control voltage V_switch is low, PMOS M_3 is on, charging output voltage V_ctrl; when control voltage V_switch is high, PMOS M_3 is off, setting charge pump not working.

9. The device of claim 1, wherein, Reset switch Reset, comprising: NMOS M_1, its gate connected to the reset signal Reset, source connected to low, drain connected to delay control voltage V_ctrl; When the input signal Reset is high, NMOS M_1 is on, pulling the voltage V_ctrl to low; when the input signal Reset is low, NMOS M_1 is off, the reset switch is not working.

10. The method of claim 1, wherein, The device of any one of claims 1-9; When the hibernation state ends, the Reset signal becomes low, the reset transistor of V_ctrl is off, and it is no longer forced to ground; the set charge pump starts to work, and the bias voltage returns to normal; At this time, V_switch is low, the set charge pump starts to charge V_ctrl, and V_ctrl starts to rise from low; Until V_switch becomes high, the set charge pump is off, and the phase frequency detector PFD and the main charge pump CP take over the control; the circuit enters closed-loop control, gradually adjusts V_ctrl, and realizes phase alignment.

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