Gate-to-source / drain contact link implemented in metallization layer of contact device layer

Abstract

An integrated circuit (IC) device has a transistor with a gate electrode coupled to a source or drain, for example, a transistor connected as a diode. The IC device may include a metallization level on the transistor (e.g., on and above the device layer) with a continuous first metal body in the metallization level and directly on the source or drain contact and the gate electrode. A second metal body in the metallization level may be on the other of the source or drain contacts. A metallization level (including the first and second metal bodies) may have a lower interface plane that contacts an upper contact plane (e.g., a gate electrode and source and drain contacts) of the transistor. The metallization level may have an upper interface plane that may be contacted by vias from an interconnect network over the transistors.

Description

Background Technology

[0001] The coupling terminals of transistors (e.g., transistors connected as diodes) can conventionally be made within the device layer or upwards in the interconnect stack, potentially away from the transistor. Making these connections within the device layer may involve additional patterning and material removal from fine structures in confined spaces. Making these connections upwards in the interconnect stack may require excessive wiring.

[0002] New technologies and structures are needed to improve transistor-diode connections in integrated circuit devices. Attached Figure Description

[0003] The materials described herein are illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference numerals have been repeated between the drawings where deemed appropriate to indicate corresponding or similar elements, for example, that have the same or similar functions. This disclosure will be described using additional features and details through the use of the accompanying drawings:

[0004] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E Isometric views, plan views, and cross-sectional profile views of an integrated circuit (IC) device according to some embodiments are shown. The IC device has a linking body at the upper surface of a transistor structure connected as a diode, which couples the gate electrode and the source or drain contact metal at contact and metallization planes.

[0005] Figure 2 This is a flowchart of a method for forming a metallization layer having a link body on the gate electrode and the drain and source contacts, according to some embodiments;

[0006] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F Isometric and plan views of an IC device at various manufacturing stages according to some embodiments are shown, the IC device having a gate electrode in the metallization level directly in the contact level and a metal body on the contact metal.

[0007] Figure 4 A schematic diagram of an example data server machine employing an IC device according to some embodiments is shown. The IC device has a metallization layer on a transistor and links gate electrodes and source or drain contacts; and

[0008] Figure 5 This is a block diagram of an example computing device according to some embodiments. Detailed Implementation

[0009] In the following detailed description, reference is made to the accompanying drawings, which illustrate by way of illustration specific embodiments in which the claimed subject matter can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. While the various embodiments differ, they are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter.

[0010] References to "an embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one implementation covered herein. Therefore, the use of the phrase "an embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Furthermore, modifications may be made to the position or arrangement of various elements within each disclosed embodiment without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be considered limiting, and the scope of the subject matter is defined only by the appended claims as properly interpreted and by the full scope of their equivalents.

[0011] As used herein, the terms “above,” “to,” “between,” and “on” can refer to the relative position of a layer with respect to other layers. A layer that is “above,” “on,” or “bonded to” another layer may be in direct contact with that layer or may have one or more intermediate layers. A layer that is “between” layers may be in direct contact with another layer or may have one or more intermediate layers.

[0012] The terms “coupling” and “connection” and their derivatives are used herein to describe structural relationships between components. These terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupling” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal, electrical, functional, etc.) relationship.

[0013] The terms “circuit” or “module” can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term “signal” can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of “a,” “an,” and “the” include plural references. The meanings of “in” include “in” and “on”.

[0014] The vertical orientation is in the z-direction, and the terms "top," "bottom," "above," and "below" refer to relative positions with their usual meaning in the z-direction. However, embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0015] The terms “substantially,” “nearly,” “approximately,” “close to,” and “about” generally refer to within + / -10% of the target value (unless specifically specified). Unless otherwise stated in the specific context of use, the term “mostly” means greater than 50% or more than half. For example, a composition that is mostly the first component means that more than half of the composition is the first component. The term “primarily” means the majority or largest portion. For example, a composition that is primarily the first component means that the composition contains more first component than any other component. A composition that is primarily the first and second component means that the composition contains more first and second component than any other component.

[0016] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates different instances of the similar objects being referenced and is not intended to imply that the objects described in this way must be in a given sequence in time, space, rank, or any other way.

[0017] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0018] Views labeled "Section," "Outline," and "Planar" correspond to orthogonal planes in the Cartesian coordinate system. Therefore, section views and outline views are taken in the xz and yz planes, respectively, and plan views are taken in the xy plane. Typically, the outline view in the xz plane is a section view. Where appropriate, the figures are labeled with coordinate axes to indicate the orientation of the figures.

[0019] Structures and techniques for improving the link structure and processing efficiency in integrated circuit (IC) devices with transistors connected as diodes are disclosed.

[0020] Transistors connected as diodes are used for a variety of purposes, including as diodes, but also as large resistors and in current mirrors, where they have multiple applications. While MOS (Metal-Oxide-Semiconductor) FETs (Field-Effect Transistors) can be connected as diodes by electrically connecting the gate to the drain, the drain and source bodies are typically physically symmetrical in FETs, so the techniques and structures described herein can also be used for gate-source connections. Transistor terminals can conventionally be electrically coupled upwards in the interconnect stack above the transistor (e.g., at met0, met1, etc.), but excessive wiring can introduce electrical defects (e.g., increased parasitic effects, etc.) and add avoidable complexity. Alternatively, other electrical connections can be made by etching the gate electrode and source or drain contact metal into the device layer, but this patterning wastes processing resources (e.g., by adding additional masks, etc.) and may increase the risk of reliability problems (e.g., by etching through one or more material layers in very confined and critical spaces). The techniques and structures described herein save processing operations without these reliability risks.

[0021] Transistors can be connected as diodes by coupling the gate electrode to the source and / or drain contacts in a metallization layer directly above the device layer but below the conventional interconnect stack. Utilizing the metallization layer saves processing operations otherwise dedicated to coupling the source and drain contacts between adjacent transistors. The gate-drain (or gate-source) metallization link can be deposited directly on the top surface of the transistor (and the gate electrode and source or drain contacts). This direct interfacing of the metallization plane and the contact plane minimizes both reliability issues and masking operations, resulting in a robust structure while efficiently utilizing processing resources.

[0022] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E Isometric views, plan views, and cross-sectional profile views of an IC device 100 according to some embodiments are shown. The IC device 100 has a link body 141 at the upper surface 147 of a transistor structure 101 connected as a diode, coupled to a gate electrode 125 and source or drain contact metals 131, 132 at contact and metallization planes 134, 143. The transistor structure 101 can be coupled to an interconnect layer 150 and an interconnect network 195 via a contact layer 130 of the transistor structure 101 or a metallization layer 140 on the contact layer 130 of the transistor structure 101. Figure 1AA cross-sectional profile view A-A' of device 100 through a row of transistor structure 101 is shown. The row of transistor structure 101 includes a diode-connected structure 101 having metal bodies 141, 142 on gate electrode 125 and source and drain metals 131, 132. Figure 1B A cross-sectional profile view B-B' of device 100 through a second row of transistor structures 101 is shown, the second row of transistor structures 101 being coupled to the first row of transistor structures 101 via link bodies 141 and / or 142 on source and drain metals 131, 132 in each row of structures 101. Figures 1C to 1E Isometric and planar views (and above) of the contact and metallization planes 134, 143, and 145 are shown, including Figure 1A and Figure 1B The orientation of the outline views A-A' and B-B'.

[0023] Device 100 includes a transistor structure 101 on a substrate 199. The transistor structure 101 (e.g., structure 101A) includes source and drain bodies 110 and a channel structure 120 between and coupling the source and drain bodies 110. Structure 101A includes a gate electrode 125 located on the channel structure 120. The substrate 199 may include or support multiple transistor structures 101, for example, on sub-fins extending upward from a crystalline layer of a semiconductor or insulating material.

[0024] Contact level 130 provides the structure and surface for mating between metallization level 140 and transistor structure 101. Contact level 130 may be above the device layer (or the uppermost level 130 of the device layer) including transistor structure 101. Contact level 130 is below metallization level 140 and includes gate electrode 125, source contact metal 132, and drain contact metal 131. Source contact metal 132 is on and over source body 110B, and drain contact metal 131 is on and over drain body 110A.

[0025] The gate electrode 125 extends upward over the channel structure 120 (e.g., in the z-direction) and into the contact layer 130. The gate electrode 125 extends over the channel structure 120 (e.g., in the z-direction) and to both sides of the channel structure 120 (e.g., in both y-directions). Figure 1A (Front and back of the xz-view plane). In a nanoribbon stack having a structure such as 120. Figure 1AIn an exemplary embodiment, the electrode 125 extends within, through, or between the channel structures 120, for example, between the various nanoribbons (e.g., extending in the y direction above one nanoribbon in the channel structure 120 and below another nanoribbon in the same channel structure 120).

[0026] Contact layer 130 has an upper and top plane 134. The upper surface 137 of the source contact metal 132, the upper surface 137 of the drain contact metal 131, and the upper surface 127 of the gate electrode 125 are coplanar on the contact plane 134 above the channel structure 120. The contact plane 134 of contact layer 130 abuts against the metallization plane 143 of metallization layer 140. The abutment of contact layer 130 and metallization layer 140 at contact and metallization planes 134 and 143 (and, for example, the abutment of bodies 141 and 142 with electrodes 125 and metals 131 and 132) refers to the direct contact of layers 130 and 140 at planes 134 and 143 without any intermediate layers or structures. Metallization layer 140 is directly on contact layer 130.

[0027] Metallization level 140 is mated to contact level 130 (at contact and metallization planes 134, 143) and to each of source contact metal 132, drain contact metal 131, and gate electrode 125. Metallization level 140 includes first and second metal bodies 141, 142 between a lower, bottom plane 143 and an upper, top plane 145. The lower surfaces 148 of metal bodies 141 and 142 are substantially coplanar in the bottom metallization plane 143 at a first height H1 above the channel structure 120. The upper surfaces 147 of metal bodies 141 and 142 are substantially coplanar in the top metallization plane 145 above the first height H1 of the metallization plane 143 above the channel structure 120 at a second height H2 above the channel structure 120.

[0028] The first metal body 141 couples the gate electrode 125 to one of the source or drain bodies 110. The first metal body 141 in the layer 140 is mated to one of the gate electrode 125 and the drain and source contact metals 131, 132 at the metallization plane 143 (and the contact plane 134). The second metal body 142 in the layer 140 is mated to the other of the drain and source contact metals 131, 132 at the metallization plane 143 (and the contact plane 134). In some embodiments, either or both of the bodies 141, 142 are mated to other drain and source contact metals 131, 132 in other transistor structures 101. For example, the metal bodies 141 and / or 142 may extend in a y-direction orthogonal to the longitudinal direction of the channel structure 120 and contact the drain and / or source contact metals 131, 132 in the transistor structure 101 with the channel structure 120, which is parallel to the longitudinal direction of the channel structure 120. Figure 1A Those described in the text.

[0029] exist Figure 1A In an exemplary embodiment, body 141 contacts gate electrode 125 and drain metal 131, and body 142 contacts source metal 132. The drain and source bodies 110 in the FET structure 101 are generally symmetrical and can be determined by electrical connections (e.g., via interconnect network 195 to a power source), thus for example... Figure 1A Any labels provided in any particular embodiment (e.g., drain and source bodies 110A, 110B and metals 131, 132 in transistor structure 101A) should not be construed as limitations on these or other embodiments, which may have different or undetermined electrical connections.

[0030] Metallic bodies 141 and 142 are located in dielectric layers 149 within a metallization level 140 above contact level 130. Metallization level 140 may include multiple dielectric layers 149, such as dielectric layers 149B and 149C at the bottom of level 140 (e.g., where dielectric layer 149C is on metallization plane 143). For example, metallization level 140 may include dielectric layers 149B and 149C serving as etch stop layers 149B and 149C above contact level 130 and device layers including transistor structure 101. The bulk or majority of dielectric layers 149 may advantageously be constructed of a low-k (low dielectric constant) dielectric material, for example, to electrically insulate the metallic bodies 141 and 142 from each other and from via 162, etc. The etch stop layers 149B and 149C can advantageously be made of low-k dielectric materials, but the etch stop layers 149B and 149C can provide etch selectivity and have a higher dielectric constant compared to the bulk or majority of the dielectric layer 149.

[0031] The metal bodies 141 and 142 may comprise any suitable material, including nonmetals. In many embodiments, bodies 141 and 142 comprise one or more of tungsten, molybdenum, cobalt, ruthenium, copper, gold, tantalum, aluminum, nickel, or other metals (including alloys). Bodies 141 and 142 may comprise other conductive materials, including nonmetals. In some embodiments, bodies 141 and 142 comprise metal nitrides, such as tantalum and titanium. In some embodiments, bodies 141 and 142 comprise a variety of materials, for example, having one or more conformal metal layers (e.g., barrier and / or seed layers) on the sidewalls of dielectric layer 149 as a liner around different bulk or filler metals, which are within or surrounded by the liner. In many embodiments, bodies 141 and 142 have the same composition, for example, due to simultaneous deposition into metallization level 140.

[0032] Metal bodies 141 are continuous on the gate electrode 125 and the drain contact metal 131, and between the gate electrode 125 and the drain contact metal 131. Metal bodies 141 and 142 are continuous between the drain and source contact metals 131 and 132 and the upper plane 145. In embodiments where one or both of bodies 141 and 142 are mated to drain and / or source contact metals 131 and 132 in other transistor structures 101, bodies 141 and 142 are continuous on the gate electrode 125 and the drain and / or source contact metals 131 and 132, and between the gate electrode 125 and the drain and / or source contact metals 131 and 132. In some embodiments, bodies 141, 142 have multiple metal layers, one or both of bodies 141, 142 are mated to gate electrode 125 and contact metal 131 or 132, and the mated bodies 141 or 142 are continuous between gate electrode 125 and contact metal 131 and / or 132. For example, although interfaces (e.g., seams) may exist between the layers of the mated bodies 141 or 142, each layer spans electrode 125 and contact metal 131 and / or 132 and is continuous between electrode 125 and contact metal 131 and / or 132 (e.g., where interfaces also span between electrode 125 and metal 131 and / or 132). There are no seams or interfaces between electrode 125 and metal 131 and / or 132.

[0033] The bodies 141, 142 can be oriented (e.g., their size and spacing adjusted) to optimize the performance of device 100, for example, to ensure sufficient interface area while minimizing parasitic capacitance. In many embodiments, such as in the example in enlarged view 102, a first distance D1 separating the metal bodies 141, 142 is greater than a second distance D2 separating the gate electrode 125 and the source contact metal 132. The body 141 is large enough to fully overlap with the electrode 125, but leaves an additional space (e.g., distance D1) between the bodies 141, 142 (e.g., relative to a body 141 that completely covers the electrode 125).

[0034] exist Figure 1A and Figure 1B In exemplary embodiments of transistor structures 101A and 101B, the main body 141 includes a first portion 144 (such as...). Figure 1A (as shown) and the second part (e.g., Figure 1B Part 146 is shown. The main body 141 is continuous between parts 144 and 146, as described. The first part 144 extends in the x-direction between the gate electrode 125 and the drain contact metal 131 of structure 101A. (As will be...) Figure 1B As described above, the second part 146 of the main body 141 extends in the y direction (e.g., in...). Figure 1A Behind the view plane, enter Figure 1B (xz view plane) and contact the drain or source contact metals 131, 132 on the drain or source body 110 of another transistor structure 101B.

[0035] Contact metals 131, 132 may be conductive (e.g., metallic) materials or structures that contact source or drain bodies 110. Contact metals 131, 132 may, for example, couple region 110 (and transistor structure 101) to interconnect layer 150 and network 195 over transistor structure 101. Contact metals 131, 132 may comprise any suitable material, including nonmetals, such as those described with respect to metal bodies 141, 142. In some embodiments, bodies 141, 142 have a first component different from the second component of contact metals 131, 132, but metals 131, 132 may have a composition substantially the same as that of bodies 141, 142. For example, in many embodiments, metals 131, 132 comprise one or more of the same metals or nonmetals (including alloys, nitrides, etc.) in the bulk of contact metals 131, 132, but with an additional layer 133 of a different metal.

[0036] In many embodiments, metals 131, 132 comprise a variety of materials, such as one or more conformal metal layers 136 (e.g., barrier and / or seed layers 136) on the sidewalls of the source or drain body 110 or dielectric layer 139 as a liner around a different bulk or filler metal 135, which is within or surrounded by layer 136. In many embodiments, metals 131, 132 include an interface layer 133 on the source or drain body 110, the interface layer 133 being or comprising an alloy (e.g., as previously listed) of a metal and a semiconductor material of the body 110 (e.g., a silicide layer 133). Dielectric layer 139 may be on the sidewalls of metals 131, 132. Dielectric layer 139 may advantageously comprise a low-k dielectric material, such as silicon oxide (e.g., silicon dioxide SiO2). For example, dielectric layer 139 may provide etch selectivity with adjacent structures or materials during processing. In some embodiments, the dielectric layer 139 includes silicon nitride, silicon oxynitride, etc., with or without carbon.

[0037] Dielectric layer 159 is located in interconnect layer 150 and above dielectric layer 149 and metallization layer 140, with bodies 141, 142 mating with layer 159 (e.g., layer 159B) at plane 145. Interconnect layer 150 may include multiple dielectric layers 159, such as dielectric layer 159B at the bottom of layer 150 (e.g., where dielectric layer 159B is on metallization layer 140, including bodies 141, 142 and dielectric layer 149). A bulk or majority portion of dielectric layer 159 may advantageously be made of a low-k dielectric material, for example, to electrically insulate vias 162, 163 from each other. Etch stop layer 159B may advantageously be made of a low-k dielectric material, but etch stop layer 159B can provide etch selectivity and may have a higher dielectric constant compared to a bulk or majority portion of dielectric layer 159.

[0038] Vias 162 and 163 couple transistor structure 101 to interconnect network 195. Vias 162 and 163 are in and at least through interconnect layer 150, which is the lowest layer 150 of interconnect network 195. A first via 163 extends through dielectric layer 159 and interconnect layer 150 and abuts against metal body 142 at upper metallization plane 145. The first via 163 extends through dielectric layer 159 to a second height H2 and contacts metal body 142. A second via 162 extends through dielectric layers 149 and 159 and layers 140 and 150 and abuts against an uncoupled gate electrode 125 (e.g., electrode 125 of another transistor structure 101) at lower metallization plane 143, and does not contact metal body 141 or 142. The second via 162 extends through the dielectric layers 149 and 159 to a first height H1 and contacts the gate electrode 125 of the adjacent transistor structure 101.

[0039] Vias 162, 163 may comprise any suitable material, including nonmetals, such as those described with respect to metallic bodies 141, 142. Via 162 may have the same or different composition as via 163. In some embodiments, bodies 141, 142 have a first composition different from a second composition of the first and second vias 163, 162, but one or both of vias 162, 163 may have the same or different composition as bodies 141, 142. For example, in many embodiments, vias 162, 163 comprise one or more of tungsten, molybdenum, cobalt, ruthenium, copper, gold, tantalum, aluminum, nickel, or other metals or nonmetals (including in the form of alloys, nitrides, etc.). In many embodiments, vias 162, 163 comprise a variety of materials, such as having one or more conformal metal layers 166 (e.g., barrier and / or seed layers 166) on the sidewalls of dielectric layers 149 and / or 159 as linings around different bulk or filler metals 165, which are within or surrounded by layers 166.

[0040] The interface between contact level 130 and metallization level 140 can be shown through metal-metal, metal-dielectric, and dielectric-dielectric interfaces at planes 134, 143, and 145. For example, in some embodiments, the metal bodies 141, 142 at and above metallization plane 143 have a first composition different from the second composition of the drain and source contact metals 131, 132 below contact plane 134 (and metallization plane 143). In some such embodiments, the seam between bodies 141, 142 and metals 131, 132 is detectable (e.g., visible or otherwise in cross-section), wherein consecutive bodies 141, 142 and metals 131, 132 are adjacent at interface planes 134, 143. In many embodiments, the metal bodies 141, 142 at and above metallization plane 143 have a composition different from the composition of the gate electrode 125 below contact plane 134 (and metallization plane 143). In some such embodiments, the seam at interface planes 134, 143 is detectable between adjacent bodies 141, 142 and electrode 125. The interface between the metal bodies 141, 142 and the contact metals 131, 132 or electrode 125 may include metal bonding at adjacent planes 134, 143.

[0041] Interfaces (e.g., metal-metal interfaces) can be detectable between metal bodies 141, 142 and contact metals 131, 132 having the same composition. In some embodiments, metal bodies 141, 142 have the same composition as the drain and source contact metals 131, 132. If not visible, the seams between bodies 141, 142 and metals 131, 132 are generally still detectable by other analyses (e.g., in cross-section). In some embodiments, metal bodies 141, 142 have the same composition as at least a portion of the gate electrode 125. Even in embodiments with adjacent metal bodies 141, 142 and contact metals 131, 132 and where seams are difficult to detect (e.g., having the same composition above and below metal-bonded interface planes 134, 143), planes 134, 143 can be detected by overhang or underhang. For example, when the overhang of the body 141 or 142 extends beyond (e.g., in the x-direction) the sidewall of the contact metal 131, 132 or the gate electrode 125, the interface planes 134, 143 may be visible. When the sidewall of the body 141 or 142 is above the contact metal 131, 132 or the gate electrode 125, the interface planes 134, 143 may also be visible at the underhang.

[0042] Even when the bulk bodies of metal bodies 141, 142 match the bulk bodies of contact metals 131, 132 or gate electrode 125, the metal-metal interface can still be detectable. For example, in embodiments where the bulk bodies of body 141 and electrode 125 have matching compositions, the interface can be detectable at planes 134, 143, where the liner metal 126 of electrode 125 terminates at plane 134 and body 141. In other embodiments, the liner metal 126 terminates at surface 127 and below plane 134. Figure 1A In an exemplary embodiment, the liner metal 136 of the contact metals 131, 132 terminates below plane 134. However, in other embodiments, for example, where the bulk bodies 141, 142 and the metals 131, 132 have matching compositions, an interface can be detected at planes 134, 143 where the liner metal 136 terminates at plane 134 and the body 141 or 142. In some embodiments, the bulk bodies 141, 142 match the bulk bodies of the contact metals 131, 132 or the gate electrode 125, and an interface can be detected at planes 134, 143 where the liner metals (not shown) of 141, 142 abut the metals 131, 132 or the electrode 125.

[0043] The interfaces between layers 130, 140, and 150 can be demonstrated by the metal-dielectric interfaces at planes 134, 143, and 145. For example, the upper metallization plane 145 can be visible at the interface between the coplanar surface 147 of the metal bodies 141 and 142 and the dielectric layer 159 (e.g., layer 159B) above the bodies 141 and 142. The dielectric layer 159 is in the interconnect layer 150 and above the dielectric layer 149 and the metallization layer 140. Interface planes 134 and 143 can be detectable at the junction of any or both of the bodies 141 and 142 with any or both of the dielectric layers 123 and 139 and / or at the junction of the contact metals 131 and 132 or any of the gate electrodes 125 with the dielectric layer 149 (e.g., layer 149C). The upper surface 127 of the dielectric layer 123 may be coplanar with the upper surface 127 of the gate electrode 125, and the contact plane 134 and the upper surface 127 of the electrode 125 may be defined or distinguished by the interface of layer 123 at the body 141 (or 142). In some embodiments, the intersection of the body 141 and the gate dielectric layer 124 on the gate electrode 125 forms obvious interface planes 134, 143 (e.g., where the upper surface 127 of the gate dielectric layer 124 is coplanar with the upper surface 127 of the electrode 125). In other embodiments, layer 124 terminates below surface 127 and plane 134.

[0044] The interface between contact layer 130 and metallization layer 140 can be represented by dielectric-dielectric interfaces at planes 134, 143, and 145. For example, interface plane 145 may be visible at the interface between the upper surface 147 of dielectric layer 149 and the dielectric layer 159 (e.g., layer 159B) of interconnect layer 150 above metallization layer 140. In the top plane 145 of metallization layer 140, the upper surface 147 of dielectric layer 149 is coplanar with the upper surfaces 147 of metal body 141 and metal body 142. The intersection of interface planes 134 and 143 with dielectric layer 149 (e.g., layer 149C) of any or both of dielectric layers 123 and 139 may be detectable. In some embodiments, the intersection of dielectric layer 149 and gate dielectric layer 124 forms visible interface planes 134 and 143. In other embodiments, layer 124 terminates below surface 127 and plane 134.

[0045] A transistor structure 101 of any conductivity type (e.g., n-type or p-type) can be coupled to a power source via a metallization layer 140 through an interconnect network 195 (including interconnect layer 150). The drain and source bodies 110 are constructed of a semiconductor material doped with donor or acceptor impurities (n-type or p-type dopants), for example, having increased charge carrier availability and associated conductivity. The bodies 110 are electrically and physically coupled to opposite ends of the channel structure 120. The drain and source bodies 110 can be polycrystalline or substantially monocrystalline, for example, having long-range order at least at adjacent ends of the channel structure 120, and (e.g., in embodiments with nanoribbon channel structure 120) merged or connected into a single body with few grain boundaries. The bodies 110 can include one or more electrically active impurities from group IV semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn) alloys).

[0046] The channel structure 120 can be constructed from any suitable material and structure. Figure 1A In an exemplary embodiment, structure 120 is a stack of silicon nanoribbons, but other embodiments may have other aspect ratios (such as the aspect ratio of nanowires or nanosheets), structures (such as fins), or materials (such as Ge, SiGe, two-dimensional (2D) materials (e.g., transition metal dichalcogenides, TMD), etc.).

[0047] The gate electrode layer 125 126 on the gate dielectric layer 124 may include at least one of a p-type work function metal (WFM) or an n-type WFM, depending on whether the transistor is a PMOS or NMOS transistor. In some embodiments, the gate electrode 125 is a stack of two or more metal layers, wherein one or more metal layers are WFM layers, and at least one metal layer is a filler metal layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as aluminum carbide, hafnium carbide, zirconium carbide, titanium carbide, and tantalum carbide. An n-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV.

[0048] Gate dielectric layer 124 provides electrical insulation between channel structure 120 and gate electrode 125. Layer 124 may have more than one layer. Layer 124 may be made of any suitable material. One or more layers of dielectric layer 124 may include silicon oxide, silicon dioxide (e.g., SiO2), silicon oxynitride, etc. Advantageously, gate layer 124 includes a high-k dielectric, which can improve transconductance and electrostatic control of electrode 125 to channel structure 120. High-k dielectric materials may include one or more of various elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc, including oxides of these elements and combinations thereof. Any other suitable material may be deployed.

[0049] Gate spacer 122 in channel structure 120 (in Figure 1A In the case of the nanoband channel structure 120, electrical insulation is provided between the gate electrode 125 and the source and drain bodies 110. The gate spacer layer 123 provides electrical insulation between the gate electrode 125 and the source and drain bodies 110, and between the gate electrode 125 and the contact metals 131, 132. The dimple spacers 122 and spacer layer 123 may comprise or be composed of the same or different dielectric materials. Spacers 122 and spacer layer 123 may comprise silicon oxide, silicon dioxide (e.g., SiO2), silicon nitride, silicon oxynitride, etc., with or without carbon. Any other suitable material may be deployed. Advantageously, spacers 122 and spacer layer 123 comprise a low-k dielectric.

[0050] Interconnect network 195 includes layers (such as interconnect level 150) having interconnects or conductors providing electrical wiring, typically formed of metal or other conductive materials. Adjacent interconnect layers may be formed of different materials and by different methods. Metallization level 140 and interconnect level 150, along with network 195, are on top of device layers including transistor structure 101 and contact level 130. Adjacent metallization layers and interconnect layers are interconnected vias (such as vias 162, 163), which may be characterized as part of a metallization layer or between metallization layers.

[0051] In the illustrated example, network 195 may be a front-side interconnect network 195 including metallization layers M0, V0, M1, M2 / V1, M3 / V2, M4 / V3, and M4-M12. However, network 195 may include any number of metallization layers, such as eight or more. Similarly, rear-side network 195 may include BM0, BM1, BM2, and BM3. However, network 195 may include any number of metallization layers, such as two to five. The metallization portions in network 195 are embedded within a dielectric material (such as layer 159).

[0052] Substrate 199 may comprise any suitable one or more materials. Any suitable semiconductor or other material may be used. Substrate 199 may be any suitable substrate, such as a wafer, die, etc. Substrate 199 may comprise crystalline materials from which transistors can be formed or formed on, such as single-crystal or polycrystalline Si, Ge, SiGe, III-V alloy materials (e.g., gallium arsenide (GaAs)), silicon carbide (SiC), sapphire (Al2O3), or any combination thereof. In some embodiments, substrate 199 comprises crystalline silicon, and subsequent components are also silicon. In some embodiments, the crystalline material of substrate 199 is removed from the back side of transistor structure 101 (e.g., by grinding) and replaced with an insulating material. Substrate 199 may be a silicon-on-insulator (SOI) substrate. Substrate 199 may also comprise semiconductor materials, metals, dielectrics, dopants, and other materials common in IC substrates.

[0053] Figure 1B The diagram shows a row of transistors 101 of device 100 in the xz plane, which is parallel to... Figure 1A The structure 101 described in the text is as follows: Figure 1B At least one structure 101 in the structure is coupled to, via a link body 141 or 142 on the drain and / or source metals 131, 132 in each row of structure 101. Figure 1A One of the structures 101. Dielectric isolation section 129 is located between some of the source or drain bodies 110. At least one of the drain and source contact metals 131, 132 is not mated with the metal bodies 141, 142.

[0054] exist Figure 1A and Figure 1B In exemplary embodiments of transistor structures 101A and 101B, the main body 141 includes a first portion 144 (such as...). Figure 1A (as described in the description) and the second part 146. The main body 141 is continuous between parts 144 and 146. (As described in the description) Figure 1A As described herein, the first portion 144 extends in the x-direction between the gate electrode 125 and the drain contact metal 131. Figure 1B In the middle, part two, 146 (in the y direction) Figure 1A and Figure 1B (Extending between the xz view planes) the drain contact metal 131 is contacted on the drain body 110A of the transistor structure 101B.

[0055] Figure 1C Isometric and planar views of the contact plane 134 in device 100 are shown, as if cropped through the xy, yz, and xz view planes, including Figure 1A and Figure 1B The orientation of the outline views A-A' and B-B'. The dashed outline of section 103 in both the isometric view and the plan view provides further reference to the views and helps in comparison. Note that more of plane 134 is visible in the plan view than in the isometric view, extending beyond section 103. It should also be noted that... Figure 1A and Figure 1B Some portions of the outline views A-A' and B-B' extend beyond section 103. The dashed ellipse indicates along... Figure 1A and Figure 1B The cross-sectional views A-A' and B-B' are the regions above transistor structures 101A and 101B.

[0056] The gate electrode 125 (e.g., upper surface 127) and the drain and source contact metals 131, 132 (e.g., upper surface 137) are exposed at the xy contact plane 134. A dielectric layer 139 lies between the electrodes 125 and the contact metals 131, 132 extending in the y-direction. The dielectric layer 139 separates or isolates adjacent transistor structures 101 between pairs of electrodes 125 and pairs of contact metals 131, 132.

[0057] A cutaway view of device 100 reveals the yz plane of the track through gate electrode 125. Channel structure 120 extends through gate electrode 125 in the x direction. Dielectric isolation portion 129 is visible in the yz plane (along the edge of section 103), replacing some of the electrodes 125, and is included in view B-B'.

[0058] The cutout of device 100 includes an xz plane passing through the gate electrode 125 and at least one drain or source contact metal 131 or 132 (but not the associated drain or source body 110). Instead of some of the contact metals 131, 132 (or between some of the contact metals 131, 132), the dielectric isolation portion 129 is visible in the xz plane.

[0059] Figure 1D Isometric and planar views of the upper metallization plane 145 in device 100 are shown, as if cropped through the xy, yz, and xz view planes, including Figure 1A and Figure 1B The orientation of the outline views A-A' and B-B'. The dashed outline of section 103 in both the isometric view and the plan view. The dashed ellipse represents along... Figure 1A and Figure 1B The cross-sectional views A-A' and B-B' are the regions above transistor structures 101A and 101B.

[0060] The upper surfaces of the metal bodies 141 and 142 are exposed at the xy metallization plane 145 at the top of the metallization layer 140. A dielectric layer 149 lies between the bodies 141 and 142, which extend primarily in the y-direction. A first portion 144 of the body 141 extends in the x-direction (e.g., parallel to and over the channel structure 120). A second portion 146 of the body 141 extends in the y-direction, for example, parallel to and over the contact metals 131 and 132, and in some cases, couples the contact metals 131 and 132 in different transistor structures 101. For example, at least one body 141 is on transistor structures 101A, 101B (e.g., on metal 131 of structures 101A, 101B), wherein a portion 146 of the body 141 extends in the y direction between structures 101A, 101B, and wherein a portion 144 extends in the x direction (e.g., on and coupled to gate electrode 125 and metal 131 in each of structures 101A, 101B).

[0061] Via 162 is exposed at a plane 145 at the top of metallization layer 140 (e.g., at the midpoint of via 162 extending down from the interconnect layer and network into layer 140 and through layer 140). Via 162 is above gate electrode 125 (e.g., on electrode 125 and coupling electrode 125).

[0062] The cut-out of device 100 includes passing through the yz plane and xz plane of the metal bodies 141, 142 and the dielectric layer 149 in the metallization layer 140, which includes dielectric layers 149B and 149C at the bottom of the metallization layer 140.

[0063] Figure 1E An isometric view of the top of the interconnect hierarchy 150 in device 100 is shown, as if cropped through the xy, yz, and xz view planes, including Figure 1A and Figure 1B The orientation of the outline views A-A' and B-B'. The dashed ellipse indicates along... Figure 1A and Figure 1B The cross-sectional views A-A' and B-B' are the regions above transistor structures 101A and 101B.

[0064] Vias 162 and 163 are visible in the xy plane above interconnect layer 150. Dielectric layer 159 is located in layer 150 above metallization layer 140. Via 163 extends downward from interconnect network 195 and through interconnect layer 150 to bodies 141 and 142 (e.g., downwardly contacting and coupling bodies 141 and 142). Via 162 extends downward from interconnect network 195 and through interconnect layer 150 and metallization layer 140 to gate electrode 125 (e.g., downwardly contacting and coupling electrode 125).

[0065] The cut-out of device 100 includes the yz plane and xz plane passing through the metal bodies 141, 142 and dielectric layers 149, 159 in layers 140, 150. Interconnect layer 150 includes dielectric layer 159B at the bottom of layer 150.

[0066] Figure 2 This is a flowchart of a method 200 for forming a metallization layer having link bodies on the gate electrode and the drain and source contacts, according to some embodiments. Method 200 includes operations 210-260. Figure 2 Some of the operations shown are optional. Additional operations may be included. Figure 2 An example sequence is shown, but operations can be performed in other orders, and some operations can be omitted. Some operations can also be performed multiple times before other operations are performed. For example, multiple openings can be patterned in the first dielectric layer before covering it with the second dielectric layer. Some operations can be included within other operations, such that... Figure 2 The number of operations shown is not a limitation on method 200.

[0067] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F Isometric and plan views of an IC device 100 at various manufacturing stages according to some embodiments are shown. The IC device 100 has a gate electrode 125 in a metallization layer 140 directly in a contact layer 130 and a metal body 141, 142 on contact metals 131, 132. Figures 3A to 3F It shows in Figure 2 Possible examples of intermediate structures during the implementation of method 200.

[0068] return Figure 2 Method 200 begins with operation 210, in which the upper surface of the transistor structure is planarized. The transistor structure can be disposed on or in a substrate, such as an IC die or wafer, for example, with respect to... Figure 1A The substrate 199 described is very similar. Transistor structures can be planarized in any suitable manner. In many embodiments, the upper surface of the transistor structure is planarized by CMP (chemical mechanical planarization or polishing) of the substrate. Planarization (e.g., polishing) can reduce and smooth any structures and materials on the substrate and the upper surface of the transistor structure. A transistor structure may include a gate electrode (e.g., on a channel structure (such as a stack or fin of nanoribbons, nanowires, etc.), source and drain bodies (e.g., ends coupled to the channel structure), contacts (e.g., metallization on the source and drain), etc. Planarizing the upper surface of the transistor structure can planarize the upper surface of the source and drain contacts and the gate electrode to approximately horizontal, such as the same height, or all on the same planarized upper surface of the transistor structure.

[0069] Figure 3A The diagram illustrates the coplanar surfaces 127, 137 of the gate electrode 125 and the drain and source contact metals 131, 132 in a transistor structure 101 of a workpiece or IC device 100, according to some embodiments, such as after performing planarization operation 210. Dashed ellipses indicate areas above transistor structures 101A, 101B. Transistor structure 101 can be... Figure 1C Very similar to that described in (etc.), wherein the upper surface 127 of electrode 125 and the upper surface 137 of metals 131, 132 are planarized (e.g., polished) to the same level or height at contact plane 134. Dielectric layer 139 provides electrical isolation, for example, between gate electrode 125 and drain and source contact metals 131, 132. The upper surfaces 127, 137 of electrodes 125 and metals 131, 132 are prepared for operation 220, etc., for example, to link and couple transistor structures 101A, 101B (and other structures 101 on the xz plane of contour views A-A' and B-B').

[0070] return Figure 2 Method 200 continues at operation 220, wherein a dielectric layer is used to cover the transistor structure. The dielectric material may be deposited as a layer over the entire substrate or over selected portions, including on the upper surfaces of the gate electrode and the source and drain contacts. The dielectric material may be deposited in any suitable manner. In many embodiments, the dielectric material is a low-k dielectric, for example, to provide good electrical isolation, thereby minimizing parasitic capacitance between conductive structures. In some embodiments, the dielectric layer is one of a plurality of dielectric layers deposited over the transistor structure. In some such embodiments, the dielectric layer is a relatively thick low-k dielectric layer over one or more relatively thin layers (e.g., etch-stop layers that may have a slightly higher dielectric constant) that provide etch selectivity. In some such embodiments, the low-k dielectric layer comprises oxygen (e.g., in oxides, such as oxides of silicon), and the layer providing etch selectivity comprises nitrogen (e.g., in nitrides, such as nitrides of silicon).

[0071] Dielectric materials can be deposited by any suitable method, such as chemical vapor deposition (CVD). In some embodiments, multiple dielectric layers are deposited in different ways, such as a low-k dielectric layer thermally grown on top of an etch-stop layer deposited by ALD (atomic layer deposition).

[0072] Figure 3B A first dielectric layer 149 (and layers 149B, 149C) is shown over a transistor structure 101 in a workpiece or IC device 100, for example, after performing a cover operation 220, according to some embodiments. Dielectric layers 149B, 149C may be etch stop layers 149B, 149C, and dielectric layer 149 has a low dielectric constant. Dielectric layer 149 is prepared for operations such as 230, for example, to link and couple the transistor structure 101.

[0073] return Figure 2Method 200 continues by patterning one or more openings in the dielectric layer at operation 230. The openings can be formed at selected locations, for example, to expose certain structures beneath the dielectric layer for subsequent coupling with deposited metal. Holes or gaps can be opened in the dielectric layer above the gate electrode and source and drain contacts. In many embodiments, gaps are opened in the dielectric layer above the gate electrodes and source and drain contacts of multiple transistors. In many embodiments, patterning one or more openings in the dielectric layer forms openings with orthogonal portions. For example, a first portion of the opening may extend in a first direction over both the gate electrode and the source or drain contact, and a second portion of the opening may extend in a second orthogonal direction over the source or drain contact of a second transistor structure. The opening may have multiple vertical first portions and / or second portions. For example, the opening may have a single second portion extending over the contacts of multiple transistor structures, wherein the first portions of the opening branch orthogonally from the contacts of the multiple transistor structures to expose the corresponding gate electrodes.

[0074] The openings can be patterned by any suitable method (e.g., photolithographically). For example, a photolithographic mask complex can be deposited, selectively exposed (e.g., in a pattern), and used to remove patterned portions of a dielectric layer, thereby leaving openings to expose structures to be coupled via metal deposited in the openings. In some embodiments (e.g., embodiments having multiple dielectric layers deposited over a planarized upper surface of a transistor structure), multiple etching operations are used to expose the underlying structure.

[0075] Figure 3COpenings 341, 342 (including orthogonal portions 344, 346) are shown in a dielectric layer 149 passing over a transistor structure 101 in a workpiece or IC device 100, according to some embodiments, such as after performing patterning operation 230. Openings 341, 342 pass through dielectric layers 149, 149B, 149C, and gate electrodes 125 and contact metals 131, 132 are exposed in openings 341, 342. Openings 341, 342 can be filled to form corresponding bodies 141, 142. Orthogonal portions 344, 346 of opening 341 can be filled to form corresponding portions 144, 146 of bodies 141. Openings 341, 342 in layer 149 are prepared for operations such as 240, for example, to link and couple transistor structure 101. For example, opening 341 may be filled with metal to form link body 141 (e.g., for linking gate electrode 125 and contact metals 131, 132 and for contacting via via 163 to couple to network 195), and opening 342 may be filled with the same metal to form body 142 (e.g., for linking contact metals in adjacent transistor structure 101 and for contacting via via 163 to couple to network 195).

[0076] return Figure 2 Method 200 continues at operation 240, depositing metal in the opening. The deposited metal can be any suitable material and can be deposited in any suitable manner. The deposited metal can be deposited on and coupled to any gate electrode and source or drain contact exposed through the opening. For example, the deposited metal can be coupled to the gate electrode, coupled to the source or drain contact exposed in the same transistor structure and through the same opening in the dielectric layer, and coupled the gate electrode and the source or drain contact (e.g., coupled to each other through the deposited metal). The metal can be deposited in the opening, on the upper (e.g., planarized) surface of the transistor structure, and on the dielectric layer (and / or photomask) above the transistor structure, for example, where the lower edge or surface of the metal is above any gate electrode, source and drain body, and source and drain contact of the transistor structure.

[0077] In embodiments having openings extending over contacts of multiple transistor structures, metal is deposited in the openings to couple the multiple transistor structures. The deposited metal can be coupled to source or drain contacts exposed through the openings and to any gate electrodes exposed by the openings, and previously exposed contacts and electrodes can be covered and coupled by the deposited metal. In many embodiments, the deposited metal is planarized, for example down to the dielectric layer, thereby removing any excess metal and leaving a planarized upper surface of the substrate, wherein the deposited metal is exposed within the dielectric layer.

[0078] Metals can be deposited by any suitable method. In some embodiments, barrier and / or seed metals (e.g., in a thin conformal layer, e.g., by ALD) are first deposited on a first dielectric layer and exposed electrode and contact metals (e.g., in a thin conformal layer, e.g., by ALD). A bulk or filler metal can then be deposited on (e.g., grown from the first metal), e.g., different metals deposited by different methods. The metals can be as described regarding... Figure 1A The main bodies 141, 142 (and metals 131, 132, including metal 135 and layer 136) are described at the location.

[0079] Figure 3D Metal bodies 141, 142 of the gate electrode 125 and contact metals 131, 132 in a transistor structure 101 of a linked workpiece or IC device 100, according to some embodiments, are shown, for example, after performing deposition operation 240. Metallization level 140 includes metal bodies 141, 142 and dielectric layers 149, 149B, 149C. An upper metallization plane 145 is located at the top of level 140 and bodies 141, 142 and layer 149. Metal body 142 is above and on contact metals 131, 132, and metal body 141 is above and on gate electrode 125 and contact metals 131, 132. Metal body 141 includes orthogonal portions 144, 146. (It is worth noting that via 162 has not yet passed through layer 149.) The metal bodies 141, 142 and the dielectric layer 149 are prepared for operation 250, for example, to cover the bodies 141, 142 and layer 149 and couple the transistor structure 101.

[0080] return Figure 2 Method 200 continues at operation 250 by covering the dielectric layer and the deposited metal with another dielectric layer. This second dielectric can be deposited as the same or a different dielectric material layer over the entire substrate or at least over the first dielectric layer and the deposited metal. The dielectric material can be any suitable material and can be deposited in any suitable manner. In many embodiments, the dielectric material is a low-k dielectric material. In some embodiments, multiple dielectric layers are deposited over the first dielectric layer. In some such embodiments, one or more etch stop layers are first deposited over the metal and the first dielectric layer, and then a low-k dielectric layer is deposited over the etch stop layers to provide electrical isolation.

[0081] Figure 3EA second dielectric layer 159 is shown over a metal body 141, 142 and a first dielectric layer 149 on a transistor structure 101 in a workpiece or IC device 100, according to some embodiments, such as after performing a covering operation 250. Layer 159C is on the metallization level 140 (including bodies 141, 142 and layer 149), and layer 159 is on layer 159C. The dielectric layer 159 and the transistor structure 101 are prepared for operation 260, for example, to couple the transistor structure 101.

[0082] return Figure 2 Method 200 continues at operation 260 by coupling the transistor structure to, for example, an interconnect network above the transistor structure. In many embodiments, the transistor structure is coupled by forming vias that at least penetrate the second dielectric layer. In many embodiments, the transistor structure is coupled by forming vias that penetrate the first and second dielectric layers. In many embodiments, the transistor structure is coupled by forming a first via (e.g., downward and contacting the metal deposited at operation 240) through the second dielectric layer and a second via (e.g., downward and contacting the gate electrode) through the first and second dielectric layers. In some embodiments, the vias are formed through the first and second dielectric layers and contact the source or drain contacts.

[0083] Vias can be made of any suitable material and can be formed in any suitable manner. For example, a via can be formed of one or more suitable metals, with respect to the metal at operation 240 or regarding... Figure 1A The vias 162 and 163 (including the barrier layer and / or seed layer 166 and the bulk or filler metal 165) described herein are very similar to those described. Vias can be formed by first opening a cavity or hole in and through one or both of the first and second dielectric layers above the transistor structure, and secondly, depositing one or more metals in at least the opening, very similar to those described by operations 230 and 240. It is noteworthy that the via opening can extend deeper and through more dielectric layers, and the via can contact the gate electrode, source or drain contacts, or the top of the metal deposited at operation 240.

[0084] Figure 3FVias 162 and 163 are shown, according to some embodiments, for example, after performing coupling operation 260, through interconnect layers 140 and 150 to a transistor structure 101 in IC device 100. Interconnect layer 150 includes dielectric layers 159 and 159B. Via 163 extends through layers 159 and 159B and interconnect layer 150 and contacts body 142, and via 163 extends through layers 149, 149B, 149C, 159, 159B and layers 140 and 150 and contacts body 141. Interconnect network 195 may be formed on metallization layer 140 (and may include layer 150) and may couple transistor structure 101 through vias 162 and 163. Transistor structure 101 may be coupled to power supply (not shown) through network 195. Transistor structure 101 and network 195 may be coupled to power supply (not shown) through an optional back-side interconnect network 395 opposite to network 195.

[0085] IC device 100 may include or be coupled to a substrate or other host component 399. Host component 399 may be a package substrate, an interposer, an IC die, etc. For example, substrate 199 may be an IC die including transistor structure 101, substrate 199 may be coupled (e.g., soldered or otherwise bonded) to host component 399, and transistor structure 101 may be coupled to a power source (not shown) through host component 399.

[0086] The substrate component 399 is a planar platform and may include dielectric and metallization structures. The substrate component 399 mechanically supports and electrically couples one or more IC devices 100. At least one side of the substrate component 399 includes a substrate interconnect interface for bonding to one or more IC devices 100. The IC device 100 may be directly bonded (e.g., hybrid bonding) to the substrate component 399 or otherwise bonded, such as via optional solder bumps. The opposite side of the substrate component 399 may include similar interfaces, such as copper pads for insertion and / or solder bumps for bonding the device 100 to a substrate component (such as a printed circuit board (PCB)). The substrate component 399 may be any substrate component having a substrate interconnect interface, such as an encapsulated substrate component 399 or an interposer. The substrate component 399 itself may be a die. In many embodiments, the substrate component 399 includes an organic dielectric, such as a resin or other polymer, between metallization layers.

[0087] Figure 4A schematic diagram of an example data server machine 406 employing an IC device according to some embodiments is shown. This IC device has a metallization layer on a transistor linking gate electrodes and source or drain contacts. The server machine 406 can be any commercial server, for example, including any number of high-performance computing platforms housed in a rack and networked together for electronic data processing. In an exemplary embodiment, it includes one or more devices 450 having a metallization layer on the transistor linking gate electrodes and source or drain contacts.

[0088] As also shown in the figures, server machine 406 includes a battery and / or power supply 415 to provide power to device 450 and, in some embodiments, provides power delivery functions such as power regulation. Device 450 may be deployed as part of package-level integrated system 410. Integrated system 410 is further shown in expanded view 420. In exemplary embodiments, device 450 (labeled “memory / processor”) includes at least one memory chip (e.g., random access memory (RAM)) and / or at least one processor chip (e.g., microprocessor, multi-core microprocessor, or graphics processor, etc.) having the characteristics discussed herein. In embodiments, device 450 is a microprocessor including static RAM (SRAM) cache memory. As shown in the figures, device 450 may be an IC device having a metallization layer on a transistor having linked gate electrodes and source or drain contacts, as discussed herein. Device 450 may be further coupled (e.g., communicatively coupled) to a board, interposer, or other substrate or base component 399, and one or more of a power management IC (PMIC) 430, an RF (radio) IC (RFIC) 425 including a broadband RF (radio) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband, and the analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and its controller 435. In some embodiments, RFIC 425, PMIC 430, controller 435, and device 450 include a metallization layer on a transistor linking the gate electrode and source or drain contacts.

[0089] Figure 5 This is a block diagram of an example computing device 500 according to some embodiments. For example, one or more components of computing device 500 may include any of the devices or structures discussed herein. Multiple components in Figure 5The components are shown as being included in computing device 500, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in computing device 500 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various components of these components may be fabricated on a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing device 500 may not include... Figure 5 The computing device 500 may include one or more components, but may include interface circuitry for coupling to one or more components. For example, the computing device 500 may not include a display device 503, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 503 may be coupled. In another set of examples, the computing device 500 may not include an audio output device 504, other output devices 505, a Global Positioning System (GPS) device 509, an audio input device 510, or other input devices 511, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, audio input device interface circuitry, and audio input device interface circuitry to which the audio output device 504, other output devices 505, GPS device 509, audio input device 510, or other input devices 511 may be coupled.

[0090] Computing device 500 may include processing device 501 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" refers to a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 501 may include memory 521, communication device 522, cooling device 523, battery / power regulation device 524, logic 525, interconnect 526 (i.e., optionally including redistribution layer (RDL) or metal-insulator-metal (MIM) devices), thermal regulation device 527, and hardware security device 528.

[0091] Processing device 501 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device.

[0092] Computing device 500 may include memory 502, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drive. In some embodiments, memory 502 includes memory that shares a die with processing device 501. The memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0093] The computing device 500 may include a thermal regulation / cooling device 506. The thermal regulation / cooling device 506 can maintain the processing device 501 (and / or other components of the computing device 500) at a predetermined low temperature during operation.

[0094] In some embodiments, computing device 500 may include communication chip 507 (e.g., one or more communication chips). For example, communication chip 507 may be configured to manage wireless communication for transmitting data to and from computing device 500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0095] The 507 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks. WiMAX is an acronym for Global Microwave Access Interoperability, a certification mark for products that pass conformance and interoperability testing of the IEEE 802.16 standard. The 507 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication chip 507 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 507 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, communication chip 507 can operate according to other wireless protocols. Computing device 500 may include antenna 513 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0096] In some embodiments, communication chip 507 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication chip 507 may include multiple communication chips. For example, a first communication chip 507 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 507 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 507 may be dedicated to wireless communications, and the second communication chip 507 may be dedicated to wired communications.

[0097] The computing device 500 may include a battery / power circuit 508. The battery / power circuit 508 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the computing device 500 to an energy source (e.g., AC line power) separate from the computing device 500.

[0098] The computing device 500 may include a display device 503 (or a corresponding interface circuit, as described above). The display device 503 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0099] The computing device 500 may include an audio output device 504 (or a corresponding interface circuit, as described above). The audio output device 504 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0100] The computing device 500 may include an audio input device 510 (or a corresponding interface circuit, as described above). The audio input device 510 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0101] The computing device 500 may include a GPS device 509 (or a corresponding interface circuit, as described above). The GPS device 509 may communicate with a satellite-based system and may receive the location of the computing device 500, as is known in the art.

[0102] The computing device 500 may include other output devices 505 (or corresponding interface circuitry, as described above). Examples of other output devices 505 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0103] The computing device 500 may include other input devices 511 (or corresponding interface circuitry, as described above). Examples of other input devices 511 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (such as mice), styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0104] Computing device 500 may include security interface device 512. Security interface device 512 may include any device that provides security measures for computing device 500, such as intrusion detection, biometric authentication, secure encoding or decoding, access list management, malware detection, or spyware detection.

[0105] The computing device 500 or a subset thereof may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device.

[0106] The subject matter of this instruction manual is not limited to Figure 1A-5 The specific application shown is illustrated. This topic can be applied to other deposition applications as well as any suitable manufacturing applications, as those skilled in the art will understand.

[0107] The following examples relate to further embodiments, and the details in the examples may be used anywhere in one or more embodiments.

[0108] In one or more first embodiments, an apparatus includes: a transistor structure including a source body, a drain body, and a gate electrode over a channel structure; a source contact metal on the source body and a drain contact metal on the drain body; a first metal body in a metallization layer that is mated to the source contact metal, the drain contact metal, and the gate electrode, the first metal body being on one of the source contact metal or the drain contact metal and the gate electrode and being continuous between the gate electrode and one of the source contact metal or the drain contact metal; and a second metal body in a metallization layer that is on the other of the source contact metal and the drain contact metal.

[0109] In one or more second embodiments, further for the first embodiment, in the contact layer below the metallization layer, the lower surface of the first metal body and the lower surface of the second metal body are substantially coplanar in the metallization plane, and the upper surface of the source contact metal, the upper surface of the drain contact metal and the upper surface of the gate electrode are substantially coplanar in the contact plane above the channel structure, and the contact plane is aligned with the metallization plane.

[0110] In one or more third embodiments, for the first or second embodiment, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, the metallization plane is a first metallization plane, the first metal body and the second metal body are in a first dielectric layer in the metallization layer and above the contact layer, the second dielectric layer is above the first dielectric layer and the metallization layer, the upper surface of the first metal body and the upper surface of the second metal body are substantially coplanar in the second metallization plane, the first via extends through the second dielectric layer and docks with the second metal body at the second metallization plane, and the second via extends through the first dielectric layer and the second dielectric layer and docks with the second gate electrode of the second transistor structure at the first metallization plane.

[0111] In one or more fourth embodiments, for the first to third embodiments, the first and second metal bodies further have a first component that is different from the second component of the first via and the second via.

[0112] In one or more fifth embodiments, for the first to fourth embodiments, the first metal body and the second metal body further have a first component that is different from the second component of the source contact metal and the drain contact metal or the third component of the gate electrode.

[0113] In one or more sixth embodiments, for the first to fifth embodiments, the first components of the first metal body and the second metal body are substantially the same as the second components of the source contact metal and the drain contact metal.

[0114] In one or more seventh embodiments, and further for the first to sixth embodiments, the first metal body includes a first portion and a second portion, the first portion extending in a first direction between the gate electrode and one of the source contact metal or the drain contact metal, and the second portion of the first metal body extending in a second direction orthogonal to the first direction.

[0115] In one or more eighth embodiments, for the first to seventh embodiments, the transistor structure is a first transistor structure, the source body is a first source body, and the drain body is a first drain body, the source contact metal is a first source contact metal, and the drain contact metal is a first drain contact metal, and a second portion of the first metal body extending in a second direction contacts the second source contact metal or the second drain contact metal on the second source or drain body of the second transistor structure.

[0116] In one or more ninth embodiments, and further for the first to eighth embodiments, the first distance separating the first and second metal bodies is greater than the second distance separating the gate electrode from the other of the source contact metal and the drain contact metal.

[0117] In one or more tenth embodiments, an apparatus includes a transistor structure comprising: a source body, a drain body, and a gate electrode over a channel structure; a source contact metal on the source body and a drain contact metal on the drain body, wherein the upper surfaces of the source contact metal, the upper surfaces of the drain contact metal, and the upper surfaces of the gate electrode are substantially coplanar over the channel structure; and a first metal body and a second metal body in a dielectric layer over the transistor structure, the first metal body being in contact with the gate electrode and one of the source contact metal or the drain contact metal, the first metal body being continuous between the gate electrode and one of the source contact metal or the drain contact metal, and the second metal body being in contact with the other of the source contact metal and the drain contact metal.

[0118] In one or more eleventh embodiments, and further for the tenth embodiment, the lower surfaces of the first metal body and the second metal body are substantially coplanar at a first height above the channel structure, and the upper surfaces of the first metal body and the second metal body are substantially coplanar at a second height above the channel structure.

[0119] In one or more twelfth embodiments, and further for the tenth or eleventh embodiment, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, the dielectric layer is a first dielectric layer, the second dielectric layer is above the first dielectric layer, the first via extends through the second dielectric layer to a second height and contacts the second metal body, and the second via extends through the first dielectric layer and the second dielectric layer to a first height and contacts the second gate electrode of the second transistor structure.

[0120] In one or more thirteenth embodiments, and further for the tenth to twelfth embodiments, the first metal body includes a first portion and a second portion, the first metal body being continuous between the first portion and the second portion, the first portion extending in a first direction between the gate electrode and one of the source contact metal or the drain contact metal, and the second portion of the first metal body extending in a second direction orthogonal to the first direction.

[0121] In one or more of the fourteenth embodiments, and further for the tenth to thirteenth embodiments, the source body is a first source body, the source contact metal is a first source contact metal, the drain body is a first drain body, the drain contact metal is a first drain contact metal, and the second portion contacts the second source contact metal or the second drain contact metal on the second source or drain body of the third transistor structure.

[0122] In one or more of the fifteenth embodiments, and further for the tenth to fourteenth embodiments, the integrated circuit (IC) die includes a transistor structure, the IC die being coupled to a substrate, and the transistor structure being coupled to a power source through the substrate.

[0123] In one or more sixteenth embodiments, a method includes: covering a transistor structure with a first dielectric layer on a gate electrode and a source or drain contact, the transistor structure including a gate electrode, a source or drain contact, and a source or drain body below the source or drain contact, the source or drain contact being on the source or drain body; patterning an opening in the first dielectric layer above the gate electrode and the source or drain contact; depositing metal in the opening, wherein the metal is on the gate electrode and the source or drain contact, and a lower edge of the metal is above the gate electrode and the source or drain contact; and covering the first dielectric layer and the metal with a second dielectric layer.

[0124] In one or more of the seventeenth embodiments, and further for the sixteenth embodiment, the method further includes: planarizing a first upper surface of the transistor structure, wherein a first dielectric layer is used to cover the transistor structure to deposit a dielectric material on a second upper surface of the gate electrode and a third upper surface of the source or drain contact, and the second upper surface of the gate electrode and the third upper surface of the source or drain contact are substantially flush at a height.

[0125] In one or more of the eighteenth embodiments, and further for the sixteenth or seventeenth embodiments, the method further includes coupling the transistor structure by forming a via at least through the second dielectric layer.

[0126] In one or more of the nineteenth embodiments, and further for the sixteenth to eighteenth embodiments, the via is a first via, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, the coupling transistor structure forms a first via through the second dielectric layer, the first via contacts the source or drain contact portion, and the method further includes: forming a second via through the first and second dielectric layers, the second via contacting the second gate electrode of the second transistor structure.

[0127] In one or more twentieth embodiments, and further for the sixteenth to nineteenth embodiments, the transistor structure is a first transistor structure, the source or drain contact is a first source or drain contact, an opening is patterned in the first dielectric layer to form an orthogonal first portion and a second portion of the opening, the first portion is above the gate electrode and the source or drain contact and extends in a first direction, and the second portion extends in a second direction above the second source or drain contact of the second transistor structure, the second direction being orthogonal to the first direction, and a metal is deposited in the opening to couple the first transistor structure and the second transistor structure.

[0128] This disclosure can be practiced through modifications and alterations, and the scope of the appended claims is not limited to the embodiments described herein. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this respect, and in various implementations, the above embodiments may include only a subset of such features, different orders of such features, different combinations of such features, and / or additional features different from those expressly listed. Therefore, the scope of the patent right should be determined with reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A transistor structure, the transistor structure including a source body, a drain body and a gate electrode above a channel structure; The source contact metal on the source body and the drain contact metal on the drain body; A first metal body in a metallization layer, the metallization layer being mated to the source contact metal, the drain contact metal and the gate electrode, the first metal body being on one of the source contact metal or the drain contact metal and the gate electrode and being continuous between the one of the source contact metal or the drain contact metal and the gate electrode; as well as A second metal body in the metallization layer, the second metal body being on the other of the source contact metal and the drain contact metal.

2. The apparatus according to claim 1, wherein: The source contact metal, the drain contact metal, and the gate electrode are in a contact layer below the metallization layer; and The lower surfaces of the first metal body and the second metal body are substantially coplanar in the metallization plane.

3. The apparatus according to claim 2, wherein, The upper surfaces of the source contact metal, the drain contact metal, and the gate electrode are substantially coplanar in the contact plane above the channel structure, and the contact plane is aligned with the metallization plane.

4. The apparatus according to claim 3, wherein: The transistor structure is a first transistor structure; The gate electrode is the first gate electrode; The metallization plane is the first metallization plane; The first metal body and the second metal body are in the first dielectric layer of the metallization level and above the contact level; The second dielectric layer is above the first dielectric layer and the metallization layer; and The upper surfaces of the first metal body and the second metal body are substantially coplanar in the second metallization plane.

5. The apparatus according to claim 4, wherein, The first via extends through the second dielectric layer and docks with the second metal body at the second metallization plane.

6. The apparatus according to claim 5, wherein, The second via extends through the first dielectric layer and the second dielectric layer, and docks with the second gate electrode of the second transistor structure at the first metallization plane.

7. The apparatus according to claim 6, wherein, The first metal body and the second metal body have a first component that is different from the second component of the first via and the second via.

8. The apparatus according to any one of claims 1-7, wherein, The first metal body and the second metal body have a first component that is different from the second component of the source contact metal and the drain contact metal or the third component of the gate electrode.

9. The apparatus according to claim 8, wherein, The first component of the first metal body and the second metal body is substantially the same as the second component of the source contact metal and the drain contact metal.

10. The apparatus according to any one of claims 1-8, wherein: The first metal body includes a first part and a second part; The first portion extends in a first direction between one of the source contact metal or the drain contact metal and the gate electrode; and The second portion of the first metal body extends in a second direction orthogonal to the first direction.

11. The apparatus according to claim 10, wherein: The transistor structure is a first transistor structure; The source body is a first source body, and the drain body is a first drain body; The source contact metal is a first source contact metal, and the drain contact metal is a first drain contact metal; and The second portion of the first metal body extending in the second direction contacts the second source contact metal or the second drain contact metal on the second source or drain body of the second transistor structure.

12. The apparatus according to any one of claims 1-8, wherein, The first distance separating the first metal body and the second metal body is greater than the second distance separating the gate electrode from the other of the source contact metal and the drain contact metal.

13. The apparatus according to any one of claims 1-8, wherein: An integrated circuit (IC) die includes the transistor structure described above; The IC die is coupled to the substrate; and The transistor structure is coupled to a power source through the substrate.

14. A method comprising: A transistor structure is covered by a first dielectric layer, the first dielectric layer being on the gate electrode and the source or drain contact portion. The transistor structure includes the gate electrode, the source or drain contact portion, and a source or drain body below the source or drain contact portion, the source or drain contact portion being on the source or drain body. An opening is patterned in the first dielectric layer above the gate electrode and the source or drain contact portion; Metal is deposited in the opening, wherein the metal is on the gate electrode and the source or drain contact, and the lower edge of the metal is above the gate electrode and the source or drain contact; as well as The first dielectric layer and the metal are covered by a second dielectric layer.

15. The method of claim 14, further comprising: Planarizing the first upper surface of the transistor structure, wherein covering the transistor structure with the first dielectric layer includes depositing dielectric material on the second upper surface of the gate electrode and the third upper surface of the source or drain contact.

16. The method of claim 14, further comprising: The transistor structure is coupled by forming a via that passes through at least the second dielectric layer.

17. The method according to claim 16, wherein, The via is a first via, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, and coupling the transistor structure includes forming the first via through the second dielectric layer, the first via contacting the source or drain contact portion.

18. The method of claim 17, further comprising: A second via is formed through the first dielectric layer and the second dielectric layer, and the second via contacts the second gate electrode of the second transistor structure.

19. The method according to any one of claims 14-18, wherein: The transistor structure is a first transistor structure; The source or drain contact portion is a first source or drain contact portion; and The opening is patterned in the first dielectric layer to form an orthogonal first portion and a second portion of the opening. The first portion extends over the gate electrode and the source or drain contact in a first direction, and the second portion extends over the second source or drain contact of the second transistor structure in a second direction, which is orthogonal to the first direction.

20. The method according to claim 19, wherein, The metal is deposited in the opening to couple the first transistor structure and the second transistor structure.

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