AgSe gate tube material and gate tube unit

Abstract

The invention relates to an AgSe gate tube material and a gate tube unit, the chemical general formula of the AgSe gate tube material is AgxSey, the value of x is greater than or equal to 0.1 and less than or equal to 0.5, and the value of y is greater than or equal to 0.5 and less than or equal to 0.9. The AgSe-based gate tube unit provided by the invention has the characteristics of low electric leakage, high gate ratio, quick response, good durability and the like, and is suitable for constructing a novel nonvolatile memory array with high density and low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, and specifically relates to an AgSe gate material and a gate unit. Background Technology

[0002] The global semiconductor market is experiencing continuous growth, driven by artificial intelligence, 5G communication, the Internet of Things, and high-performance computing. This has led to an explosive increase in demand for data storage, with memory playing a crucial role. However, memory technology faces multiple bottlenecks. Traditional memories such as DRAM and NAND Flash, while dominating the market for a long time, also face challenges such as miniaturization limitations, high power consumption, speed constraints, and declining reliability. As process nodes fall below 10 nm, the quantum tunneling effect intensifies, making it difficult to balance device performance and integration density, thus limiting their application in next-generation high-performance computing and intelligent systems. In contrast, novel non-volatile memories (such as RRAM, PCM, MRAM, and FeRAM) demonstrate enormous development potential due to their advantages of high-speed read / write, low power consumption, good scalability, and non-volatility. They are not only expected to break through the bottlenecks of traditional storage technologies but also support the development of new computing architectures such as "in-memory computing" and "edge AI," becoming key to next-generation high-density, high-efficiency storage solutions.

[0003] However, large-scale integration in novel memory arrays remains severely constrained by crosstalk and leakage current issues. To address the "selectivity" problem, gating devices have emerged as key components, typically forming 1S1R (one memory + one gating) or cross-array structures with memory cells to achieve high-density, high-reliability memory systems. Among these, threshold switching materials with high nonlinearity, low leakage current, and fast response characteristics have become a research hotspot.

[0004] Existing gate devices mainly include omnidirectional threshold switches (OTS), which can reversibly switch from a high-resistance state to a low-resistance state in both positive and negative voltage directions. They offer advantages such as simple structure, fast switching speed, and low power consumption, making them a widely adopted gate selection scheme in novel memory arrays. However, existing threshold switch materials still suffer from several unresolved issues, such as high leakage current, insufficient switching current ratio, poor thermal stability, and performance degradation at the nanoscale, severely impacting device selectivity and array reliability. Therefore, we need to actively explore novel OTS materials with superior performance. Summary of the Invention

[0005] The purpose of this invention is to provide an AgSe gate tube material and gate tube unit, aiming to solve the technical problems of large leakage current, low driving current, poor thermal stability and slow response speed in OTS materials.

[0006] This invention provides an AgSe gate material, whose chemical formula is Ag. x Se y In the formula, the value of x is 0.1≤x≤0.5, and the value of y is 0.5≤y≤0.9.

[0007] Preferably, doping elements are introduced into the AgSe gate material, including but not limited to one or more of C, N, Si, In, P, Ag, Pt, Al, Ge, Zn, Ta, and W.

[0008] Preferably, the AgSe gate material is Ag. 0.2 Se 0.8 or Ag 0.5 Se 0.5 .

[0009] Preferably, the AgSe gate material is a bidirectional threshold gate material.

[0010] Preferably, when the AgSe gate material reaches the threshold voltage under the excitation of an electrical signal, it can achieve an instantaneous transition from a high to a low resistance state, and after the voltage is removed, it returns to a high resistance state.

[0011] Furthermore, when the applied electric field strength exceeds 1×10 6 At V / cm, the material switches from a high-resistivity state to a low-resistivity state; after the applied electric field is removed, the material can spontaneously recover to the high-resistivity state within 15 ns, exhibiting typical electro-switching behavior.

[0012] Preferably, the AgSe gate material, after high-temperature annealing, remains in an amorphous state and still possesses threshold gate characteristics.

[0013] Preferably, the switching time of the AgSe gate material is on the order of nanoseconds.

[0014] The present invention also provides a gate tube unit, which comprises, from top to bottom: an upper electrode layer, an OTS material layer and a lower electrode layer; the OTS material layer comprises the aforementioned AgSe gate tube material.

[0015] Preferably, the thickness of the upper electrode layer is 40-80 nm.

[0016] Preferably, the thickness of the OTS material layer is 5-20 nm.

[0017] Preferably, the thickness of the lower electrode layer is 100-200 nm.

[0018] Preferably, the materials of the upper electrode layer and the lower electrode layer include one or more of Au, Ag, Pt, Cu, W, Al, Ni, and TiN.

[0019] Preferably, the gate unit can be integrated with the memory unit through a nano-interconnect structure, and at the same time has the function of driving the memory unit connected thereto.

[0020] Furthermore, the memory unit includes one or more of phase-change memory units, resistive switching memory units, magnetic memory units, or ferroelectric memory units.

[0021] Preferably, the gate unit and the memory unit form a three-dimensional cross-shaped array to achieve high-density storage.

[0022] The fabrication method of the above-mentioned gate tube unit includes the following steps:

[0023] S1. Prepare the lower electrode layer;

[0024] S2. An OTS material layer is prepared on the lower electrode layer; the OTS material layer includes the above-mentioned AgSe gate material;

[0025] S3. Prepare an upper electrode layer on the OTS material layer.

[0026] Preferably, the preparation method of the lower electrode layer, OTS material layer or upper electrode layer includes, but is not limited to, any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and molecular beam epitaxy.

[0027] Beneficial effects

[0028] (1) By precisely controlling the chemical ratio of Ag and Se atoms, the present invention optimizes the structure and properties of the amorphous AgSe system, which can significantly improve the thermal stability and fatigue resistance of the material.

[0029] (2) The gate tube unit in this invention uses AgSe gate tube material as the middle functional layer and forms a sandwich structure with the upper and lower electrodes. It can achieve good compatibility with mainstream memory units such as phase change memory (PCRAM) and resistive random access memory (RRAM) and can be integrated into a cross-type array to support high-density storage applications.

[0030] (3) The present invention is expected to realize the function of a self-gating device by applying a specific pulse.

[0031] (4) This invention combines low toxicity, high performance and process compatibility, providing an efficient and environmentally friendly solution for next-generation non-volatile memory and electronic switches. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of the selection tube unit of the present invention.

[0033] Figure 2The 20 nm Ag in Example 1 0.2 Se 0.8 Pulse test curve of the selector unit.

[0034] Figure 3 The 20 nm Ag in Example 1 0.2 Se 0.8 Characterization diagram of the turn-on speed of the selector unit.

[0035] Figure 4 The 20 nm Ag in Example 1 0.2 Se 0.8 Characterization diagram of the closing speed of the selector unit.

[0036] Figure 5 The 20 nm Ag in Example 1 0.2 Se 0.8 Pulse response test curve of the self-gating function of the gate tube unit.

[0037] Figure 6 The 20 nm Ag in Example 1 0.2 Se 0.8 Input voltage-output current curves for pulse response testing of the self-gating function of the selector unit. Detailed Implementation

[0038] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0039] Example 1

[0040] This embodiment provides an AgSe gate material and a gate tube unit, wherein the chemical formula of the AgSe gate material is Ag. 0.2 Se 0.8 Its preparation method includes the following steps:

[0041] S1. The lower electrode layer was prepared by magnetron sputtering, using TiN as the material. Specific preparation parameters were: vacuum level controlled at 4.0 × 10⁻⁶. -4 Below Pa, a TiN alloy target was used for deposition under 50 W DC target conditions, with high-purity argon (Ar) as the working gas and a gas flow rate of 20 sccm. The prepared cylindrical lower electrode has a diameter of 200 nm and a height of 120 nm. Figure 1 As shown in layer ①.

[0042] S2. Subsequently, an OTS material layer, namely amorphous Ag, is deposited above the TiN lower electrode layer. 0.2 Se 0.8 Thin film; deposited at room temperature by radio frequency magnetron sputtering using Ag 0.2 Se 0.8 The alloy target material, with a thin film thickness controlled at around 20 nm, ensures good electric field distribution and stable switching behavior, such as... Figure 1 As shown in layer ②; the vacuum level was maintained at 4.0 × 10⁻⁶ during the deposition process. -4 Below Pa, the working gas is high-purity Ar, the flow rate is also set to 20 sccm, and the RF sputtering power is 20 W to obtain an amorphous thin film structure with uniform composition and dense surface; after deposition, the composition of the material is confirmed by energy dispersive spectroscopy (EDS).

[0043] S3. Finally, the TiN upper electrode layer was prepared using the same method and process parameters as the lower electrode layer (with different sputtering times to control the thickness). The thickness of the upper electrode layer was set to 40 nm. Figure 1 As shown in layer ③. This completes the process from the TiN lower electrode layer and Ag... 0.2 Se 0.8 A three-layer vertical structure gate unit consisting of a material layer and a TiN upper electrode layer.

[0044] Electrical performance tests were performed on the above-mentioned selector unit.

[0045] Figure 2 The image shows Ag with a thickness of 20 nm. 0.2 Se 0.8 The pulse response test curve of the selector unit. The test results show that the threshold voltage is approximately 1.65 V, the holding voltage is approximately 1.40 V, and the turn-on current is approximately 0.8 mA. Figure 2 The display shows that as the voltage gradually increases, the selector unit exhibits a distinct on-state behavior at approximately 1.65 V. Upon voltage removal, it quickly returns to a high-impedance state, demonstrating typical bidirectional threshold switching characteristics.

[0046] Figure 3 and Figure 4 Ag was displayed 0.2 Se 0.8 Switching speed test results of the selector unit. The tests show that Ag... 0.2 Se 0.8 The switching time of the gating transistor units is less than 15 ns, which meets the response speed requirements of high-speed memory arrays for gating devices.

[0047] Figure 5 , Figure 6 Ag was displayed 0.2 Se 0.8The gate unit can achieve self-gating by applying a specific pulse to obtain two different threshold voltages. The threshold voltages for the two states are 2.5 V and 3.0 V, respectively, with a storage window of 0.5 V.

[0048] In summary, AgSe-based gate transistors possess characteristics such as low leakage current, high gating ratio, fast response, and good durability, making them suitable for constructing novel high-density, low-power non-volatile memory arrays.

Claims

1. An AgSe gating tube material, characterized by, The chemical general formula of the AgSe gating tube material is Ag x Se y , wherein the value of x is 0.1≤x≤0.5, and the value of y is 0.5≤y≤0.

9.

2. The AgSe gating tube material of claim 1, wherein, The AgSe gating tube material is introduced with a doping element, including one or more of C, N, Si, In, P, Ag, Pt, Al, Ge, Zn, Ta, and W.

3. The AgSe gating tube material of claim 1, wherein, The AgSe gating tube material is a bidirectional threshold gating tube material.

4. The AgSe gating tube material of claim 1, wherein, When the AgSe gating tube material reaches a threshold voltage under the excitation of an electrical signal, it realizes an instantaneous transition of a high resistance state to a low resistance state, and after the voltage is removed, it returns to the high resistance state.

5. The AgSe gating tube material of claim 1, wherein, The switching time of the AgSe gating tube material is in the order of nanoseconds.

6. A gated-tube cell, characterized by, The gating tube unit comprises, from top to bottom, an upper electrode layer, an OTS material layer, and a lower electrode layer; the OTS material layer comprises the AgSe gating tube material according to claim 1.

7. A gate-tube unit according to claim 6, characterized in that The thickness of the upper electrode layer is 40-80 nm; the thickness of the OTS material layer is 5-20 nm; and the thickness of the lower electrode layer is 100-200 nm.

8. The gate-tube unit of claim 6, wherein, The material of the upper electrode layer and the lower electrode layer comprises one or more of Au, Ag, Pt, Cu, W, Al, Ni, and TiN.

9. The gate-tube unit of claim 6, wherein, The gating tube unit and the memory unit are integrated through a nano-interconnection structure; the memory unit comprises one or more of a phase change memory unit, a resistive random access memory unit, a magnetic memory unit, or a ferroelectric memory unit.

10. The gate-tube unit of claim 6, wherein, The gating tube unit and the memory unit form a three-dimensional cross-type array to realize high-density storage.

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