Method for preventing copper nodules from being formed on board-level packaging edge

Abstract

The invention discloses a method for preventing copper nodules from being formed at the edge of board-level packaging, which comprises the following steps of: forming a circle of ring with lateral erosion or undercutting, which protrudes upwards, at the edge of the top of a polyimide insulating layer by adopting a polyimide material in an exposure and over-development mode, and placing an electroplating clamp at the top of the polyimide insulating layer at the inner side of the ring for electroplating. According to the invention, through the arrangement of the ring protruding upwards, the seed layer is discontinuous in the sputtering process, so that current transmission is influenced; in addition, the exposure amount of the ring is reduced in the exposure process, so that the bottom of the ring is not sufficiently cured to form lateral erosion or undercutting under the attack of developing liquid, current transmission is further blocked, the electroplating clamp is arranged at the top of the polyimide insulating layer on the inner side of the ring for electroplating, and the ring is arranged to prevent the periphery of the electroplating clamp from conducting electricity so as not to grow copper nodules.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more particularly to a method for avoiding the formation of copper nodules at the edges of board-level packages. Background Technology

[0002] In chip packaging, during physical vapor deposition (PVD), the sealing structure of the CSS (Chip Scale Package Seal Ring) is designed to be located inside the PVD deposition surface. This prevents the formation of a complete seal from the metal seed layer (usually copper) around the sealing ring. This incomplete seal leads to abnormal accumulation of copper ions during the electroplating process, ultimately forming irregular copper protrusions, or "copper nodules," at the package edge. The existing electroplating fixture mounting positions are as follows: Figure 1-4 As shown.

[0003] The direct effects of copper nodules: (1) Electrical short circuit risk Adjacent line bridging: Copper abscesses may cross the insulation layer, causing short circuits in adjacent RDL lines or sealing rings.

[0004] High-frequency signal interference: In millimeter-wave packages (such as 5G RF modules), copper nodules can introduce parasitic capacitance, which degrades signal integrity.

[0005] (2) Mechanical reliability issues Stress concentration: Local stress in copper nodules leads to dielectric layer cracks (common in thermal cycling tests).

[0006] Interface delamination: The copper nodule does not match the CTE of the surrounding material, accelerating the EMC / PI interface delamination.

[0007] (3) Interference with subsequent processes Photolithography defects: Copper nodules cause uneven coating of photoresist (PR), resulting in exposure blind spots.

[0008] Poor soldering: In the Flip Chip process, copper nodules interfere with the coplanarity of the solder balls, causing cold solder joints.

[0009] Therefore, a method is needed to avoid the formation of copper nodules at the edges of board-level packages to solve the above problems. Summary of the Invention

[0010] The purpose of this invention is to design a method to avoid the formation of copper nodules at the edge of board-level packages in order to solve the above-mentioned problems.

[0011] The present invention achieves the above objectives through the following technical solutions: A method for avoiding the formation of copper nodules at the edge of a board-level package includes: forming an upwardly protruding ring with side etching or undercut at the top edge of a polyimide insulating layer using a polyimide material through exposure and overdevelopment, and performing electroplating on the top of the polyimide insulating layer inside the ring using an electroplating fixture.

[0012] Specifically, the exposure amount during the ring formation process is lower than that during the formation of the polyimide insulating layer.

[0013] Preferably, the exposure amount of the ring during the exposure formation process is 50% of the exposure amount used to form the polyimide insulating layer.

[0014] Preferably, the height of the ring is 5um-100um and the width is 0um-20um.

[0015] Preferably, the ring position is 0-14.5 mm from the edge of the glass substrate.

[0016] The beneficial effects of this invention are as follows: In this invention, the upward-protruding ring causes the seed layer to be discontinuous during sputtering, thus affecting current transmission. In addition, the ring reduces the exposure during exposure, resulting in insufficient curing at the bottom of the ring, which leads to side etching or undercutting under the attack of the developer, further blocking current transmission. The electroplating fixture is placed on top of the polyimide insulating layer inside the ring for electroplating. The ring prevents the electroplating fixture from conducting electricity, thus preventing the growth of copper nodules. Attached Figure Description

[0017] Figure 1 This is a schematic diagram (cross-section) of a pre-wiring, post-mount packaging structure. Figure 2 A top view of the wiring-before-mount packaging structure. Figure 3 This is a cross-sectional view of a pre-mounted and post-wiring package structure. Figure 4 A top view of the pre-mount, post-wiring packaging structure. Figure 5 This is a cross-sectional view of the ring structure in a pre-wiring, post-mount packaging structure. Figure 6 This is a cross-sectional view of the ring structure in a pre-wiring, post-mount packaging structure. Figure 7 This is a cross-sectional view of the ring structure in a pre-wiring, post-mount packaging structure. Figure 8 This is a top view of the ring structure in a pre-wiring, post-mount packaging structure. Figure 9 This is a schematic diagram illustrating the current direction during the electroplating process of a pre-wiring and post-mount packaging structure.

[0018] In the figure: 1-glass substrate; 2-rewiring layer; 3-adhesion layer; 4-epoxy molding compound; 5-polyimide insulating layer; 6-electroplation fixture; 7-seed layer; 8-ring. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the invention clearer, the technical solutions of the embodiments of the invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the invention, not all embodiments. The components of the embodiments of the invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of the invention, it should be understood that the terms "upper," "lower," "inner," "outer," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of the invention and to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention.

[0023] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0024] In the description of the invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in the invention according to the specific circumstances.

[0025] The specific embodiments of the invention will now be described in detail with reference to the accompanying drawings.

[0026] A method for avoiding copper nodules at the edge of a board-level package includes: forming an upwardly protruding ring 8 with side etching or undercutting at the top edge of a polyimide insulating layer 5 using a polyimide material through exposure and overdevelopment; and performing electroplating on the top of the polyimide insulating layer 5 inside the ring 8 using an electroplating fixture 6. The exposure amount of the ring 8 during exposure formation is 50% of the exposure amount used to form the polyimide insulating layer 5. The height of the ring 8 is 5µm-100µm, and the width is 0µm-20µm. The position of the ring 8 is 0-14.5mm from the edge of the glass substrate 1.

[0027] In some embodiments, such as Figure 5 and 6 As shown, this is a wiring-before-mount packaging structure. A redistribution layer 2 is formed above the glass substrate 1, followed by an adhesion layer 3. An epoxy molding compound 4 layer is formed above the adhesion layer 3. A polyimide insulating layer 5 is formed above the epoxy molding compound 4 layer. A ring 8 is located at the top edge of the polyimide insulating layer 5. A seed layer 7 is located on top of the polyimide insulating layer 5, ring 8, epoxy molding compound 4, redistribution layer 2, and the sidewall of the adhesion layer 3. An electroplating fixture 6 is placed on top of the polyimide insulating layer 5 inside the ring 8 for electroplating. The electroplating principle is as follows: current is conducted through the electroplating fixture 6, allowing the seed layer 7 (Ti & Cu layers) to acquire electrons and react with Cu in the electroplating solution. 2+ An electrochemical reaction occurs, and the ring 8 acts as a barrier to prevent the electroplating fixture 6 from conducting electricity, thus hindering the growth of copper nodules. In this embodiment, the width of the ring 8 is 0-5 μm.

[0028] In other embodiments, such as Figure 7-9 As shown, this is a pre-mount, post-wiring packaging structure. A redistribution layer 2 is formed above the glass substrate 1, and a polyimide insulating layer 5 is formed above the redistribution layer 2. A ring 8 is located at the top edge of the polyimide insulating layer 5. A seed layer 7 is located on top of the polyimide insulating layer 5 and the redistribution layer 2. An electroplating fixture 6 is placed inside the ring 8 on top of the polyimide insulating layer 5 for electroplating. The electroplating principle is as follows: current is conducted through the electroplating fixture 6, allowing the seed layer 7 (Ti & Cu layers) to acquire electrons and react with Cu in the electroplating solution. 2+ An electrochemical reaction occurs, and ring 8 deposits, which prevents the electroplating fixture 6 from conducting electricity, thus hindering the growth of copper nodules. In this embodiment, the width of ring 8 is 0µm-5µm. Figure 9 As shown, the direction of the current during electroplating is illustrated.

[0029] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for avoiding the formation of copper nodules at the edge of a board-level package, characterized in that, include: A ring with side etching or undercut is formed at the top edge of the polyimide insulating layer by exposure and over-development using polyimide material. The electroplating fixture is placed on top of the polyimide insulating layer inside the ring for electroplating.

2. The processing method according to claim 1 for avoiding copper nodules at the edge of board-level packages, characterized in that, The exposure amount during ring formation is lower than that during the formation of the polyimide insulating layer.

3. The processing method for avoiding copper nodules at the edge of a board-level package according to claim 2, characterized in that, The exposure amount during the ring formation process is 50% of the exposure amount used to form the polyimide insulating layer.

4. The processing method for avoiding the formation of copper nodules at the edge of a board-level package according to claim 1, wherein the height of the ring is 5um-100um and the width is 0um-20um.

5. The processing method for avoiding the formation of copper nodules at the edge of a board-level package according to claim 1, wherein the ring position is 0-14.5 mm from the edge of the glass substrate.

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