General PCB (Printed Circuit Board) health management method based on zero ohmic resistance time-varying information

Abstract

The invention discloses a PCB general health management method based on zero-ohmic resistor time-varying information, and the method comprises the steps: densely packaging a plurality of zero-ohmic resistors on a PCB, carrying out the reverse deduction of the stress damage condition of a PCB product through monitoring the change of the resistance value of the zero-ohmic resistors, recognizing the damage degree of the product in the whole process from the crack initiation period to a permanent fault, and carrying out the recognition of the damage degree of the product. The zero-ohm resistor is used as a circuit function element to be embedded in PCB wiring, non-intrusive monitoring is achieved, the installation cost of additional devices is avoided, continuous work can be started from the production stage, the whole service life cycle of the product is throughout, the limitation that a traditional strain gauge can only be used in a specific test stage is broken through, and the test efficiency is improved. The whole-course stress damage analysis from manufacturing, transportation to actual use is provided for the product, high-density point distribution can be achieved through the micro-packaged zero-ohm resistor, a data sampling set for whole-plate stress damage analysis is formed through multi-point data association analysis, and therefore the stress concentration area is accurately positioned, and compared with a traditional single-point measurement method, the method has the advantages that the measurement accuracy is high, and the measurement cost is low. And the monitoring precision and reliability are obviously improved.

Description

Technical Field

[0001] This invention belongs to the field of chip testing technology and relates to stress testing of PCB boards. Specifically, it is a general health management method for PCB boards based on time-varying information of zero ohmic resistance. Background Technology

[0002] During the production and testing process, PCB boards are subjected to varying degrees of stress. In recent years, the electronics industry has seen a significant increase in the use of lead-free solders instead of traditional tin-lead solders, leading to a surge in stress-induced soldering problems. Since component solder joints are highly sensitive to strain failure, the strain characteristics of PCB boards under harsh conditions are crucial. Excessive strain can lead to various failure modes depending on the solder alloy, package type, surface treatment, or laminate material. These failures include solder ball cracking, circuit damage, laminate-related adhesion failures (pad lifting) or cohesion failures (pad pitting), and package substrate cracking.

[0003] Therefore, stress-strain testing of PCBs is necessary during processes such as PCB depaneling, ICT testing, screw tightening, and drop testing in production. Strain measurement is used to control PCB warpage and identify and improve production operations (which carry a high risk of interconnect damage). Currently, the mainstream measurement method is strain gauge measurement, which has significant limitations: First, the application of strain gauges alters the local stiffness of the PCB, affecting measurement accuracy; second, it only provides single-point data, making it difficult to comprehensively reflect the stress distribution across the entire board; most importantly, this method cannot be applied to mass-produced PCB products and can only be used on experimental boards during the experimental stage, failing to enable continuous, regular monitoring and analysis of stress damage during the use of PCB products. Summary of the Invention

[0004] To address the technical problems existing in the background art, this invention proposes a general health management method for PCB boards based on time-varying information of zero-ohm resistance. By monitoring the change in the resistance value of zero-ohm resistance on the PCB board, the stress damage of the PCB board product can be inferred, thus realizing the monitoring of the entire product life cycle.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A general health management method for PCBs based on time-varying information of zero ohm resistance includes the following steps:

[0007] Step S1: Package one or more zero-ohm resistors in the vulnerable areas of the PCB board.

[0008] Step S2: Periodically detect the resistance value of the zero-ohm resistor and establish a database of correspondence between vulnerable areas and the resistance values ​​of zero-ohm resistors packaged in those areas.

[0009] Step S3: Analyze the stress damage degree of the vulnerable area of ​​the PCB board based on the resistance change of one or more zero-ohm resistors in the vulnerable area.

[0010] Furthermore, in step S1, the zero-ohm resistor package is directly embedded in the wiring of the PCB board as part of the PCB board circuit function, and is connected in series in the power supply or signal path of the circuit.

[0011] Furthermore, in step S1, the vulnerable areas of the zero-ohm resistor include: the four corner areas of the PCB board, the screw fixing hole areas where stress is concentrated, the solder joint area of ​​the BGA packaged chip, and the mounting area of ​​the power filter capacitor.

[0012] Furthermore, for the solder joint area of ​​the critical function of the BGA packaged chip, the surrounding area is used as multiple accompanying reference monitoring areas, and the average resistance of the zero-ohm resistance of the multiple reference monitoring areas is used as the equivalent evaluation resistance of the critical function solder joint area.

[0013] Furthermore, in step S3, a model is established to establish the correspondence between the zero-ohm resistance value of the vulnerable area of ​​the PCB board and the stress damage cracks in that area. The process and trend of crack propagation are characterized by the increasing zero-ohm resistance value, so as to analyze the stress damage degree of the vulnerable area of ​​the PCB board. Specifically:

[0014] When the resistance value R of the zero-ohm resistor is less than 1Ω, the analysis result output is that the vulnerable area is healthy.

[0015] When 1Ω≤R<10Ω, the analysis results show that the vulnerable area is in the stress damage initiation stage.

[0016] When 10Ω≤R<30Ω, the analysis results show that the vulnerable area is in the stress damage propagation stage.

[0017] When 30Ω≤R<100Ω, the analysis results show that the vulnerable area is in an intermittent failure period.

[0018] When 100Ω≤R<200Ω, the analysis results show that the vulnerable area is in a period of frequent failures.

[0019] When R≥200Ω, the analysis results output as permanent faults in the vulnerable area.

[0020] Furthermore, step S3 also includes predicting the crack propagation trend in vulnerable areas of the PCB board:

[0021] Based on the resistance change of the zero-ohm resistor and the detection cycle, calculate the resistance change rate dR / dt of the zero-ohm resistor in the vulnerable area of ​​the PCB board.

[0022] When dR / dt≥10Ω / cycle, a level 2 warning signal is issued, indicating abnormal stress damage to the PCB board, and an LSTM neural network is used to predict the failure probability of the vulnerable area in the next 72 hours.

[0023] Furthermore, step S3 also includes predicting the remaining lifetime of the vulnerable area, and using a modified Coffin-Manson model to calculate the stress cycle number N of the remaining lifetime of the vulnerable area. f :

[0024]

[0025] Where C is the material ductility coefficient, n is the fatigue index, and Δε p This represents the plastic strain amplitude.

[0026] Δε p =α(kR)+β;

[0027] Where α is the strain-resistance conversion coefficient, β is the temperature compensation term, and k is the calibration coefficient.

[0028] Furthermore, based on the predicted remaining lifespan of vulnerable areas on the PCB board, the periodic inspection cycle in step S2 is revised:

[0029] When N f When the value is ≥500, maintain the original testing cycle;

[0030] When 100≤N f When the value is less than 500, the detection cycle should be shortened to one-fifth of the original detection cycle.

[0031] When N f If the value is less than 100, a shutdown maintenance prompt will be displayed.

[0032] Furthermore, it also includes:

[0033] Step S4: Record the stress damage degree of each vulnerable area on the PCB board after periodic inspection, form a data sampling set for whole board stress damage analysis, and mark the damage degree of vulnerable areas with critical functions to conduct whole board safety risk assessment. When a permanent fault is detected in any vulnerable area on the PCB board, a first-level warning signal is issued and a shutdown protection mechanism is implemented.

[0034] Furthermore, it also includes:

[0035] Step S5: Based on the stress damage degree of multiple vulnerable areas on the PCB board, analyze the stress damage of the entire board, reconstruct the global stress field of the PCB board using the finite element interpolation algorithm, establish a three-dimensional stress distribution model of the PCB board, and output a visual heat map to identify high-risk areas of stress damage on the PCB board.

[0036] The beneficial effects of this invention are:

[0037] 1. Significantly reduce monitoring costs and complexity: By using zero-ohm resistors to replace traditional strain gauges, the need for dedicated sensors and complex signal conditioning circuits is eliminated, greatly simplifying the monitoring system structure. Since the zero-ohm resistor itself is embedded in the PCB wiring as a circuit functional component, non-invasive monitoring is achieved, and the installation cost of additional components is avoided, making it suitable for large-scale mass production applications.

[0038] 2. Enable continuous monitoring throughout the product lifecycle: By incorporating zero-ohm resistance packaging as an inherent component of the product, it can operate continuously from the production stage throughout the entire product lifecycle. This breaks through the limitation of traditional strain gauges, which can only be used in specific testing stages, and provides the product with the ability to track stress state throughout the entire process from manufacturing and transportation to actual use.

[0039] 3. Improved monitoring accuracy and reliability: The miniature packaged zero-ohm resistor can achieve high-density point distribution. Through multi-point data correlation analysis, it can accurately locate stress concentration areas, which is significantly better than the traditional single-point measurement method. Furthermore, the zero-ohm resistor using the four-wire Kelvin connection method can eliminate the influence of lead resistance. Combined with the temperature compensation algorithm, it can ensure the accuracy of resistance measurement.

[0040] 4. Intelligent early warning and prediction function: By establishing a precise correspondence model between resistance and stress damage level, it can identify the damage level throughout the entire process from crack initiation to permanent failure, realizing early anomaly detection and failure prediction.

[0041] 5. Overall Board Safety Risk Assessment: By analyzing the stress damage degree of multiple vulnerable areas on the PCB board, a data sampling set for overall board stress damage analysis is formed to analyze the stress damage situation of the entire board.

[0042] 6. Improve product quality and reliability: By recording historical data on the changes in stress damage in vulnerable areas, it is easier to analyze the root causes of failures, such as cumulative damage caused by vibration and thermal cycling, and to carry out timely maintenance and adjustments to extend the product's service life.

[0043] In summary, the method proposed in this application innovatively encapsulates multiple zero-ohm resistors densely on a PCB board. By monitoring the changes in the resistance value of the zero-ohm resistors and inferring the stress damage of the PCB board product based on the correspondence between the resistance value and cracks, the method achieves monitoring of the entire product lifecycle. This provides a new approach for the reliability assessment of high-density electronic packaging products and is of great significance for improving the quality control level of the entire electronics manufacturing industry. Attached Figure Description

[0044] Figure 1This is a schematic diagram of the process of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] like Figure 1 As shown, this invention provides a general health management method for PCB boards based on time-varying information of zero-ohm resistance. It utilizes a zero-ohm resistor instead of strain gauges in existing technologies, and monitors stress damage on the PCB board online by periodically detecting changes in the resistance of the zero-ohm resistor. The method specifically includes the following steps:

[0047] Step S1: Package one or more zero-ohm resistors in the vulnerable areas of the PCB board. First, because the cost of zero-ohm resistors is far lower than strain gauges, and no additional signal conditioning circuitry (such as a Wheatstone bridge) is required, the state of the vulnerable area can be determined by the change in resistance value of the zero-ohm resistor without disassembling the PCB board, greatly simplifying stress damage detection of the PCB board and making it suitable for online detection. Second, zero-ohm resistors can be directly embedded in the PCB board wiring during packaging, serving as part of the PCB board circuit function, connected in series in the power or signal path of the circuit. No complex bonding process is required, allowing real-time monitoring of the stress damage state of vulnerable areas throughout the entire lifecycle of the PCB board product (production, transportation, and use). Third, due to the small package size of zero-ohm resistors (such as 0402 and 0201), they have high space utilization and can be densely arranged in high-stress areas of the PCB board (such as around solder joints, connectors, and mounting holes) to achieve multi-point monitoring. By observing the resistance change trend of multiple zero-ohm resistors, specific broken solder joints or stress concentration areas on the PCB board can be accurately located, significantly superior to the single-point measurement of traditional strain gauges. Fourth, it enables PCB products to have dynamic early warning capabilities. By monitoring the trend of the resistance value of zero-ohm resistors in vulnerable areas from a small change (e.g., 0Ω→200Ω) to a complete open circuit (∞), fatigue risks in vulnerable areas can be predicted in advance. Fifth, zero-ohm resistors can eliminate the influence of lead resistance through the four-wire method (Kelvin connection), and parasitic parameters are controllable in high-frequency scenarios, effectively suppressing noise during the detection process. The resistance value change directly reflects the physical connection status and is not affected by temperature drift (combined with temperature compensation algorithms), exhibiting strong environmental adaptability. Sixth, zero-ohm resistors embedded in PCB circuits can also be used as debugging jumpers, ground isolation, or noise suppression components, achieving functional reuse beyond PCB stress damage monitoring.

[0048] Specifically, in step S1, the vulnerable areas of the zero-ohm resistor package include: the four corner areas of the PCB board, the screw fixing hole areas where stress is concentrated, the solder joint areas of the BGA packaged chip, and the mounting area of ​​the power supply filter capacitor. Of course, if there are sufficient BGA packaged chip resources, all solder joint areas on the PCB board can be monitored as vulnerable areas. For the solder joint areas of the critical functions of the BGA packaged chip, the surrounding areas are used as multiple accompanying reference monitoring areas, and the average resistance value of the zero-ohm resistors in the multiple reference monitoring areas is used as the equivalent evaluation resistance value of the critical function solder joint area. For the solder joint areas of the critical functions of the BGA packaged chip, a redundant monitoring design can also be adopted: multiple zero-ohm resistors are arranged in parallel along the stress path, and the weighted average value of each resistor is taken as the final monitoring value. By arranging zero-ohm resistors along multiple paths, the circuit function can still be maintained even in the event of partial failure, improving the system fault tolerance.

[0049] Step S2: Periodically check the resistance value of the zero-ohm resistor and establish a database of correspondence between vulnerable areas and the resistance values ​​of zero-ohm resistors packaged in those areas. Specifically, the resistance value of the zero-ohm resistor can be obtained using the method proposed in the applicant's previously filed invention patents "FPGA Solder Joint Fault Diagnosis Method and Device Based on Single Capacitor (Application No.: CN109932639B)" and "A High-Precision FPGA Solder Joint Fault Real-Time Diagnosis Method and Device (Application No.: CN109932640B)". In these patents, the N solder joint pins of the FPGA are replaced with N test points of the zero-ohm resistor on the PCB board of this application. The test points of the zero-ohm resistor are designed using vias or pads without solder paste. The specific testing steps are as follows:

[0050] Step S21: Connect each of the N test points Pin1 to PinN to an external capacitor;

[0051] Step S22: Set all N test points Pin1 to PinN to output a low level state to discharge the external capacitor;

[0052] Step S23: Set the test point PinE to output a high level, charge the external capacitor, and set all test points PinF to a high resistance state, where 1≤E<N and 1≤F≤N, F≠E, E+1.

[0053] Step S24: Use a high-frequency clock to sample the signal at test point Pin(E+1) and obtain the status of test point Pin(E+1) in real time.

[0054] Step S25: When the test point Pin(E+1) outputs a high level, the charging time of the external capacitor can be obtained by recording the number of cycles of the high-frequency clock, and then the zero-ohm resistance value corresponding to the test point PinE can be calculated.

[0055] Step S26: Set all N test points Pin1 to PinN to output a low level state again to discharge the external capacitor.

[0056] Step S27: Continuously set the value of E to E+1, and repeat steps S23 to S25 until E = N-1, to obtain the zero-ohm resistance values ​​corresponding to test points Pin1 to Pin(N-1).

[0057] Step S28: Set all N test points Pin1 to PinN to output a low level state again to discharge the external capacitor;

[0058] Step S29: Set the output of test point PinN to a high level, charge the external capacitor, and set all test points except Pin1 and PinN to a high resistance state. By sampling the signal of test point Pin1, obtain the zero-ohm resistance value corresponding to test point PinN.

[0059] Step S3: Analyze the stress damage degree of the vulnerable area of ​​the PCB board based on the resistance change of one or more zero-ohm resistors in the vulnerable area.

[0060] Specifically, in step S3, a model is established to correlate the zero-ohm resistance value of the vulnerable area of ​​the PCB board with the stress-induced cracks in that area. The process and trend of crack propagation are characterized by the increasing zero-ohm resistance value, thereby analyzing the degree of stress damage in the vulnerable area of ​​the PCB board. The model corresponding to the zero-ohm resistance value of the vulnerable area of ​​the PCB board with the stress-induced cracks in that area was determined through the following experiments:

[0061] First, electrical characteristic analysis is performed on the solder joints corresponding to the FPGA chip under test. An oscilloscope is used for detection and monitoring. An adjustable resistor is connected in series with a solder joint that appears to be well soldered to simulate the expansion and closure of cracks in the solder joint. The resistance value of the adjustable resistor is gradually increased, and the waveform of the oscilloscope is collected and viewed simultaneously. Intermittent signal anomalies can be clearly observed on the oscilloscope. The resistance value of the adjustable resistor at this time is the fault criterion for the electrical characteristics of the corresponding solder joint on the FPGA chip under test. The abnormal electrical signal is manifested as the critical point where the theoretical high level output changes to a low level. In this way, the detection basis for intermittent faults, frequent faults and permanent faults of this type of solder joint is found, and the corresponding solder joint resistance value is set as the critical value for each type of fault.

[0062] In specific experiments, based on the data obtained from multiple tests in Table 1, it can be determined that a critical point for the transition from a high level to a low level occurs when the adjustable resistor value reaches 200 ohms. Therefore, when a solder joint crack causes a zero-ohm resistance value to reach 200 ohms, it can be considered a permanent solder joint failure. When the adjustable resistor value is between 100 and 200 ohms, it can be considered a period of frequent solder joint failures. When the adjustable resistor value is between 30 and 100 ohms, it can be considered a period of intermittent solder joint failures. Of course, the specific defect severity and threshold of the solder joint can also be determined by the user through experiments based on different solder joint types.

[0063] Table 1. Resistance values ​​for different ranges (unit: Ω)

[0064]

[0065] In this embodiment, based on the experimental data in Table 1, the stress damage level analysis of the vulnerable areas of the PCB board is as follows:

[0066] When the resistance value R of the zero-ohm resistor is less than 1Ω, the analysis result output is that the vulnerable area is healthy.

[0067] When 1Ω≤R<10Ω, the analysis results show that the vulnerable area is in the stress damage initiation stage.

[0068] When 10Ω≤R<30Ω, the analysis results show that the vulnerable area is in the stress damage propagation stage.

[0069] When 30Ω≤R<100Ω, the analysis results show that the vulnerable area is in an intermittent failure period.

[0070] When 100Ω≤R<200Ω, the analysis results show that the vulnerable area is in a period of frequent failures.

[0071] When R≥200Ω, the analysis results output as permanent faults in the vulnerable area.

[0072] Step S3 also includes predicting the crack propagation trend in vulnerable areas of the PCB board:

[0073] Based on the resistance change of the zero-ohm resistor and the detection cycle, calculate the resistance change rate dR / dt of the zero-ohm resistor in the vulnerable area of ​​the PCB board.

[0074] When dR / dt≥10Ω / cycle, a level 2 warning signal is issued, indicating abnormal stress damage to the PCB board, and an LSTM neural network is used to predict the failure probability of the vulnerable area in the next 72 hours.

[0075] Step S3 also includes predicting the remaining lifetime of the vulnerable area, using a modified Coffin-Manson model to calculate the stress cycle number N of the remaining lifetime of the vulnerable area.f :

[0076]

[0077] Where C is the material ductility coefficient, n is the fatigue index, and Δε p This represents the plastic strain amplitude.

[0078] Δε p =α(kR)+β;

[0079] Where α is the strain-resistance conversion coefficient, β is the temperature compensation term, and k is the calibration coefficient.

[0080] Based on the predicted remaining lifespan of vulnerable areas on the PCB board, the periodic inspection cycle in step S2 is adjusted:

[0081] When N f When the value is ≥500, maintain the original testing cycle;

[0082] When 100≤N f When the value is less than 500, the detection cycle should be shortened to one-fifth of the original detection cycle.

[0083] When N f If the value is less than 100, a shutdown maintenance prompt will be displayed.

[0084] Step S4: Record the stress damage degree of each vulnerable area on the PCB board after periodic inspection, form a data sampling set for whole board stress damage analysis, and mark the damage degree of vulnerable areas with critical functions to conduct whole board safety risk assessment. When a permanent fault is detected in any vulnerable area on the PCB board, a first-level warning signal is issued and a shutdown protection mechanism is implemented.

[0085] Step S5: Based on the stress damage degree of multiple vulnerable areas on the PCB board, analyze the stress damage of the entire board, reconstruct the global stress field of the PCB board using the finite element interpolation algorithm, establish a three-dimensional stress distribution model of the PCB board, and output a visual heat map to identify high-risk areas of stress damage on the PCB board.

[0086] The above description is merely an example and illustration of the structure of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the structure of the invention or exceed the scope defined in the claims, all of which should fall within the protection scope of the present invention.

Claims

1. A general health management method for PCB boards based on time-varying information of zero ohmic resistance, characterized in that, Includes the following steps: Step S1: Package one or more zero-ohm resistors in the vulnerable areas of the PCB board. Step S2: Periodically detect the resistance value of the zero-ohm resistor and establish a database of correspondence between vulnerable areas and the resistance values ​​of zero-ohm resistors packaged in those areas. Step S3: Analyze the stress damage degree of the vulnerable area of ​​the PCB board based on the resistance change of one or more zero-ohm resistors in the vulnerable area.

2. The general health management method for PCB boards according to claim 1, characterized in that, In step S1, the zero-ohm resistor package is directly embedded in the wiring of the PCB board as part of the PCB board circuit function, and is connected in series in the power supply or signal path of the circuit.

3. The general health management method for PCB boards according to claim 2, characterized in that, In step S1, the vulnerable areas of the zero-ohm resistor include: the four corner areas of the PCB board, the screw fixing hole areas where stress is concentrated, the solder joint area of ​​the BGA packaged chip, and the mounting area of ​​the power filter capacitor.

4. The general health management method for PCB boards according to claim 3, characterized in that, For the solder joint area of ​​the critical function of the BGA packaged chip, the surrounding area is used as multiple accompanying reference monitoring areas, and the average resistance of the zero-ohm resistance of the multiple reference monitoring areas is used as the equivalent evaluation resistance of the critical function solder joint area.

5. The general health management method for PCB boards according to claim 1, characterized in that, In step S3, a model is established to correlate the zero-ohm resistance value of the vulnerable area of ​​the PCB board with the stress-induced cracks in that area. The process and trend of crack propagation are characterized by the increasing zero-ohm resistance value, thereby analyzing the degree of stress damage in the vulnerable area of ​​the PCB board. Specifically: When the resistance value R of the zero-ohm resistor is less than 1Ω, the analysis result output is that the vulnerable area is healthy. When 1Ω≤R<10Ω, the analysis results show that the vulnerable area is in the stress damage initiation stage. When 10Ω≤R<30Ω, the analysis results show that the vulnerable area is in the stress damage propagation stage. When 30Ω≤R<100Ω, the analysis results output that the vulnerable area is in an intermittent failure period; When 100Ω≤R<200Ω, the analysis results show that the vulnerable area is in a period of frequent failures. When R≥200Ω, the analysis results output as permanent faults in the vulnerable area.

6. The general health management method for PCB boards according to claim 5, characterized in that, Step S3 also includes predicting the crack propagation trend in vulnerable areas of the PCB board: Based on the resistance change of the zero-ohm resistor and the detection cycle, calculate the resistance change rate dR / dt of the zero-ohm resistor in the vulnerable area of ​​the PCB board. When dR / dt≥10Ω / cycle, a level 2 warning signal is issued, indicating abnormal stress damage to the PCB board, and an LSTM neural network is used to predict the failure probability of the vulnerable area in the next 72 hours.

7. The general health management method for PCB boards according to claim 5, characterized in that, Step S3 also includes predicting the remaining lifetime of the vulnerable area, and using a modified Coffin-Manson model to calculate the stress cycle number N of the remaining lifetime of the vulnerable area. f : Where C is the material ductility coefficient, n is the fatigue index, and Δε p This represents the plastic strain amplitude. No p =α(kR)+β; Where α is the strain-resistance conversion coefficient, β is the temperature compensation term, and k is the calibration coefficient.

8. The general health management method for PCB boards according to claim 7, characterized in that, Based on the predicted remaining lifespan of vulnerable areas on the PCB board, the periodic inspection cycle in step S2 is adjusted: When N f When the value is ≥500, maintain the original testing cycle; When 100≤N f When the value is less than 500, the detection cycle should be shortened to one-fifth of the original detection cycle. When N f If the value is less than 100, a shutdown maintenance prompt will be displayed.

9. The general health management method for PCB boards according to claim 5, characterized in that, Also includes: Step S4: Record the stress damage degree of each vulnerable area on the PCB board after periodic inspection, form a data sampling set for whole board stress damage analysis, and mark the damage degree of vulnerable areas with critical functions to conduct whole board safety risk assessment. When a permanent fault is detected in any vulnerable area on the PCB board, a first-level warning signal is issued and a shutdown protection mechanism is implemented.

10. The general health management method for PCB boards according to claim 9, characterized in that, Also includes: Step S5: Based on the stress damage degree of multiple vulnerable areas on the PCB board, analyze the stress damage of the entire board, reconstruct the global stress field of the PCB board using the finite element interpolation algorithm, establish a three-dimensional stress distribution model of the PCB board, and output a visual heat map to identify high-risk areas of stress damage on the PCB board.

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