Built-in self-test system

Abstract

The invention relates to a built-in self-test system. A built-in self-test (BIST) system for an electronic circuit is provided. The system comprises a test circuit device and a clock circuit. The test circuitry applies a test process to the electronic circuit. The clock circuit is configured to provide a clock signal to the test circuitry and adjust a clock frequency of the clock signal.

Description

Background Technology

[0001] This disclosure relates to a built-in self-test (BIST) system for electronic circuits.

[0002] Built-in Self-Test (BIST) is a process used by a device to test itself. The BIST process is typically applied during the device's startup phase to ensure that the device functions properly during normal operation.

[0003] BIST is commonly used in automotive applications and can ensure that the system complies with compliance standards, such as those related to the Automotive Safety Integrity Level (ASIL) classification system.

[0004] For example, during the power-on / start-up phase of a microcontroller unit (MCU) implemented within an automotive system, such as an anti-lock braking system (ABS) for automobiles, the BIST process is enforced to ensure that the device operates correctly in accordance with ASIL requirements. Summary of the Invention

[0005] The aim is to provide an improved built-in self-test system for electronic circuits.

[0006] According to a first aspect of this disclosure, a built-in self-test (BIST) system for electronic circuits is provided, the system including a test circuit device and a clock circuit, the test circuit device being used to apply a test process to the electronic circuit, and the clock circuit being configured to provide a clock signal to the test circuit device and adjust the clock frequency of the clock signal.

[0007] Optionally, the test circuit device is configured to apply a test process to the electronic circuit during the power-on phase.

[0008] Optionally, the test circuit device is a digital logic circuit.

[0009] Optionally, the BIST system is configured to be coupled to a power source.

[0010] Optionally, the power source includes a battery.

[0011] Alternatively, the electronic circuitry is configured to be coupled to a power source.

[0012] Alternatively, the BIST system and electronic circuitry are implemented in integrated circuits.

[0013] Alternatively, the integrated circuit is a microcontroller unit (MCU) or a system-on-a-chip (SoC).

[0014] Optionally, the BIST system is configured to operate in either a first mode or a second mode and switch between the first and second modes, wherein the clock circuit is configured to adjust the clock frequency of the clock signal to a first frequency value during the first mode and / or adjust the clock frequency of the clock signal to a second frequency value during the second mode.

[0015] Optionally, the first mode is a high-power mode, the second mode is a low-power mode, and the first frequency value is greater than the second frequency value.

[0016] Optionally, the clock circuit is configured to provide a clock signal with an initial frequency value before adjusting the clock frequency of the clock signal.

[0017] Optionally, the BIST system includes a memory element for storing an initial frequency value, wherein a clock circuit is configured to receive the initial frequency value from the memory element.

[0018] Optionally, the memory element includes a non-volatile memory element.

[0019] Alternatively, the non-volatile memory element is a flash memory that includes an option byte, and the initial frequency value is stored in the option byte.

[0020] Optionally, the clock circuit includes a frequency adjustment unit configured to: receive a clock signal from a clock signal generator, adjust the clock frequency of the clock signal received from the clock signal generator, and provide a clock signal with the adjusted clock frequency to the test circuit device.

[0021] Optionally, the frequency adjustment unit includes a prescaler.

[0022] Optionally, the clock circuit includes a clock signal generator.

[0023] Optionally, the electronic circuitry is configured to receive a clock signal from a clock signal generator.

[0024] According to a second aspect of this disclosure, an apparatus is provided comprising an electronic circuit and a built-in self-test (BIST) system for the electronic circuit, the BIST system including test circuitry for applying a test process to the electronic circuit and a clock circuit configured to provide a clock signal to the test circuitry and adjust the clock frequency of the clock signal provided to the test circuitry.

[0025] It should be understood that the apparatus of the second aspect may include any of the features listed in the first aspect, and may be combined with other features described herein.

[0026] According to a third aspect of this disclosure, a method is provided for performing a test process on an electronic circuit using a built-in self-test (BIST) system, the method comprising: applying a test process to the electronic circuit using a test circuit device, providing a clock signal to the test circuit device using a clock circuit, and adjusting the clock frequency of the clock signal provided to the test circuit device using the clock circuit.

[0027] It should be understood that the approach of the third aspect may include providing and / or using the features listed in the first and / or second aspects, and may be combined with other features described herein. Attached Figure Description

[0028] The present disclosure is described in more detail below with reference to examples and the accompanying drawings, in which:

[0029] Figure 1A This is a schematic diagram of a BIST system for electronic circuits according to a first embodiment of the present disclosure;

[0030] Figure 1B It is shown Figure 1A A timing diagram of an example clock signal during the first mode of example operation of a BIST system;

[0031] Figure 1C It is shown Figure 1A A timing diagram of an example clock signal during the second mode of example operation of a BIST system;

[0032] Figure 1D This is a schematic diagram of a specific embodiment of the BIST system and electronic circuit according to the second embodiment of the present disclosure;

[0033] Figure 1E This is a schematic diagram of a specific embodiment of the BIST system and electronic circuit according to the third embodiment of this disclosure;

[0034] Figure 2A This is a timing diagram showing the power supply current of a known BIST system as a function of time.

[0035] Figure 2B This is a timing diagram showing the current consumption of the actual implementation of the BIST system and electronic circuits;

[0036] Figure 3A This is a schematic diagram of a specific embodiment of a BIST system for electronic circuits according to the fourth embodiment of the present disclosure;

[0037] Figure 3B This is a schematic diagram of a specific embodiment of a BIST system for electronic circuits according to the fifth embodiment of the present disclosure;

[0038] Figure 4AThis is a schematic diagram of a specific embodiment of the BIST system according to the sixth embodiment of the present disclosure; and

[0039] Figure 4B This is a schematic diagram of another specific embodiment of the BIST system according to the seventh embodiment of the present disclosure. Detailed Implementation

[0040] Figure 1A This is a schematic diagram of a BIST system 100 for electronic circuit 102 according to a first embodiment of the present disclosure. The BIST system 100 includes a test circuit device 104. During operation, the test circuit device 104 applies a test process to the electronic circuit 102. It should be understood that the test process may be referred to as a "BIST process". The test circuit device 104 may be a digital logic circuit.

[0041] In a specific embodiment, the test circuit device 104 may apply the test process, for example, by providing a control signal 106 to the electronic circuit 102, which causes the electronic circuit 102 to perform a series of steps to verify that it is working properly.

[0042] In a specific embodiment, control signal 106 can provide instructions for electronic circuit 102 to execute a sequence of steps, wherein data required for executing the sequence of steps is stored in a memory element (not shown). The memory element can be an internal memory element of electronic circuit 102 or an external memory element of electronic circuit 102. In another embodiment, control signal 106 can include data related to the sequence of steps to be executed by electronic circuit 102.

[0043] In a specific embodiment, electronic circuit 102 can provide an indication of the status of the test process, which may include information about whether electronic circuit 102 has been evaluated as functioning correctly based on its performance during the test process. This indication can be provided to BIST system 100, which can respond differently based on whether the test process is successful or unsuccessful.

[0044] After the electronic circuit 102 is successfully evaluated as being in normal operation based on the test process, the electronic circuit 102 can continue to enter a new operation phase, such as an operation phase related to the normal operation of the electronic circuit 102.

[0045] The test circuit device 104 can be configured to apply the test process during the power-on phase. The power-on phase can occur between a low-power phase where the electronic circuit 102 is substantially inactive and an operational phase where the electronic circuit 102 is performing its normal operation. The power-on phase can be referred to as the startup phase. The low-power phase can be a phase where the electronic circuit 102 is supplied with minimum power or no power at all.

[0046] The BIST system 100 also includes a clock circuit 108 configured to provide a clock signal 110 to the test circuit device 104. The clock signal 110 can oscillate between a high and low state at a clock frequency, wherein the operation of the test circuit device 104 is synchronized with the clock frequency. The clock signal 110 can, for example, be a voltage signal having a square wave profile and a fixed duty cycle.

[0047] The clock circuit 108 is also configured to adjust the clock frequency of the clock signal 110.

[0048] BIST systems are known to operate at a fixed clock frequency, which results in a fixed execution time and fixed current consumption for the BIST process. For some applications, this fixed combination of time and current is a drawback, and such applications can benefit from shorter execution times or lower current consumption during the BIST process.

[0049] In embodiments of this disclosure, the clock frequency of clock signal 110 is adjustable, rather than fixed. Adjusting the clock frequency of clock signal 110 provided to test circuit device 104 provides a mechanism for adjusting the execution time and / or current consumption of the BIST process. It should be understood that the power consumption characteristics of the BIST process can be adjusted by regulating current consumption.

[0050] For example, certain applications can benefit from a fast BIST process, enabling electronic circuit 102 to quickly begin its normal operation. In such an example, the clock frequency of clock signal 110 can be increased, which will increase current consumption (and therefore power consumption), but can shorten the BIST process execution time.

[0051] In another example, a particular application can benefit from reduced power consumption during the BIST process. In such an example, the clock frequency of clock signal 110 can be reduced, which will reduce current consumption (and therefore power consumption), but will require a longer BIST process execution time.

[0052] Compared to known BIST systems, BIST system 100 offers greater flexibility in controlling power consumption characteristics. The flexibility to adjust the current consumption characteristics of BIST system 100, compared to known systems with fixed current consumption requirements, reduces the complexity of the power supply circuitry used in applications.

[0053] In a specific embodiment, the BIST system 100 can be configured to operate in a first mode or a second mode, and switch between the two modes. During the first mode, the clock circuit 108 adjusts the clock frequency of the clock signal 110 to a first frequency value, and / or during the second mode, the clock circuit 108 adjusts the clock frequency of the clock signal 110 to a second frequency value.

[0054] The clock circuit 108 can provide a clock signal 110 with an initial frequency value before adjusting the clock signal to a first frequency value or a second frequency value.

[0055] Figure 1B This is a timing diagram illustrating an example of the clock signal 110 during the first mode of example operation of the BIST system 100. Figure 1C This is a timing diagram illustrating an example of the clock signal 110 during a second mode of example operation of the BIST system 100. In this example, the first mode can be considered a high-power mode, and the second mode can be considered a low-power mode, wherein the first frequency value is greater than the second frequency value.

[0056] Figure 1D This is a schematic diagram of a specific embodiment of the BIST system 100 and electronic circuitry 102 according to a second embodiment of the present disclosure. In this embodiment, the BIST system 100 is configured to be coupled to a power source 112. During operation, the power source 112 provides power to the BIST system 100. The BIST system 100 and electronic circuitry 102 may share the same power source 112. The power source 112 may include a battery 114.

[0057] In this embodiment, the BIST system 100 includes a memory element 116 for storing an initial frequency value. During operation, the clock circuit 108 can receive the initial frequency value from the memory element 116 and then set the clock frequency of the clock signal 110 to the initial frequency value before adjustment. A first frequency value and / or a second frequency value may also be stored in the memory element 116 and provided to the clock circuit 108 to adjust the clock signal 110.

[0058] Memory element 116 may include non-volatile memory (NVM) element 118. NVM element 118 may be flash memory including option bytes, and an initial frequency value may be stored in the option bytes.

[0059] Figure 1E This is a schematic diagram of a specific embodiment of the BIST system 100 and electronic circuit 102 according to a third embodiment of the present disclosure. In this embodiment, the BIST system 100 and electronic circuit 102 are implemented in an integrated circuit 120. The BIST system 100 and electronic circuit 102 together form a "device" that undergoes the BIST process as part of the operation of the integrated circuit 120. The integrated circuit 120 may be a microcontroller unit (MCU) or a system-on-a-chip (SoC).

[0060] It should be understood that, in another embodiment, the BIST system 100 may include a memory element 116, for example, as per [reference to...]. Figure 1D As stated above.

[0061] It should be understood that, in another embodiment, integrated circuit 120 may be coupled to a power source for supplying power to one or both of the BIST system 100 and electronic circuitry 102, for example, as... Figure 1D The power supply 112 is shown.

[0062] Figure 2A This is a timing diagram 200 (shown by trace 202) illustrating the power supply current versus time for a practical implementation of a known BIST system. The known BIST system uses a clock signal with a fixed clock frequency. The power supply current is the current supplied to the entire device, which includes the BIST system and the electronic circuitry undergoing testing before normal operation.

[0063] Before time t1, the BIST system and electronic circuits are in a low-power state or off state. At time t1, the BIST system and electronic circuits enter the startup phase, and the power supply current rises to I. BIST It indicates the current consumption during the BIST process. The duration T of the BIST process... BIST Until time t2, the power supply current increases further, and the circuit begins to operate normally.

[0064] Figure 2B This is timing diagram 204 showing the current consumption of the actual implementation of the BIST system 100 and electronic circuit 102. The following description will refer to... Figure 1A The BIST system 100 and electronic circuit 102 shown herein, however, should be understood that actual implementations of any of the embodiments described herein may exhibit characteristics such as Figure 2B The current consumption characteristics are shown.

[0065] Trace 206 shows the supply current over time in high-power mode, and trace 208 shows the supply current over time in low-power mode. Trace 202 shows... Figure 2A The power supply current is shown and provided for reference.

[0066] Referring to the high-power mode, as shown by trace 206, before time t1, the BIST system 100 and electronic circuit 102 are in a low-power state or a shutdown state. At time t1, the BIST system 100 and electronic circuit 102 enter the startup phase, and the supply current rises to I. BIST"A” It indicates the current consumption during the high-power mode BIST process. The duration T of the BIST process... BIST"A” Until time t2A, the power supply current decreases, and circuit 102 begins to operate normally.

[0067] High-power mode is suitable for applications requiring short startup times and fast response times to quickly respond to external signals. Figure 2A Compared to the example shown, the increase in clock frequency indicates that BIST executes faster, and the test circuit device 104 can start operating normally and therefore react more quickly.

[0068] Referring to the low-power mode, as shown by trace 208, before time t1, the BIST system 100 and electronic circuit 102 are in a low-power state or a shutdown state. At time t1, the BIST system 100 and electronic circuit 102 enter the startup phase, and the supply current rises to I. BIST"B” It indicates the current consumption during the low-power mode BIST process. The duration T of the BIST process... BIST"B” Until time t2B, the power supply current increases, and circuit 102 begins to operate normally.

[0069] Low-power mode is suitable for applications requiring low current consumption and is achieved by reducing the clock frequency, and... Figure 2A This results in lower current consumption compared to the example shown.

[0070] Figure 3A This is a schematic diagram of a specific embodiment of a BIST system 100 for electronic circuit 102 according to a fourth embodiment of the present disclosure. In this embodiment, a specific implementation of clock circuit 108 is shown. As will be understood by those skilled in the art, the specific implementation of clock circuit 108 in this embodiment can be used with any of the embodiments described herein.

[0071] In this embodiment, the clock circuit 108 includes a frequency adjustment unit 300 configured to receive a clock signal 110 from the clock generator 302.

[0072] The frequency adjustment unit 300 then adjusts the clock frequency of the clock signal 110, and after adjustment, provides the clock signal 110 to the test circuit device 104.

[0073] The clock generator 302 can provide an unregulated clock signal 110 to the electronic circuit 102.

[0074] The frequency adjustment unit 300 may include a prescaler 304 for adjusting the clock frequency of the clock signal 110, thereby controlling the power / frequency consumption characteristics of the BIST system 100. The prescaler 304 may be referred to as a frequency divider and is a known circuit component for reducing the frequency of the received signal.

[0075] In one specific example, prescaler 304 may reduce the clock frequency of clock signal 110 during high-power mode and further reduce the clock frequency of clock signal 110 during low-power mode. In another embodiment, prescaler 304 may not perform the frequency reduction operation in high-power mode and simply pass clock signal 110, wherein the frequency reduction operation is performed by prescaler 304 during low-power mode.

[0076] Figure 3B This is a schematic diagram of a specific embodiment of a BIST system 100 for electronic circuit 102 according to a fifth embodiment of the present disclosure. In this embodiment, the clock circuit 108 includes a clock generator 302.

[0077] Figure 4A This is a schematic diagram of a specific embodiment of a BIST system 100 for electronic circuit 102 (not shown) according to the sixth embodiment of the present disclosure.

[0078] In this embodiment, the BIST system 100 also includes a central processing unit (CPU) block 400 and an "other IP" block 402; the clock circuit 108 includes a clock selector 404 and reset logic 406 configured to receive a reset signal, the clock selector 404 including multiple frequency outputs; the memory element 116 includes a flash memory cell 408 and a RAM memory cell 410; and the clock generator 302 is coupled to a crystal oscillator 412.

[0079] During operation of the BIST system 100 in this embodiment, an adjustable frequency, controlled by a prescaler 304, is provided for the power clock of the BIST. This provides options for adjusting the power current or execution time as needed by the application. The initial value of the frequency can be defined via option bytes stored in flash memory or NVM (“non-volatile memory”).

[0080] Figure 4B This is a schematic diagram of a specific embodiment of a BIST system 100 for electronic circuit 102 (not shown) according to a seventh embodiment of the present disclosure. In this example, specific embodiments of a clock generator 302 and a prescaler 304 are shown.

[0081] Clock generator 302 may include a selector 414 for a master clock; one or more clock dividers 416 and / or one or more PLL circuits 418; and one or more internal oscillators 420 and / or one or more external oscillators 422.

[0082] The prescaler 304 may include a clock divider 422 configured to divide the master clock by a fraction of the master clock frequency. The master clock frequency originates from the clock generator 302. The prescaler 304 may also include a selector 424 configured to select a desired frequency from the clock divider 422 and provide it to the test circuit device 104. The selector 424 may be controlled by an "option byte" stored in the flash memory cell 408 prior to a "system reset".

[0083] In summary, the embodiments of this disclosure can be used in MCU or SoC products that have a BIST process performed during the power-on / boot phase. Typically, applications with ASIL standards require BIST to be performed during power-on / boot to ensure proper operation.

[0084] Embodiments of this disclosure can be used to control the current / power consumption characteristics of a device using the BIST process. As provided by the embodiments described herein, introducing an adjustable frequency for the power supply clock of the BIST can allow adjustment of the power supply current or execution time to meet the needs of a specific application.

[0085] Because power requirements can be controlled, using an adjustable clock frequency for BIST execution offers more options for power supply design compared to systems using a fixed-frequency clock. Specifically, it simplifies power supply circuit design compared to known systems, and thus reduces design time, testing time, and cost.

[0086] Common reference numerals and variables among the figures indicate common features.

[0087] Various improvements and modifications may be made to the above content without departing from the scope of this disclosure.

Claims

1. A built-in self-test BIST system for electronic circuits, comprising: A test circuit apparatus for applying a test process to the electronic circuit; as well as The clock circuit is configured as follows: Provide a clock signal to the test circuit device; as well as Adjust the clock frequency of the clock signal.

2. The BIST system of claim 1, wherein the test circuit device is configured to apply the test process to the electronic circuit during the power-on phase.

3. The BIST system according to claim 1, wherein the test circuit device is a digital logic circuit.

4. The BIST system of claim 1, wherein the BIST system is configured to be coupled to a power source.

5. The BIST system of claim 4, wherein the power source comprises a battery.

6. The BIST system of claim 4, wherein the electronic circuitry is configured to be coupled to the power source.

7. The BIST system of claim 1, wherein the BIST system and the electronic circuit are implemented in an integrated circuit.

8. The BIST system of claim 7, wherein the integrated circuit is a microcontroller unit (MCU) or a system-on-a-chip (SoC).

9. The BIST system of claim 1, wherein the BIST system is configured to: It can operate in either the first or second mode; and Switch between the first mode and the second mode; in: The clock circuit is configured as follows: During the first mode, the clock frequency of the clock signal is adjusted to a first frequency value; and / or During the second mode, the clock frequency of the clock signal is adjusted to a second frequency value.

10. The BIST system according to claim 9, wherein: The first mode is the high-power mode; The second mode is a low-power mode; and The first frequency value is greater than the second frequency value.

11. The BIST system of claim 9, wherein the clock circuit is configured to provide the clock signal having an initial frequency value before adjusting the clock frequency of the clock signal.

12. The BIST system of claim 11, further comprising a memory element for storing the initial frequency value, wherein the clock circuit is configured to receive the initial frequency value from the memory element.

13. The BIST system of claim 12, wherein the memory element comprises a non-volatile memory element.

14. The BIST system according to claim 13, wherein: The non-volatile memory element is a flash memory that includes option bytes; and The initial frequency value is stored in the option byte.

15. The BIST system of claim 1, wherein the clock circuit includes a frequency adjustment unit, the frequency adjustment unit being configured to: Receive the clock signal from the clock signal generator; Adjust the clock frequency of the clock signal received from the clock signal generator; as well as The test circuit device is provided with a clock signal having the adjusted clock frequency.

16. The BIST system of claim 15, wherein the frequency adjustment unit includes a prescaler.

17. The BIST system of claim 15, wherein the clock circuit includes the clock signal generator.

18. The BIST system of claim 15, wherein the electronic circuitry is configured to receive the clock signal from the clock signal generator.

19. An apparatus comprising: Electronic circuits; as well as A built-in self-test BIST system for the electronic circuit, the BIST system comprising: Test circuit apparatus for applying a test process to the electronic circuit; and The clock circuit is configured as follows: Provide a clock signal to the test circuit device; and Adjust the clock frequency of the clock signal provided to the test circuit device.

20. A method for performing a test procedure on an electronic circuit using a built-in self-test BIST system, the method comprising: The electronic circuit is tested using a test circuit device. A clock circuit is used to provide a clock signal to the test circuit device; as well as The clock frequency of the clock signal provided to the test circuit device is adjusted using the clock circuit.

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