Optical interconnection device, light quantum computer, photon chip device and preparation method thereof

Abstract

The embodiment of the invention provides an optical interconnection device, an optical quantum computer, a photon chip device and a preparation method of the photon chip device. The photon chip device comprises a base body and a plurality of photon chips. The base body is provided with a first connecting hole array and a second connecting hole array, the first connecting hole array is located on the first side face of the base body and provided with a plurality of first ports located on the first side face, and the second connecting hole array is located on the second side face of the base body and provided with a plurality of second ports located on the second side face. The plurality of photon chips are arranged in the base body, each photon chip is provided with a first end face and a second end face, the first end face is communicated with each first port in the plurality of first ports, each first optical fiber in the first optical fiber array is connected with the first end face, the second end face is communicated with each second port in the plurality of second ports, and the first optical fiber array is connected with the second optical fiber array. Each second optical fiber in the second optical fiber array is connected with the second end face.

Description

Technical Field

[0001] This application relates to the field of optical communication technology, and in particular to an optical interconnect device, an optical quantum computer and a photonic chip device and a method for fabricating the same. Background Technology

[0002] Photonic chips are hailed as the next-generation engine of the information age, with enormous potential in data processing speed and energy efficiency. Their emergence provides our world with a brand-new and more powerful "information superhighway".

[0003] A photonic chip is a microchip that uses light (laser) to replace or assist electrical signals for information transmission, processing, and computation. Since the carrier of information is photons, information can be represented by the presence or absence of photons, as well as the intensity, phase, and wavelength of light. Moreover, photonic chips have multiple disruptive advantages such as high transmission rate, large bandwidth, and low power consumption, enabling a comprehensive "light-speed upgrade" of the entire society's information infrastructure.

[0004] Photonic chips are typically nanometers in size, while the external world (usually optical fibers) is typically micrometers in size. During the connection process between the photonic chip and the external optical fiber, this size difference not only causes mode field mismatch but also directly leads to very high insertion loss. Furthermore, the alignment process between the traditional optical fiber core and the three-dimensional photonic chip requires sub-micrometer precision adjustments in six degrees of freedom, a process that is extremely time-consuming, labor-intensive, and reliant on expensive active alignment equipment. Summary of the Invention

[0005] In view of this, this application provides an optical interconnect device, an optical quantum computer, and a photonic chip device and its fabrication method, aiming to solve to some extent the problems of large insertion loss, mode field mismatch, and complex connection process in the current process of connecting three-dimensional photonic chips with external optical fibers.

[0006] In a first aspect, one embodiment of this application provides a photonic chip device, which includes a substrate and a plurality of photonic chips. The substrate has a first connection hole array and a second connection hole array. The first connection hole array is located on a first side of the substrate and has a plurality of first ports located on the first side. The second connection hole array is located on a second side of the substrate and has a plurality of second ports located on the second side. The plurality of photonic chips are disposed inside the substrate. Each of the plurality of photonic chips has a first end face and a second end face. The first end face communicates with each of the plurality of first ports to connect each of the first optical fibers in a first optical fiber array to the first end face. The second end face communicates with each of the plurality of second ports to connect each of the second optical fibers in a second optical fiber array to the second end face.

[0007] Secondly, an embodiment of this application also provides an optical interconnect device, which includes a photonic chip device, a first fiber array, a second fiber array, and a package housing, wherein the photonic chip device is disposed in the internal cavity of the package housing.

[0008] Secondly, one embodiment of this application also provides an optical quantum computer, which includes a single-photon source, an optical quantum chip, and a single-photon detector, wherein one or more of the single-photon source, optical quantum chip, and single-photon detector include the optical interconnect device described above.

[0009] Fourthly, one embodiment of this application also provides a method for fabricating a photonic chip device, comprising providing a substrate; forming a first connection hole array on a first side of the substrate and a second connection hole array on a second side of the substrate, the first connection hole array having a plurality of first ports located on the first side and the second connection hole array having a plurality of second ports located on the second side; forming a plurality of photonic chips inside the substrate, each of the plurality of photonic chips having a first end face and a second end face, the first end face communicating with each of the plurality of first ports to connect each of the first optical fibers in a first optical fiber array to the first end face, and the second end face communicating with each of the plurality of second ports to connect each of the second optical fibers in a second optical fiber array to the second end face.

[0010] By embedding multiple photonic chips within a substrate, both ends of these chips can be directly connected to a second fiber array (such as a single-core fiber) and a first fiber array (multi-core fiber). This allows for accurate connection between the multiple photonic chips and external fibers simply by inserting the external fiber into either the first or second connection hole, eliminating the need for expensive active alignment equipment. This not only improves alignment accuracy but also reduces the manufacturing and installation difficulty of the photonic chips and external fibers, shortening installation time. Furthermore, the external first and second fiber arrays can be inserted into the first and second connection hole arrays simultaneously, facilitating mass production.

[0011] Moreover, by flexibly designing the dimensions of the first and second connector arrays, it is beneficial to achieve precise correspondence between the first fiber array and the first connector array, the second fiber array and the second connector array, thereby helping to reduce insertion loss and solve problems such as mode field mismatch.

[0012] Furthermore, this photonic chip device essentially uses multiple photonic chips themselves as optical information processing and connection units, only needing to collect and distribute optical signals, which helps reduce transmission losses. Moreover, this built-in structure helps protect the photonic chips from external interference and also improves their reliability. Attached Figure Description

[0013] It should be understood that the following figures only illustrate certain embodiments of this application and should not be construed as limiting the scope.

[0014] It should be understood that the same or similar reference numerals are used in the accompanying drawings to denote the same or similar elements.

[0015] It should be understood that the accompanying drawings are only schematic, and the dimensions and scales of the elements in the drawings are not necessarily precise.

[0016] Figure 1 This is a schematic diagram of the structure of a photonic chip device provided in an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of the second side of a photonic chip device according to an embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the first side of a photonic chip device provided in an embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the first side of a photonic chip device provided in an embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the structure of a photonic chip device provided in an embodiment of this application.

[0021] Figure 6 for Figure 5 A schematic diagram of the provided photonic chip device from another perspective.

[0022] Figure 7 This is a schematic diagram of the structure of a first fiber optic array provided in an embodiment of this application.

[0023] Figure 8 This is a schematic diagram showing the connection between a photonic chip device and a second optical fiber, according to an embodiment of this application.

[0024] Figure 9 This is a schematic diagram showing the connection between a photonic chip device and a first fiber optic array according to an embodiment of this application.

[0025] Figure 10 This is a schematic diagram showing the connection between a photonic chip device provided in an embodiment of this application and a first fiber array and a second fiber array.

[0026] Figure 11 This is a schematic diagram showing the connection between a photonic chip device provided in an embodiment of this application and a first fiber array and a second fiber.

[0027] Figure 12 This is a schematic diagram of the structure of an optical interconnect device provided in an embodiment of this application.

[0028] Figure 13 This is a schematic diagram of the structure of an optical quantum computer provided in an embodiment of this application.

[0029] Figure 14 A flowchart illustrating a method for fabricating a photonic chip device according to an embodiment of this application. Detailed Implementation

[0030] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that there are various ways to implement this application, and it should not be construed as being limited to the embodiments described herein. The embodiments described herein are only for a more thorough and clear understanding of this application.

[0031] Application Overview: With the development of technology, data center traffic has experienced explosive growth, creating an urgent need for bandwidth in data center interconnects. Data center interconnects and cabling are two core components supporting the efficient operation of modern data centers.

[0032] Data center interconnection primarily enables geographically dispersed data centers to work collaboratively as a unified whole, facilitating communication, data synchronization, and load balancing between them. This is mainly reflected in technologies such as multi-layered collaborative interconnection, high-speed optical interconnection, and co-packaged optics (CPO). Its development trends include high speed, high density, low latency, low cost, and ease of maintenance. Cabling is the "vascular system" of a data center, addressing the physical connections between devices within a single data center. Its development trends include single-mode replacing multi-mode, multi-core replacing single-core, and Consortium for On-Board Optics (COBO) / Co-Packaged Optics (CPO) replacing hot-swappable cabling. Specifically, single-mode fiber, with its long-distance transmission capability and high bandwidth potential, meets the needs of interconnection across racks and data centers; multi-core fiber, while significantly increasing cable size, directly increases the fiber capacity several times, greatly satisfying the needs of high density, high integration, and low cost; CPO can co-package optical engines with professional integrated circuits (such as switch chips) on the same substrate, thereby shortening the distance of electrical channels, reducing power consumption, and achieving higher port density; COBO, as an intermediate solution, allows optical modules to be fixed inside the device to increase density and optimize heat dissipation.

[0033] However, data center interconnection and cabling still rely on traditional optical fibers (including single-mode, multi-mode, and multi-core optical fibers) and copper cables. As a result, when facing future computing power demands, challenges such as bandwidth density bottlenecks, power consumption crises, high-frequency signal distortion, and high operation and maintenance complexity will be encountered.

[0034] A three-dimensional photonic chip is a miniature optical path channel fabricated on a chip substrate (such as silicon or glass) using micro- and nano-fabrication techniques (such as photolithography and etching). It allows optical signals to be guided, split, coupled, and routed in three-dimensional space, and is considered one of the key technological paths to address this crisis, possessing enormous potential. Three-dimensional photonic chips have the following advantages: 1. Increased bandwidth: By stacking multiple waveguides in the Z-axis direction, the number of connection channels per unit projected area can be increased by orders of magnitude. By utilizing the entire chip area and even the vertical dimension for wiring and crossing, the bottleneck of bandwidth density can be broken.

[0035] 2. Reduced Power Consumption: Three-dimensional photonic chips can directly guide optical signals to various receiving points on the surface of the ASIC chip, achieving ideal interconnection between co-packaged optics and near-packaged optics, eliminating long-distance high-speed PCB traces. This allows electrical signals to be transmitted over millimeter-level distances, significantly reducing losses and power consumption, and even avoiding the use of high-power serializers / deserializers (SerDes).

[0036] 3. Avoiding the problem of high-frequency electrical signal integrity: Since the loss of optical signals is not sensitive to frequency when they are transmitted in waveguides, three-dimensional photonic chips are used inside the chip package to replace high-frequency PCB traces to transmit signals, which solves the signal integrity problems such as attenuation, crosstalk and impedance matching faced by high-speed electrical signals.

[0037] 4. Enhanced Reliability and Ease of Maintenance: 3D photonic chips can integrate numerous discrete optical paths that previously required fiber optic patch cords into a single, fixed photonic chip, thereby reducing the number of external connection points. Fewer external fibers are needed for aggregation, thus reducing maintenance complexity and improving long-term reliability.

[0038] Furthermore, as an information "processing center" or "exchange center," the information processed by the three-dimensional photonic chip needs to be transmitted over optical fibers to reach distant locations. Therefore, connecting to standard optical fibers is a crucial way for photonic chips to integrate into global information networks.

[0039] Due to the huge size difference between nanoscale three-dimensional photonic chip arrays and the micrometer-scale core diameter of standard fiber arrays, direct coupling of micrometer-scale fiber modes with nanoscale photonic chips results in severe light energy leakage and significant losses. Furthermore, traditional methods require each fiber array to be independently aligned to submicrometer precision in six dimensions, a process that is extremely cumbersome, time-consuming, and expensive.

[0040] To overcome the above problems, refer to Figures 1 to 14This application provides a photonic chip device 100, an optical interconnect device 200, an optical quantum computer 300, and a method for fabricating the photonic chip device 100. By utilizing fast coupling fan-out technology, multiple photonic chips and external optical fibers can be connected quickly and accurately. This not only helps to reduce the loss of the connection between the three-dimensional photonic chip and the external optical fiber, but also solves the problem of mode field mismatch.

[0041] Exemplary optical waveguide device: refer to Figures 1 to 10 An embodiment of this application provides a photonic chip device 100 that may include a substrate 110 and a plurality of photonic chips 120. The substrate 110 has a first connection hole array 1310 and a second connection hole array 1320. The first connection hole array 1310 is located on a first side 131 of the substrate 110 and has a plurality of first ports 1311 located on the first side 131. The second connection hole array 1320 is located on a second side 132 of the substrate 110 and has a plurality of second ports 1321 located on the second side 132.

[0042] The substrate 110 can be made of glass, such as ordinary glass or quartz glass. Preferably, the substrate 110 is prepared from quartz glass. Of course, the substrate 110 can also be made of transparent rigid plastic or rigid polymer, such as polymethyl methacrylate, polycarbonate or cyclic olefin polymer, without being specifically limited here.

[0043] Multiple photonic chips 120 are disposed inside the substrate 110. Each photonic chip 121 in the multiple photonic chips 120 has a first end face 1211 and a second end face 1212. The first end face 1211 is connected to each of the multiple first ports 1311 so that each first optical fiber 141 in the first optical fiber array 140 is connected to the first end face 1211. The second end face 1212 is connected to each of the multiple second ports 1321 so that each second optical fiber 151 in the second optical fiber array 150 is connected to the second end face 1212.

[0044] In other words, in addition to housing multiple photonic chips 120, the quartz glass substrate also has connection hole arrays located on two sides. The first connection hole array 1310 communicates with multiple first end faces 1211 of the photonic chips 120, allowing the first fiber array 140 to pass through the first connection hole array 1310 and connect to each of the first end faces 1211. Similarly, the second connection hole array 1320 communicates with multiple second end faces 1212 of the photonic chips 120, allowing the second fiber array 150 to pass through the second connection hole array 1320 and connect to each of the second end faces 1212 of the photonic chips 120. In other words, the first fiber array 140 is inserted into the first through hole array 1310, and the second fiber array 150 is inserted into the second through hole array 1320, thereby achieving the connection between the first fiber array 140 and the first end faces 1211 of the photonic chips 120, and the connection between the second fiber array 150 and the second end faces 1212 of the photonic chips 120.

[0045] By embedding multiple photonic chips 120 in the substrate 110, both ends of the multiple photonic chips 120 can be directly connected to the second fiber array 150 (such as a single-core fiber) and the first fiber array 140 (multi-core fiber). In this way, the connection between the multiple photonic chips and the external fiber only requires the external fiber to be inserted into the first or second connection hole to achieve accurate connection, without the need for expensive active alignment equipment. This not only helps to improve alignment accuracy, but also helps to reduce the manufacturing and installation difficulty of the photonic chips and the external fiber, and reduce installation time. Moreover, the external first fiber array and second fiber array can be inserted into the first connection hole array and the second connection hole array at the same time, which is beneficial for mass production.

[0046] Moreover, by flexibly designing the dimensions of the first and second connector arrays, it is beneficial to achieve precise correspondence between the first fiber array and the first connector array, the second fiber array and the second connector array, thereby helping to reduce insertion loss and solve the problem of mode field mismatch.

[0047] Furthermore, this photonic chip device essentially uses multiple photonic chips themselves as optical information processing and connection units, only needing to collect and distribute optical signals, which helps reduce transmission losses. Moreover, this built-in structure helps protect the photonic chips from external interference and also improves their reliability.

[0048] It should be noted that the first fiber array 140 may include multiple independent optical fibers, and each first optical fiber in the first fiber array 140 can be a standard optical fiber or other common optical fibers. Each optical fiber 151 in the second fiber array 150 can also be a single-core optical fiber. Moreover, the size, arrangement order, and quantity of the first fiber array 140 and the second fiber array 150 can be flexibly designed according to the type and precision of the transmitted data. For example, the arrangement structure of the first fiber array 140 can be rectangular, ring, circular, etc., and the arrangement order of the second fiber array 150 can be rectangular, ring, circular, etc.

[0049] Preferably, refer to Figure 2 and Figure 3 The size b of each first connector 1311 in the first connector array 1310 matches the size of the core of each first optical fiber 141, and the size a of each second connector 1321 in the second connector array 1321 matches the size of the core of each second optical fiber 151.

[0050] It is understandable that this photonic chip device only needs to design the size of the first connection hole 1311 according to the size of the first optical fiber 141, and the size of the second connection hole 1321 according to the size of the second optical fiber 151. The first optical fiber 141 and the second optical fiber 151 can then pass through the first connection hole 1311 and the second connection hole 1321 respectively, and connect to the first end face 1211 and the second end face 1212 of the multiple photonic chips 120 respectively. This avoids the problem of large connection loss caused by the large size difference between nanoscale three-dimensional photonic chips and micron-scale optical fibers. This helps to reduce the transmission loss of optical signals through micron-scale ordinary optical fibers and nanoscale photonic chips, improve the signal-to-noise ratio, and reduce power consumption.

[0051] Since only the size of each first through-hole 1311 in the first through-hole array 1310 needs to match the core size of each first fiber 141 in the first fiber array 140, and the size of each second through-hole 1321 in the second through-hole array 1320 needs to match the core size of each second fiber 151 in the second fiber array 150, losses during the connection process can be reduced without relying on expensive alignment mechanisms, which helps to further reduce installation costs. Moreover, the first fiber array 140 and the second fiber array 150 can be inserted at once, which has many advantages such as simple operation and easy installation.

[0052] refer to Figures 5 to 10 Optionally, the first side 131 may have a groove 133, and the first connection hole array 1310 is located inside the groove 133 to guide each first optical fiber 141 through each first connection hole 1311 to connect with the first end face 1211.

[0053] This design is equivalent to setting positioning grooves on the outside of multiple photonic chips 120 for guiding the installation of photonic chips 121, so that the external first fiber array 1310 can be aligned and inserted into the first connection hole array 1310 in one go, connecting with the first end face 1211 of the multiple photonic chips 120. This helps to improve the installation efficiency of the multiple first fiber arrays 1310. The depth of the groove 133 can be flexibly designed according to needs and process tolerances, for example, it can be 1.1mm, 2mm, 2.5mm, 3.6mm, etc., without specific limitation here.

[0054] In one example, the groove 133 can be disposed on the second side 132, and the second connection hole array 1320 is located inside the groove 133. The groove 133 can be used to guide the second fiber array 150 to be aligned and inserted into the second connection hole array 1320 in one go, and connected to the first end face 1211 of the multiple photonic chips 120.

[0055] In another example, a groove 133 may be disposed on a first side 131 and a second side 132. A first connector array 1310 is located inside the groove 133 to guide each first optical fiber 141 through each first connector hole 1311 to connect with a first end face 1211. A second connector array 1320 is located inside the groove 133. The groove 133 may be used to guide a second optical fiber array 150 to be aligned and inserted into the second connector array 1320 in one go, connecting with the first end face 1211 of a plurality of photonic chips 120.

[0056] refer to Figure 4 The groove 133 can be circular in shape, matching the shape of the internal connecting hole, to improve guidance and further reduce installation difficulty. Of course, the shape of the groove can also be flexibly designed as needed, and no limitations are imposed here.

[0057] It is understood that multiple photonic chips 120 may include three-dimensional photonic chips. In the case where multiple photonic chips 120 include multiple photonic chips stacked in multiple layers, the first connection hole array 1310 may include a two-dimensional first connection hole array, and the second connection hole array 1320 may include a two-dimensional second connection hole array. This allows the three-dimensional photonic chips to break through the one-dimensional fixed installation mode and realize the fixed installation of two-dimensional multi-layer photonic chips. This increases the dimension of photonic chip fixed installation, which is beneficial to improve the density of three-dimensional photonic chips and reduce the size of photonic chip devices.

[0058] In one example, multiple photonic chips 120 can be formed inside the substrate 110. This means that the photonic chips are naturally surrounded by the quartz glass substrate, which helps prevent interference and improves the stability of the photonic chips during use. Furthermore, three-dimensional photonic chips can also be formed directly within the substrate 110. Correspondingly, the first interconnect array 1310 can include a two-dimensional array of first interconnect holes, and the second interconnect array 1320 can include a two-dimensional array of second interconnect holes. This allows for further increasing the density of three-dimensional photonic chips within the existing size of the photonic chip device, thereby improving space utilization.

[0059] Furthermore, the first fiber array 140 may include a multi-core fiber 141, and the second fiber array 150 may include a single-core fiber array. It should be noted that the multi-core fiber 141 is a novel type of optical fiber with multiple independent cores within a common cladding region. The cladding employs a fluorine-doped refractive index profile structure to achieve long-distance, low-crosstalk space-division multiplexing optical signal transmission. Based on the space-division multiplexing concept, multi-core optical fibers can simultaneously transmit multiple optical signals within a single fiber, significantly improving communication capacity and breaking through the current transmission capacity limits of ordinary single-mode optical fibers. In this embodiment, the number of cores in the multi-core fiber (125µm±1µm) can range from 3 to 128, for example, 3, 7, 8, 16, etc.

[0060] Of course, multiple photonic chips 120 can also be set inside the substrate 110 in other ways, such as by growth or by making a quartz glass substrate on the basis of the original multiple photonic chips 120. No specific limitation is made here.

[0061] Preferably, multiple photonic chips 120 are prepared by femtosecond laser direct writing combined with chemical etching.

[0062] Specifically, firstly, femtosecond laser direct writing is used to etch the substrate 110 (quartz glass substrate) to modify the substrate. The following explanation uses a quartz glass substrate as an example. Because laser direct writing alters the internal properties of the quartz substrate (such as refractive index and chemical activity) through the interaction between the laser and the material (e.g., photopolymerization, ablation, modification), it ensures the processing precision of the photonic chip structure 100. This method not only reduces processing steps but also allows for flexible processing based on different arrangements and sizes of the two-dimensional via array 120. Furthermore, this method can achieve nanometer-level precision, which is beneficial for improving the fabrication accuracy of photonic chip devices, thereby further improving efficiency.

[0063] It is understood that femtosecond lasers are focused into the interior of materials, such as glass, crystals, polymers, and transparent ceramics, through an objective lens to induce structural changes and increase the refractive index, thereby forming photonic chips (such as three-dimensional optical waveguides) within the material. This application uses quartz glass as the substrate for forming the optical waveguide; for example, oxide glass or fluoride glass can be used. The optical waveguides written by femtosecond lasers in various glasses can achieve single-mode and multi-mode optical waveguides by changing the refractive index and core diameter through altering the laser irradiation conditions, with a loss of less than 0.3 dB / cm in the optical communication band. The first and second connecting hole arrays, as direct-interface structures, can also be fabricated using femtosecond laser direct-writing technology: first, a femtosecond laser is focused into the interior of the material through an objective lens to induce structural modification, thus forming a modified structure within the material. Then, using chemical solvents such as hydrofluoric acid, the temperature of the solvent and the frequency of stirring are adjusted to etch the first and second connecting hole arrays, which perfectly correspond to the optical waveguide, at both ends of the three-dimensional optical waveguide.

[0064] It should be noted that after the photonic chip device 100 is fabricated, the first connector array, the first fiber array, the second connector array, and the second fiber array are installed. In one example, refer to... Figures 7 to 10 The coating layer 142 of the ground and cut multi-core optical fiber 140 is stripped to expose the fiber core 143, and it is directly inserted into the first connection hole array 1310 of the etched photonic chip device 100. Then, the multi-core optical fiber 140 is fixed in the groove 133 with UV-curable adhesive, and aligned with the multiple first ports 1211 one by one (such as by rotating the optical fiber after docking). After the multi-core optical fiber 140 is fixed, it is cured and fixed with UV adhesive. Similarly, the coating layer 142 of the second optical fiber 151 (such as a single-core optical fiber) in the second optical fiber array 150 is also stripped to expose the fiber core 143, and it is directly inserted into the second connection hole array 1320 of the etched photonic chip device 100. Then, the second optical fiber array 150 is fixed in the groove 133 with UV-curable adhesive, and aligned with the multiple second ports 1212 one by one.

[0065] It should be noted that the second optical fiber 151 provided in one embodiment of this application can be a single-mode single-core optical fiber. A single-mode optical fiber can be an optical fiber with a very thin central glass core that can only transmit one mode. Moreover, the intermodal dispersion of a single-mode optical fiber is very small, which places high demands on the spectral width and stability of the light source. Each single-mode single-core optical fiber in the second optical fiber array 150 can be stripped of its coating, cut or ground to the required bare fiber size, and directly inserted into the etched second connector array. After complete alignment, it can be cured and fixed with UV adhesive.

[0066] It should also be noted that the reference Figures 7 to 11The fabrication method of the photonic chip device provided in one embodiment of this application specifically includes: setting up an improved six-dimensional optical adjustment system, which includes a chip holder in the middle, a six-dimensional precision optical adjustment frame on each side, and is equipped with a corresponding laser light source, a dual-channel optical power meter, an optical power meter, an ultraviolet curing system, a CCD camera monitoring system, an illumination light source, and a shockproof optical platform. Then, the connection ends of the three single-mode single-core fibers and the multi-core fiber are cleaned and installed into the chip holder of the six-dimensional optical adjustment system. Next, the single-mode single-core fiber is installed into the clamp on the left side (i.e., the second side of the photonic chip device) of the six-dimensional optical adjustment system using a clamp, and connected to the light source. Subsequently, the multi-core fiber is installed into the special clamp on the right side (i.e., the first side of the photonic chip device) of the six-dimensional optical adjustment system, and the multi-core fiber is directly connected to the multi-core power meter probe. Under the observation of the CCD camera monitoring system, the insertion loss value of the optical power meter is monitored, and the six-dimensional precision optical adjustment frame on both sides is continuously adjusted until the insertion loss value reaches the preset value. When the insertion loss value reaches the preset value, it indicates that the single-mode single-core fiber is aligned with the second end face 1212 of the three-dimensional photonic chip, and the multi-core fiber is aligned with the first end face 1211 of the three-dimensional photonic chip. If necessary, the optical adjustment frame can be finely adjusted to make the loss values ​​of the first or second connecting hole equal. After the loss value stabilizes, it is completely cured with ultraviolet glue. Since the first connecting hole array and the second connecting hole array are pre-set at both ends of the three-dimensional photonic chip, the installation can be completed simply by finely adjusting the single-mode single-core fiber and the multi-core fiber after removing the coating layer. Therefore, this method has many advantages such as fast installation, simplicity, and convenience.

[0067] The following describes the structure of the photonic chip device 100 provided in this application, taking the first fiber array 140 as an N×8 strip fiber (that is, each fiber array 140 may include 8 independent single-core fibers 141, each group of 8 single-core fibers 141 is a group, and N such groups of 8-core fibers are stacked together in a strip shape), the second fiber array 150 as a multi-core fiber, and the photonic chip 141 of a single-mode single-core fiber and the corresponding single-mode single-core second fiber 151 as an example.

[0068] refer to Figures 1 to 11One embodiment of this application provides a photonic chip device 100, which includes a substrate 110. A first side 131 of the substrate 110 has a first connection hole array 1310, and a second side 132 of the substrate 110 has a second connection hole array 1320. The first connection hole array 1310 has a plurality of first ports 1311 located on the first side 131, and the second connection hole array 1320 has a plurality of second ports 1321 located on the second side 132. The size of each first connection hole 1311 in the first connection hole array 1310 matches the size of the core of each first optical fiber 141, and the size of each second connection hole 1321 in the second connection hole array 1320 matches the size of the core of each second optical fiber 151.

[0069] The photonic chip device 100 also includes a three-dimensional photonic chip formed inside the substrate 110. The first interconnect array 1310 may include a two-dimensional array of first interconnects, and the second interconnect array 1320 may include a two-dimensional array of second interconnects.

[0070] In addition, the first side 131 may have a groove 133, and the first connection hole array 1310 may be located inside the groove 133 to guide each first optical fiber 141 through each first connection hole 1311 to connect with the first end face 1211.

[0071] It should be noted that the photonic chip device 100 provided in this application can serve as an implementation of current fast coupling fan-out technology. Current fast coupling fan-out technology achieves efficient mode switching through precise micro / nano structures (such as grating couplers, end-face couplers, and adiabatic tapered devices), reducing losses to 1 dB or even below 0.5 dB. The photonic chip device provided in this application, by fabricating a three-dimensional photonic chip in a quartz glass substrate and using it as a coupling device, facilitates a further increase in alignment tolerance, thereby reducing packaging time and cost.

[0072] Specifically, fast fan-out technology typically uses a high-precision silicon photonics interposer or substrate with microstructures etched on it to match the chip waveguide spacing. This allows the dense waveguide channels to be "fanned out" to a spacing that matches standard fiber arrays (such as MT ferrules with a 0.25mm pitch). Through advanced wafer-level micromachining techniques (such as through-silicon vias and microlens arrays), fan-outers containing dozens or even hundreds of channels can be manufactured. This allows for permanent bonding with the chip with only a one-time, collective active or passive alignment. Once the connection point is solidified and encapsulated, it provides a standard, robust Mechanically Transferable (MT) / Multi-fiber Push-On (MPO) interface to the outside. Moreover, in case of damage, external fiber optic patch cords can be replaced like network cables without touching the core optical chip, greatly improving reliability and maintainability.

[0073] Exemplary optical interconnect devices and optical quantum computers: refer to Figures 9 to 12 Based on the aforementioned photonic chip device 100, one embodiment of this application provides an optical interconnect device 200, which may include the photonic chip device 100, a first fiber array 140, a second fiber array 150, and a packaging shell 210. The photonic chip device 100 is disposed in the internal cavity of the packaging shell 210. The specific structure of the photonic chip device 100 can be found in the description above, and will not be elaborated here.

[0074] refer to Figure 13 Based on the aforementioned optical interconnect device 200, one embodiment of this application also provides an optical quantum computer 300, which includes a single photon source 310, an optical quantum chip 320, and a single photon detector 330. One or more of the single photon source 310, the optical quantum chip 320, and the single photon detector 330 include the optical interconnect device 200 described above.

[0075] It can be understood that the optical quantum computer 300 mainly comprises a single-photon source, an optical quantum chip, and a detection system. An optical quantum computer is a quantum computing device that uses photons (light particles) as qubits for information processing. The single-photon source generates high-quality single photons as qubit carriers by exciting quantum dots with lasers or by spontaneous parametric down-conversion (SPDC). The optical quantum processor consists of optical components such as optical fibers, waveguides, beam splitters, phase modulators, and mirrors to achieve optical transmission and logical operations (such as Hadamard gates and CNOT gates). The detection system can measure the final state of the photons (such as polarization or path) and output the calculation results. For a detailed description of the specific processing procedures of the optical quantum computer, please refer to the relevant technical descriptions; they will not be elaborated upon here.

[0076] Exemplary method for fabricating a photonic chip device: based on Figures 1 to 14 An embodiment of this application also provides a method for fabricating a photonic chip device 100, the method comprising the following steps: S10 provides a substrate 110 (such as a quartz glass substrate).

[0077] Specifically, based on the design dimensions of the photonic chip device 100, the quartz glass is cut into quartz glass substrates of different sizes, and then the surface is cleaned with low-concentration hydrofluoric acid, pure alcohol, hydrogen peroxide and purified water.

[0078] S20, a first connecting hole array 1310 is formed on a first side 131 of the substrate 110 (e.g., a quartz glass substrate), and a second connecting hole array 1320 is formed on a second side 132 of the quartz glass substrate. The first connecting hole array 1310 has a plurality of first ports 1311 located on the first side 131, and the second connecting hole array 1320 has a plurality of second ports 1321 located on the second side 132.

[0079] Specifically, the first via array 1310 and the second via array 1320 are formed directly by chemical etching. In one example, the second via array 1320 is first etched using a femtosecond laser direct writing method to induce etching of the pre-etched area of ​​the quartz glass substrate, and then the etched area is etched using chemical reagents, i.e., the etched area is etched by stirring the chemical solution, thus completing the second via array 1320. Similarly, the first via array 1310 can also be etched first by femtosecond laser direct writing, and then etched by chemical etching. Of course, the first via array 1310 and the second via array 1320 can both be obtained by first undergoing femtosecond laser direct writing etching, and then the etched area is etched by chemical reagents.

[0080] In another example, the first interconnect array 1310 and the second interconnect array 1320 are first formed by etching with chemical reagents, and then the pre-etched area of ​​the quartz glass substrate is induced by femtosecond laser direct writing using a precise positioning method.

[0081] S30, a plurality of photonic chips 120 are formed inside the substrate 110 (e.g., a quartz glass substrate). Each photonic chip 121 in the plurality of photonic chips 120 has a first end face 1211 and a second end face 1212. The first end face 1211 is connected to each of the plurality of first ports 1311 so that each of the first optical fibers 141 in the first optical fiber array 140 is connected to the first end face 1211. The second end face 1212 is connected to each of the plurality of second ports 1321 so that each of the second optical fibers 151 in the second optical fiber array 150 is connected to the second end face 1212.

[0082] Specifically, the quartz glass is modified by etching it directly onto the quartz glass substrate using a femtosecond laser, so that multiple photonic chips 120 (such as three-dimensional photonic chips) can be fabricated inside the quartz glass substrate.

[0083] In one example, a groove 133 is formed on the first side 131 of the quartz glass substrate. The pre-etched area of ​​the quartz glass substrate is first etched by femtosecond laser direct writing using a precise positioning method through chemical etching such as hydrofluoric acid. Then, the etched area is etched by chemical reagents. The femtosecond laser direct writing area is etched by chemical solution stabilization and stirring frequency to complete the prefabrication of multiple grooves 133.

[0084] In addition, each functional unit or module in the various embodiments of this application can be integrated into one processing unit or module, or each unit or module can exist physically separately, or two or more units or modules can be integrated into one unit or module.

[0085] It is understood that in this application, directional descriptions such as "upper," "lower," "inner," and "outer" are relative rather than absolute. These directional terms may be applicable when the photonic chip device provided in this application is placed in the posture and position shown in the accompanying drawings.

[0086] It should be understood that although terms such as "first" or "second" may be used in this application to describe various elements (such as the first fiber array and the second fiber array), these elements are not defined by these terms, which are only used to distinguish one element from another.

[0087] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0088] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0089] The components and devices described in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the accompanying drawings. As those skilled in the art will recognize, these components and devices can be connected, arranged, and configured in any manner.

[0090] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A photonic chip device, characterized in that, include: The substrate has a first array of connecting holes and a second array of connecting holes. The first connection hole array is located on a first side of the substrate, and the first connection hole array has a plurality of first ports located on the first side. The second connection hole array is located on the second side of the substrate, and the second connection hole array has a plurality of second ports located on the second side; Multiple photonic chips are disposed inside the substrate, and each photonic chip has a first end face and a second end face. The first end face is connected to each of the plurality of first ports, so that each first fiber in the first fiber array is connected to the first end face. The second end face is connected to each of the plurality of second ports, so that each second fiber in the second fiber array is connected to the second end face.

2. The photonic chip device according to claim 1, characterized in that, The size of each first connector in the first connector array matches the size of the core of each first optical fiber, and the size of each second connector in the second connector array matches the size of the core of each second optical fiber.

3. The photonic chip device according to claim 1, characterized in that, The first side has a groove, and the first connection hole array is located inside the groove to guide each of the first optical fibers through each of the first connection holes to connect with the first end face.

4. The photonic chip device according to claim 1, characterized in that, The plurality of photonic chips include three-dimensional photonic chips, the first connection hole array includes a two-dimensional arrangement of a first connection hole array, and the second connection hole array includes a two-dimensional arrangement of a second connection hole array.

5. The photonic chip device according to claim 1, characterized in that, The multiple photonic chips were obtained through femtosecond laser direct writing.

6. The photonic chip device according to claim 1, characterized in that, The plurality of photonic chips are formed inside the substrate.

7. The photonic chip device according to claim 6, characterized in that, The photonic chip array includes a three-dimensional photonic chip, the first connection hole array includes a two-dimensional arrangement of first connection holes, and the second connection hole array includes a two-dimensional arrangement of second connection holes. The first fiber array includes multi-core optical fibers, and the second fiber array includes a single-core optical fiber array.

8. An optical interconnect device, comprising a photonic chip device, a first fiber array, a second fiber array, and a package housing as described in any one of claims 1 to 7, wherein the photonic chip device is disposed in an internal cavity of the package housing.

9. A quantum optical computer, characterized in that, It includes a single-photon source, a quantum chip, and a single-photon detector, wherein one or more of the single-photon source, the quantum chip, and the single-photon detector include the optical interconnect device as described in claim 8.

10. A method for fabricating a photonic chip device as described in any one of claims 1 to 7, characterized in that, include: Provide a matrix; A first array of connecting holes is formed on a first side of the substrate, and a second array of connecting holes is formed on a second side of the substrate, wherein... The first connection hole array has a plurality of first ports located on the first side, and the second connection hole array has a plurality of second ports located on the second side; Multiple photonic chips are formed inside the substrate, each of the multiple photonic chips having a first end face and a second end face, wherein... The first end face is connected to each of the plurality of first ports, so that each first fiber in the first fiber array is connected to the first end face. The second end face is connected to each of the plurality of second ports, so that each second fiber in the second fiber array is connected to the second end face.

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