Chip ATE test temperature control method

Abstract

The invention provides a chip ATE test temperature control method, and belongs to the technical field of chip test.The control method comprises the steps that temperature signals of a wafer temperature measuring diode and an IP core temperature sensing module of a chip are collected in real time; determining a reference source of temperature regulation and control according to the received test item instruction; if the test item is a chip overall performance test, controlling a temperature control head and a temperature control socket to perform bidirectional temperature adjustment on the chip by taking the temperature of the wafer temperature measurement diode as a reference temperature, so that the wafer temperature measurement diode reaches a first target temperature, and applying a test vector or current and voltage to the chip in linkage with the ATE; and if the test item is a chip IP core performance test, the temperature of the IP core temperature sensing module is taken as a reference temperature, the temperature control head and the temperature control socket are controlled to carry out bidirectional temperature adjustment on the chip, so that the IP core reaches a second target temperature, and the ATE is linked to apply a test vector to the IP core of the chip.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a method for controlling the temperature during chip ATE testing. Background Technology

[0002] After packaging, chips undergo Thermal Expansion (FT) testing via ATE (Automatic Test Equipment) to verify their performance. Passing the FT test allows the chip to be considered a qualified product. For consumer-grade and industrial-grade chips, the FT test temperature is generally room temperature, while high and low temperature tests are defined according to the chip type. Due to the complex application environment of automotive chips, automotive-grade chips require three-temperature FT testing (low temperature, room temperature, and high temperature). Only after passing all three tests can they be considered qualified. During high-temperature testing, the ambient temperature may exceed 100℃ (for example, for chips passing AEC-Q100 Grade 0, the ambient temperature for high-temperature testing reaches 150℃). The chip needs to be powered on during testing, and combined with the chip's own heat generation, high-power chips with significant heat generation may experience instantaneous temperatures exceeding the safe junction temperature range, leading to malfunctions or burnout. Therefore, during high-temperature testing, the temperature of the high-power chip needs to be reduced quickly to reach the required test temperature within the safe junction temperature range. Furthermore, for SOC chips composed of different IPs, abnormal temperatures in various parts of the chip during test vector loading can cause deviations in test results, affecting the final test outcome. Therefore, when loading test vectors for the IPs of such chips, temperature control must achieve high precision to ensure the stability of the test results. During low-temperature testing, the internal temperature of the chip may need to reach -40°C. However, due to the heat generated during chip operation, the internal temperature may exceed -40°C. The data measured in this case may not be the desired data, which can negatively impact the confirmation of the chip's operating boundary conditions. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and proposes a method for controlling the temperature of chip ATE testing.

[0004] In a first aspect, embodiments of the present invention provide a chip ATE test temperature control method, wherein the method is executed in a test system comprising an automatic tester ATE, a temperature acquisition and control card, a temperature control head located above the chip and a temperature control socket located below the chip, wherein the chip is mounted on the temperature control socket and fixed by pressure bonding via the temperature control head, and the chip wafer integrates a temperature sensing diode and its IP core integrates a temperature sensing module.

[0005] The method is executed by the temperature acquisition and control card, and includes:

[0006] The temperature signals of the wafer temperature sensing diode and IP core temperature sensing module of the chip are collected in real time.

[0007] Based on the received test project instructions, determine the reference source for temperature control;

[0008] If the test item is a chip overall performance test, the temperature of the wafer temperature sensing diode is used as the reference temperature. The temperature control head and the temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the wafer temperature sensing diode reaches the first target temperature. The ATE is then linked to apply a test vector or current and voltage to the chip.

[0009] If the test item is a chip IP core performance test, the temperature of the IP core temperature sensing module is used as the reference temperature. The temperature control head and the temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the IP core reaches the second target temperature. The ATE is then linked to apply a test vector to the chip's IP core.

[0010] In some embodiments, the bidirectional temperature regulation of the chip specifically includes the temperature acquisition and control card synchronously or asynchronously controlling the temperature control head and the temperature control socket to heat or cool.

[0011] In some embodiments, when the chip contains multiple IP cores, in response to a performance test command for a specific IP core, the temperature of the temperature sensing module of that specific IP core is used as a reference temperature.

[0012] In some embodiments, the first target temperature and the second target temperature are independently set temperature values; the range of the first target temperature and the second target temperature is -40°C to 150°C.

[0013] In some embodiments, the chip is an automotive-grade SOC chip.

[0014] Secondly, embodiments of the present invention provide a chip ATE test temperature control method, wherein the method is executed in a test system including an automatic tester ATE, a temperature acquisition and control card, a temperature control head located above the chip and a temperature control socket located below the chip, wherein the chip is mounted on the temperature control socket and fixed by pressure bonding via the temperature control head, and the chip wafer integrates a temperature sensing diode and its IP core integrates a temperature sensing module.

[0015] The method is executed by the automated test equipment (ATE), including:

[0016] The temperature acquisition and control card is issued test item instructions and target temperatures; the test item instructions include overall chip performance testing or chip IP core performance testing.

[0017] During the test, the following temperature control results executed by the temperature acquisition and control card are received:

[0018] In response to the overall chip performance test command, the temperature of the temperature sensing diode on the chip wafer is used as the reference temperature. The temperature control head and temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the temperature sensing diode on the wafer reaches the first target temperature.

[0019] In response to the chip IP core performance test command, the temperature of the chip IP core's temperature sensing module is used as the reference temperature. The temperature control head and temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the IP core reaches the second target temperature.

[0020] Apply a test vector or current / voltage corresponding to the test item command to the chip, and collect the chip's test output.

[0021] Thirdly, embodiments of the present invention provide a chip ATE test temperature control system, the system comprising: an automatic test equipment (ATE), a temperature control socket, a temperature control head, and a temperature acquisition and control card; wherein;

[0022] An automated test equipment (ATE) is used to apply voltage, current, and test vectors to a chip, and to collect the voltage, current, and output vectors to determine the compliance of the test results.

[0023] The temperature control socket is located below the chip and is used to support the chip and provide temperature control for the area below the chip.

[0024] A temperature control head is positioned above the chip to press the chip and provide temperature control above the chip.

[0025] A temperature acquisition and control card, located within the ATE or configured to communicate with the ATE, is configured to: acquire the temperatures of the wafer temperature sensing diode and the IP core temperature sensing module of the chip in real time; determine the reference source for temperature regulation based on test item instructions from the ATE; during overall chip performance testing, use the temperature of the wafer temperature sensing diode as the reference temperature to control the temperature control head and the temperature control socket to achieve a first target temperature for the wafer; and during chip IP core performance testing, use the temperature of the IP core temperature sensing module as the reference temperature to control the temperature control head and the temperature control socket to achieve a second target temperature for the IP core.

[0026] In some embodiments, the temperature acquisition and control card achieves bidirectional temperature regulation of the chip by controlling the temperature of the liquid flowing through the liquid cooling circuit in the temperature control head and controlling the thermoelectric modulator in the temperature control socket.

[0027] Fourthly, embodiments of the present invention provide an electronic device, comprising:

[0028] One or more processors;

[0029] Memory, used to store one or more programs;

[0030] When the one or more programs are executed by the one or more processors, the one or more processors perform the method as described above.

[0031] Fifthly, embodiments of the present invention provide a computer-readable medium on which a computer program is stored, the computer program being executed by a processor to implement the steps in the method described above.

[0032] The chip ATE test temperature control method provided by this invention acquires the temperature of the chip wafer and IP core in real time by a temperature acquisition and control card, and intelligently switches the temperature control benchmark according to the test project instructions. It coordinates the temperature control head located above the chip and the temperature control socket located below the chip to perform bidirectional temperature adjustment, thereby achieving rapid, accurate and stable control of the chip test temperature. This effectively prevents the chip from overheating and being damaged due to its own heat generation during high-temperature testing, while ensuring the accuracy of temperature conditions when testing different functional modules, thus significantly improving the reliability of the test results. Attached Figure Description

[0033] Figure 1 This is a structural block diagram illustrating an application scenario of a chip ATE test temperature control method provided in an embodiment of the present invention.

[0034] Figure 2 A schematic flowchart of a chip ATE test temperature control method provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the temperature acquisition and control card execution flow of a chip ATE test temperature control method provided in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the automatic test machine ATE execution flow of a chip ATE test temperature control method provided in an embodiment of the present invention;

[0037] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the technical solutions of the present invention, exemplary embodiments of the present invention are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0039] Where there is no conflict, the various embodiments of the present invention and the features thereof may be combined with each other.

[0040] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0042] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0043] In the technical solution of this invention, the collection, storage, use, processing, transmission, provision, and disclosure of user personal information all comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations (e.g., the "Information Security Technology - Personal Information Security Specification"). For example: appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identity targeting is eliminated when using personal information to avoid precisely locating a specific individual.

[0044] Explanation of abbreviations and key terms:

[0045] ATE: Automatic Test Equipment.

[0046] FT: Final test, the final performance test of a chip during the manufacturing process.

[0047] AEC-Q100 Grade 0: Automotive Electronics Council Qualification, the chip can operate normally in an ambient temperature range of -40℃ to 150℃.

[0048] SOC: System on ChIP (SoC) includes components such as processor and power management.

[0049] IP (Intellectual Property Core) refers to a mature design of a circuit module with independent functionality within a chip. This circuit module design can be applied to other chip design projects that include it, thereby reducing design workload, shortening the design cycle, and improving the success rate of chip design.

[0050] IP core temperature sensing module: A temperature sensing circuit is embedded in a pre-designed circuit functional module and used to sense the temperature of the IP.

[0051] Temperature acquisition and control card: A type of board in ATE that can acquire temperature data and perform temperature control.

[0052] Temperature-controlled socket: A chip test socket with temperature control function. It is a carrier for bringing out the chip pins, so that the electrical connection of the chip can be achieved without soldering.

[0053] Die: A chip wafer, formed by cutting a crystal into pieces.

[0054] Temperature control head: It is generally made of metal with high thermal conductivity; according to the instructions of the temperature control board, it cools and heats itself through liquid cooling circuit and heating element, and directly contacts the chip under test, thereby realizing the heating and cooling of the chip under test.

[0055] In related technologies, patent document CN115963383A discloses a temperature control system, method, and process for chip ATE testing. The temperature of the chip temperature diode / IP core temperature sensing module is read by the ATE temperature sensing board and compared with the chip's target temperature. If the actual chip temperature is greater than the target temperature, the actual chip temperature is reduced by cooling the temperature control head on top of the chip. Conversely, if the actual chip temperature is less than the target temperature, the actual chip temperature is increased by heating the temperature control head on top of the chip, thereby achieving precise control of the chip's actual temperature.

[0056] This patent document adjusts the chip temperature through a unidirectional (top) temperature control device. However, the FT test time of the chip is often very short, and the loading time of some test vectors is only at the millisecond level. For high-power chips such as automotive-grade SOCs that generate a lot of heat and use resin as the encapsulation material, the temperature adjustment speed of the top-side unidirectional chip temperature control method may not achieve the effect of rapid cooling when performing high-temperature tests. This may lead to deviations in the test results.

[0057] Patent document CN116643143A discloses a fully automatic chip temperature testing system and method based on an ATE tester. The testing process is as follows: according to the temperature-resistance resistor's datasheet, the relationship between temperature and resistance values ​​is found and input into the ATE tester. Then, the chip is connected to the test board. After the test board and temperature sampling device are connected to the ATE tester, the test board and temperature sampling device are placed in a high and low temperature test chamber. The high and low temperature test chamber is started. When the temperature inside the high and low temperature test chamber reaches the initial set value for chip testing, the ATE tester is started. The temperature value and the chip's voltage and current parameters are recorded synchronously by the ATE tester.

[0058] This patent document uses the ambient temperature measured by a thermistor as the chip temperature. It cannot sense the internal temperature of the chip, nor can it measure the temperature based on the actual IP core temperature sensing module or temperature diode of the chip. It only meets the testing needs of chips with low temperature control requirements.

[0059] To address at least one of the technical problems existing in the aforementioned related technologies, this invention provides a chip ATE testing temperature control method. This method employs bidirectional temperature regulation, using an upper temperature control head and a bottom temperature control socket to regulate the temperature. This bidirectional temperature regulation prevents excessive temperature gradients within the chip and enables rapid and stable temperature adjustment for chips requiring precise temperature control during testing. Upon receiving a temperature adjustment command, the bottom temperature control socket and the upper temperature control head can rapidly adjust the temperature based on the real-time temperature detected by the die temperature sensing diode and the IP core temperature sensing module. Figure 2 and Figure 3This is a flowchart illustrating a chip ATE test temperature control method provided in an embodiment of the present invention.

[0060] In some embodiments, reference Figure 2 and Figure 3 The present invention provides a chip ATE test temperature control method. The method is executed in a test system including an automatic tester ATE, a temperature acquisition and control card, a temperature control head located above the chip and a temperature control socket located below the chip. The chip is mounted on the temperature control socket and fixed by the temperature control head. The chip wafer integrates a temperature sensing diode and its IP core integrates a temperature sensing module.

[0061] The method is executed by the temperature acquisition and control card, and includes: real-time acquisition of temperature signals from the wafer temperature sensing diode and the IP core temperature sensing module of the chip; determining the reference source for temperature regulation based on the received test item instructions; if the test item is an overall chip performance test, the temperature of the wafer temperature sensing diode is used as the reference temperature, and the temperature control head and the temperature control socket are controlled to perform bidirectional temperature regulation on the chip, so that the wafer temperature sensing diode reaches a first target temperature, and the ATE is linked to apply a test vector or current and voltage to the chip; if the test item is a chip IP core performance test, the temperature of the IP core temperature sensing module is used as the reference temperature, and the temperature control head and the temperature control socket are controlled to perform bidirectional temperature regulation on the chip, so that the IP core reaches a second target temperature, and the ATE is linked to apply a test vector to the chip IP core.

[0062] This invention targets high-power chips such as automotive-grade SoCs, where the die includes a temperature-sensing diode and contains an IP core temperature sensing module. Figure 1 As shown, the die temperature sensing diodes can be located on both sides of the die to measure the overall temperature of the chip. The IP core temperature sensing module is located inside the IP. The real-time temperature of the die temperature sensing diodes and the IP core temperature sensing module can be acquired through a temperature acquisition and control card, and the chip temperature can be adjusted in real time and quickly through a temperature control head and a temperature control socket.

[0063] This invention is based on high-power chips such as SOCs (System-on-a-Chip) whose dies include temperature-sensing diodes and contain IP core temperature sensing modules. This invention provides a chip ATE (Automatic Test Equipment) temperature control method, such as... Figure 1As shown, this temperature control method requires the following components to work together: ATE (Automatic Temperature Controller), chip, temperature acquisition and control card, temperature control head, and temperature control socket. The ATE loads voltage, current, and test vectors onto the chip, and after loading the current / voltage / test vectors, it acquires the voltage, current, and output vectors, and judges the compliance of the test results. Temperature regulation during the chip's testing process is completed jointly by the temperature acquisition and control card, temperature control head, and temperature control socket. The specific steps are as follows (see reference). Figure 2 and Figure 3 .

[0064] The test parameters and temperature control reference source for the chip were confirmed to be the Die temperature sensing diode / IP core temperature sensing module, and the test temperature was confirmed. The chip was installed in the ATE's temperature control socket, and the temperature control head applied pressure to the chip, pressing the chip's pins firmly into the socket. The temperature acquisition and control card in the ATE continuously monitored the temperatures of the IP core temperature sensing module and the Die temperature sensing diode. When testing the overall chip performance, the temperature of the Die temperature sensing diode was used as the reference temperature to control the temperature control head and the temperature control socket, ensuring the chip's Die temperature sensing diode reached the target temperature. The ATE then applied test vectors or current and voltage to the chip and acquired the chip's output test vectors and voltage / current. The temperature acquisition and control card in the ATE continuously monitored the temperatures of the IP core temperature sensing module and the Die temperature sensing diode. When testing the chip's IP core performance, the temperature of the IP core temperature sensing module was used as the reference temperature to control the temperature control head and the temperature control socket, ensuring the chip's IP core reached the target temperature. The ATE then applied test vectors to the chip's IP core and acquired the chip's output test vectors.

[0065] This embodiment utilizes bidirectional temperature control technology to rapidly regulate the internal temperature of the chip, avoiding testing problems caused by temperature deviations and ensuring the stability of the testing process. It reduces chip test failures or burnout caused by the combined effects of high-temperature testing and the chip's own heat generation, thereby lowering testing costs.

[0066] The key points of this invention are: temperature can be regulated by the upper temperature control head and the bottom temperature control socket, which can quickly adjust the temperature of automotive-grade chips during FT testing, preventing the chip from burning out due to the internal temperature exceeding the safe junction temperature during high-temperature operation; and avoiding the chip's boundary operating conditions caused by the chip itself heating up during low-temperature operation and failing to meet the required standards during low-temperature testing.

[0067] In some embodiments, the bidirectional temperature regulation of the chip specifically includes the temperature acquisition and control card synchronously or asynchronously controlling the temperature control head and the temperature control socket to heat or cool.

[0068] In some embodiments, a synchronous control mode is employed: In this mode, the temperature acquisition and control card simultaneously sends control commands to both the temperature control head and the temperature control socket, enabling them to work together to simultaneously heat or cool the chip. This "pincer" approach achieves the fastest heat exchange, significantly shortening the temperature stabilization time. It is particularly suitable for scenarios with extremely short test cycles or high chip heat generation, effectively preventing chip damage due to instantaneous overheating during high-temperature testing.

[0069] Asynchronous control mode: In this mode, the temperature acquisition and control card can control the temperature control components at different times, alternately, or according to different power levels. For example, in the fine-tuning stage, one component (such as the temperature control socket) can be mainly relied upon for fine-tuning, while the other component (such as the temperature control head) remains constant or assists in adjustment. This mode helps to achieve more precise temperature control and may reduce the overall power consumption of the system. At the same time, it helps to reduce the thermal stress generated inside the chip due to excessive instantaneous heat flow during the adjustment process.

[0070] By providing both synchronous and asynchronous temperature control strategies, the system described in this invention has stronger adaptability and flexibility. It can select the optimal temperature control mode according to different testing needs (such as pursuing ultimate speed or ultimate accuracy) and different chip types (such as different package thermal resistance), thereby ensuring testing accuracy while further improving testing efficiency and equipment lifespan.

[0071] In some embodiments, when the chip contains multiple IP cores, in response to a performance test command for a specific IP core, the temperature of the temperature sensing module of that specific IP core is used as a reference temperature.

[0072] This localized temperature control strategy for specific IP cores solves the thermal gradient problem caused by differences in structure and power density within complex SoC chips. It ensures that when testing a particular IP core, that core is always under a precise target temperature environment, thus obtaining the most realistic and reliable test data. This is crucial for ensuring the functional safety and reliability of high-performance, multi-core automotive-grade chips under extreme temperature conditions.

[0073] In some embodiments, the first target temperature and the second target temperature are independently set temperature values; the range of the first target temperature and the second target temperature is -40°C to 150°C.

[0074] In some embodiments, the first target temperature and the second target temperature are independently set temperature values. This means that two completely different temperature environments can be set and maintained for overall chip performance testing and for specific IP core performance testing. For example, an overall test can be performed with a first target temperature of 125°C; while an IP core test can be performed immediately afterward with a second target temperature independently set to -20°C. This independence provides great flexibility to the testing process.

[0075] Furthermore, these target temperatures are set strictly in accordance with automotive-grade chip testing standards. The typical range for the first and second target temperatures is -40°C to 150°C. This range fully covers the extreme operating temperature requirements of AEC-Q100 Grade 0 certification.

[0076] In some embodiments, the chip is an automotive-grade SOC chip.

[0077] In some embodiments, the present invention is specifically applied to automotive-grade system-on-a-chips (SOCs). These chips are high-reliability chips that meet stringent standards such as the Automotive Electronics Industry Association (AEC) Q100, and their testing requirements are far higher than those for consumer-grade or industrial-grade chips.

[0078] The requirement for automotive-grade SoC chips to operate stably and reliably in extremely harsh temperature environments (such as -40°C to 150°C) throughout their entire lifecycle has spurred the mandatory requirement for three-temperature (low temperature, room temperature, and high temperature) thermal FT testing. Furthermore, automotive-grade SoC chips typically integrate multiple high-performance IP cores (such as processors, power management, and communication interfaces), resulting in complex functions and significant power consumption and heat generation. This presents them with the dual challenges of instantaneous overheating and burnout risk, as mentioned in the background section, and inaccurate testing due to uneven internal temperature.

[0079] Therefore, the technical solution provided by this invention, which allows for rapid bidirectional temperature adjustment and intelligent switching of the temperature reference based on the test object (whole system or IP core), is designed to directly and effectively solve the aforementioned special technical challenges faced by automotive-grade SOC chips in FT testing.

[0080] This invention also provides a method for controlling the temperature of a chip ATE test, as described in the following embodiments. Figure 4 The method is performed in a test system comprising an automatic tester (ATE), a temperature acquisition and control card, a temperature control head located above the chip, and a temperature control socket located below the chip. The chip is mounted on the temperature control socket and fixed by pressure bonding via the temperature control head. The chip's wafer integrates a temperature sensing diode, and its IP core integrates a temperature sensing module.

[0081] The method is executed by the automated test equipment (ATE), including:

[0082] The temperature acquisition and control card is issued test item instructions and target temperatures; the test item instructions include overall chip performance testing or chip IP core performance testing.

[0083] During the test, the following temperature control results executed by the temperature acquisition and control card are received:

[0084] In response to the overall chip performance test command, the temperature of the temperature sensing diode on the chip wafer is used as the reference temperature. The temperature control head and temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the temperature sensing diode on the wafer reaches the first target temperature.

[0085] In response to the chip IP core performance test command, the temperature of the chip IP core's temperature sensing module is used as the reference temperature. The temperature control head and temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the IP core reaches the second target temperature.

[0086] Apply a test vector or current / voltage corresponding to the test item command to the chip, and collect the chip's test output.

[0087] This invention also provides a final chip test (FT) method, which is executed by an automated test equipment (ATE) as the core control unit. The implementation of this method relies on a collaborative testing system, which includes the ATE itself, a temperature acquisition and control card, a temperature control head located above the chip, and a temperature control socket located below the chip. The chip under test is mounted in the temperature control socket and fixed by pressure bonding via the temperature control head, and its wafer integrates a temperature-sensing diode, while its IP core integrates a temperature sensing module.

[0088] The method is executed by the ATE and includes the following steps:

[0089] Test initialization and command issuance: The ATE first issues specific test item commands and target temperatures to the temperature acquisition and control card according to the preset test program. The test item commands are used to clarify whether the current test object is the overall performance of the chip or the performance of a specific IP core.

[0090] Waiting for precise temperature control to be achieved: After the command is issued, the ATE enters a waiting state and receives a signal from the temperature acquisition and control card indicating that the temperature has been reached. This signal is feedback from the temperature acquisition and control card after successfully completing precise temperature control. Specifically, this result is achieved through any of the following methods:

[0091] In response to the overall chip performance test command, the temperature acquisition and control card uses the temperature of the temperature sensing diode on the chip wafer as the reference temperature, and controls the upper temperature control head and the lower temperature control socket to perform bidirectional temperature adjustment on the chip until the temperature sensing diode on the wafer reaches the first target temperature.

[0092] In response to the chip IP core performance test command, the temperature acquisition and control card uses the temperature of the IP core's temperature sensing module as the reference temperature, and controls the temperature control head and temperature control socket to perform bidirectional temperature adjustment on the chip until the IP core reaches the second target temperature.

[0093] Functional testing and result acquisition: Once a signal indicating that the temperature has met the standard is received, the ATE immediately applies a test vector or current / voltage corresponding to the test item command to the chip to activate the function of the chip or specific IP core. Subsequently, the ATE acquires the response signals such as test vectors, voltages, or currents output by the chip and judges the compliance of the test results according to preset pass / fail standards.

[0094] This embodiment clearly outlines a highly automated and streamlined complete testing solution. It encapsulates the core, underlying precise temperature control method of this invention into a reliable service invoked by ATE (Automatic Test Equipment).

[0095] This invention also provides a chip ATE test temperature control system, see reference. Figure 1 The system includes: an automatic testing machine (ATE), a temperature control socket, a temperature control head, and a temperature acquisition and control card; wherein,

[0096] An automated test equipment (ATE) is used to apply voltage, current, and test vectors to a chip, and to collect the voltage, current, and output vectors to determine the compliance of the test results.

[0097] The temperature control socket is located below the chip and is used to support the chip and provide temperature control for the area below the chip.

[0098] A temperature control head is positioned above the chip to press the chip and provide temperature control above the chip.

[0099] A temperature acquisition and control card, located within the ATE or configured to communicate with the ATE, is configured to: acquire the temperatures of the wafer temperature sensing diode and the IP core temperature sensing module of the chip in real time; determine the reference source for temperature regulation based on test item instructions from the ATE; during overall chip performance testing, use the temperature of the wafer temperature sensing diode as the reference temperature to control the temperature control head and the temperature control socket to achieve a first target temperature for the wafer; and during chip IP core performance testing, use the temperature of the IP core temperature sensing module as the reference temperature to control the temperature control head and the temperature control socket to achieve a second target temperature for the IP core.

[0100] The specific implementation details of each module can be found in the above description of the limitations on the chip ATE test temperature control method, and will not be repeated here.

[0101] In some embodiments, the temperature acquisition and control card achieves bidirectional temperature regulation of the chip by controlling the temperature of the liquid flowing through the liquid cooling circuit in the temperature control head and controlling the thermoelectric modulator in the temperature control socket.

[0102] In some embodiments, the temperature acquisition and control card achieves efficient and precise bidirectional temperature regulation of the chip by coordinating the control of two temperature control actuators based on different principles:

[0103] For the temperature control head located above the chip, the temperature acquisition and control card regulates its temperature by controlling the temperature of the liquid flowing through its internal liquid cooling circuit. For the temperature control socket located below the chip, the temperature acquisition and control card regulates its temperature by controlling its internally integrated thermoelectric modulator. By simultaneously leveraging the complementary advantages of both the liquid cooling circuit and the thermoelectric modulator, the temperature acquisition and control card achieves unprecedented temperature control performance.

[0104] Rapid temperature regulation: When rapid cooling is required, the liquid cooling circuit at the top can powerfully "absorb" a large amount of heat, while the TEC at the bottom can simultaneously provide auxiliary cooling, achieving the fastest temperature switching speed.

[0105] Ultra-high precision and stability: The liquid cooling circuit is responsible for stabilizing the temperature within the target range, while the bottom TEC can make high-frequency fine adjustments to compensate for the chip's own heat generation or environmental fluctuations, firmly "locking" the chip temperature at the target value and ensuring extreme stability under test conditions.

[0106] Based on the same inventive concept, embodiments of the present invention also provide an electronic device. Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of the present invention. Figure 5As shown, an embodiment of the present invention provides an electronic device including: one or more processors 101, a memory 102, and one or more I / O interfaces 103. The memory 102 stores one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the chip ATE test temperature control method as described in any of the above embodiments; the one or more I / O interfaces 103 are connected between the processor and the memory, configured to enable information interaction between the processor and the memory.

[0107] The processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus).

[0108] In some embodiments, the processor 101, memory 102, and I / O interface 103 are interconnected via bus 104, and thus connected to other components of the computing device.

[0109] In some embodiments, the one or more processors 101 include a field-programmable gate array.

[0110] This invention also provides a computer-readable medium. The computer-readable medium stores a computer program, which, when executed by a processor, implements the steps of any of the chip ATE test temperature control methods described in the above embodiments. The computer-readable storage medium can be volatile or non-volatile.

[0111] This invention also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is run in the processor of an electronic device, the processor in the electronic device executes the above-described chip ATE test temperature control method.

[0112] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0113] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0114] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0115] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0116] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0117] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0118] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0119] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0120] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0121] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for controlling the temperature of a chip ATE test, characterized in that, The method is performed in a test system comprising an automatic tester (ATE), a temperature acquisition and control card, a temperature control head located above the chip, and a temperature control socket located below the chip. The chip is mounted on the temperature control socket and fixed by pressure bonding via the temperature control head. The chip's wafer integrates a temperature sensing diode, and its IP core integrates a temperature sensing module. The method is executed by the temperature acquisition and control card, and includes: The temperature signals of the wafer temperature sensing diode and IP core temperature sensing module of the chip are collected in real time. Based on the received test project instructions, determine the reference source for temperature control; If the test item is a chip overall performance test, the temperature of the wafer temperature sensing diode is used as the reference temperature. The temperature control head and the temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the wafer temperature sensing diode reaches the first target temperature. The ATE is then linked to apply a test vector or current and voltage to the chip. If the test item is a chip IP core performance test, the temperature of the IP core temperature sensing module is used as the reference temperature. The temperature control head and the temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the IP core reaches the second target temperature. The ATE is then linked to apply a test vector to the chip's IP core.

2. The method according to claim 1, characterized in that, The bidirectional temperature regulation of the chip specifically includes the temperature acquisition and control card synchronously or asynchronously controlling the temperature control head and the temperature control socket to heat or cool.

3. The method according to claim 1, characterized in that, When the chip contains multiple IP cores, in response to a performance test command for a specific IP core, the temperature of the temperature sensing module of that specific IP core is used as the reference temperature.

4. The method according to claim 1, characterized in that, The first target temperature and the second target temperature are independently set temperature values; the range of the first target temperature and the second target temperature is -40℃ to 150℃.

5. The method according to claim 1, characterized in that, The chip is an automotive-grade SOC chip.

6. A method for controlling the temperature of a chip ATE test, characterized in that, The method is performed in a test system comprising an automatic tester (ATE), a temperature acquisition and control card, a temperature control head located above the chip, and a temperature control socket located below the chip. The chip is mounted on the temperature control socket and fixed by pressure bonding via the temperature control head. The chip's wafer integrates a temperature sensing diode, and its IP core integrates a temperature sensing module. The method is executed by the automated test equipment (ATE), including: The temperature acquisition and control card is issued test item instructions and target temperatures; the test item instructions include overall chip performance testing or chip IP core performance testing. During the test, the following temperature control results executed by the temperature acquisition and control card are received: In response to the overall chip performance test command, the temperature of the temperature sensing diode on the chip wafer is used as the reference temperature. The temperature control head and temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the temperature sensing diode on the wafer reaches the first target temperature. In response to the chip IP core performance test command, the temperature of the chip IP core's temperature sensing module is used as the reference temperature. The temperature control head and temperature control socket are controlled to perform bidirectional temperature adjustment on the chip so that the IP core reaches the second target temperature. Apply a test vector or current / voltage corresponding to the test item command to the chip, and collect the chip's test output.

7. A chip ATE test temperature control system, characterized in that, The system includes: An automated test equipment (ATE) is used to apply voltage, current, and test vectors to a chip, and to collect the voltage, current, and output vectors to determine the compliance of the test results. The temperature control socket is located below the chip and is used to support the chip and provide temperature control for the area below the chip. A temperature control head is positioned above the chip to press the chip and provide temperature control above the chip. A temperature acquisition and control card, located within the ATE or configured to communicate with the ATE, is configured to: acquire the temperatures of the wafer temperature sensing diode and the IP core temperature sensing module of the chip in real time; determine the reference source for temperature regulation based on test item instructions from the ATE; during overall chip performance testing, use the temperature of the wafer temperature sensing diode as the reference temperature to control the temperature control head and the temperature control socket to achieve a first target temperature for the wafer; and during chip IP core performance testing, use the temperature of the IP core temperature sensing module as the reference temperature to control the temperature control head and the temperature control socket to achieve a second target temperature for the IP core.

8. The system according to claim 7, characterized in that, The temperature acquisition and control card achieves bidirectional temperature regulation of the chip by controlling the temperature of the liquid flowing through the liquid cooling circuit in the temperature control head and controlling the thermoelectric modulator in the temperature control socket.

9. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 5.

10. A computer-readable medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 5.

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