Multi-sensor signal processing method based on FPGA common operator library

Abstract

The invention discloses a multi-sensor signal processing method based on an FPGA (Field Programmable Gate Array) common operator library, which constructs a three-layer software architecture of common operator library logic, algorithm acceleration control logic and application algorithm aiming at the problems of long dynamic reconfiguration time and low hardware resource utilization rate of the FPGA in the prior art. An FPGA dynamic partition is divided into a common operator library partition which is kept stable after being loaded and an algorithm acceleration control logic partition which can be quickly reconfigured, and a time-triggered scheduling mechanism is combined, so that only lightweight algorithm control logic needs to be dynamically configured during task switching; and thus, bottom-layer common computing resources can be reused by various heterogeneous algorithms such as radar pulse compression, infrared image filtering, integrated navigation and the like. According to the invention, the data volume and time of dynamic reconfiguration are reduced, microsecond-level switching is realized, the utilization rate of FPGA computing resources and the real-time performance of the system are improved, the flexibility and expandability of the system are enhanced, and the requirements of the unmanned system for high real-time performance, low power consumption and small size are met.

Description

Technical Field

[0001] This invention relates to the field of unmanned aerial vehicle signal processing technology, specifically to a multi-sensor signal processing method based on an FPGA common operator library. Background Technology

[0002] With the continuous development of unmanned aerial vehicle (UAV) technology, their mission scenarios are becoming increasingly complex, and the types and number of sensors they carry are also constantly increasing. Multiple sensors, such as radar, infrared imaging, inertial navigation, and satellite navigation, are working in concert, placing higher demands on the real-time performance, integration, power consumption, size, and cost of information processing platforms. Traditional UAV sensor processing systems typically employ a discrete computing architecture, equipping each sensor subsystem with an independent "DSP+FPGA" or dedicated computing unit. While this approach can meet the basic computing needs of each subsystem, it also leads to problems such as large system size, heavy weight, high power consumption, high cost, and poor scalability, making it difficult to adapt to the future trend of unmanned systems moving towards integration, software-based architecture, and low cost.

[0003] To improve system integration and resource utilization efficiency, heterogeneous computing architectures based on Field-Programmable Gate Arrays (FPGAs) are gradually becoming the mainstream solution. FPGAs possess advantages such as reconfigurability, strong parallel computing capabilities, and low latency, making them suitable for the high-efficiency computing needs of multi-sensor signal processing scenarios. In recent years, with the development of FPGA virtualization and dynamic partitioning technologies, by dividing the physical resources of an FPGA into multiple logically isolated dynamic partitions, parallel execution of multiple tasks and dynamic allocation of resources can be achieved, thereby improving resource reuse and system flexibility to a certain extent.

[0004] However, when applied to scenarios such as unmanned aerial vehicles (UAVs) with high requirements for real-time performance, power consumption, and integration, existing FPGA virtualization and dynamic partitioning solutions still have the following significant technical bottlenecks:

[0005] 1. Long loading time for dynamic partitions makes it difficult to meet the demands of high real-time tasks: In existing virtualization solutions, the reconfiguration process (i.e., bitstream loading) of FPGA partitions is time-consuming. For example, under 50MHz, 32-bit configuration bus conditions, loading 2MB of partition code typically takes about 10ms. This time far exceeds the response requirements of millisecond-level or even sub-millisecond-level tasks in high-speed unmanned aerial vehicles (such as the 5ms cycle of flight control tasks or the 20ms cycle of infrared target detection tasks), becoming a major bottleneck restricting the real-time performance of the system.

[0006] 2. Low hardware resource reuse efficiency and utilization needs improvement: Existing solutions typically require loading separate partitioned bitstreams containing complete computational logic for different functions, resulting in the inability of underlying computing resources (such as DSP slices) to be effectively shared between different tasks. A large number of computing units cannot be reused in partitions, leading to resource idleness and redundant configuration, thus limiting the overall utilization of hardware resources.

[0007] 3. High functional coupling, resulting in insufficient system flexibility and scalability: Traditional FPGA acceleration designs typically tightly bind specific algorithms with their corresponding control logic, forming highly coupled hardware modules. When the algorithm needs to be updated or task requirements change, it is often necessary to redesign, compile, and load the entire FPGA logic. This not only leads to a long development cycle but also makes it difficult to achieve rapid dynamic reconfiguration during operation, resulting in poor overall system flexibility and maintainability.

[0008] 4. High system size, power consumption and cost: Although the discrete "DSP+FPGA" architecture can meet basic processing requirements, it brings obvious problems of size redundancy, increased power consumption and increased cost, which limits its large-scale application in low-cost, lightweight unmanned systems.

[0009] In summary, existing FPGA virtualization and dynamic partitioning technologies still suffer from significant drawbacks when applied to high real-time, low-power, and integrated applications of multi-sensor signal processing in unmanned aerial vehicles (UAVs). These drawbacks include long reconfiguration times, low resource reuse rates, insufficient system flexibility, and high overall costs. Therefore, there is an urgent need in this field for a novel processing architecture and method that can effectively shorten configuration time, improve hardware resource reuse rates, enable flexible task scheduling, and reduce system costs. This will drive the development of unmanned system information processing platforms towards higher integration, stronger real-time performance, and better scalability. Summary of the Invention

[0010] To address the problems of existing FPGA virtualization and dynamic partitioning technologies, this invention proposes a multi-sensor signal processing method based on an FPGA common operator library. This method combines an innovative software architecture with an FPGA dynamic partitioning strategy to achieve rapid reconfiguration and efficient reuse of hardware resources. The method constructs a three-layer software architecture: "common operator library logic + algorithm acceleration control logic + application algorithm." Logically, the FPGA dynamic partitioning is divided into a common operator library partition with large storage capacity and stable operation after loading, and an algorithm acceleration control logic partition with small storage capacity and rapid dynamic reconfiguration. During task switching, only the lightweight control logic needs to be reconfigured, achieving lightweight and rapid dynamic reuse of FPGA computing resources. This significantly shortens configuration time and decouples computing tasks from hardware resources, enabling the underlying common computing resources to be shared by various heterogeneous algorithms. This supports integrated and high-efficiency processing of multi-sensor tasks for unmanned aerial vehicles.

[0011] The technical solution of this invention is as follows:

[0012] A multi-sensor signal processing method based on an FPGA common operator library is applied to an integrated computing platform containing a multi-core processor and an FPGA, wherein the logic resources of the FPGA are divided into multiple dynamic partitions; the method includes the following steps:

[0013] Step S1: Construct a three-layer software architecture, which includes a bottom layer of FPGA common operator library logic layer, a middle layer of algorithm acceleration control logic layer, and a top layer of application algorithm layer;

[0014] Common Operator Library Logic Layer: Encapsulates and provides reusable basic hardware computing units, such as massively parallel floating-point multiply-accumulator arrays.

[0015] Algorithm acceleration control logic layer: Contains control and scheduling logic for specific algorithms, used to organize and call common operators at the lower level to complete the full algorithm function, such as FFT / IFFT, Gaussian filtering, Kalman filtering matrix operations, etc.

[0016] Application algorithm layer: Runs on a multi-core processor, implements business logic and calls the hardware acceleration functions of the lower layer.

[0017] Step S2: Logically divide the dynamic partition of the FPGA into a common operator library partition and an algorithm acceleration control logic partition; wherein, the common operator library partition encapsulates and provides reusable basic hardware computing units, and the algorithm acceleration control logic partition deploys and calls the algorithm control logic of the basic hardware computing units;

[0018] Specifically, the common operator library partition is used to deploy the common operator library logic. It has a large storage capacity and contains numerous computing units, such as a DSP48E array. After being loaded at the beginning of a task scheduling cycle, this partition remains stable for several subsequent cycles without frequent reconfiguration. The algorithm acceleration control logic partition is used to deploy the algorithm acceleration control logic. It has a smaller storage capacity and mainly contains control flow and state machines. This partition can be quickly and dynamically reconfigured in different time slots according to task requirements.

[0019] Step S3: At the start of a task scheduling cycle, load the application task for the specified processor core and configure the required common operator library logic for the FPGA dynamic partition bound to it.

[0020] By analyzing the computational characteristics of typical multi-sensor task algorithms for unmanned aerial vehicles, such as radar pulse compression, infrared image filtering, and integrated navigation filtering, common computational patterns centered on floating-point multiplication and addition are extracted, thereby designing and hardware-implementing two types of common operators:

[0021] Massive parallel double-precision floating-point multiply-accumulate logic, such as an integrated array of 32 double-precision floating-point multipliers;

[0022] Massive parallel single-precision floating-point multiply-accumulate logic, such as an integrated array of 64 single-precision floating-point multipliers;

[0023] Design standardized interfaces for the aforementioned operators, such as the AXI bus interface and command / semaphore mechanism, and deploy them in the common operator library partition.

[0024] Step S4: In the subsequent time slot of the task scheduling cycle, run the application task on the processor core, and dynamically configure the algorithm acceleration control logic that matches the current task stage for the corresponding FPGA dynamic partition, so as to call the configured common operator library logic to execute the signal processing task.

[0025] In steps S3 and S4, a time-triggered dynamic scheduling mechanism is adopted to divide the unmanned aerial vehicle (UAV) mission into different stages (such as startup, takeoff, autonomous flight, and terminal guidance). A static scheduling table is generated for each stage, dividing a scheduling cycle into multiple time slots: in the first time slot, the application task is loaded for the specified processor core, and the required common operator library logic is configured for the FPGA dynamic partition bound to it; in subsequent time slots, the application task on the processor core is run according to the scheduling table, and the algorithm acceleration control logic matching the current task stage is dynamically configured for its corresponding FPGA partition, such as FFT control logic and Gaussian filter control logic. Through the above time-division multiplexing mechanism, the efficient and orderly reuse of the same set of FPGA underlying computing resources for heterogeneous sensor algorithms such as radar, infrared, and navigation is achieved.

[0026] In a further preferred embodiment, in step S1, the FPGA common operator library logic layer includes hardware logic for implementing large-scale parallel floating-point multiply-accumulate operations; the algorithm acceleration control logic layer includes control logic for implementing at least one of the following algorithms: radar pulse compression FFT / IFFT, infrared image preprocessing Gaussian filtering, and combined navigation Kalman filter matrix operation; and the application algorithm layer runs on the multi-core processor.

[0027] In a further preferred embodiment, the FPGA common operator library logic layer specifically includes: massively parallel double-precision floating-point multiply-accumulate logic, which integrates multiple double-precision floating-point multiplier arrays; and massively parallel single-precision floating-point multiply-accumulate logic, which integrates multiple single-precision floating-point multiplier arrays.

[0028] In a further preferred embodiment, the common operator library partition includes a first partition and a second partition. The first partition is deployed with the massively parallel double-precision floating-point multiply-accumulate logic, and the second partition is deployed with the massively parallel single-precision floating-point multiply-accumulate logic and an FFT core computing kernel built based on the single-precision floating-point multiply-accumulate logic.

[0029] A further preferred embodiment includes the following steps for performing radar pulse compression FFT operations based on the aforementioned common operator library:

[0030] a) Configure the FFT algorithm control logic in the algorithm acceleration control logic partition;

[0031] b) The FFT algorithm control logic decomposes the FFT operation into multi-level butterfly operations;

[0032] c) For each level of butterfly operation, the FFT core computing core in the second partition is called to perform complex multiplication operations in parallel using its integrated single-precision floating-point multiplier array;

[0033] d) Rearrange the input and output data of each operation according to the preset mapping relationship to complete the FFT calculation.

[0034] A further preferred embodiment includes the following steps for performing Gaussian filtering on infrared images based on the common operator library:

[0035] a) Configure Gaussian filter algorithm control logic in the algorithm acceleration control logic partition;

[0036] b) The Gaussian filtering algorithm control logic reads the image convolution window data from memory;

[0037] c) Call the massively parallel single-precision floating-point multiply-accumulate logic in the second partition to calculate the weighted sum of each pixel in the convolution window in parallel;

[0038] d) Output the filtered pixel data and slide the window until the entire image has been processed.

[0039] In a further preferred embodiment, the dynamic configuration in steps S3 and S4 is implemented based on a time-triggered scheduling mechanism. The method further includes: pre-generating a static scheduling table according to the mission phase of the unmanned aerial vehicle, wherein the scheduling table divides a scheduling cycle into multiple time slots; the mission phase includes at least an autonomous flight phase and a terminal guidance phase; in the autonomous flight phase, a radar signal processing task is scheduled, and the corresponding FPGA dynamic partition is configured for FFT / IFFT algorithm control logic; in the terminal guidance phase, an infrared image processing task is scheduled, and the corresponding FPGA dynamic partition is configured for Gaussian filter algorithm control logic.

[0040] In a further preferred embodiment, one processor core in the multi-core processor serves as the main system controller, used to switch the static scheduling table and send task scheduling instructions; the processor core communicates with the FPGA dynamic partition via an AXI bus interface for command and data exchange.

[0041] In addition, the present invention also proposes an electronic device and a computer-readable storage medium.

[0042] An electronic device is characterized in that it comprises: a multi-core processor, an FPGA, and a memory; the logic resources of the FPGA are divided into multiple dynamic partitions, including at least one common operator library partition and at least one algorithm acceleration control logic partition; the memory stores a computer program, which, when executed by the multi-core processor, implements the above-described method.

[0043] A computer-readable storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it implements the above-described method.

[0044] Beneficial effects

[0045] Compared with the prior art, the technical solution provided by the present invention has the following significant advantages:

[0046] 1. Extremely high real-time performance: By simplifying the reconfiguration object from complete algorithm logic to lightweight control logic, the amount of data and time for dynamic reconfiguration are reduced by several orders of magnitude, from milliseconds to hundreds of microseconds, which can meet the strong real-time task switching and response requirements of unmanned systems.

[0047] 2. High resource reuse rate: The common operator library (such as multiply-accumulator array) in this invention serves as a general computing resource that can be shared by algorithms from completely different fields such as radar signal processing, infrared image processing, and integrated navigation calculation. This greatly improves the utilization rate of FPGA underlying dedicated computing resources (such as DSP Slice) and avoids resource idleness.

[0048] 3. Excellent flexibility and scalability: The three-layer architecture proposed in this invention decouples the computational core (common operators) from the algorithm control core. When adding or modifying algorithms, only the corresponding algorithm acceleration control logic needs to be designed or updated, without modifying the underlying common operator library, which significantly improves the system's flexibility and maintainability and shortens the development cycle.

[0049] 4. Low power consumption and miniaturization: This invention uses an integrated computing platform to replace multiple discrete "DSP+FPGA" processing units. Through resource sharing and efficient scheduling, the overall size, weight and power consumption of the system are significantly reduced, which is more in line with the requirements of future unmanned systems for low cost and high integration.

[0050] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0051] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0052] Figure 1 This is a diagram of a three-tier software architecture.

[0053] Figure 2 It is a time-sharing sequence diagram of different tasks being deployed and run in a time-sharing manner.

[0054] Figure 3 This is a schematic diagram of the principle of a matched filter in pulse compression.

[0055] Figure 4 This is a schematic diagram illustrating the principle of butterfly operations in the FFT algorithm.

[0056] Figure 5 This is a mapping diagram of the input and output relationships for each butterfly operation in a 32-point FFT operation.

[0057] Figure 6 This is a schematic diagram illustrating the principle of the Gaussian filtering algorithm for infrared images. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the specific embodiments of this invention will be described in detail below with reference to the accompanying drawings and examples. It should be noted that the following description is based on preferred embodiments of the core ideas of this invention and is not intended to limit the scope of protection of this invention.

[0059] This embodiment uses an integrated system-on-a-chip (SoC) (FMQL100TAI) that integrates a multi-core ARM processor and an FPGA as the hardware platform. The ARM side runs a real-time operating system (such as Tianmai or Yihui) and is responsible for upper-layer application scheduling and system management; the programmable logic resources on the FPGA side are pre-divided into multiple independent logic regions through dynamic partitioning technology.

[0060] Based on the above hardware platform, the multi-sensor signal processing method based on an FPGA common operator library used in this embodiment includes the following steps:

[0061] Step S1: Construct a three-layer software architecture, which includes a bottom layer of FPGA common operator library logic layer, a middle layer of algorithm acceleration control logic layer, and a top layer of application algorithm layer.

[0062] Step S2: Logically divide the dynamic partition of the FPGA into a common operator library partition and an algorithm acceleration control logic partition.

[0063] like Figure 1 As shown, a common operator library logic layer and an algorithm acceleration control logic layer are deployed on the FPGA side:

[0064] Common Operator Library Logic Layer: Two large dynamic partitions are created on the FPGA as common operator library partitions.

[0065] Partition A: Deploys "massive parallel double-precision floating-point multiply-accumulate logic". This logic integrates an array of 32 parallel double-precision floating-point multipliers, occupying a total of 576 DSP48E units, and is dedicated to high-precision navigation filtering and other calculations.

[0066] Partition B: Deploys "massively parallel single-precision floating-point multiply-accumulate logic" and a "32-point FFT core (FFT_COMPUTER_CORE)". The single-precision multiply-accumulate logic integrates an array of 64 parallel single-precision floating-point multipliers, occupying 64 DSP48E units. FFT_COMPUTER_CORE implements... Figure 4 The butterfly arithmetic unit shown can perform 64 complex multiplication operations in parallel at once by calling the single-precision multiplier resources within the partition. These two operators provide services externally through a standardized AXI interface and command / semaphore mechanism.

[0067] Algorithm acceleration control logic layer: Three smaller dynamic partitions are created on the FPGA as algorithm acceleration control logic partitions.

[0068] Partition C: Deploy the "Combined Navigation Kalman Filter Matrix Multiplication Control Logic".

[0069] Partition D: Deploy "Radar Pulse Compression FFT / IFFT Control Logic".

[0070] Partition E: Deploy the "Infrared Image Preprocessing Gaussian Filter Control Logic".

[0071] These control logic partitions do not contain a large number of computational units, but only state machines, data flow control, and interface logic for calling the underlying common operator library. Therefore, the bitstream file size is small and can be quickly reconfigured.

[0072] Deploying the application algorithm layer on the ARM side:

[0073] Various sensor signal processing application software, such as radar pulse compression applications, infrared image target detection applications, and integrated navigation solution applications, are developed and run on the ARM processor core. These programs call the corresponding algorithms on the FPGA through driver interfaces to accelerate the control logic.

[0074] Step S3: At the start of a task scheduling cycle, load the application task for the specified processor core and configure the required common operator library logic for the FPGA dynamic partition bound to it.

[0075] Step S4: In the subsequent time slot of the task scheduling cycle, run the application task on the processor core, and dynamically configure the algorithm acceleration control logic that matches the current task stage for the corresponding FPGA dynamic partition, so as to call the configured common operator library logic to execute the signal processing task.

[0076] refer to Figure 2 The time-sharing deployment sequence diagram shown below illustrates the system scheduling process as follows:

[0077] Scheduling Tables and Phase Division: The system's main controller (usually running on ARM core 0) pre-sets multiple static scheduling tables based on the UAV mission profile (e.g., MODEL0 corresponds to the autonomous flight phase, MODEL1 corresponds to the terminal guidance phase). Each scheduling table divides a scheduling cycle into multiple fixed-length time slots (e.g., T0, T1, T2...).

[0078] Initialization phase (first scheduling cycle T0): During the first scheduling cycle after system startup or task phase switch:

[0079] The main controller loads the corresponding application task software (such as radar signal processing program) for the specified ARM core (e.g., core 1) according to the current scheduling table.

[0080] Simultaneously, through a dynamic partitioning controller, corresponding bitstreams (such as single-precision floating-point multiply-accumulate and FFT core computation cores) are configured for FPGA common operator library partitions (e.g., partition B) bound to this ARM core. This configuration involves a large amount of data, but is only executed once at the beginning of the phase.

[0081] Task loop execution phase (subsequent time slots T1, T2...):

[0082] At a predetermined time slot (e.g., T1), ARM core 1 begins executing its application task. Simultaneously, the system dynamically reconfigures a lightweight bitstream of "1K-point FFT control logic" for its corresponding FPGA algorithm control logic partition (e.g., partition D). Since this bitstream contains only control code, the loading time is extremely short, reaching the level of hundreds of microseconds.

[0083] After the FFT control logic runs, it acquires radar echo data from the ARM terminal via the AXI bus and calls the "FFT_COMPUTER_CORE" common operator, which has been stably stored in partition B, to complete 5 levels of butterfly operations (such as...). Figure 5 The input / output mapping shown in the diagram enables pulse compression. The result is returned to ARM core 1 via the AXI bus.

[0084] In the next time slot (e.g., T2), the scheduler switches to the infrared processing task. ARM core 2 runs the infrared application, while FPGA partition E is quickly reconfigured as "Gaussian filter control logic". This control logic calls the single-precision floating-point multiply-accumulate operator in partition B to perform a 3x3 convolution filter on the infrared image. The processed image can then be delivered to the AI ​​accelerator for subsequent target recognition.

[0085] The following is an example of how key algorithms are mapped in the architecture:

[0086] 1. For example Figures 3-5 As shown, the implementation process of radar pulse compression (FFT algorithm) is as follows:

[0087] Hardware platform: FMQL100TAI is used. Its ARM side runs a real-time operating system, and the FPGA side logic resources are partitioned. The common operator library partition is configured as a hardware macro containing 1024 parallel single-precision floating-point multipliers.

[0088] The application layer (ARM core 1) initiates a pulse compression task, sequentially calling FFT, frequency domain multiplication, and IFFT;

[0089] When FFT is invoked, the algorithm acceleration control logic (partition D) is activated; its internal state machine performs the following operations: decomposes the 1K-point data into 32-point data blocks; calls "FFT_COMPUTER_CORE" in partition B five times in a loop; after each call, based on... Figure 5 The mapping relationship is used to rearrange the data until all FFT calculations are completed.

[0090] In this process, all core complex multiplication operations are performed in parallel by 512 pre-loaded single-precision multipliers fixed in partition B, realizing the reuse of computing resources.

[0091] 2. For example Figure 6 As shown, the implementation process of Gaussian filtering for infrared images is as follows:

[0092] During the final guidance phase, the application layer (ARM core 2) initiates an infrared image preprocessing request.

[0093] After the algorithm acceleration control logic (partition E) is configured, the following process is executed: read the 3x3 image window data from memory; organize the 9 pixel data and Gaussian kernel coefficients into multiply-add pairs; call the single-precision floating-point multiply-add operator in partition B to calculate the weighted sum in parallel; output the convolution result and slide the window until the entire image is processed.

[0094] Furthermore, this embodiment also provides an example of dynamic scheduling in multiple task phases:

[0095] The system dynamically schedules different combinations of hardware and software based on the flight mission phase:

[0096] Startup phase: Deploy minimal FPGA logic, including only bus interface control such as 1553B, and initialize system communication.

[0097] Flight Prep Phase: The main controller loads the flight prep schedule. In slot T0, the navigation program is loaded for ARM core 3, and double-precision floating-point multiply-accumulate logic is configured for FPGA partition A. In slot T1, the navigation task is run, and Kalman filter control logic is configured for partition C to process inertial navigation / satellite navigation data.

[0098] Autonomous flight phase: Load single-precision floating-point multiply-accumulate logic and FFT control logic to process radar echo signals in real time.

[0099] Terminal guidance phase: Deploy Gaussian filter control logic to perform infrared image preprocessing and target recognition.

[0100] As can be seen from the above specific implementation methods, this invention, through the design of "fixed common operator library and dynamic algorithm control logic," combined with strict time-triggered scheduling, solves the problems of long FPGA reconfiguration time and inability to share resources, achieving high real-time and high-efficiency processing of multi-sensor heterogeneous algorithms on an integrated hardware platform. The method described in this invention is not limited to the radar, infrared, and navigation applications described in the embodiments; its layered decoupling concept is also applicable to other heterogeneous computing scenarios requiring FPGA acceleration.

[0101] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A multi-sensor signal processing method based on an FPGA common operator library, characterized in that, An integrated computing platform comprising a multi-core processor and an FPGA, wherein the logic resources of the FPGA are divided into multiple dynamic partitions; the method includes the following steps: Step S1: Construct a three-layer software architecture, which includes a bottom layer of FPGA common operator library logic layer, a middle layer of algorithm acceleration control logic layer, and a top layer of application algorithm layer; Step S2: Logically divide the dynamic partition of the FPGA into a common operator library partition and an algorithm acceleration control logic partition; wherein, the common operator library partition is used to encapsulate and provide reusable basic hardware computing units, and the algorithm acceleration control logic partition is used to deploy and call the algorithm control logic of the basic hardware computing units. Step S3: At the start of a task scheduling cycle, load the application task for the specified processor core and configure the required common operator library logic for the FPGA dynamic partition bound to it. Step S4: In the subsequent time slot of the task scheduling cycle, run the application task on the processor core, and dynamically configure the algorithm acceleration control logic that matches the current task stage for the corresponding FPGA dynamic partition, so as to call the configured common operator library logic to execute the signal processing task.

2. The method according to claim 1, characterized in that, In step S1, the FPGA common operator library logic layer includes hardware logic for implementing large-scale parallel floating-point multiply-accumulate operations; the algorithm acceleration control logic layer includes control logic for implementing at least one of the following algorithms: radar pulse compression FFT and IFFT, infrared image preprocessing Gaussian filtering, and combined navigation Kalman filter matrix operation; the application algorithm layer runs on the multi-core processor.

3. The method according to claim 2, characterized in that, The FPGA common operator library logic layer specifically includes: massively parallel double-precision floating-point multiply-accumulate logic, which integrates multiple double-precision floating-point multiplier arrays; and massively parallel single-precision floating-point multiply-accumulate logic, which integrates multiple single-precision floating-point multiplier arrays.

4. The method according to claim 3, characterized in that, The common operator library partition includes a first partition and a second partition. The first partition is equipped with the massively parallel double-precision floating-point multiply-accumulate logic, and the second partition is equipped with the massively parallel single-precision floating-point multiply-accumulate logic and the FFT core computing core built based on the single-precision floating-point multiply-accumulate logic.

5. The method according to claim 4, characterized in that, The steps for performing radar pulse compression FFT based on the aforementioned common operator library include: a) Configure the FFT algorithm control logic in the algorithm acceleration control logic partition; b) The FFT algorithm control logic decomposes the FFT operation into multi-level butterfly operations; c) For each level of butterfly operation, the FFT core computing core in the second partition is called to perform complex multiplication operations in parallel using its integrated single-precision floating-point multiplier array; d) Rearrange the input and output data of each operation according to the preset mapping relationship to complete the FFT calculation.

6. The method according to claim 4, characterized in that, The steps for performing Gaussian filtering on infrared images based on the aforementioned common operator library include: a) Configure Gaussian filter algorithm control logic in the algorithm acceleration control logic partition; b) The Gaussian filtering algorithm control logic reads the image convolution window data from memory; c) Call the massively parallel single-precision floating-point multiply-accumulate logic in the second partition to calculate the weighted sum of each pixel in the convolution window in parallel; d) Output the filtered pixel data and slide the window until the entire image has been processed.

7. The method according to claim 1, characterized in that, The dynamic configuration in steps S3 and S4 is implemented based on a time-triggered scheduling mechanism. The method further includes: pre-generating a static scheduling table according to the mission phase of the unmanned aerial vehicle, wherein the scheduling table divides a scheduling cycle into multiple time slots; the mission phase includes at least an autonomous flight phase and a terminal guidance phase; in the autonomous flight phase, a radar signal processing task is scheduled, and the corresponding FPGA dynamic partition is configured for FFT and IFFT algorithm control logic; in the terminal guidance phase, an infrared image processing task is scheduled, and the corresponding FPGA dynamic partition is configured for Gaussian filter algorithm control logic.

8. The method according to claim 7, characterized in that, One of the processor cores in the multi-core processor acts as the main system controller, used to switch the static scheduling table and send task scheduling instructions; the processor core communicates with the FPGA dynamic partition via an AXI bus interface for command and data communication.

9. An electronic device, characterized in that, include: The system comprises a multi-core processor, an FPGA, and a memory; the logic resources of the FPGA are divided into multiple dynamic partitions, including at least one common operator library partition and at least one algorithm acceleration control logic partition; the memory stores a computer program, which, when executed by the multi-core processor, implements the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 8.

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