Data processing method, nonvolatile memory module and nonvolatile memory

Abstract

The invention provides a data processing method, a non-volatile memory module and a non-volatile memory, and the method comprises the steps: after re-electrification, a fifth switch element and a sixth switch element input high levels, and pre-charging signals input by a seventh switch element and an eighth switch element are high levels, so as to carry out charging; the fifth switch element and the sixth switch element are kept at high levels, the seventh switch element and the eighth switch element are suspended, write enable signals input by the seventh switch element and the eighth switch element are at high levels, control signals input by the ninth switch element and the tenth switch element are at high levels, and write enable signals input by the ninth switch element and the tenth switch element are at high levels. The ninth switch element and the tenth switch element input low level so as to read data; and configurable grounding signals input by the fifth switch element and the sixth switch element are low levels, so that the volatile storage unit latches the read data. According to the data processing method, the nonvolatile storage module and the nonvolatile memory provided by the embodiment of the invention, the reliability of data recovery is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a data processing method, a non-volatile memory module, and a non-volatile memory. Background Technology

[0002] Non-volatile static random access memory (NV-SRAM). By combining SRAM with non-volatile memory, the high-speed characteristics of SRAM are maintained while data non-volatility is achieved, thus improving storage reliability.

[0003] Magnetic random access memory (MRAM) stores data based on the resistance changes of a magnetic tunnel junction (MTJ). For NV-SRAM combined with MRAM, data stored in the SRAM is transferred to the non-volatile MTJ before power is turned off, and the data in the MTJ is restored to the SRAM after power is restored, thus realizing NV-SRAM data storage. Since magnetoresistive non-volatile static random access memory (MNV-SRAM) lacks an external read circuit, its data recovery process directly reads the resistance state of the MTJ during the SRAM's power-on process. However, when the voltage difference between the two nodes of the SRAM decreases, the read margin diminishes, making it susceptible to interference from non-ideal factors in the circuit, leading to read failures and a significantly increased data recovery error rate.

[0004] Therefore, how to solve the problem of high data recovery error rate in current NV-SRAM data recovery has become an important research topic in this field. Summary of the Invention

[0005] To address the problems in the prior art, embodiments of the present invention provide a data processing method, a non-volatile storage module, and a non-volatile memory, which can at least partially solve the problems existing in the prior art.

[0006] In a first aspect, the present invention proposes a data processing method applied to a non-volatile storage module, wherein the non-volatile storage module includes volatile storage units and non-volatile storage units, wherein:

[0007] The volatile memory unit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a first node, and a second node. The control terminal of the first switching element is used to input a write signal, and its first terminal is used to input a bit line signal. The second terminal of the first switching element is connected to the first node. The control terminal of the second switching element is used to input a write signal, and its first terminal is connected to the second node. The second terminal of the first switching element is also used to input a complementary bit line signal. The first terminals of the third and fourth switching elements are connected to a high level. The second terminal of the third switching element is connected to the first node, and its control terminal is connected to the second node. The second terminal of the fourth switching element is connected to the second node, and its control terminal is connected to the first node. The first terminal of the fifth switching element is connected to the first node, and its control terminal is connected to the second node. The first terminal of the sixth switching element is connected to the second node, and its control terminal is connected to the first node.

[0008] The non-volatile memory cell includes a seventh switching element, an eighth switching element, a ninth switching element, a tenth switching element, a first magnetic tunnel junction, and a second magnetic tunnel junction. The first terminals of the seventh and eighth switching elements are used to input a precharge signal. The second terminal of the seventh switching element is connected to the first terminal of the first magnetic tunnel junction. The control terminals of the seventh and eighth switching elements are used to input a write enable signal. The second terminal of the eighth switching element is connected to the first terminal of the second magnetic tunnel junction. The control terminals of the ninth and tenth switching elements are used to input a control signal. The first terminal of the ninth switching element is connected to the third terminal of the first magnetic tunnel junction. The second terminals of the ninth and tenth switching elements are used to input a bias signal. The first terminal of the tenth switching element is connected to the third terminal of the second magnetic tunnel junction. The second terminal of the first magnetic tunnel junction is connected to the first node, and the second terminal of the second magnetic tunnel junction is connected to the second node.

[0009] The method includes:

[0010] After the non-volatile storage module is powered on again, the configurable ground signal input to the second terminal of the fifth switch element and the second terminal of the sixth switch element is at a high level, and the pre-charge signal input to the first terminal of the seventh switch element and the first terminal of the eighth switch element is at a high level, so as to charge the first node and the second node.

[0011] The second terminals of the fifth and sixth switching elements are kept at a high level, the first terminals of the seventh and eighth switching elements are left floating, the write enable signals input to the control terminals of the seventh and eighth switching elements are at a high level, the control signals input to the control terminals of the ninth and tenth switching elements are at a high level, and the bias signals input to the second terminals of the ninth and tenth switching elements are at a low level, so as to read the data stored in the first and second magnetic tunnel junctions;

[0012] When the configurable ground signal input to the second terminal of the fifth switching element and the second terminal of the sixth switching element is low, the volatile memory cell latches the data read from the first magnetic tunnel junction and the second magnetic tunnel junction.

[0013] Furthermore, the data processing method provided in this embodiment of the invention also includes:

[0014] The write signal input to the control terminal of the first switch element and the control terminal of the second switch element is low level, the write enable signal input to the control terminal of the seventh switch element and the control terminal of the eighth switch element is low level, the first terminal of the seventh switch element and the first terminal of the eighth switch element input a first level, and the bias signal input to the second terminal of the ninth switch element and the second terminal of the tenth switch element is a second level, so as to store the data in the volatile memory cell into the first magnetic tunnel junction and the second magnetic tunnel junction of the non-volatile memory cell.

[0015] Furthermore, the first voltage level is lower than the high voltage level and higher than the low voltage level; the second voltage level is a negative voltage.

[0016] Furthermore, the data processing method provided in this embodiment of the invention also includes:

[0017] Power is turned off on the non-volatile memory module, causing it to enter standby mode.

[0018] Furthermore, the data processing method provided in this embodiment of the invention also includes:

[0019] The control signals input to the control terminals of the ninth and tenth switching elements are at a low level, the write signals input to the control terminals of the first and second switching elements are at a high level, and the write enable signals input to the control terminals of the seventh and eighth switching elements are at a high level, thus putting the non-volatile memory module into static random access memory mode.

[0020] In a second aspect, the present invention provides a non-volatile storage module, comprising volatile storage units and non-volatile storage units, wherein:

[0021] The volatile storage unit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a first node, and a second node;

[0022] The control terminal of the first switching element is used to input a write signal, the first terminal of the first switching element is used to input a bit line signal, the second terminal of the first switching element is connected to the first node, the control terminal of the second switching element is used to input a write signal, the first terminal of the second switching element is connected to the second node, and the second terminal of the first switching element is used to input a complementary bit line signal.

[0023] The first terminal of the third switching element and the first terminal of the fourth switching element are connected to a high level. The second terminal of the third switching element is connected to the first node, and the control terminal of the third switching element is connected to the second node. The second terminal of the fourth switching element is connected to the second node, and the control terminal of the fourth switching element is connected to the first node.

[0024] The first end of the fifth switching element is connected to the first node, the control end of the fifth switching element is connected to the second node, the first end of the sixth switching element is connected to the second node, and the control end of the sixth switching element is connected to the first node.

[0025] The non-volatile memory cell includes a seventh switching element, an eighth switching element, a ninth switching element, a tenth switching element, a first magnetic tunnel junction, and a second magnetic tunnel junction;

[0026] The first terminal of the seventh switching element and the first terminal of the eighth switching element are used to input a precharge signal. The second terminal of the seventh switching element is connected to the first terminal of the first magnetic tunnel junction. The control terminal of the seventh switching element and the control terminal of the eighth switching element are used to input a write enable signal. The second terminal of the eighth switching element is connected to the first terminal of the second magnetic tunnel junction.

[0027] The control terminals of the ninth and tenth switching elements are used to input control signals. The first terminal of the ninth switching element is connected to the third terminal of the first magnetic tunnel junction. The second terminals of the ninth and tenth switching elements are used to input bias signals. The first terminal of the tenth switching element is connected to the third terminal of the second magnetic tunnel junction.

[0028] The second end of the first magnetic tunnel junction is connected to the first node, and the second end of the second magnetic tunnel junction is connected to the second node.

[0029] Furthermore, the first magnetic tunnel junction and the second magnetic tunnel junction are voltage-controlled spin-orbit torque magnetic tunnel junctions.

[0030] Furthermore, the resistance of the pressure-controlled spin-orbit torque magnetic tunnel junction is greater than 1 kΩ and less than 10 MΩ.

[0031] Thirdly, the present invention provides a non-volatile memory, comprising an array of multiple non-volatile memory modules as described in any of the above embodiments.

[0032] Fourthly, the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor and / or the memory includes a non-volatile memory module as described in any of the above embodiments.

[0033] The data processing method, non-volatile storage module, and non-volatile memory provided in this embodiment of the invention, after the non-volatile storage module is powered on again, the configurable ground signal input to the second terminal of the fifth switch element and the second terminal of the sixth switch element is at a high level, and the pre-charge signal input to the first terminal of the seventh switch element and the first terminal of the eighth switch element is at a high level, so as to charge the first node and the second node; the second terminal of the fifth switch element and the second terminal of the sixth switch element remain at a high level, and the first terminal of the seventh switch element and the first terminal of the eighth switch element are floating, and the seventh switch element's... The write enable signal input to the control terminal and the control terminal of the eighth switching element is high, the control signal input to the control terminal of the ninth switching element and the control terminal of the tenth switching element is high, and the bias signal input to the second terminal of the ninth switching element and the second terminal of the tenth switching element is low, so as to read the data stored in the first magnetic tunnel junction and the second magnetic tunnel junction; the configurable ground signal input to the second terminal of the fifth switching element and the second terminal of the sixth switching element is low, so that the volatile memory cell latches the data read from the first magnetic tunnel junction and the second magnetic tunnel junction, providing high reliability of data recovery. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0035] Figure 1This is a schematic diagram of the structure of a non-volatile memory module provided in an embodiment of the present invention.

[0036] Figure 2 This is a schematic flowchart of a data processing method provided in an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of the physical structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0039] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0040] In-plane magnetic anisotropic tunnel junction (I-MTJ): A type of magnetic tunnel junction based on in-plane anisotropic magnetic tunnel junction.

[0041] Magnetoresistive nonvolatile static random access memory: a nonvolatile static random access memory that uses MTJ as the nonvolatile backup data device.

[0042] Spin-Transfer Torque (STT): A technique that enables the magnetic moment of a magnetic tunnel junction device to be flipped.

[0043] Spin-Orbit Torque (SOT): A technique where a heavy metal layer exists beneath a magnetic tunnel junction, and the magnetic moment of the junction is reversed when current flows through the heavy metal layer.

[0044] Voltage-Controlled Magnetic Anisotropy (VCMA): Applying VCMA technology to SOT-MTJ can reduce the switching barrier of the MTJ, thereby reducing the switching current and increasing the switching speed.

[0045] Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction (VG-SOT MTJ): Combines spin-orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA) effects to achieve more efficient storage and computing capabilities.

[0046] Data backup (Store): In NV-SRAM, the process of storing data from SRAM into MTJ.

[0047] Data recovery (Restore): In NV-SRAM, this is the process of restoring data from the MTJ to the SRAM. Since NV-SRAM lacks external read circuitry, its data recovery process essentially involves directly reading the MTJ resistance state during the SRAM's power-on process. This method works well when the MTJ resistance is low, but as the MTJ resistance increases, the difference between it and the on-resistance of the transistors in the circuit widens, leading to a decrease in the voltage difference between the two SRAM nodes. This reduces the read margin and makes the system more susceptible to interference from non-ideal factors in the circuit, causing read failures and significantly increasing the data recovery error rate. For NV-SRAM, a recovery error rate exceeding 1% is unacceptable.

[0048] Therefore, this invention proposes a data processing method that improves upon current NV-SRAM data recovery schemes. By reusing some transistors in the 6T-SRAM and write path, a three-step data recovery strategy of pre-charging, reading data, and latching is implemented without increasing the number of transistors. This solves the problem that the error rate of MNV-SRAM data recovery is affected by MTJ resistance and process fluctuations, reduces the error rate of data recovery, and improves the reliability of data recovery.

[0049] Figure 1 This is a schematic diagram of the structure of a non-volatile memory module provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the non-volatile storage module provided in this embodiment of the invention includes a volatile storage unit 100 and a non-volatile storage unit 200, wherein:

[0050] The volatile storage unit 100 includes a first switching element N3, a second switching element N4, a third switching element P1, a fourth switching element P2, a fifth switching element N1, a sixth switching element N2, a first node Q, and a second node QB;

[0051] The control terminal of the first switching element N3 is used to input the write signal WL, the first terminal of the first switching element N3 is used to input the bit line signal BL, the second terminal of the first switching element N3 is connected to the first node Q, the control terminal of the second switching element N4 is used to input the write signal WL, the first terminal of the second switching element N4 is connected to the second node QB, and the second terminal of the first switching element N3 is used to input the complementary bit line signal BLB.

[0052] The first terminal of the third switching element P1 and the first terminal of the fourth switching element P2 are connected to a high level. The second terminal of the third switching element P1 is connected to the first node Q, and the control terminal of the third switching element P1 is connected to the second node QB. The second terminal of the fourth switching element P2 is connected to the second node QB, and the control terminal of the fourth switching element P2 is connected to the first node Q.

[0053] The first terminal of the fifth switching element N1 is connected to the first node Q, the control terminal of the fifth switching element N1 is connected to the second node QB, and the first terminal of the sixth switching element N2 is connected to the second node QB.

[0054] The non-volatile memory cell 200 includes a seventh switching element P3, an eighth switching element P4, a ninth switching element N5, a tenth switching element N6, a first magnetic tunnel junction M1, and a second magnetic tunnel junction M2.

[0055] The first terminal of the seventh switching element P3 and the first terminal of the eighth switching element P4 are used to input the precharge signal Vpre. The second terminal of the seventh switching element P3 is connected to the first terminal of the first magnetic tunnel junction M1. The control terminal of the seventh switching element P3 and the control terminal of the eighth switching element P4 are used to input the write enable signal WE. The second terminal of the eighth switching element P4 is connected to the first terminal of the second magnetic tunnel junction M2.

[0056] The control terminals of the ninth switch element N5 and the tenth switch element N6 are used to input the control signal CTRL. The first terminal of the ninth switch element N5 is connected to the third terminal of the first magnetic tunnel junction M1. The second terminals of the ninth switch element N5 and the tenth switch element N6 are used to input the bias signal VB. The first terminal of the tenth switch element N6 is connected to the third terminal of the second magnetic tunnel junction M2.

[0057] The second end of the first magnetic tunnel junction M1 is connected to the first node Q, and the second end of the second magnetic tunnel junction M2 is connected to the second node QB.

[0058] Specifically, the volatile memory cell 100 includes six switching elements, forming a 6T-SRAM memory cell used for data reading, writing, and retention. The first switching element N3 receives the write signal WL and the bit line signal BL, and the second switching element N4 receives the write signal WL and the complementary bit line signal BLB. The third switching element P1, the fourth switching element P2, the fifth switching element N1, and the sixth switching element N2 constitute a cross-coupled inverter. The third switching element P1 and the fifth switching element N1 form one inverter, and the fourth switching element P2 and the sixth switching element N2 form another inverter. The first node Q and the second node QB serve as memory nodes. The first switching element N3, the second switching element N4, the third switching element P1, and the fourth switching element P2 are PMOS transistors; the fifth switching element N1 and the sixth switching element N2 are NMOS transistors.

[0059] The non-volatile memory cell 200 includes four switching elements and two magnetic tunnel junctions (MTJs) for backing up the data stored in the volatile memory cell 100. Upon power-up, the backup data is used to restore the data at the first node Q and the second node QB of the volatile memory cell 100. The seventh switching element P3 and the eighth switching element P4 are PMOS transistors, and the ninth switching element N5 and the tenth switching element N6 are NMOS transistors. The two ends of the heavy metal layer of the first MTJ M1 are the first end and the second end, respectively. Current flowing from the first end to the second end of the first MTJ M1 switches it to the RP state, and current flowing from the second end to the first end switches it to the RAP state. The top electrode of the first MTJ M1 is the third end. The heavy metal layer of the second magnetic tunnel junction M2 has a first terminal and a second terminal, respectively. Current flowing from the first terminal to the second terminal of M2 switches it to the RP state, and current flowing from the second terminal to the first terminal switches it to the RAP state. The top electrode of the second magnetic tunnel junction M2 is the third terminal. The first magnetic tunnel junction M1 and the second magnetic tunnel junction M2 can be an I-MTJ.

[0060] Table 1 shows the control signals for the non-volatile memory module. VDD represents a high level, Data represents written data, Data_B represents inverted data, * represents floating, and GND represents a low level. The first level is less than the high level but greater than the low level, and the second level is a negative voltage. The high level, low level, first level, and second level can be set according to actual needs, and this embodiment of the invention does not limit them. Based on the control of the write signal WL, the bit line signal BL, and the complementary bit line signal BLB, data retention, writing, and reading of the volatile memory cell 100 can be realized. Based on the control of the configurable ground signal GN, the precharge signal Vpre, the write enable signal WE, the control signal CTRL, and the bias signal VB, data backup and data recovery of the non-volatile memory cell can be realized.

[0061] Table 1 Control signals for non-volatile memory modules

[0062]

[0063] Based on the above embodiments, the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2 further adopt a pressure-controlled spin-orbit torque magnetic tunnel junction.

[0064] Voltage-controlled spin-orbit torque magnetic tunnel junctions require lower write current, which allows for a reduction in the size of write-driven switching elements in volatile memory cells, thereby reducing power consumption and increasing integration.

[0065] For VGSOT-MTJ devices with in-plane magnetic anisotropy, applying a negative voltage bias across the MTJ reduces the required switching current and increases the switching speed.

[0066] Building upon the above embodiments, the resistance of the voltage-controlled spin-orbit torque magnetic tunnel junction (MTJ) is further defined as being greater than 1 kΩ and less than 10 MΩ, for example, 10 kΩ. The larger resistance of the MTJ avoids interference from the STT effect, effectively improving the device's lifespan.

[0067] Based on the above embodiments, the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2 further adopt I-MTJ.

[0068] Traditional SOT-MTJs require a large write current, which cannot be provided within NV-SRAM cells. Therefore, in I-MTJs, by applying a negative bias voltage across the MTJ, the energy barrier between the parallel (P) and antiparallel (AP) states is reduced, thereby enabling the switching of the free layer magnetization direction at a lower write current and changing the MTJ's resistance state. This invention uses an I-MTJ device employing the VCMA effect, which has the following advantages: (1) It requires a lower write current, effectively reducing the write power consumption of the MTJ, which also meets the requirement of NV-SRAM to complete the Restore process solely through the cell without additional write drive; (2) It improves the integration density of the memory. Due to the reduction in write current, only a smaller write transistor is needed to complete the write, allowing NV-SRAM cells to achieve a higher integration density based on the original 6T-SRAM cells.

[0069] Figure 2 This is a flowchart illustrating a data processing method provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the data processing method provided in this embodiment of the invention, applied to the non-volatile storage module described in any of the above embodiments, includes:

[0070] S201. After the non-volatile storage module is powered on again, the pre-charge signal input to the second terminal of the fifth switch element and the second terminal of the sixth switch element is at a high level, and the pre-charge signal input to the first terminal of the seventh switch element and the first terminal of the eighth switch element is at a high level, so as to charge the first node and the second node.

[0071] Specifically, after the non-volatile storage module is powered on again, it restores the data stored in the non-volatile storage unit to the volatile storage unit. In this embodiment of the invention, data restoration is divided into three processes: pre-charging, reading data, and latching.

[0072] During the pre-charging process, the configurable ground signal GN and the pre-charge signal Vpre are set to high level. The second terminals of the fifth switch element N1 and the sixth switch element N2 are input with high level, and the first terminals of the seventh switch element P3 and the eighth switch element P4 are input with high level, thus charging the first node Q and the second node QB. At this time, the write signal WL, the control signal CTRL, the write enable signal WE, and the bias signal VB are all low level. The seventh switch element P3 and the eighth switch element P4 are turned on, and the first switch element N3, the second switch element N4, the ninth switch element N5, and the tenth switch element N6 are turned off. The first node Q and the second node QB will be charged to a high potential.

[0073] In existing technologies, the data recovery process charges the first node Q and the second node QB via the bit line signal BL. However, a voltage drop occurs after transmission through the first switching element N3 and the second switching element N4, resulting in insufficient charging of the first node Q and the second node QB. Consequently, the charging levels of the first node Q and the second node QB are unequal, affecting reliability. This application performs pre-charging when the pre-charge signal is high. The seventh switching element P3 and the eighth switching element P4 are PMOS transistors. When the pre-charge signal is high, no threshold loss occurs after passing through the seventh switching element P3 and the eighth switching element P4, resulting in higher reliability. Furthermore, it eliminates the need for an external balancing transistor to balance the potentials of the first node Q and the second node QB.

[0074] S202, the second terminals of the fifth and sixth switching elements are kept at a high level, the first terminals of the seventh and eighth switching elements are left floating, the write enable signals input to the control terminals of the seventh and eighth switching elements are at a high level, the control signals input to the control terminals of the ninth and tenth switching elements are at a high level, and the bias signals input to the second terminals of the ninth and tenth switching elements are at a low level, so as to read the data stored in the first magnetic tunnel junction and the second magnetic tunnel junction;

[0075] Specifically, after pre-charging is complete, data is read from the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2. The write enable signal WE and the control signal CTRL are set to high, the configurable ground signal GN is kept high, the pre-charge signal Vpre is left floating, and the bias signal VB is low. Then, the control terminals of the seventh switch element P3 and the eighth switch element P4, the ninth switch element N5 and the tenth switch element N6 are input to high levels, the second terminals of the fifth switch element N1 and the sixth switch element N2 remain high, the first terminals of the seventh switch element P3 and the eighth switch element P4 are left floating, and the bias signal input to the second terminals of the ninth switch element N5 and the tenth switch element N6 is low. At this time, the seventh switch element P3 and the eighth switch element P4 are turned off, and the ninth switch element N5 and the tenth switch element N6 are turned on. Since the first node Q and the second node QB are pre-charged to a high level, they begin to discharge at this time. The discharge branch A of the first node Q is: first node Q → first magnetic tunnel junction M1 → ninth switching element N5 → GND; the discharge branch B of the second node QB is: second node QB → second magnetic tunnel junction M2 → tenth switching element N6 → GND. Because the first magnetic tunnel junction M1 is in a low-resistance state (RP) and the second magnetic tunnel junction M2 is in a high-resistance state (RAP), the discharge rates of discharge branch A and discharge branch B are different. The data stored in the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2 can be read by using the difference in discharge rate.

[0076] During data reading, the third switching element P1 and the fourth switching element P2 have latching functions. Simultaneously, because the configurable ground signal GN is set to a high level, the resistance of the fifth switching element N1 is much greater than the resistance of the first magnetic tunnel junction M1, and the resistance of the sixth switching element N2 is much greater than the resistance of the second magnetic tunnel junction M2. This achieves electrical isolation between the fifth switching element N1 and the sixth switching element N2, giving the technical solution of this application good resistance adaptability and enabling highly reliable data recovery within a wide resistance range (1K ohms-10M ohms).

[0077] S203, the configurable ground signal input to the second terminal of the fifth switching element and the second terminal of the sixth switching element is at a low level, so that the volatile memory cell latches the data read from the first magnetic tunnel junction and the second magnetic tunnel junction.

[0078] Specifically, after reading the data, the configurable ground signal GN is set to low, the write enable signal WE and the control signal CTRL remain high, the precharge signal remains floating, and the bias signal VB remains low. Then, the second terminals of the fifth switching element N1 and the sixth switching element N2 are connected to low, while the states of the remaining switching elements remain unchanged. At this time, the cross-coupled inverters in the volatile memory cell operate normally. When the voltage of either the first node Q or the second node QB is less than the threshold voltage of the cross-coupled inverter, the two inverters latch the voltages of the first node Q and the second node QB, thereby converting the resistance values ​​of the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2 into the data latched in the volatile memory cell.

[0079] This application replaces the existing power-on reading scheme with a three-step reading process of pre-charge-read-latch, delaying the rise time of the configurable ground signal so that the voltage difference between the first node Q and the second node QB stabilizes at the maximum voltage difference before latching through the volatile memory unit, which can significantly improve the reliability of data recovery.

[0080] The data processing method provided in this embodiment of the invention, after the non-volatile memory module is powered on again, has the configurable ground signal input to the second terminal of the fifth switch element and the second terminal of the sixth switch element be at a high level, and the pre-charge signal input to the first terminal of the seventh switch element and the first terminal of the eighth switch element be at a high level, to charge the first node and the second node; the second terminal of the fifth switch element and the second terminal of the sixth switch element remain at a high level, the first terminal of the seventh switch element and the first terminal of the eighth switch element are left floating, the write enable signal input to the control terminal of the seventh switch element and the control terminal of the eighth switch element is at a high level, the control signal input to the control terminal of the ninth switch element and the control terminal of the tenth switch element is at a high level, and the bias signal input to the second terminal of the ninth switch element and the second terminal of the tenth switch element is at a low level, to read the data stored in the first magnetic tunnel junction and the second magnetic tunnel junction; the configurable ground signal input to the second terminal of the fifth switch element and the second terminal of the sixth switch element is at a low level, so that the volatile memory cell latches the data read from the first magnetic tunnel junction and the second magnetic tunnel junction, providing high reliability for data recovery.

[0081] Based on the above embodiments, the data processing method provided by the embodiments of the present invention further includes:

[0082] The write signal input to the control terminals of the first and second switching elements is low, the write enable signal input to the control terminals of the seventh and eighth switching elements is low, the first terminal of the seventh and eighth switching elements inputs a first level, and the control signal input to the control terminals of the ninth and tenth switching elements is a second level, so as to store the data in the volatile memory cell into the first magnetic tunnel junction and the second magnetic tunnel junction of the non-volatile memory cell.

[0083] Specifically, the volatile memory cell will lose data after power failure, so the data in the volatile memory cell needs to be written into the non-volatile memory cell before power failure, that is, written into the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2.

[0084] In storage mode, the write signal WL and write enable signal WE are set to low, the control signal CTRL is set to high, the precharge signal is set to the first level, and the bias signal VB is set to the second level. Then, the control terminals of the first and second switching elements N3 and N4 are input to low levels, the control terminals of the seventh and eighth switching elements P3 and P4 are input to low levels, the first terminal of the seventh switching element P3 and the first terminal of the eighth switching element P4 are input to the first level, and the control signals input to the control terminals of the ninth and tenth switching elements N6 are at the second level. At this time, the seventh and eighth switching elements P3 and P4 are turned on, the ninth and tenth switching elements N5 and N6 are turned on, and the precharge signal is set to the first level to maintain the SOT current required by the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2.

[0085] Due to the potential difference between the first node Q and the second node QB of the volatile memory cell, a current is generated between the first node Q and the second node QB, flowing through the heavy metal (HM) layers of the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2, as well as the seventh switching element P3 and the eighth switching element P4. If the potential of the first node Q is lower than the potential of the second node QB, the generated current flows from the second node QB to the first node Q. Starting from the second node QB, the current flows sequentially through the second magnetic tunnel junction M2, the eighth switching element P4, the seventh switching element P3, and the first magnetic tunnel junction M1, finally reaching the first node Q. The current flows from the first end to the second end of the first magnetic tunnel junction M1, switching the first magnetic tunnel junction M1 into the RP state. The current flows from the second end to the first end of the second magnetic tunnel junction M2, switching the second magnetic tunnel junction M2 into the RAP state. If the potential of the first node Q is higher than the potential of the second node QB, a SOT write current will be generated from the first node Q to the second node QB, thereby switching the first magnetic tunnel junction M1 to the RAP state and the second magnetic tunnel junction M2 to the RP state.

[0086] The bias signal provides the VCMA voltage for the first magnetic tunnel junction M1 and the second magnetic tunnel junction M2. It is usually set to GND or a negative voltage to reduce the potential barrier of the MTJ, thereby reducing the spin-orbit torque current required to flip the MTJ resistive state. This allows the MTJ to be written without additional write circuitry, reduces the requirements for write transistor size, enables high-speed and low-power storage operations, and improves the storage density of non-volatile memory cells, thus optimizing write operations.

[0087] Based on the above embodiments, the first level is lower than the high level and higher than the low level, and the second level is a negative voltage.

[0088] For example, the first voltage level is greater than 0.4V and less than 0.8V, such as 0.75V.

[0089] For example, the second level is -0.5V.

[0090] By applying a negative voltage bias across the MTJ, the required switching current of the MTJ is reduced, thereby increasing the switching speed.

[0091] Based on the above embodiments, the data processing method provided by the embodiments of the present invention further includes:

[0092] Power is turned off on the non-volatile memory module, causing it to enter standby mode.

[0093] Specifically, after storing data from the volatile memory cell to the non-volatile memory cell through the storage mode, the non-volatile memory module can be powered off, putting it into standby mode. In standby mode, due to the non-volatility of the MTJ in the non-volatile memory cell, the data stored in the MTJ in advance will not be lost, and can be restored to the first node Q and the second node QB of the volatile memory cell in the subsequent data recovery mode, which can effectively reduce the static power consumption of the circuit.

[0094] Based on the above embodiments, the data processing method provided by the embodiments of the present invention further includes:

[0095] The control signals input to the control terminals of the ninth and tenth switching elements are at a low level, the write signals input to the control terminals of the first and second switching elements are at a high level, and the write enable signals input to the control terminals of the seventh and eighth switching elements are at a high level, thus putting the non-volatile memory module into static random access memory mode.

[0096] Specifically, by setting the control signal CTRL to low and the write signal WL and write enable signal WE to high, the control terminals of the ninth and tenth switching elements N5 and N6 are input to low levels, while the control terminals of the first and second switching elements N3 and N4 are input to high levels, and the control terminals of the seventh and eighth switching elements P3 and P4 are input to high levels. At this time, the seventh and eighth switching elements P3 and P4 are turned off, and the ninth and tenth switching elements N5 and N6 are turned off, thus completely isolating the volatile and non-volatile memory cells, i.e., completely isolating the two VG-SOT devices from the 6T-SRAM. The entire non-volatile memory module can then be equivalent to a single 6T-SRAM cell.

[0097] The present invention provides a non-volatile memory comprising an array of multiple non-volatile memory modules as described in any of the above embodiments.

[0098] The non-volatile storage module and data processing method provided in this invention can be applied to wearable and embedded devices to reduce storage power consumption. In the context of the current explosive growth of user data, applying this technical solution to the storage unit of wearable devices is in line with the future trend of development towards high density and low power consumption.

[0099] In the aerospace field, by adopting the technical solution of this invention, for aerospace memory chips, data in SRAM can be backed up in MTJ before power failure, thereby avoiding errors caused by high-energy particle bombardment and significantly improving memory reliability. At the same time, the static power consumption of MTJ is extremely low after power failure, and no additional energy loss occurs. If SRAM is affected by radiation or other factors and data is lost or erroneous, the original data in SRAM can be recovered based on the backed-up data in MTJ, ensuring data correctness and improving memory reliability.

[0100] In the IoT field, typical applications like industrial and agricultural sensors have distinct operating modes: they are mostly in sleep mode, only waking up at fixed intervals (e.g., every few hours or days) to perform data acquisition and transmission tasks. Using traditional SRAM solutions presents two major problems: firstly, the SRAM needs continuous power during sleep to maintain data storage, resulting in unnecessary static power consumption; secondly, each time the device wakes up from sleep, it needs to load the required data from external flash memory, which is not only slow but also consumes a significant amount of additional power, severely impacting the device's battery life and operating efficiency. The NV-SRAM proposed in this design effectively solves these problems. First, before the device enters sleep or power failure mode, there is no need to rely on external storage media; the data recovery process can be completed directly within the storage unit. Second, all NV-SRAM units can perform data recovery operations synchronously and in parallel, eliminating the need for complex initialization loading processes. This feature not only significantly improves the speed of data recovery, but also avoids the power consumption and time delay caused by external loading in traditional solutions. At the same time, it does not require continuous power supply to maintain data during sleep, which significantly reduces the overall power consumption of the device and is more in line with the long-term operation requirements of IoT devices for low power consumption and high efficiency.

[0101] The data processing method, non-volatile storage module, and non-volatile memory provided in this invention effectively solve the key technical problems of existing NV-SRAM circuits, such as the mutual constraints between reliability, low power consumption, SRAM performance, and non-volatile functions. Its technical effects have the following advantages.

[0102] 1. Low-power NV-SRAM circuit.

[0103] (1) Non-volatile device optimization reduces write current and improves switching speed, significantly reducing power consumption of data backup operation: VGSOT-MTJ device based on in-plane anisotropy is adopted. By applying negative bias voltage across the MTJ to reduce the energy barrier, lower write current and faster MTJ resistance state switching are achieved.

[0104] (2) Reduce SRAM transistor size and reduce power consumption during read and write in SRAM mode: The data recovery path of the proposed 10T-2MNV-SRAM cell is optimized so that the transistor size of SRAM is not limited by the MTJ drive requirements, achieving the smallest SRAM transistor size in similar designs and reducing the power consumption of NV-SRAM in SRAM mode.

[0105] (3) The use of pre-charged reading and high-resistance MTJ devices reduces the power consumption of data recovery operation: The resistance of VGSOT-MTJ is much greater than that of ordinary SOT-MTJ, which makes the current flowing through MTJ smaller during data recovery. At the same time, the use of pre-charged reading scheme reduces the overall power consumption of data recovery operation.

[0106] 2. Optimize cell size to improve memory integration.

[0107] (1) Optimization of area for data backup operation: Due to the significant reduction in write current, only a smaller write transistor is needed to complete the write operation. This allows the MNV-SRAM cell to complete the write operation by simply adding a small transistor to the original 6T-SRAM cell, achieving high integration and overcoming the problem of large transistor size and limited integration caused by the large write current of traditional SOT-MTJ, thus taking into account both non-volatility and high-density storage requirements.

[0108] (2) Optimization of area for data recovery operation: Using the transistor inside the cell as the precharge transistor eliminates the need for additional large-size precharge transistors on the BL, thus reducing area overhead.

[0109] 3. Pre-charge reading scheme improves data recovery reliability.

[0110] (1) Pre-charging stage: The first node Q and the second node QB are charged directly through the pre-charging signal Vpre. There is no voltage loss when the signal is transmitted through P3-P4. This solves the problem of voltage drop caused by charging through BL and transmitting through N3-N4 in the traditional design, which leads to insufficient charging. Data recovery is more reliable.

[0111] (2) Reading Stage: During the reading stage, the two pull-down NMOS transistors in the SRAM are isolated to prevent them from being connected in parallel with the VGSOT-MTJ device, thus avoiding their impact on the total resistance of the two read paths. During this process, since the signal does not reach its full swing, the two PMOS transistors in the SRAM are connected in series with the VGSOT-MTJ device for data latching, giving the read circuit excellent resistance adaptability. This makes the read scheme highly reliable over a wide range of MTJ resistance values ​​and TMR variations.

[0112] (3) Latching stage: A strategy of delaying the rise of the GN voltage is adopted. After the voltage difference between the first node Q and the second node QB stabilizes, the data is latched through a cross-coupled inverter. This design overcomes the problem of voltage fluctuations deteriorating the read margin when discharging and reading are performed simultaneously in the traditional scheme.

[0113] In summary, this invention, through the combination of VCMA-assisted I-MTJ device design and a three-step read strategy, achieves synergistic optimization of "low power consumption, high integration, and high reliability" while maintaining the high-speed characteristics and non-volatility of SRAM. It solves the problems of excessive write current in existing magnetic non-volatile static random access memories, which leads to high power consumption and area overhead. Furthermore, it proposes a highly reliable recovery scheme that enables reads over a wide resistance range, significantly improving the storage efficiency, stability, and applicability of NV-SRAM, better meeting the needs of high-density, low-power, and high-reliability storage applications.

[0114] An embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor and / or the memory includes the non-volatile memory module described in the above embodiments.

[0115] The non-volatile storage units described in the above embodiments can be specifically located in a product device with a certain function. A typical implementation device is a computer device, specifically, a computer device can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0116] In a typical example, a computer device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor and / or the memory includes a non-volatile memory module as described in this embodiment.

[0117] The following is for reference. Figure 3 It shows a schematic diagram of the structure of a computer device 600 suitable for implementing the embodiments of this application.

[0118] like Figure 3As shown, the computer device 600 includes a central processing unit (CPU) 601, which can perform various appropriate tasks and processes based on programs stored in read-only memory (ROM) 602 or programs loaded from storage section 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the computer device 600. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0119] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal feedback (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 610 as needed so that computer programs read from it can be installed in storage section 608 as needed.

[0120] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0121] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0122] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0123] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0124] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can be applied to one or more computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0125] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0126] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0127] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A data processing method, characterized in that, This is applied to a non-volatile storage module, which includes volatile storage units and non-volatile storage units, wherein: The volatile memory unit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a first node, and a second node. The control terminal of the first switching element is used to input a write signal, and its first terminal is used to input a bit line signal. The second terminal of the first switching element is connected to the first node. The control terminal of the second switching element is used to input a write signal, and its first terminal is connected to the second node. The second terminal of the first switching element is also used to input a complementary bit line signal. The first terminals of the third and fourth switching elements are connected to a high level. The second terminal of the third switching element is connected to the first node, and its control terminal is connected to the second node. The second terminal of the fourth switching element is connected to the second node, and its control terminal is connected to the first node. The first terminal of the fifth switching element is connected to the first node, and its control terminal is connected to the second node. The first terminal of the sixth switching element is connected to the second node, and its control terminal is connected to the first node. The non-volatile memory cell includes a seventh switching element, an eighth switching element, a ninth switching element, a tenth switching element, a first magnetic tunnel junction, and a second magnetic tunnel junction. The first terminals of the seventh and eighth switching elements are used to input a precharge signal. The second terminal of the seventh switching element is connected to the first terminal of the first magnetic tunnel junction. The control terminals of the seventh and eighth switching elements are used to input a write enable signal. The second terminal of the eighth switching element is connected to the first terminal of the second magnetic tunnel junction. The control terminals of the ninth and tenth switching elements are used to input a control signal. The first terminal of the ninth switching element is connected to the third terminal of the first magnetic tunnel junction. The second terminals of the ninth and tenth switching elements are used to input a bias signal. The first terminal of the tenth switching element is connected to the third terminal of the second magnetic tunnel junction. The second terminal of the first magnetic tunnel junction is connected to the first node, and the second terminal of the second magnetic tunnel junction is connected to the second node. The method includes: After the non-volatile storage module is powered on again, the configurable ground signal input to the second terminal of the fifth switch element and the second terminal of the sixth switch element is at a high level, and the pre-charge signal input to the first terminal of the seventh switch element and the first terminal of the eighth switch element is at a high level, so as to charge the first node and the second node. The second terminals of the fifth and sixth switching elements are kept at a high level, the first terminals of the seventh and eighth switching elements are left floating, the write enable signals input to the control terminals of the seventh and eighth switching elements are at a high level, the control signals input to the control terminals of the ninth and tenth switching elements are at a high level, and the bias signals input to the second terminals of the ninth and tenth switching elements are at a low level, so as to read the data stored in the first and second magnetic tunnel junctions; When the configurable ground signal input to the second terminal of the fifth switching element and the second terminal of the sixth switching element is low, the volatile memory cell latches the data read from the first magnetic tunnel junction and the second magnetic tunnel junction.

2. The method according to claim 1, characterized in that, Also includes: The write signal input to the control terminal of the first switch element and the control terminal of the second switch element is low level, the write enable signal input to the control terminal of the seventh switch element and the control terminal of the eighth switch element is low level, the first terminal of the seventh switch element and the first terminal of the eighth switch element input a first level, and the bias signal input to the second terminal of the ninth switch element and the second terminal of the tenth switch element is a second level, so as to store the data in the volatile memory cell into the first magnetic tunnel junction and the second magnetic tunnel junction of the non-volatile memory cell.

3. The method according to claim 2, characterized in that, The first voltage level is lower than the high voltage level and higher than the low voltage level; the second voltage level is a negative voltage.

4. The method according to claim 2, characterized in that, Also includes: Power is turned off on the non-volatile memory module, causing it to enter standby mode.

5. The method according to claim 1, characterized in that, Also includes: The control signals input to the control terminals of the ninth and tenth switching elements are at a low level, the write signals input to the control terminals of the first and second switching elements are at a high level, and the write enable signals input to the control terminals of the seventh and eighth switching elements are at a high level, thus putting the non-volatile memory module into static random access memory mode.

6. A non-volatile storage module, characterized in that, Includes volatile and non-volatile memory units, wherein: The volatile storage unit includes a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a first node, and a second node; The control terminal of the first switching element is used to input a write signal, the first terminal of the first switching element is used to input a bit line signal, the second terminal of the first switching element is connected to the first node, the control terminal of the second switching element is used to input a write signal, the first terminal of the second switching element is connected to the second node, and the second terminal of the first switching element is used to input a complementary bit line signal. The first terminal of the third switching element and the first terminal of the fourth switching element are connected to a high level. The second terminal of the third switching element is connected to the first node, and the control terminal of the third switching element is connected to the second node. The second terminal of the fourth switching element is connected to the second node, and the control terminal of the fourth switching element is connected to the first node. The first end of the fifth switching element is connected to the first node, the control end of the fifth switching element is connected to the second node, the first end of the sixth switching element is connected to the second node, and the control end of the sixth switching element is connected to the first node. The non-volatile memory cell includes a seventh switching element, an eighth switching element, a ninth switching element, a tenth switching element, a first magnetic tunnel junction, and a second magnetic tunnel junction; The first terminal of the seventh switching element and the first terminal of the eighth switching element are used to input a precharge signal. The second terminal of the seventh switching element is connected to the first terminal of the first magnetic tunnel junction. The control terminal of the seventh switching element and the control terminal of the eighth switching element are used to input a write enable signal. The second terminal of the eighth switching element is connected to the first terminal of the second magnetic tunnel junction. The control terminals of the ninth and tenth switching elements are used to input control signals. The first terminal of the ninth switching element is connected to the third terminal of the first magnetic tunnel junction. The second terminals of the ninth and tenth switching elements are used to input bias signals. The first terminal of the tenth switching element is connected to the third terminal of the second magnetic tunnel junction. The second end of the first magnetic tunnel junction is connected to the first node, and the second end of the second magnetic tunnel junction is connected to the second node.

7. The non-volatile storage module according to claim 6, characterized in that, The first magnetic tunnel junction and the second magnetic tunnel junction are voltage-controlled spin-orbit torque magnetic tunnel junctions.

8. The non-volatile storage module according to claim 7, characterized in that, The resistance of the pressure-controlled spin-orbit torque magnetic tunnel junction is greater than 1 kΩ and less than 10 MΩ.

9. A non-volatile memory, characterized in that, It includes multiple non-volatile memory modules arranged in an array as described in any one of claims 6-8.

10. A computer device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor and / or the memory includes a non-volatile memory module as described in any one of claims 6-8.

Images