Ultra-weak light full-color single-photon detector structure and preparation method thereof

Abstract

The structure comprises a plurality of low-light full-color pixel structures which are arranged in an array mode, and each low-light full-color pixel structure comprises a P-type epitaxial layer, an N-type buried layer, a P-type silicon substrate, an anti-reflection layer and buried metal full-groove isolation structures on the two sides which are arranged from bottom to top; an N buried layer electrode plate is led out from the upper end of the buried metal full-groove isolation structure to contact the upper surface of the N-type buried layer; a deep P well, an N well and a central P + well are sequentially arranged in the P-type epitaxial layer from top to bottom in a semi-surrounding manner, and a first avalanche region, a second avalanche region and a third avalanche region are sequentially formed between every two of the deep P well, the N well and the central P + well and respectively perform detection efficiency response on red light, green light and blue light; n + wells are arranged in the N wells on the two sides of the central P + well; p + wells are arranged in the deep P wells on the two sides of the N well and in the central P + well; and a central P + electrode, an NW electrode, an HPW electrode and an N buried layer electrode are correspondingly arranged at the bottom. According to the invention, the visible light multi-spectrum detection efficiency is improved through a compact structure.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic optoelectronic device technology, specifically relating to the structure and fabrication method of an extremely weak light full-color single-photon detector. Background Technology

[0002] High-definition color imaging in extremely low-light environments has always been a major bottleneck in the development of the security industry. Traditional nighttime surveillance solutions generally suffer from problems such as loss of color detail, low clarity, difficulty in target identification, low image brightness, and high noise. While traditional methods of adding supplementary lights can provide sufficient illumination, they also cause "light pollution," affecting the surrounding environment and leading to other accidents. Secondly, because the illumination from supplementary lights weakens with distance, cameras can only capture areas with sufficient light, making it impossible to capture large scenes or distant views.

[0003] Single-photon avalanche diodes (SPADs) are core devices for low-light detection, boasting advantages such as high detection sensitivity, picosecond-level high temporal resolution, and low dark noise, with their response wavelength covering the visible light band. SPADs fabricated using CMOS technology also offer high integration, enabling monolithic integration of device arrays and readout processing circuitry. By utilizing single-photon detectors combined with high-efficiency visible light detection, full-color night vision capabilities can be achieved under extremely low light conditions, providing technical support for panoramic monitoring of large-scale outdoor scenes without light sources, such as complex low-light areas, parks, bridges, rivers, borders, coastal defenses, forests, mines, construction sites, and power facilities. However, their peak efficiency is around 450nm; as the wavelength increases, their detection efficiency decreases significantly, and the refraction and reflection caused by multiple dielectric layers result in large fluctuations in detection efficiency. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides an extremely weak light full-color single-photon detector structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide an extremely low-light full-color single-photon detector structure, comprising a plurality of low-light full-color pixel structures arranged in an array in a two-dimensional direction, each low-light full-color pixel structure comprising: The structure consists of a P-type epitaxial layer, an N-type buried layer, a P-type silicon substrate, an anti-reflection layer, and a buried metal full-groove isolation structure arranged from bottom to top. The surface of the anti-reflection layer away from the N-type buried layer is the light incident surface. An N-type buried layer electrode plate is led out from the upper end of the buried metal full-groove isolation structure to contact the upper surface of the N-type buried layer. Within the P-type epitaxial layer, from top to bottom, a deep P-well, an N-well, and a central P+ well are arranged in a semi-enclosed manner. The central P+ well and the N-well form the first avalanche zone, which has a hemispherical cross-section. The N-well and the deep P-well form the second avalanche zone, and the deep P-well and the N-type buried layer form the third avalanche zone. The three avalanche zones provide detection efficiency responses for red, green, and blue light, respectively. N+ wells are arranged in the N-wells on both sides of the central P+ well. P+ wells are arranged in the deep P-wells on both sides of the N-well and in the central P+ well. A central P+ electrode is arranged at the bottom of the central P+ well. An NW electrode is arranged at the bottom of the N+ well. An HPW electrode is arranged at the bottom of the P+ well on one side, and an N buried layer electrode is arranged at the bottom of the buried metal full-groove isolation structure on the same side. An STI shallow trench isolation zone is arranged between adjacent N+ wells and P+ wells on the side.

[0005] In one embodiment of the present invention, the buried metal full-slot isolation structure includes a full-slot oxide layer isolation structure and a buried metal pillar filling structure disposed in the middle of the full-slot oxide layer isolation structure; wherein, the N buried layer electrode is disposed at the bottom of the buried metal pillar filling structure and is led out through the N buried layer electrode plate; two adjacent low-light full-color pixel structures share a buried metal full-slot isolation structure.

[0006] In one embodiment of the present invention, the doping concentration of the N-type buried layer is greater than or equal to .

[0007] In one embodiment of the present invention, the central P+ well, N well, deep P well, N-type buried layer and anti-reflection layer are circular, rectangular, rounded rectangle or regular polygon.

[0008] In one embodiment of the present invention, the buried metal full-slot isolation structure, N+ well, P+ well, central P+ electrode, NW electrode, HPW electrode, and N buried layer electrode are arranged in a ring shape.

[0009] In one embodiment of the present invention, both the second avalanche region and the third avalanche region are planar PN junctions.

[0010] In one embodiment of the present invention, the antireflection layer is composed of a periodic arrangement of cylindrical microstructures of the same height but different diameters.

[0011] In one embodiment of the present invention, each low-light full-color pixel structure further includes: a first bias circuit, a second bias circuit, and a third bias circuit that provide bias voltages for the first avalanche region, the second avalanche region, and the third avalanche region, respectively; and a quenching and gating unit connected to the first bias circuit, the second bias circuit, and the third bias circuit; the quenching and gating unit is used to control one of the first bias circuit, the second bias circuit, and the third bias circuit to operate, so as to provide a bias voltage for the corresponding avalanche region and put it in an avalanche state.

[0012] In a second aspect, embodiments of the present invention provide a method for fabricating an extremely weak light full-color single-photon detector structure, used to fabricate the extremely weak light full-color single-photon detector structure described in the first aspect, the method comprising: S1, Obtain a P-type silicon substrate and prepare an N-type buried layer on the upper surface of the P-type silicon substrate; S2, a P-type epitaxial layer is grown on the upper surface of the N-type buried layer; S3. Using an etching process, deep trenches are etched on both sides of the current structure, penetrating the P-type epitaxial layer and reaching the N-type buried layer. An insulating oxide layer is grown on the sidewall and bottom of the deep trench to form a full-trench oxide layer isolation structure. Then, the center of the deep trench is filled with metal to form a buried metal pillar filling structure, which together with the adjacent full-trench oxide layer isolation structure constitutes a buried metal full-trench isolation structure. S4 defines the active region and forms a trench for the STI shallow trench isolation structure that isolates adjacent active regions; S5, a deep P-well is formed in the P-type epitaxial layer between the two sides of the buried metal full-groove isolation structure by photolithography and ion implantation process; S6. In the top central region within the deep P-well, an N-well is formed by photolithography and ion implantation processes. S7, N+ wells are formed in the top two sides of the N-well by photolithography and ion implantation processes; S8, a central P+ well is formed in the top center region of the N-well between the two N+ wells by photolithography and ion implantation. S9, P+ wells are formed in the top regions of the deep P wells on both sides of the N well and in the top center region of the P+ well through photolithography and ion implantation processes, and are filled in the trenches of the STI shallow trench isolation structure formed between adjacent N+ wells and P+ wells on the side to form an STI shallow trench isolation region; wherein, the central P+ well and the N well constitute a first avalanche region with a hemispherical cross-section; the N well and the deep P well constitute a second avalanche region; and the deep P well and the N-type buried layer constitute a third avalanche region; S10, prepare contact holes and deposit metal to prepare a central P+ electrode at the bottom of the middle P+ well; prepare an NW electrode at the bottom of the N+ well; prepare an HPW electrode at the bottom of the P+ well on one side, and prepare an N buried layer electrode at the bottom of the buried metal pillar filling structure of the buried metal full trench isolation structure on the same side. Then perform multilayer metal interconnection and expose the PADs that need to be connected. S11, a passivation layer is deposited for protection, and then the upper wafer and the lower CMOS circuit wafer are bonded by three-dimensional integration technology; wherein, the lower CMOS circuit wafer includes a first bias circuit, a second bias circuit and a third bias circuit, as well as quenching and gating units connected to the first bias circuit, the second bias circuit and the third bias circuit. S12, flip the bonded stacked wafer structure and perform substrate thinning from the back side of the P-type silicon substrate; S13, an N-type buried electrode plate is formed on the back side of the thinned P-type silicon substrate, so that it makes electrical contact with the buried metal pillar filling structure in the exposed buried metal full-groove isolation structure, thereby conducting to the N-type buried layer. S14, an antireflection layer is prepared on the entire back side, with the surface away from the N-type buried layer being the light incident surface; S15 employs a packaging scheme suitable for back-illuminated devices for dicing, packaging, and wire bonding to complete the fabrication of an extremely weak light full-color single-photon detector.

[0013] The beneficial effects of this invention are: This invention combines optical and electrical designs to provide an extremely low-light full-color single-photon detector structure, wherein the low-light full-color pixel structures are periodically arranged. Each low-light full-color pixel structure has three avalanche zones from bottom to top, which respectively provide detection efficiency responses for red, green, and blue light, and the avalanche zones can be controlled by a bias circuit to be in an avalanche state at different times. This invention can provide a high-detection-efficiency device structure without increasing the number of masks or manufacturing costs, and can alleviate the burden of subsequent complex algorithms caused by inconsistent spectral responses under extremely low light conditions. Attached Figure Description

[0014] Figure 1 This is a cross-sectional schematic diagram of the low-light full-color pixel structure in an extremely low-light full-color single-photon detector structure provided in an embodiment of the present invention. Figure 2 This is a potential profile diagram of the central P+ well 1 and N well 2 in an embodiment of the present invention; Figure 3 This is a schematic diagram of the antireflection layer 5 in this invention. Figure 4 This is a schematic diagram of the low-light full-color pixel structure connected to the bias circuit provided in an embodiment of the present invention. Figure 5 This is a schematic flowchart illustrating a method for fabricating an extremely weak light full-color single-photon detector structure according to an embodiment of the present invention. Figure label: 1: Central P+ well; 2: N-well; 3: Deep P-well; 4: N-type buried layer; 5: Anti-reflection layer; 6: Buried metal full-slot isolation structure; 61: Full-slot oxide layer isolation structure; 62: Buried metal pillar filling structure; 7: N+ well; 8: P+ well; 9: Central P+ electrode; 10: NW electrode; 11: HPW electrode; 12: N buried layer electrode; 121: N buried layer electrode plate; 21: First avalanche zone; 22: Second avalanche zone; 23: Third avalanche zone. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] Under extremely low light conditions, detectors often exhibit inconsistent spectral responses, meaning that photons of different wavelengths show varying detection efficiencies. Since the number of incident photons is already extremely small, this non-uniformity in response is amplified, directly leading to increased signal bias and noise levels. To ensure the reliability of measurement results, subsequent processing must rely on more complex correction and compensation algorithms. Methods such as response curve modeling, normalization, or statistical optimization are needed to recover the true signal as much as possible even with low signal-to-noise ratios. A better engineering approach is to improve or pre-compensate the detector's response characteristics at the hardware level, allowing subsequent algorithms to achieve stable and reliable signal recovery with minimal adjustments.

[0017] To alleviate the burden on subsequent complex algorithms caused by inconsistent spectral responses under extremely weak light conditions, this invention proposes a structure and fabrication method for an extremely weak light full-color single-photon detector by directly improving the hardware and combining optical and electrical design. This method provides a high-efficiency device structure without increasing manufacturing costs by adding excessive masks. The proposed solution is applicable to filter-free, high-efficiency low-light full-color single-photon detection systems. The details are described below.

[0018] In a first aspect, embodiments of the present invention provide an extremely low-light full-color single-photon detector structure, comprising multiple low-light full-color pixel structures arranged in an array in a two-dimensional direction, such as... Figure 1 The cross-sectional view shown illustrates that each low-light full-color pixel structure includes: The structure consists of, from bottom to top, a P-type epitaxial layer, an N-type buried layer 4, a P-type silicon substrate, an antireflection layer 5, and a buried metal full-groove isolation structure 6 disposed on both sides of the P-type epitaxial layer and the N-type buried layer 4; wherein, the surface of the antireflection layer 5 away from the N-type buried layer 4 is the light incident surface; and an N-type buried layer electrode plate 121 is led out from the upper end of the buried metal full-groove isolation structure 6 to contact the upper surface of the N-type buried layer 4. Within the P-type epitaxial layer, from top to bottom, a deep P-well 3, an N-well 2, and a central P+well 1 are arranged in a semi-enclosed manner. The central P+well 1 and the N-well 2 form a first avalanche zone 21 with a hemispherical cross-section. The N-well 2 and the deep P-well 3 form a second avalanche zone 22, and the deep P-well 3 and the N-type buried layer 4 form a third avalanche zone 23. The three avalanche zones provide detection efficiency responses for red, green, and blue light, respectively. N+wells 7 are arranged in the N-wells 2 on both sides of the central P+well 1. P+wells 8 are arranged in the deep P-wells 3 on both sides of the N-well 2 and in the central P+well 1. A central P+ electrode 9 is arranged at the bottom of the central P+well 8. An NW electrode 10 is arranged at the bottom of the N+well 7. An HPW electrode 11 is arranged at the bottom of the P+well 8 on one side, and an N-buried layer electrode 12 is arranged at the bottom of the buried metal full-groove isolation structure 6 on the same side. An STI shallow trench isolation zone is arranged between adjacent N+wells 7 and P+wells 8 on the side.

[0019] See Figure 1 As shown, the incident light is incident downwards from the antireflection layer 5. From bottom to top, the layers are a P-type epitaxial layer, an N-type buried layer 4, a P-type silicon substrate, and an antireflection layer 5. Figure 1 For simplicity, the P-type silicon substrate is not shown. The central P+ well 1, N-well 2, deep P-well 3, buried metal full-trench isolation structure 6, N+ well 7, P+ well 8, first avalanche region 21, second avalanche region 22, and third avalanche region 23 are all within the P-type epitaxial layer. The STI shallow trench isolation region is located between N+ well 7 and P+ well 8 on the same side, and the material filled in the STI shallow trench isolation region is silicon dioxide.

[0020] In this embodiment of the invention, the shapes of the central P+ well 1, N well 2, deep P well 3, N-type buried layer 4 and anti-reflection layer 5 are circular, rectangular, rounded rectangle or regular polygon.

[0021] Specifically, in CMOS processes, the layout shape of diodes has a significant impact on their electrical characteristics. Curvature at edges leads to uneven electric field distribution; sharp corners or narrow edges are prone to localized electric field enhancement, thereby reducing breakdown voltage and exacerbating leakage current. To mitigate this "curvature effect," rounded rectangles are often used for diode layouts to effectively reduce electric field concentration at corners while ensuring area utilization. Circular layouts offer the smallest curvature, the most uniform electric field distribution, and the best breakdown resistance, but may be less efficient than rectangles in terms of area utilization and process alignment. Polygonal layouts fall between these two extremes; their electric field distribution depends on the number and shape of the corners. More sides result in a closer approximation to a circle, and a weaker curvature effect. Overall, rounded rectangles represent a trade-off between performance and layout efficiency in practical designs, while circles offer the best electrical uniformity.

[0022] The buried metal full-slot isolation structure 6, N+ well 7, P+ well 8, central P+ electrode 9, NW electrode 10, HPW electrode 11, and N buried layer electrode 12 are arranged in a ring shape, such as a circular ring, a rectangular ring, a rounded rectangular ring, or a regular polygonal ring. Figure 1 The diagram shown is a cross-sectional view of the low-light full-color pixel structure. It can be understood that, from the top view perspective, the N+ wells 7 on both sides form a ring shape, and the P+ wells 8 on both sides form a ring shape.

[0023] Figure 1 In the middle, the lower arc-shaped area corresponds to the first avalanche zone 21, the area below it is the central P+ well 1, and the rectangular area above it is the N well 2; the N well 2 surrounds the central P+ well 1 above and on both sides, so the N well 2 is a semi-encirclement of the central P+ well 1.

[0024] The intersecting grid-like region is the second avalanche region 22, the rectangular region below it is the N-well 2, and the rectangular region above it is the deep P-well 3; the deep P-well 3 surrounds the N-well 2 on the top and sides, also forming a semi-enclosed shape; since the device ion implantation is from the P+, ​​n+ side, that is, from... Figure 1 It is injected from below upwards, and the depth increases with distance from the injection surface, hence the name deep P-trap.

[0025] The horizontally shaded area is the third avalanche region 23, the rectangular area below it is the deep P-well 3, and the diagonally shaded rectangle above it is the N-type buried layer 4; the doping concentration of the N-type buried layer 4 is greater than or equal to This ensures that the back electrode can form a good ohmic contact.

[0026] As mentioned above, Figure 1 In the structure, the first avalanche zone 21 is formed between the central P+ well 1 and the N well 2; the second avalanche zone 22 is formed between the N well 2 and the deep P well 3; and the third avalanche zone 23 is formed between the deep P well 3 and the N-type buried layer 4. The first avalanche zone 21, the second avalanche zone 22, and the third avalanche zone 23 are distributed from bottom to top, respectively providing high-efficiency response to red light, green light, and blue light.

[0027] In semiconductor materials, the absorption depth of photons of different wavelengths in silicon varies significantly: short-wavelength blue light (≈450 nm) has the largest absorption coefficient in silicon and is easily absorbed in the shallow region near the surface after incident; medium-wavelength green light (≈550 nm) has a moderate absorption depth and can penetrate to the middle depth before being effectively absorbed; while long-wavelength red light (≈650–700 nm) has the smallest absorption coefficient in silicon, has stronger penetrating ability, and often penetrates to a deeper substrate region before being absorbed.

[0028] Based on this physical principle, in the avalanche photodiode structure using CMOS technology, this invention achieves efficient response to different wavelengths of light by arranging multiple avalanche multiplication regions at different depths. Specifically, the first avalanche region 21 at the bottom corresponds to the main absorption position of red light, thereby enhancing red light detection efficiency; the second avalanche region 22 in the middle matches the absorption depth of green light, improving the response to green light; and the third avalanche region 23 at the top is located in a shallow layer near the surface, effectively collecting electron-hole pairs generated by blue light photons. Therefore, the bottom-up distribution of the three avalanche regions corresponds to the absorption depth patterns of red, green, and blue light in silicon, achieving high detection efficiency over a wide spectral range.

[0029] The first avalanche region 21 has a hemispherical profile, and through reasonable doping at different angles, it is formed to have a shape similar to... Figure 2 The potential lines shown are uniformly hemispherical, and within the first avalanche region 21, the electric field lines extend along the hemispherical shape from N-well 2 to the central P-well 1.

[0030] In traditional CMOS processes, single-photon avalanche diodes (SPADs) typically employ a planar structure. This structure requires a guard ring around the active region to suppress excessive electric field enhancement at the device edges due to curvature effects, thereby preventing premature breakdown. However, the guard ring occupies additional layout area and has limited ability to collect photogenerated carriers from the surrounding area.

[0031] Designing the depletion region as an approximate hemispherical shape allows for a more uniform electric field distribution in space, significantly reducing edge field concentration and theoretically reducing or even eliminating the need for a guard ring. Furthermore, the hemispherical depletion region has greater volume extension, effectively expanding the carrier collection range and enhancing the collection efficiency of photogenerated electron-hole pairs generated in the device's periphery, thereby improving the detector's overall photoresponse and fill factor. Figure 2 As can be seen, since the potential lines are uniformly spherical, no protective ring structure is needed around the central P+ well 1, which can save chip area.

[0032] The intersecting grid-like region between N-well 2 and deep P-well 3 is the second avalanche region 22, which is a planar PN junction.

[0033] In traditional SPAD fabrication, a low-doped guard ring is often introduced at the device edge to mitigate edge electric field concentration caused by geometric curvature effects and prevent premature breakdown. However, under advanced process conditions, the inevitable lateral diffusion during deep-well implantation and annealing causes the doping distribution to gradually become shallower and more transitional at the edge region, naturally forming a low-doped gradient edge structure. This structure is functionally equivalent to a guard ring, effectively smoothing the electric field distribution and reducing the peak edge field strength, while eliminating the need for an additional independent guard ring layout and process steps. Therefore, utilizing the lateral diffusion effect of deep wells not only simplifies the process flow but also improves edge breakdown voltage and device reliability while maintaining high device sensitivity.

[0034] In this embodiment of the invention, the deep P-well 3 has a large lateral diffusion coefficient. Specifically, compared with other P-wells, generally, the deeper the well, the larger the lateral diffusion coefficient. This is because, in the formation of CMOS and related semiconductor devices, it is often necessary to construct well regions of different depths (such as P-well, N-well, deep P-well, deep N-well, etc.) through multiple ion implantation and epitaxial processes to achieve effective control over channels, isolation, and parasitic effects. Generally speaking, the greater the depth of the well region, the more obvious its lateral diffusion, and thus the lateral expansion coefficient increases accordingly. This is because, during high-energy implantation and long-term annealing activation, impurity atoms not only diffuse into the substrate in the depth direction but also undergo stronger epitaxial migration in the lateral direction, making the deep well exhibit a wider occupied area on the layout. This rule directly affects the isolation design, parasitic capacitance control, and layout matching of the device. Therefore, in the process design, it is necessary to consider the trade-off between well depth and lateral expansion. By using its lateral diffusion to form a virtual protection ring for the second avalanche region 22, it can save chip area.

[0035] The horizontal shaded area between the deep P-well 3 and the N-type buried layer 4 is the third avalanche region 23. The third avalanche region 23 is a planar PN junction. Similar to the deep P-well 3, the N-type buried layer 4 also has a large lateral diffusion coefficient, which forms a virtual protective ring for the third avalanche region 23 through its lateral diffusion, thus saving chip area.

[0036] It is understood that the low-light full-color pixel structure of this invention incorporates a triple multiplication layer. In the design of avalanche photodiodes, by introducing PN junction structures at different depths, multiple independent multiplication regions can be formed within the device. Multiplication regions at different depths correspond to the effective absorption and triggering of photons of different wavelengths, thereby expanding the spectral response range of the device. In particular, when the three multiplication layers of this invention are arranged sequentially from top to bottom, the shallow layer efficiently absorbs short-wavelength photons, the middle layer responds to mid-wavelength photons, and the deep layer enhances the detection capability for long-wavelength photons. This layered multiplication structure not only significantly improves the width of the spectral response but also optimizes the overall detection efficiency, providing favorable conditions for achieving high sensitivity and wide-spectrum low-light detection. In this embodiment of the invention, the buried metal full-slot isolation structure 6 includes a full-slot oxide layer isolation structure 61 and a buried metal pillar filling structure 62 disposed in the middle of the full-slot oxide layer isolation structure 61; wherein, the N-type buried electrode 12 is disposed at the bottom of the buried metal pillar filling structure 62 and is led out through the N-type buried electrode plate 121; two adjacent low-light full-color pixel structures share one buried metal full-slot isolation structure 6. See also Figure 1 As shown, both sides are equipped with embedded metal full-groove isolation structures 6.

[0037] The full-deep rench isolation structure 61 achieves complete electrical isolation between adjacent pixels, while the buried metal pillar filling structure 62 achieves electrical isolation through optical reflection. The combination of these two structures achieves complete optoelectronic isolation, significantly reducing crosstalk between adjacent pixels and resulting in higher imaging quality. In high-density image sensors, electrical and optical crosstalk inevitably exists between adjacent pixels. Conventional full-deep rench isolation (F-DTI) typically uses silicon dioxide filling, which effectively blocks the lateral diffusion of charge carriers between pixels, thus achieving near-complete electrical isolation. However, since silicon dioxide is almost transparent in the visible light range, optical crosstalk caused by photon penetration or scattering within the substrate still exists, reducing pixel independence and affecting imaging quality. To simultaneously suppress optical and electrical crosstalk, a buried metal pillar filling structure can be introduced within the Deep Trench Isolation (DTI) trench. Utilizing the strong reflection and absorption properties of metal for photons, a highly reflective barrier is formed at the pixel boundary, effectively blocking cross-pixel light transmission. Simultaneously, the metal pillar maintains its synergistic effect with the silicon dioxide isolation layer, continuing to suppress carrier diffusion. In this way, DTI not only achieves electrical isolation but also further achieves optical isolation, thus achieving complete optoelectronic isolation. This significantly reduces crosstalk between adjacent pixels and substantially improves the spatial resolution and imaging quality of the image sensor.

[0038] In this embodiment of the invention, the N-buried electrode 12 is located on the bottom surface of the low-light full-color pixel structure, electrically connected to the buried metal pillar filling structure 62, and led out through the N-buried electrode plate 121. The metal of the N-buried electrode plate 121 can be the same as the source and drain metal.

[0039] The radius of the N-type buried electrode plate 121 is slightly larger than that of the N-type buried layer 4. That is, the N-type buried electrode plate 121 covers part of the surface of the N-type buried layer 4, and the two overlap slightly. This design is to avoid manufacturing errors and to provide incident surface optical isolation for adjacent pixels. Please see Figure 3 In this embodiment of the invention, the antireflection layer 5 is composed of periodically arranged cylindrical microstructures of the same height but different diameters. Let the diameter of each cylinder be D, the height be H, and the period be T, with each cylinder serving as a microlens unit. The aforementioned geometric parameters of the antireflection layer 5 directly determine the phase delay and optical focusing effect that can be generated. During the design process, the ideal phase distribution required for the detector surface is first calculated based on the target focal length and working wavelength distribution. Then, this phase distribution is sampled on the plane with a period T. Subsequently, a microlens unit with a diameter of D is placed at each sampling position, and its height H is adjusted to generate a phase delay corresponding to the target phase at that position. Through this "phase-geometry" mapping relationship, the entire array forms a phase distribution in space equivalent to an ideal lens, and the incident light wave converges and forms an image at the photosensitive area after transmission. Compared with a flat structure, this microlens array-based design not only effectively improves the light focusing capability but also significantly increases the incident photon collection efficiency in the photosensitive area, thereby improving the effective pixel fill rate and overall detection sensitivity.

[0040] This invention employs 3D FDTD Solution software to calculate the phase abrupt change and transmittance generated by the vertically incident microstructure of the TM mode plane wave, thereby optimizing the optical parameters within the visible light broadband. By distributing these cylindrical microstructures in a certain order to the corresponding phase plane positions, focusing functionality can be achieved, and the effective fill rate can be improved.

[0041] The antireflection layer 5 can be made of silicon dioxide (SiO2). ) or silicon nitride ( ).

[0042] In addition, in this embodiment of the invention, each low-light full-color pixel structure further includes: a first bias circuit, a second bias circuit, and a third bias circuit that provide bias voltages for the first avalanche region 21, the second avalanche region 22, and the third avalanche region 23, respectively; and a quenching and gating unit connected to the first bias circuit, the second bias circuit, and the third bias circuit; the quenching and gating unit is used to control one of the first bias circuit, the second bias circuit, and the third bias circuit to operate, so as to provide a bias voltage for the corresponding avalanche region and put it in an avalanche state.

[0043] Please see Figure 4 The first, second, and third bias circuits are represented by bias circuit 1, bias circuit 2, and bias circuit 3, respectively. Specifically, the two ends of bias circuit 1 are connected to the center P+ electrode 9 and the NW electrode 10, respectively; the two ends of bias circuit 2 are connected to the NW electrode 10 and the HPW electrode 11, respectively; and the two ends of bias circuit 3 are connected to the HPW electrode 11 and the N-buried layer electrode 12, respectively. All three bias circuits are connected to the quenching and gating unit. The specific circuit design of each bias circuit and the quenching and gating unit can be implemented using existing related technologies, and no specific restrictions are imposed here.

[0044] During the photosensitization process, one of the bias circuits is activated by the quenching and gating unit, causing its corresponding avalanche region to be in an avalanche state. Other avalanche regions are not in an avalanche state because their bias voltage is lower than the breakdown voltage. By having different bias circuits operate in a time-division manner, the separate sensing of blue, green, and red light can be achieved.

[0045] This invention provides a SPAD device structure based on optoelectronic co-design, offering an extremely low-light full-color single-photon detector structure in which low-light full-color pixel structures are periodically arranged. Each low-light full-color pixel structure has three avalanche zones from bottom to top, respectively providing detection efficiency responses for red, green, and blue light, and each avalanche zone can be controlled by a bias circuit to be in an avalanche state at different times. This invention can provide a high-detection-efficiency device structure without increasing the number of masks or manufacturing costs, and can alleviate the burden of subsequent complex algorithms caused by inconsistent spectral responses under extremely low light conditions.

[0046] Secondly, embodiments of the present invention provide a method for fabricating an extremely weak light full-color single-photon detector structure, used to fabricate the extremely weak light full-color single-photon detector structure described in the first aspect. For example... Figure 5 As shown, the method includes the following steps S1 to S15: S1, Obtain a P-type silicon substrate and prepare an N-type buried layer 4 on the upper surface of the P-type silicon substrate; Specifically, firstly, a P-type wafer (a P-type wafer is a semiconductor material that is based on silicon single crystal and is made to conduct electricity mainly by holes by doping with group III elements such as boron) is selected as the substrate. The surface of the silicon wafer is cleaned and prepared to remove impurities and contaminants, thereby obtaining a P-type silicon substrate.

[0047] Next, the P-type silicon substrate is cleaned to remove surface contaminants; then, a shielding oxide layer (such as silicon dioxide) is grown on the surface of the P-type silicon substrate through a thermal oxidation process; the N-type buried layer region is defined by a photolithography process, and a high concentration of N-type impurities (phosphorus or arsenic ions, with a doping concentration greater than or equal to) is implanted into this region using an ion implantation process. A high-concentration N-type thin epitaxial layer, with a thickness of 0.5-0.8 μm, is doped onto a P-type silicon substrate to form an N-type buried layer. After removing the photoresist, high-temperature annealing is performed to activate impurities and advance the junction depth, forming a flat N-type buried layer 4. In this embodiment of the invention, the high-temperature annealing temperature can be 900°~1000°.

[0048] S2, a P-type epitaxial layer is grown on the upper surface of the N-type buried layer 4; First, the substrate with the N-type buried layer 4 is cleaned to remove surface contaminants and the native oxide layer, preparing a clean silicon surface for epitaxial growth. Then, a P-type epitaxial layer (i.e., a P-type doped single-crystal silicon layer, doped with boron) with specific resistivity and thickness is grown on the surface of the N-type buried layer 4 using a chemical vapor deposition (CVD) epitaxial process with in-situ doping. The doping concentration and thickness of this P-type epitaxial layer need to be precisely controlled (doping concentration is...). This ensures that the first avalanche zone 21, the second avalanche zone 22, and the third avalanche zone 23 formed subsequently have the required electric field distribution and photoelectric response characteristics.

[0049] S3. Using an etching process, deep trenches are etched on both sides of the current structure, penetrating the P-type epitaxial layer and reaching the N-type buried layer 4. An insulating oxide layer is grown on the sidewall and bottom of the deep trench to form a full-trench oxide layer isolation structure 61. Then, the center of the deep trench is filled with metal to form a buried metal pillar filling structure 62, which together with the adjacent full-trench oxide layer isolation structure 61 constitutes a buried metal full-trench isolation structure 6. Specifically, S3 may include the following steps: S31, Surface passivation and hard mask fabrication: A thin first oxide layer is grown on the surface of a wafer with a P-type epitaxial layer using a thermal oxidation process; subsequently, a first silicon nitride layer is deposited on the first oxide layer using chemical vapor deposition (CVD). The first oxide layer is used to relieve stress in subsequent processes and protect the silicon surface; the first silicon nitride layer serves as a barrier layer and hard mask for subsequent deep trench etching and chemical mechanical polishing (CMP) to protect the non-isolated areas.

[0050] S32, Define the isolation region pattern: Coat photoresist on the first silicon nitride layer, perform photolithography using a photomask that defines the full-groove isolation region pattern, and transfer the pattern onto the photoresist; then, using the photoresist as a mask, selectively etch the underlying first silicon nitride layer and first pad oxide layer to expose the silicon region that needs to be etched into a deep trench.

[0051] The purpose of this step is to precisely pattern the location of the full-groove isolation structure onto the wafer surface, preparing it for deep trench etching.

[0052] S33, Deep Trench Etching: Using a patterned first silicon nitride layer as a mask, an anisotropic dry etching process (such as reactive ion etching, RIE) is employed to etch deep trenches into the exposed silicon region, penetrating the P-type epitaxial layer and ultimately contacting the upper surface of the N-type buried layer 4. This forms a deep trench structure that physically isolates adjacent pixels and serves as a channel for subsequent metal filling.

[0053] S34, Preparation of the trench wall insulating layer and filling oxide: The etched deep trench is cleaned and subjected to thermal oxidation treatment to grow a high-quality padding silicon dioxide layer on the sidewalls and bottom of the deep trench; subsequently, silicon dioxide is deposited in the deep trench using methods such as high-density plasma chemical vapor deposition (HDP-CVD). The medium is used to basically fill it.

[0054] Among them, thermally grown padding silica is used to repair etching damage and ensure the insulation properties of the trench wall; the silica deposited in the deep trench constitutes the main body of the full-trench oxide layer isolation structure 61, realizing electrical isolation between pixels.

[0055] S35, Oxide Planarization: Using chemical mechanical polishing (CMP) process, with the first silicon nitride layer as the stop layer, excess silicon dioxide on the wafer surface is removed to planarize the wafer surface and form the final full-groove oxide layer isolation structure 61.

[0056] The purpose of this step is to remove excess dielectric material from the surface, achieve global planarization of the wafer, and provide a smooth surface for subsequent metal filling and device fabrication.

[0057] S36, forming a metal conduction pillar: using a selective etching process, a portion of the silicon dioxide in the center of the full-groove oxide layer isolation structure 61 is removed to form a channel for metal filling; subsequently, a metal barrier layer (such as Ti / TiN) and a metal core material (such as W or Cu) are deposited sequentially, and the channel is completely filled by a process combining chemical vapor deposition (CVD) or physical vapor deposition (PVD) with electroplating.

[0058] The metal barrier layer is used to prevent unfavorable diffusion between the metal and the silicon material; the filled metal is used to form a buried metal pillar filling structure 62 that is in 4-ohm contact with the N-type buried layer.

[0059] S37, Metal Planarization: Chemical mechanical polishing (CMP) is used again to remove excess metal and metal barrier layer material from the surface, making the surface of the metal pillar flush with the surrounding oxide layer surface, thus completing the preparation of the buried metal full-groove isolation structure 6.

[0060] The purpose of this step is to achieve the final planarization of the wafer surface, ensure that the buried metal pillar filling structure 62 is confined within the trench, and together with the full-trench oxide layer isolation structure 61, form a complete buried metal full-trench isolation structure 6, providing a vertical conductive path for the N buried electrode 12.

[0061] Through steps S31 to S37 above, the fabrication of the buried metal full-groove isolation structure 6 is completed. This structure simultaneously achieves the dual functions of electrical isolation between adjacent pixels and providing a low-resistance vertical current path for the N-type buried layer 4.

[0062] S4 defines the active region and forms a trench for the STI shallow trench isolation structure that isolates adjacent active regions; The purpose of this step is to precisely delineate the active region of the device on the wafer and prepare for the subsequent formation of the STI shallow trench isolation region between adjacent N+ wells 7 and P+ wells 8 on the side.

[0063] Specifically, this may include the following steps: S41, Growth of the second oxygen cushion layer and deposition of the hard mask layer: On the wafer surface where the buried metal full-groove isolation structure 6 has been fabricated, a thin base silicon dioxide layer is grown as a second base oxide layer using a thermal oxidation process. Subsequently, a second silicon nitride layer and a silicon oxynitride layer are deposited sequentially by chemical vapor deposition (CVD) as hard mask layers for subsequent etching.

[0064] The second oxygen pad layer is used to relieve stress; the composite hard mask layer composed of the second silicon nitride layer / silicon oxynitride layer has good etching selectivity and barrier properties, and is used to protect the active area in subsequent shallow trench etching and planarization processes.

[0065] S42, active area lithography: Photoresist is coated on the hard mask layer obtained in S41. Photolithography is performed using a photomask that defines the active area pattern (i.e., the inverse pattern of the silicon body region should be preserved) to transfer the designed active area pattern onto the photoresist.

[0066] This step precisely defines the silicon region where future device structures such as traps and electrodes will be fabricated. The areas not protected by photoresist are the areas where STI isolation trenches are planned to be formed.

[0067] S43, active region etching to form STI trenches: Using a patterned photoresist as a mask, the silicon oxynitride layer, the second silicon nitride layer, and the second oxide pad layer are selectively etched sequentially. Subsequently, anisotropic dry etching (such as reactive ion etching, RIE) is employed to etch the exposed silicon, forming a shallow trench of a certain depth, less than the depth of N-well 2. The N-well junction depth is between 1.2 and 1.5 μm, thus allowing STI to be controlled to approximately 1 μm. This shallow trench is the trench of the STI shallow trench isolation structure, and its location precisely corresponds to the planned isolation region between adjacent N+ well 7 and P+ well 8 in the device structure.

[0068] This step forms isolation trenches through physical etching, laying the foundation for subsequent filling with insulating medium and achieving electrical isolation between adjacent active regions.

[0069] S44, Trench oxidation and insulation material filling: The etched shallow trenches are cleaned and subjected to thermal oxidation to grow a high-quality silica backing layer on the trench walls and bottom to repair the etching damage. Then, the shallow trenches are completely filled with insulating media such as silica using methods such as high-density plasma chemical vapor deposition (HDP-CVD).

[0070] The silica liner grown in the shallow trench in this step improves the interface properties; the filled insulating medium is used to achieve electrical isolation.

[0071] S45, Chemical Mechanical Polishing and Hard Mask Removal: Chemical mechanical polishing (CMP) is used, with the second silicon nitride layer as a stop layer, to remove excess insulating dielectric from the wafer surface, thereby planarizing the wafer surface. Subsequently, selective wet or dry etching processes are used to remove the hard mask layer and the second oxide pad layer composed of the second silicon nitride / silicon oxynitride layer.

[0072] The purpose of this step is to achieve global planarization of the wafer and provide a clean, flat silicon surface for subsequent processes. At this point, the shallow trench filled with insulating dielectric and flush with the silicon surface constitutes the final STI shallow trench isolation region.

[0073] Through the above steps S41 to S45, the active region was defined and the STI shallow trench isolation structure was fabricated, providing precise boundary constraints for the subsequent formation of N+ well 7 and P+ well 8 in the isolated active region by ion implantation, ensuring reliable isolation between the electrodes of the device.

[0074] S5, a deep P-well 3 is formed in the P-type epitaxial layer between the two sides of the metal-buried full-groove isolation structure 6 by photolithography and ion implantation process; In this embodiment of the invention, the well is fabricated from deep to shallow before the flipping device is constructed.

[0075] The photolithography and ion implantation processes involved in S5 can be roughly divided into the following parts: S51, photolithography process: First, a layer of photoresist is uniformly coated on the surface of the wafer.

[0076] Then, photolithography is performed using a specially designed deep P-well mask. The pattern of this mask defines the area where the deep P-well 3 needs to be implanted. After UV exposure and development, only the photoresist above the P-type epitaxial layer where the deep P-well 3 area is to be formed is removed, exposing it, while the other areas are protected by the remaining photoresist.

[0077] S52, ion implantation process: Next, using patterned photoresist as a mask, high-energy ion implantation is performed on the wafer. The implanted ions are P-type dopants, typically boron (B) ions.

[0078] Because a relatively deep junction is required, this step employs a high implantation energy (typically in the range of hundreds of keV to MeV) to ensure that the dopant ions can penetrate to a certain depth, forming a deep P-well 3 structure that encapsulates the subsequent N-well 2. The implantation dose is precisely designed to achieve the desired doping concentration. The doping concentration of the deep P-well 3 can be... The doping concentration of the N-type buried layer 4 can be The latter has a slightly higher doping concentration, causing the electric field peak to be slightly biased towards the 4th side of the N-type buried layer.

[0079] S53, Photoresist Removal and Annealing: After ion implantation, the remaining photoresist is completely removed by methods such as ashing or chemical stripping.

[0080] Subsequently, a high-temperature annealing process is performed. This annealing process has a dual purpose: first, to activate the implanted boron impurity atoms, making them substitute atoms to play a P-type doping role; second, to repair the damage caused by ion implantation to the silicon lattice and promote a certain degree of redistribution of impurities, thereby forming the final junction depth and doping profile of the deep P-well 3 that meets the design requirements.

[0081] Among them, the deep P-well 3 and the N-type buried layer 4 form the third avalanche zone 23.

[0082] S6, In the top center region within the deep P-well 3, an N-well 2 is formed by photolithography and ion implantation processes; S6 aims to form an N-type doped region, i.e., N-well 2, in the top central region inside the already formed deep P-well 3 through photolithography and ion implantation processes. S6 may include the following steps: S61, photolithography process: Photoresist is coated on the surface of the wafer.

[0083] Photolithography is performed using a specially designed N-well mask. The pattern window of this mask is smaller than and completely contained within the pattern of the deep P-well 3, thus precisely defining the injection area of ​​the N-well 2. After exposure and development, only the central region where the N-well 2 is to be formed is exposed.

[0084] S62, ion implantation process: Using patterned photoresist as a mask, medium- to high-energy ion implantation is performed. The implanted ions are N-type dopants, typically phosphorus (P) or arsenic (As) ions.

[0085] S6 uses an N-type dopant (phosphorus / arsenic), the opposite of the P-type dopant (boron) in S5, to form a PN junction.

[0086] The N-well 2 and the deep P-well 3 form the second avalanche zone 22.

[0087] In this step, the implantation energy of N-well 2 is typically lower than that of the deep P-well 3 to ensure that the junction depth of N-well 2 is smaller than that of the deep P-well 3, thus completely surrounding it. The implantation dose is also precisely designed to form a doping concentration that matches that of the deep P-well 3, together constituting a performance-optimized second avalanche region 22. The doping concentration of N-well 2 can be... .

[0088] S63, Photoresist Removal and Annealing: After injection, the photoresist is removed.

[0089] High-temperature annealing is performed to activate N-type impurities and repair lattice damage. This annealing process is typically performed in conjunction with subsequent annealing processes for other well regions to optimize the overall thermal budget.

[0090] S7, N+ wells 7 are formed in the top two sides of the N well 2 by photolithography and ion implantation processes; Step S7 involves forming a heavily doped N-type contact region, i.e., N+ well 7, within the already formed N-well 2.

[0091] S7 may include the following steps: S71, photolithography process: Photoresist is coated on the surface of the wafer.

[0092] Photolithography is performed using a specially designed N+ well mask. The pattern of this mask precisely defines the contact regions that require heavy doping, located on both sides of the upper surface of the N-well 2. After exposure and development, only these small, specific areas are exposed.

[0093] S72, ion implantation process: Using patterned photoresist as a mask, low-energy, high-dose ion implantation is performed. The implanted ions are N-type dopants, typically phosphorus or arsenic.

[0094] The purpose of S5 / S6 is to form the depletion region of the PN junction, while the purpose of S7 is to form a low-resistance ohmic contact.

[0095] S72 employs high-dose implantation, resulting in a doping concentration in N+ well 7 that is much higher than that in N well 2, thereby significantly reducing the contact resistance of the subsequently fabricated NW electrode 10.

[0096] This step employs low-energy implantation to ensure the heavily doped region is very shallow, confined to the surface of N-well 2, avoiding excessive influence on the electric field distribution of the underlying PN junction. N+ well 7 represents the ohmic contact doping concentration, which can be... about.

[0097] S73, Photoresist Removal and Annealing: After injection, the photoresist is removed.

[0098] Rapid thermal annealing is performed. The main purpose of this annealing is to activate the high concentration of impurities and control their diffusion depth, thereby forming a precise, shallow-junction, heavily doped region. Through step S7, N+ wells 7 were successfully fabricated on both sides of the surface of N well 2. This provides a key ohmic contact interface for the fabrication of low-resistance NW electrode 10 in the subsequent step S10, ensuring that the bias voltage can be efficiently applied to the second avalanche region 22.

[0099] S8, a central P+ well 1 is formed in the top center region of N-well 2 between two N+ wells 7 by photolithography and ion implantation process; S8 is designed to form a heavily doped P-type region, namely the central P+ well 1, on the inner upper surface of N-well 2 and in the central region between the two N+ wells 7, through photolithography and ion implantation processes.

[0100] The central P+ well 1 and N well 2 form the first avalanche zone 21, which has a hemispherical cross-section.

[0101] S8 may include the following steps: S81, photolithography process: Photoresist is coated on the surface of the wafer.

[0102] Photolithography is performed using a specially designed central P+ well mask. The mask is patterned as a small window located in the center of N-well 2, isolated from the N+ wells 7 on both sides. After exposure and development, only this central area is exposed.

[0103] S82, ion implantation process: Using patterned photoresist as a mask, low-energy, high-dose ion implantation is performed. The implanted ions are P-type dopants, typically boron (B) ions.

[0104] S82 uses heavy P-type doping (P+) to form a local P+ region in the background of the N-type N-well 2. This is to form an abrupt junction with N-well 2, the depletion region of which will extend from the junction surface to the N-well side. Under the action of an electric field, it is easy to form a hemispherical depletion region, which is why the first avalanche region 21 has a special shape.

[0105] S82 employs low-energy, high-dose implantation. Low energy is used to form a shallow junction, ensuring the P+ region is confined to the N-well surface; high dose is used to achieve heavy doping, ensuring the formation of an abrupt junction and obtaining the desired electric field distribution. The central P+ well 1 has an ohmic contact doping concentration that can be achieved... about.

[0106] S83, Photoresist Removal and Annealing: After injection, the photoresist is removed.

[0107] Rapid thermal annealing is performed to activate boron impurities and control their diffusion, ultimately forming a precise central P+ well 1 structure.

[0108] Through step S8, a heavily doped central P+ well 1 was successfully fabricated at the center of N-well 2. The interface between the two constitutes the first avalanche region 21, which is sensitive to red light and has a hemispherical profile. This is one of the key structures for achieving full-color detection.

[0109] S9, P+ wells 8 are formed in the top region of deep P wells 3 on both sides of N well 2 and the top center region of P+ well 1 by photolithography and ion implantation process, and are filled in the trench of the STI shallow trench isolation structure formed in the region between adjacent N+ wells 7 and P+ wells 8 on the side to form an STI shallow trench isolation region. Step S9 includes two core operations: first, forming a heavily doped P+ contact region (P+ well 8) in a designated area; and second, completing the final fabrication of the STI shallow trench isolation structure etched in S4.

[0110] S9 may include the following steps: S91, photolithography process: Photoresist is coated on the surface of the wafer.

[0111] Photolithography is performed using a specially designed P+ well mask. The pattern of this mask simultaneously exposes two regions: the top region within the deep P-wells 3 on both sides of the N-well 2, and the top central region within the central P+ well 1. After exposure and development, only these regions are exposed.

[0112] S92, ion implantation process: Using patterned photoresist as a mask, low-energy, high-dose ion implantation is performed. The implanted ions are P-type dopants, typically boron (B) ions.

[0113] The purpose of this step is very similar to S7 (forming an N+ well), but it targets the P-type region: Its function is to form heavily doped P+ contact regions in the deep P-well 3 and the central P+ well 1, so as to provide low-resistance ohmic contacts for the subsequent fabrication of HPW electrode 11 and central P+ electrode 9.

[0114] This step employs low-energy, high-dose implantation to ensure the formation of a shallow junction, heavily doped region, thereby minimizing contact resistance. Here, P+ well 8 represents the ohmic contact doping concentration, which can be... about.

[0115] S93, Photoresist Removal and Annealing: After injection, the photoresist is removed.

[0116] A final annealing is typically performed in conjunction with the previous annealing process to simultaneously activate impurities in all well regions.

[0117] S94, complete the filling of the STI shallow trench isolation zone: After ion implantation of all well regions (including S5-S93) is completed, the STI trenches etched in step S4 and running through the adjacent N+ wells 7 and P+ wells 8 are finally filled with dielectric (usually silicon dioxide) and chemically mechanically polished to form the final STI shallow trench isolation region.

[0118] This operation achieves electrical isolation between the two adjacent heavily doped regions, N+ well 7 and P+ well 8, preventing short circuits or leakage between them.

[0119] It should be noted that both the central p+ well 1 and the extracted p+ well 8 are generated through ion implantation, but the concentration of the central p+ well 1 is lower, requiring fewer doping cycles.

[0120] Step S9 completed the fabrication of all heavily doped regions (P+ well 8 and N+ well 7) for electrode contacts, and finally achieved reliable isolation between them through STI. At this point, the semiconductor body structure of the device (all well regions and PN junctions) has been fully fabricated, preparing for subsequent electrode fabrication and metal interconnection.

[0121] S10, prepare contact holes and deposit metal to prepare a central P+ electrode 9 at the bottom of the middle P+ well 8; prepare an NW electrode 10 at the bottom of the N+ well 7; prepare an HPW electrode 11 at the bottom of the P+ well 8 on one side, and prepare an N buried layer electrode 12 at the bottom of the buried metal pillar filling structure 62 of the buried metal full trench isolation structure 6 on the same side. Then perform multilayer metal interconnection and expose the PADs that need to be connected. S10 marks the beginning of the "back-end process," with its core objective being to fabricate metal electrodes and build interconnect systems on the semiconductor structure where all well implantation has been completed. This involves bringing the individual electrodes within the pixel to bonding pads and may include the following steps: S101, Interlayer medium layer: After all ion implantation and annealing processes are completed, a thick layer of silicon dioxide or a low-k dielectric material is deposited on the wafer surface using methods such as chemical vapor deposition as an interlayer dielectric layer. The purpose is to achieve electrical isolation between subsequent metal interconnects and the silicon substrate and the device structures therein.

[0122] S102, forming a contact hole: The contact hole pattern is defined on the interlayer dielectric layer using photolithography. Subsequently, a dry etching process is used to etch deep holes in the dielectric layer, exposing the silicon surfaces of the underlying central P+ well 8, N+ well 7, and the P+ well 8 on one side, as well as the top of the buried metal pillar filling structure 62 in the buried metal full-groove isolation structure 6 on the same side. The purpose is to establish an electrical connection channel between the metal electrode and the silicon active region or the underlying metal pillar.

[0123] S103, metallization and contact electrode formation: First, a contact metal barrier / adhesion layer (such as Ti / TiN) is deposited on the entire wafer surface, followed by the deposition of a contact metal (such as tungsten W) to completely fill the contact holes.

[0124] Then, excess metal on the wafer surface is removed by chemical mechanical polishing (CMP), leaving only the metal plugs inside the holes. These metal plugs constitute the contact electrodes that form ohmic contact with the underlying material, corresponding to the bottom contact points of the future central P+ electrode 9, NW electrode 10, HPW electrode 11, and N buried electrode 12, respectively.

[0125] S104, constructing multilayer metal interconnects: This process is repeated cyclically to build the required interconnect layers, specifically including: S1041, Deposit intermetallic dielectric layer: Deposit another dielectric layer on the wafer surface where contact holes have been filled.

[0126] This step is part of the standard process and will not be described in detail here. S1042, Photolithography and Etching of Through-Hole / Metalline Trench: Through-holes connecting the lower and upper metal layers, as well as metalline trenches for wiring, are formed in the dielectric layer deposited in S1041 by photolithography and etching.

[0127] S1043, Metal Filling and Planarization: Deposit metals such as copper (usually using a damascene process), fill vias and trenches, and planarize using CMP. This forms a single layer of metal interconnects.

[0128] Repeat the above sub-steps, building layer by layer, until a multi-layer metal interconnect network is formed that connects each contact electrode to a predetermined location.

[0129] S105, forming the top layer bonding pad: At the top layer of the multilayer metal interconnect, bonding pads are defined and formed on the top metal through photolithography and etching.

[0130] The positions of these pads are precisely aligned with the corresponding circuit pads on the lower-layer CMOS circuit wafer. This provides an interface for electrical connection and mechanical fixation for the subsequent three-dimensional integration bonding in step S11. The corresponding circuit cells on the lower-layer CMOS circuit wafer include a first bias circuit, a second bias circuit, and a third bias circuit, as well as quenching and gating units connected to the first, second, and third bias circuits.

[0131] Through steps S101 to S105 above, the entire metallization process on the front side of the upper-layer detector wafer is completed, forming functional electrodes and interconnect systems, preparing for three-dimensional integration with the lower-layer processing circuit wafer. In CMOS processes, electrode formation is a standardized process step and will not be described in more detail here.

[0132] S11, a passivation layer is deposited for protection, and then the upper wafer and the lower CMOS circuit wafer are bonded together using three-dimensional integration technology; The lower-layer CMOS circuit wafer includes a first bias circuit, a second bias circuit, and a third bias circuit, as well as a quenching and gating unit connected to the first bias circuit, the second bias circuit, and the third bias circuit. S11 is the core of 3D integration, designed to permanently bond the upper-layer detector wafer to the lower-layer CMOS circuit wafer, achieving electrical interconnection and mechanical support. Specifically, it may include the following steps: S111, deposited front passivation layer: On the front side of the upper wafer where the top metal interconnects and bonding pads (PADs) have been fabricated, a dense passivation layer (typically a composite layer of silicon nitride or silicon oxide and inorganic materials) is deposited using methods such as chemical vapor deposition (CVD). The purpose is to protect the front-side metal interconnect structure from contamination, scratches, and wet corrosion during subsequent processes, ensuring the long-term reliability of the device.

[0133] S112, Photolithography definition bonding window: The bonding window pattern is defined on the passivation layer using photolithography. Then, a dry or wet etching process is used to precisely remove the passivation layer above the bonding pads (PADs), exposing the metal pads while preserving the passivation layer in other areas for protection. This provides a clean, exposed metal contact surface for subsequent copper-copper bonding or other bonding processes.

[0134] S113, Surface pretreatment and activation: Surface pretreatment (such as chemical mechanical polishing (CMP) and cleaning) is performed on the bonding surfaces of the upper-layer wafer and the lower-layer CMOS circuit wafer to ensure that the surfaces achieve extremely high flatness, cleanliness and smoothness.

[0135] The bonding surfaces are activated using techniques such as plasma treatment to increase surface energy and enhance bonding strength.

[0136] The purpose of S113 is to provide the necessary surface conditions for obtaining high-yield, high-strength permanent bonding.

[0137] S114, Precision Alignment and Permanent Bonding: In a dedicated bonding apparatus, the upper-layer detector wafer and the lower-layer CMOS circuit wafer are precisely aligned to ensure that the bonding pads of each pixel on the upper-layer wafer precisely overlap with the pads of the corresponding circuit units (such as bias circuits, quenching and gating units' input / output terminals) on the lower-layer wafer.

[0138] Under certain pressure and temperature, a physicochemical reaction occurs at the bonding interface of the two wafers, achieving permanent bonding. For copper-copper hybrid bonding, the bonding process causes the copper pads on both sides to diffuse and fuse, while the dielectric layer also undergoes covalent bonding, thus achieving the integration of electrical interconnection and mechanical fixation. Specific pressure and temperature parameters are set as needed.

[0139] The purpose of this step is to achieve a high-density, low-parasitic-effect electrical connection in the vertical direction between the upper detector pixels and the lower processing circuitry, and to solidify the two wafers into a single stacked structure.

[0140] S115, Post-bonding processing and verification: After bonding is completed, post-processing such as annealing may be required to enhance the stability of the bonding interface.

[0141] The quality of the bonding interface was initially verified through electrical testing and other means.

[0142] The aim is to ensure the mechanical strength and electrical reliability of the three-dimensional integrated structure.

[0143] Through steps S111 to S115 above, the upper-layer detector wafer and the lower-layer CMOS circuit wafer are successfully integrated into a single unit. Subsequently, the back side of the P-type silicon substrate of the upper-layer wafer will serve as the light incident surface and the surface for subsequent processing, while the lower-layer CMOS wafer provides indispensable mechanical support for the subsequent back-side thinning process.

[0144] S12, flip the bonded stacked wafer structure and perform substrate thinning from the back side of the P-type silicon substrate; The bonded stacked wafer structure is flipped over, and the P-type silicon substrate is mechanically ground and chemically mechanically polished from the back side to thin the substrate to the target thickness of 3-10 μm.

[0145] S13, an N-type buried electrode plate 121 is formed on the back side of the thinned P-type silicon substrate, so that it makes electrical contact with the buried metal pillar filling structure 62 in the exposed buried metal full-groove isolation structure 6, thereby conducting to the N-type buried layer 4. S13 aims to lead out a common bias electrode from the back side of the wafer for the N-type buried layer 4. Its successful implementation depends on the exposure of the ends of the buried metal pillar filling structure 62 in the buried metal full-groove isolation structure 6 to the back side after the thinning in S12. S13 may specifically include the following steps: S131, Backside passivation and hard mask fabrication: On the back side of the thinned and cleaned P-type silicon substrate, a thin silicon dioxide layer is grown as a passivation layer using thermal oxidation or chemical vapor deposition. On this passivation layer, a silicon nitride layer is deposited by CVD as a hard mask layer for subsequent photolithography and etching.

[0146] The passivation layer of S131 is used to protect the fragile back side of the thinned silicon, while the hard mask layer is used for precise pattern transfer.

[0147] S132, Photolithography defines the N-buried electrode plate region: Photoresist is coated onto the silicon nitride layer obtained in S131.

[0148] Photolithography is performed using an N-layer buried electrode mask to transfer the pattern of the electrode plate onto the photoresist. This pattern window is precisely aligned with and larger than the cross-section of the exposed buried metal pillar filling structure 62 below.

[0149] The purpose of S132 is to define the area that the metal electrode plate needs to cover.

[0150] S133, etching to open the contact window: Using patterned photoresist as a mask, the silicon nitride hard mask layer and the underlying silicon dioxide passivation layer in the exposed area are etched away in sequence, opening a contact window that reaches the end of the buried metal pillar filling structure 62.

[0151] Remove the photoresist.

[0152] The purpose is to expose the surface of the metal pillars that require electrical connections, in preparation for metal deposition.

[0153] S134, Metal deposition and patterning to form electrode plates: A layer of metal (such as aluminum or copper-based alloy) is deposited on the entire back side using processes such as physical vapor deposition (PVD, such as sputtering).

[0154] The metal layer is patterned through photolithography and etching processes to form an N-buried electrode plate 121 that is in close contact with the buried metal pillar filling structure 62, and excess metal is removed.

[0155] The purpose of S134 is to form a large-area, low-resistance back common electrode and to achieve electrical connection to the N-type buried layer 4 through buried metal pillars.

[0156] S14, an antireflection layer 5 is prepared on the entire back side, with its surface away from the N-type buried layer 4 being the light incident surface; S14 is the core of the optical processing, designed to maximize the coupling efficiency of light incident from the back side. This step must be performed after all back-side patterning processes (such as electrode fabrication in S13) have been completed to avoid damaging the delicate optical structure in subsequent processes.

[0157] S14 may include the following steps: S141, Surface cleaning and planarization: After completing S13, the back side of the wafer is thoroughly cleaned to ensure a clean surface. If structures such as metal electrode plates formed during S13 cause surface unevenness, dielectric filling and chemical mechanical polishing (CMP) may be required to achieve global planarization. This provides an ideal optical interface for fabricating a high-quality antireflection layer.

[0158] S142, Deposition of antireflection films or fabrication of micro / nano structures: S142 can include two schemes, either of which can be used to form an anti-reflection layer 5 on the back of the device, which is composed of a periodic arrangement of cylindrical microstructures of the same height and different diameters. The surface of the anti-reflection layer 5 away from the N-type buried layer 4 is the light incident surface, which is used to improve the incident and coupling efficiency of red, green and blue light.

[0159] In the antireflection layer 5, composed of periodically arranged cylindrical microstructures, the height of each part is approximately 200-400 nm, and the diameter ranges from 40-200 nm, covering 0-2 The phase range. Specifically, the two schemes are: Option 1 (Multilayer Dielectric Film): Multiple dielectric films with different refractive indices are sequentially deposited on the back side using methods such as plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). , , (A combination of these elements) forms a broadband antireflective coating based on the principle of optical interference.

[0160] Option 2 (Micro / Nano Structure): An antireflection layer 5, as described in the claims, is formed on the back silicon surface using nanoimprinting or mask-based etching processes. This layer consists of a periodic arrangement of cylindrical microstructures of the same height but different diameters. This structure reduces reflection through a gradient refractive index effect.

[0161] The purpose of S142 is to significantly reduce the reflection loss of incident light (especially red light) on the silicon surface and improve photon detection efficiency. The final antireflection layer 5, located away from the outermost surface of the N-type buried layer 4, is the light incident surface of the device.

[0162] S15 employs a packaging scheme suitable for back-illuminated devices for dicing, packaging, and wire bonding to complete the fabrication of an extremely weak light full-color single-photon detector.

[0163] This step involves using a packaging form suitable for a back-illuminated structure, allowing light to pass through the anti-reflection layer 5 from the back and enter the device interior, thus achieving full-color single-photon detection in extremely weak light.

[0164] This invention provides a device structure with high detection efficiency without increasing the manufacturing cost by adding too many masks, and can reduce the pressure of subsequent complex algorithms caused by inconsistent spectral response under extremely weak light conditions.

Claims

1. A structure for an extremely weak light full-color single-photon detector, characterized in that, It includes multiple low-light full-color pixel structures arranged in an array in a two-dimensional direction, each low-light full-color pixel structure comprising: The structure consists of a P-type epitaxial layer, an N-type buried layer (4), a P-type silicon substrate, an anti-reflection layer (5), and a buried metal full-groove isolation structure (6) arranged from bottom to top. The surface of the anti-reflection layer (5) away from the N-type buried layer (4) is the light incident surface. An N-type buried layer electrode plate (121) is led out from the upper end of the buried metal full-groove isolation structure (6) to contact the upper surface of the N-type buried layer (4). Within the P-type epitaxial layer, from top to bottom, a deep P-well (3), an N-well (2), and a central P+well (1) are arranged in a semi-enclosed manner. The central P+well (1) and the N-well (2) form the first avalanche zone (21), which has a hemispherical profile. The N-well (2) and the deep P-well (3) form the second avalanche zone (22), and the deep P-well (3) and the N-type buried layer (4) form the third avalanche zone (23). The three avalanche zones respectively provide detection efficiency responses for red light, green light, and blue light. The N-wells (2) on both sides of the central P+well (1) are... An N+ well (7) is provided inside the N+ well (2); P+ wells (8) are provided inside the deep P-wells (3) on both sides of the N-well (2) and inside the central P+ well (1); a central P+ electrode (9) is provided at the bottom of the central P+ well (8); an NW electrode (10) is provided at the bottom of the N+ well (7); an HPW electrode (11) is provided at the bottom of the P+ well (8) on one side, and an N-buried layer electrode (12) is provided at the bottom of the buried metal full-groove isolation structure (6) on the same side; an STI shallow trench isolation area is provided between the adjacent N+ wells (7) and P+ wells (8) on the side.

2. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, The buried metal full-slot isolation structure (6) includes a full-slot oxide layer isolation structure (61) and a buried metal pillar filling structure (62) disposed in the middle of the full-slot oxide layer isolation structure (61); wherein, the N buried layer electrode (12) is disposed at the bottom of the buried metal pillar filling structure (62) and is led out through the N buried layer electrode plate (121); two adjacent low-light full-color pixel structures share a buried metal full-slot isolation structure (6).

3. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, The doping concentration of the N-type buried layer (4) is greater than or equal to .

4. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, The shapes of the central P+ trap (1), N trap (2), deep P trap (3), N-type buried layer (4) and anti-reflection layer (5) are circular, rectangular, rounded rectangle or regular polygon.

5. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, The shape of the buried metal full-slot isolation structure (6), N+ trap (7), P+ trap (8), central P+ electrode (9), NW electrode (10), HPW electrode (11), and N buried layer electrode (12) is ring-shaped.

6. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, Both the second avalanche zone (22) and the third avalanche zone (23) are planar PN junctions.

7. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, The antireflection layer (5) is composed of a periodic arrangement of cylindrical microstructures of the same height but different diameters.

8. The structure of the extremely weak light full-color single-photon detector according to claim 1, characterized in that, Each low-light full-color pixel structure further includes: a first bias circuit, a second bias circuit, and a third bias circuit that provide bias voltages for the first avalanche region (21), the second avalanche region (22), and the third avalanche region (23), respectively; and a quenching and gating unit connected to the first bias circuit, the second bias circuit, and the third bias circuit; the quenching and gating unit is used to control one of the first bias circuit, the second bias circuit, and the third bias circuit to work, so as to provide a bias voltage for the corresponding avalanche region and put it in an avalanche state.

9. A method for fabricating an extremely weak light full-color single-photon detector structure, characterized in that, The method for preparing the extremely weak light full-color single-photon detector structure according to any one of claims 1-8 includes: S1, obtain a P-type silicon substrate and prepare an N-type buried layer on the upper surface of the P-type silicon substrate (4); S2, a P-type epitaxial layer is grown on the upper surface of the N-type buried layer (4); S3, using an etching process, deep trenches are etched on both sides of the current structure, penetrating the P-type epitaxial layer and reaching the N-type buried layer (4). An insulating oxide layer is grown on the sidewall and bottom of the deep trench to form a full-trench oxide layer isolation structure (61). Then, the center of the deep trench is filled with metal to form a buried metal pillar filling structure (62), which together with the adjacent full-trench oxide layer isolation structure (61) constitutes a buried metal full-trench isolation structure (6). S4 defines the active region and forms a trench for the STI shallow trench isolation structure that isolates adjacent active regions; S5, a deep P-well (3) is formed in the P-type epitaxial layer between the two sides of the buried metal full-groove isolation structure (6) by photolithography and ion implantation process; S6, an N-well (2) is formed in the top center region within the deep P-well (3) by photolithography and ion implantation. S7, N+ wells (7) are formed in the top two sides of the N well (2) by photolithography and ion implantation process; S8, a central P+ well (1) is formed in the top center region of the N-well (2) between the two N+ wells (7) by photolithography and ion implantation process; S9, P+ wells (8) are formed in the top region of the deep P wells (3) on both sides of the N well (2) and in the top center region of the P+ well (1) by photolithography and ion implantation, and are filled in the trench of the STI shallow trench isolation structure formed between the adjacent N+ wells (7) and P+ wells (8) on the side to form an STI shallow trench isolation area; wherein, the central P+ well (1) and the N well (2) form a first avalanche zone (21) and have a hemispherical cross-section; the N well (2) and the deep P well (3) form a second avalanche zone (22), and the deep P well (3) and the N-type buried layer (4) form a third avalanche zone (23); S10, prepare contact holes and deposit metal to prepare a central P+ electrode (9) at the bottom of the middle P+ well (8); prepare an NW electrode (10) at the bottom of the N+ well (7); prepare an HPW electrode (11) at the bottom of the P+ well (8) on one side, and prepare an N buried electrode (12) at the bottom of the buried metal pillar filling structure (62) of the buried metal full trench isolation structure (6) on the same side. Then perform multilayer metal interconnection and expose the PADs that need to be connected. S11, a passivation layer is deposited for protection, and then the upper wafer and the lower CMOS circuit wafer are bonded by three-dimensional integration technology; wherein, the lower CMOS circuit wafer includes a first bias circuit, a second bias circuit and a third bias circuit, as well as quenching and gating units connected to the first bias circuit, the second bias circuit and the third bias circuit. S12, flip the bonded stacked wafer structure and perform substrate thinning from the back side of the P-type silicon substrate; S13, an N-type buried electrode plate (121) is formed on the back side of the thinned P-type silicon substrate, so that it makes electrical contact with the buried metal pillar filling structure (62) in the exposed buried metal full trench isolation structure (6), thereby conducting to the N-type buried layer (4). S14, an antireflection layer (5) is prepared on the entire back side, and the surface away from the N-type buried layer (4) is the light incident surface; S15 employs a packaging scheme suitable for back-illuminated devices for dicing, packaging, and wire bonding to complete the fabrication of an extremely weak light full-color single-photon detector.

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