Time-to-digital conversion device, integrated circuit die, and count value generation method

Abstract

The embodiment of the invention discloses a time-to-digital conversion device, an integrated circuit die and a count value generation method. A time-to-digital conversion device embodiment includes a first oscillator configured to output a first clock signal in response to a first event and a second oscillator configured to output a second clock signal in response to a second event. The time-to-digital conversion device embodiment also includes a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, the clock counter is configured to generate a count value based on the first clock signal in response to a detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. The count value represents a time difference between the first event and the second event.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to time-to-digital conversion devices, integrated circuit dies, and methods of generating a count value. BACKGROUND

[0002] Time-to-digital conversion devices, such as time-to-digital converters (TDCs), are configured to convert time information into a digital value. In some applications, time-to-digital conversion devices, in combination with a voltage time converter (VTC), can be used to sense a waveform on an integrated circuit (IC) die to monitor power integrity (PI) characteristics of the IC die. In some applications, time-to-digital conversion devices can be used to measure phase noise of a phase-locked loop (PLL). In some applications, time-to-digital conversion devices can be used to measure time-of-flight (ToF) of a wireless signal, an acoustic signal, and / or an optical signal.

[0003] In some waveform measurement applications with good accuracy and flexibility, a time-to-digital conversion device with sub-100 femtosecond (fs) resolution and large dynamic range can be used. In some applications, an area budget for implementing the time-to-digital conversion device can limit the resolution and / or the dynamic range of the time-to-digital conversion device. SUMMARY

[0004] According to an aspect of embodiments of the present application, there is provided a time-to-digital conversion device, comprising: a first oscillator configured to output a first clock signal in response to a first event, the first clock signal having a first clock period; a second oscillator configured to output a second clock signal in response to a second event, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal; and a clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal, the count value indicating a time difference between the first event and the second event.

[0005] According to another aspect of embodiments of the present application, a method of generating a count value indicative of a time difference between a first event and a second event is provided, including: outputting, by a first oscillator, a first clock signal in response to the first event, the first clock signal having a first clock period; outputting, by a second oscillator, a second clock signal in response to the second event, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; generating, by a phase detector, a detection signal based on a phase relationship between the first clock signal and the second clock signal; and generating, by a clock counter, the count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal.

[0006] According to yet another aspect of embodiments of the present application, an integrated circuit die is provided, including: one or more digital circuit blocks configured to output a first reference signal and a second reference signal; and a time-to-digital conversion device configured to output a count value indicative of a time difference between a first event and a second event, the time-to-digital conversion device including: a first oscillator configured to output a first clock signal in response to the first event based on the first reference signal, the first clock signal having a first clock period; a second oscillator configured to output a second clock signal in response to the second event based on the second reference signal, the second clock having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal; and a clock counter configured to generate the count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale, and are merely intended as illustrative. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] FIGS. 1A-1B is a block diagram of an application example based on a time-to-digital conversion device according to some embodiments.

[0009] FIG. 2 is a block diagram of a time-to-digital conversion device example according to some embodiments.

[0010] FIG. 3 is a process flow diagram of a process flow example performed by a time-to-digital conversion device according to some embodiments.

[0011] FIG. 4Ais a circuit diagram of an oscillator example according to some embodiments.

[0012] FIG. 4B is a circuit diagram of a phase detector example according to some embodiments. FIG. 4A is a circuit diagram of a NAND gate in a delay circuit in

[0013] FIG. 5 is a circuit diagram of a clock gating circuit example according to some embodiments.

[0014] FIG. 6A is a circuit diagram of a clock gating circuit example according to some embodiments.

[0015] FIGS. 6B-6C is a circuit diagram of a counter example according to some embodiments. FIG. 6A is a circuit diagram of a clock gating circuit example according to some embodiments.

[0016] FIG. 7 is a block diagram of a time-to-digital conversion device example according to some embodiments.

[0017] FIGS. 8A-8D is a block diagram of a time-to-digital conversion device example according to some embodiments. FIGS. 2-6A and FIG. 7 is a graph of signal waveforms and / or digital values for a time-to-digital conversion session example of a time-to-digital conversion device example.

[0018] FIGS. 9A-9B is a graph of a phase interpolator-based delay circuit example according to some embodiments.

[0019] FIGS. 10A-10C is a graph of a tunable load resistor-based delay circuit example according to some embodiments.

[0020] FIG. 11 is a circuit diagram of an oscillator configured to correspond to different clock periods according to some embodiments.

[0021] FIG. 12 is a flowchart of a method of generating a count value indicative of a time difference between a first event and a second event according to some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides a number of different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0023] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, the term "made" can mean "comprising" or "consisting of." In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), unless otherwise indicated, and does not mean one element from A, one element from B, and one element from C.

[0024] Recent developments in computer technology have led to an increase in demand for computing power. For example, artificial intelligence (AI) is now more powerful than ever, with advanced large language models having a large number of parameters. Training large language models and / or inference operations based on large language models require a large amount of computing power, which increases the demand for high-performance computing (HPC) devices. Processing circuits and components in HPC devices, such as central processing units (CPUs), graphics processing units (GPUs), and / or tensor processing units (TPUs), face challenges in power integrity due to large currents, which can be addressed by monitoring the power impedance of the processing circuits and components.

[0025] In some applications, monitoring the power impedance includes monitoring an in-chip waveform or a signal delay relative to a reference signal. For example, FIG. 1A is a block diagram 100A of a first application example for determining clock skew within digital logic 110 in an integrated circuit die, in accordance with some embodiments. In FIG. 1AIn some applications, time-to-digital converter devices based on a Vernier delay line configuration are capable of achieving fine resolution (e.g., sub-100 femtoseconds (fs)), but at the cost of increased delay stages, area, complexity, and thus cost.

[0026] In addition, FIG. 1B is a block diagram 100B of a second application example for sensing a voltage level of a waveform in an integrated circuit die according to some embodiments. In FIG. 1B In some applications, time-to-digital converter devices based on a Vernier delay line configuration are capable of achieving fine resolution (e.g., sub-100 femtoseconds (fs)), but at the cost of increased delay stages, area, complexity, and thus cost.

[0027] In some applications, time-to-digital converter devices based on a Vernier delay line configuration are capable of achieving fine resolution (e.g., sub-100 femtoseconds (fs)), but at the cost of increased delay stages, area, complexity, and thus cost.

[0028] The present disclosure describes, in one or more embodiments, a time-to-digital converter device based on a clock period difference between two oscillators. In some embodiments, the two oscillators are started in response to two events, and the later started clock signal chases the earlier started clock in increments of the clock period difference per clock period. In some embodiments, the configuration according to one or more embodiments of the present application still has fine resolution (e.g., sub-80 femtoseconds resolution) and a measurable range of 0 to 245 picoseconds in the time domain without increasing the number of delay stages, which in turn improves layout efficiency, reduces circuit complexity, and reduces manufacturing cost in an integrated circuit die.

[0029] FIG. 2 is a block diagram of a time-to-digital converter device 200 according to some embodiments. FIG. 2 The time-to-digital converter device 200 in The time-to-digital converter device 200 in some embodiments is shown as a non-limiting example. In some embodiments, some components of the time-to-digital converter device 200 areFIG. 2 The Chinese characters are simplified or omitted.

[0030] exist FIG. 2 In this embodiment, the time-to-digital converter 200 includes a first oscillator 210, a second oscillator 220, a phase detector 230, and a clock counter 240. The first oscillator 210 is configured to receive a first reference signal START1 and a first deceleration control signal SLOW1. The first oscillator 210 is configured to output a first clock signal CKA_M in response to a first event. In some embodiments, the first oscillator 210 is further configured to output a first buffered clock signal CKA_OUT, which is obtained based on the first clock signal CKA_M through a buffer stage of the first oscillator 210. In some embodiments, the first clock signal CKA_M and the first buffered clock signal CKA_OUT have a first clock period T1.

[0031] Furthermore, the second oscillator 220 is configured to receive a second reference signal START2 and a second deceleration control signal SLOW2. The second oscillator 220 is configured to output a second clock signal CKB_M in response to a second event. In some embodiments, the second clock signal CKB_M has a second clock period T2. In some embodiments, the first event occurs before the second event. In some embodiments, the first clock period T1 is greater than the second clock period T2. In some embodiments, the second clock period T2 is at least 100 times the period difference ΔT between the first clock period T1 and the second clock period T2. In some embodiments, the second clock period T2 ranges from 2 nanoseconds (ns) to 6 ns. In some embodiments, the period difference ΔT ranges from 60 femtoseconds (fs) to 100 fs.

[0032] In some embodiments, as a non-limiting example, the first event corresponds to the first reference signal START1 changing from a first logic state (e.g., logic low or low in this disclosure) to a second logic state (e.g., logic high or high in this disclosure). In some embodiments, the second event corresponds to the second reference signal START2 changing from a first logic state (e.g., low) to a second logic state (e.g., high). In some embodiments, the first oscillator 210 is configured to be deactivated based on the first reference signal START1 being in the first logic state and activated based on the first reference signal START1 being in the second logic state. In some embodiments, the second oscillator 220 is configured to be deactivated based on the second reference signal START2 being in the first logic state and activated based on the second reference signal START2 being in the second logic state.

[0033] In some embodiments, the first clock period Tl can be adjusted based on the first slow down control signal SLOWl, and the second clock period T2 can be adjusted based on the second slow down control signal SLOW2. In some embodiments, the first oscillator 210 and the second oscillator 220 are based on the same hardware configuration. In some embodiments, the first oscillator 210 is a first ring oscillator that includes one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two successive inverting stages of the first oscillator 210, and is configured to set a first configurable delay of the first oscillator 210. In some embodiments, the second oscillator 220 is a second ring oscillator that includes one or more of a second load capacitance, a second load resistance, or a second phase interpolator between two successive inverting stages of the second oscillator 200, and is configured to set a second configurable delay of the second oscillator 220. In some embodiments, the first clock period Tl can be determined based on the first configurable delay of the first oscillator 210, and the second clock period T2 can be determined based on the second configurable delay of the second oscillator 220.

[0034] During operation of the time-to-digital conversion device 200, the first clock period Tl and the second clock period T2 are set based on the first slow down control signal SLOWl and the second slow down control signal SLOW2. For example, during operation, the first slow down control signal SLOWl is set to the second logic state (e.g., high) indicating that the first clock period Tl corresponds to a slower clock setting of the first oscillator 210 (e.g., setting the first configurable delay to a larger value), while the second slow down control signal SLOW2 is set to the first logic state (e.g., low) indicating that the second clock period T2 corresponds to a faster clock setting of the second oscillator 220 (e.g., setting the second configurable delay to a smaller value).

[0035] In some alternative embodiments, the first oscillator 210 and the second oscillator 220 are based on different hardware configurations, respectively corresponding to outputting clock signals having the first clock period Tl and the second clock period T2. In some embodiments, based on the hardware configurations of the first oscillator 210 and the second oscillator 220, no adjustable delay is available, and thus the first slow down control signal SLOWl and / or the second slow down control signal SLOW2 are omitted.

[0036] Phase detector 230 is configured to generate a detection signal HITB based on the phase relationship between a first clock signal CKA_M and a second clock signal CKB_M. In some embodiments, as a non-limiting example, the detection signal HITB has a first logic state (e.g., low) indicating that the phase of the first clock signal CKA_M lags behind the phase of the second clock signal CKB_M, and a second logic state (e.g., high) indicating that the phase of the second clock data CKB_M lags behind the phase of the first clock signal CKA_M.

[0037] Clock counter 240 is configured to generate a count value TDC_OUT based on the first clock signal CKA_M in response to a detection signal HITB indicating that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M. In some embodiments, the count value TDC_OUT indicates the time difference between the first event and the second event. In some embodiments, clock counter 240 is configured to receive and count the clock cycles of the first clock signal CKA_M. In some embodiments, clock counter 240 is configured to receive and count the clock cycles of the first buffered clock signal CKA_OUT. In other embodiments, clock counter 240 is configured to generate a count value TDC_OUT based on the second clock signal CKB_M (instead of the first clock signal CKA_M or the first buffered clock signal CKA_OUT) in response to a detection signal HITB indicating that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M.

[0038] exist FIG. 2In this example, clock counter 240 includes clock gating circuit 250 and counter 260. In some embodiments, clock gating circuit 250 is configured to generate count clock signal CKC based on first clock signal CKA M (or first buffered clock signal CKA OUT derived from first clock signal CKA M) and detection signal HITB. In some embodiments, clock gating circuit 250 is configured to generate count clock signal CKC having the same frequency and period as first clock signal CKA M in response to detection signal HITB being in a second logic state (e.g., high), which indicates that the phase of second clock signal CKB M lags behind the phase of first clock signal CKA M. In some embodiments, clock gating circuit 250 is configured to set count clock signal CKC to a logic state (e.g., a first logic state or low) in response to detection signal HITB being in a first logic state (e.g., low). In this example, clock gating circuit 250 includes a clock terminal (depicted with a triangle marker) configured to receive first clock signal CKA M or first buffered clock signal CKA OUT, an enable terminal (labeled with “EN”) configured to receive detection signal HITB, and an output terminal configured to output count clock signal CKC.

[0039] In some embodiments, counter 260 is an N-bit counter, and TDC OUT is a count value of an N-bit unsigned integer. In some embodiments, N ranges from 6 to 12, or 8 to 10. In this example, counter 260 includes a clock terminal (depicted with a triangle marker) configured to receive count clock signal CKC and an output terminal configured to output count value TDC OUT.

[0040] In some embodiments, an integrated circuit die includes one or more digital circuit blocks configured to output various reference signals (e.g., first reference signal START1 and second reference signal START2). In some embodiments, the integrated circuit die also includes time-to-digital converter device 200 configured to output a count value (e.g., count value TDC OUT) indicative of a time difference between a first event based on the first reference signal and a second event based on the second reference signal.

[0041] FIG. 3 is a process flow diagram of a process flow 300 performed by a time-to-digital converter device according to some embodiments. In some embodiments, process flow 300 is illustrated based on various operations performed by time-to-digital converter device 200 in FIG. 2 In some embodiments, process flow 300 is illustrated based on various operations performed by time-to-digital converter device 200 in FIG. 3 In this example, process flow 300 includes stages 310-355.

[0042] At stage 310, various components of the time-to-digital conversion device are reset. For example, the phase detector 230, the clock gating circuit 250, and the counter 260 are reset to clear any data or logic states from a previous time-to-digital conversion session. At stage 310, the detection signal HITB is set to disable the clock gating circuit 250, and the count clock signal CKC is set to cause no action at the counter 260.

[0043] At stage 315, a first reference signal (e.g., the first reference signal START1) changes from a first logic state (e.g., low) to a second logic state (e.g., high), and the change in logic state indicates the occurrence of a first event. At stage 320, a first oscillator (e.g., the first oscillator 210) outputs a first clock signal (e.g., the first clock signal CKA_M) as an oscillating signal in response to the first event. In some embodiments, the first clock signal CKA_M has a first clock period T1.

[0044] At stage 325, based on the presence of the first clock signal CKA_M (as the oscillating signal) and the absence of the second clock signal CKB_M (as the ringing signal), the phase detector 230 begins to output the detection signal HITB in the first logic state (e.g., low) indicating that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M, which in turn enables the clock gating circuit 250, which in turn enables the counter 260.

[0045] At stage 330, a second reference signal (e.g., the second reference signal START2) changes from a first logic state (e.g., low) to a second logic state (e.g., high), and the change in logic state indicates the occurrence of a second event. In some embodiments, the change in logic state of the second reference signal START2 from low to high is delayed by a time difference Tsense compared to the change in logic state of the first reference signal START1 from low to high. At stage 335, a second oscillator (e.g., the second oscillator 220) outputs a second clock signal (e.g., the second clock signal CKB_M) as an oscillating signal in response to the second event. In some embodiments, the second clock signal CKB_M has a second clock period T2 equal to (T1 - AT). At stage 335, the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M, and thus the clock gating circuit 250 and the counter 260 remain enabled.

[0046] At stage 340, after the Tsense / AT period, the phase of the second clock signal CKB M catches up to and leads the phase of the first clock signal CKA M. At stage 345, in response to the updated phase relationship of the first clock signal CKA M and the second clock signal CKB M, the phase detector 230 outputs the detection signal HITB in a second logic state (e.g., high) indicating that the phase of the first clock signal CKA M lags behind the phase of the second clock signal CKB M.

[0047] At stage 350, the detection signal HITB in the second logic state (e.g., high) in turn disables the clock gating circuit 250. At stage 350, the clock gating circuit 250 sets the count clock signal CKC to a fixed logic state to render the counter 260 inoperative. At stage 355, the counter 260 stops. The counter output (e.g., the count value TDC OUT) is read as the conversion result. In some embodiments, the count value TDC OUT represents a ratio between the time difference Tsense and the period difference AT. In some embodiments, the time difference Tsense is determined based on TDC OUT x AT. In some embodiments, AT also represents a time domain resolution of the time-to-digital conversion device, and the range of the count value of the counter 260 corresponds to a measurable range of the time-to-digital conversion device.

[0048] FIG. 4A is a circuit diagram of an oscillator 400 that is a ring oscillator according to some embodiments. In some embodiments, the hardware configuration of the oscillator 400 is a non-limiting example that can be used to implement the first oscillator 210 and / or the second oscillator 220 in FIG. 2 .

[0049] The oscillator 400 includes a first NAND (NAND) gate 412 as an input stage, a first set of inverters 414, a second set of inverters 415, a third set of inverters 416, a second NAND gate 417, and an inverter 418. The oscillator 400 also includes a buffer circuit 420 after the third set of inverters 416, and a delay circuit 430 between the second set of inverters 415 and the third set of inverters 416. In some embodiments, the buffer circuit 420 includes one or more inverters. In this example, the delay circuit 430 includes a drive stage 432 (including one or more inverters, e.g., one inverter in this example) and a third NAND gate 434. In some embodiments, the delay circuit 430 is configured to introduce a delay of AT / 2 to the phase of the second clock signal CKB M. FIG. 4AIn some embodiments, the first NAND gate 412, the first set of inverters 414, the second set of inverters 415, the drive stage 432 of the delay circuit 430, the third set of inverters 416, the second NAND gate 417, and the inverter 418 are sequentially electrically coupled to form a ring of K inverting stages, K being an odd positive integer. In some embodiments, the signal at the output terminal of the first set of inverters 414 is output by the oscillator 400 as the clock signal CK M.

[0050] In some embodiments, the first NAND gate 412 includes a first input terminal configured to receive the feedback clock signal CK F from the inverter 418, and a second input signal configured to receive the reference signal START. In some embodiments, in response to the reference signal START being in a first logic state (e.g., low), the first NAND gate 412 outputs a second logic state (e.g., high), effectively disabling the oscillator 400. In some embodiments, in response to the reference signal START being in a second logic state (e.g., high), the first NAND gate 412 outputs an inversion of the feedback clock signal CK F at its output.

[0051] In some embodiments, the second NAND gate 417 includes a first input terminal electrically coupled to the output terminal of the third set of inverters 416, and a second input signal configured to receive the enable signal EN. In some embodiments, in response to the enable signal EN being in a first logic state (e.g., low), the second NAND gate 417 outputs a second logic state (e.g., high), effectively disabling the oscillator 400. In some embodiments, in response to the enable signal EN being in a second logic state (e.g., high), the second NAND gate 417 outputs an inverted signal of the signal from the output terminal of the third set of inverters 416 at its output. In some embodiments, the second NAND gate 417 is replaced with an inverter, and the enable signal EN is omitted.

[0052] In some embodiments, the buffer circuit 420 is configured to output a buffered clock signal CK OUT having the same frequency and period as the clock signal CK M. In some embodiments, the buffer circuit 420 provides greater drive capability for the buffered clock signal CK OUT than the clock signal CK M, while minimizing interference with the K inverting stage ring of the oscillator 400.

[0053] In some embodiments, the delay circuit 430 is configured to introduce an adjustable delay to the K inverting stage ring of the oscillator 400. In this example, the third NAND gate 434 is shown as a non-limiting example. In some embodiments, a NOR (or NOT) gate is used in place of the third NAND gate 434.

[0054] In this example, the third NAND gate 434 includes a first input terminal (labeled the "LOAD" terminal) coupled to the output terminal of the drive stage 432, a second input terminal configured to receive a slow-down control signal SLOW, and an output terminal that is not electrically coupled to other circuitry. In some embodiments, in response to the slow-down control signal SLOW being in a first logic state (e.g., low), the first input terminal presents a first equivalent load capacitance. In some embodiments, in response to the slow-down control signal SLOW being in a second logic state (e.g., high), the first input terminal presents a second equivalent load capacitance that is greater than the first equivalent load capacitance.

[0055] In a first oscillator 210 based on one example of the oscillator 400, FIG. 4A the reference signal START and the corresponding terminal in FIG. 2 the first reference signal START1 and the corresponding terminal; FIG. 4A the clock signal CK_M and the corresponding terminal in FIG. 2 the first clock signal CKA_M and the corresponding terminal, FIG. 4A the buffered clock signal CK_OUT and the corresponding terminal in FIG. 2 the first buffered clock signal CKA_OUT and the corresponding terminal, FIG. 4A the slow-down control signal SLOW and the corresponding terminal in FIG. 2 the first slow-down control signal SLOW1 and the corresponding terminal.

[0056] FIG. 4B is a circuit diagram of a NAND gate 434 in the delay circuit 430 according to some embodiments as a non-limiting example FIG. 4A In this example, the third NAND gate 434 includes a first input terminal (labeled the "LOAD" terminal) coupled to the output terminal of the drive stage 432, a second input terminal configured to receive a slow-down control signal SLOW, and an output terminal that is not electrically coupled to other circuitry. In some embodiments, in response to the slow-down control signal SLOW being in a first logic state (e.g., low), the first input terminal presents a first equivalent load capacitance. In some embodiments, in response to the slow-down control signal SLOW being in a second logic state (e.g., high), the first input terminal presents a second equivalent load capacitance that is greater than the first equivalent load capacitance. FIG. 4B In this example, the third NAND gate 434 includes a first input terminal (labeled the "LOAD" terminal) coupled to the output terminal of the drive stage 432, a second input terminal configured to receive a slow-down control signal SLOW, and an output terminal that is not electrically coupled to other circuitry. In some embodiments, in response to the slow-down control signal SLOW being in a first logic state (e.g., low), the first input terminal presents a first equivalent load capacitance. In some embodiments, in response to the slow-down control signal SLOW being in a second logic state (e.g., high), the first input terminal presents a second equivalent load capacitance that is greater than the first equivalent load capacitance. FIG. 4A In this example, the third NAND gate 434 includes a first input terminal (labeled the "LOAD" terminal) coupled to the output terminal of the drive stage 432, a second input terminal configured to receive a slow-down control signal SLOW, and an output terminal that is not electrically coupled to other circuitry. In some embodiments, in response to the slow-down control signal SLOW being in a first logic state (e.g., low), the first input terminal presents a first equivalent load capacitance. In some embodiments, in response to the slow-down control signal SLOW being in a second logic state (e.g., high), the first input terminal presents a second equivalent load capacitance that is greater than the first equivalent load capacitance.

[0057] The NAND gate 434 includes a first p-type transistor 452, a second p-type transistor 454, a first n-type transistor 456, and a second n-type transistor 458. A first drain / source terminal of the first p-type transistor 452 and a drain / source terminal of the second p-type transistor 454 are electrically coupled to a first power supply node configured to carry a first power supply voltage (e.g., VDD). A second drain / source terminal of the first p-type transistor 452, a second source / drain terminal of the second p-type transistor 454, and a first drain / source terminal of the first n-type transistor 456 are electrically coupled to an output terminal 446 of the NAND gate 434. A second drain / source terminal of the first n-type transistor 456 is electrically coupled to a first drain / drain terminal of the second n-type transistor 458. A second drain / source terminal of the second n-type transistor 458 is electrically coupled to a second power supply node configured to carry a second power supply voltage (e.g., VSS or ground). A gate terminal of the first p-type transistor 452 and a gate terminal of the first n-type transistor 456 are electrically coupled to a first input terminal 442 of the NAND gate 434. A gate terminal of the second p-type transistor 454 and a gate terminal of the second n-type transistor 458 are electrically coupled to a second input terminal 444 of the NAND gate 434.

[0058] In this example, in response to the slowdown control signal SLOW being in the first logic state (e.g., low), the second p-type transistor 454 is on, the second n-type transistor 458 is off, and the load capacitance observable at the first input terminal 442 is primarily based on the parasitic capacitance (represented by the capacitor having a capacitance Cp) between the first input terminal 442 and the output terminal 446. Further, in response to the slowdown control signal SLOW being in the second logic state (e.g., high), the second p-type transistor 454 is off, the second n-type transistor 458 is on, the load capacitance observable at the first input terminal 442 is based on the Miller effect amplification of the parasitic capacitance (e.g., the capacitance Cp), which is effectively (1+M) x Cp, where M is the gain from the output terminal 446 to the first input terminal 422.

[0059] In this example, the load difference between the slowdown control signal SLOW being in the first logic state and the second logic state is M x Cp. In some embodiments, an oscillator based on the oscillator 400 having the load capacitance Cp and another oscillator based on the oscillator 400 having the load capacitance (1+M) x Cp will have different clock periods, and the difference in clock periods can be determined from the load difference M x Cp.

[0060] FIG. 5 is a circuit diagram of a phase detector 500 according to some embodiments. In some embodiments, the phase detector 500 is a non-limiting example of the phase detector 230 in FIG. 2

[0061] ​In FIG. 5 In some embodiments, the phase detector 500 includes a D-type flip-flop 510, a first buffer stage including series-coupled inverters 522 and 524, a second buffer stage including series-coupled inverters 532 and 534, and an output stage including an inverter 542. In some embodiments, the inverters 522 and 524 are configured to buffer a first clock signal (e.g., the first clock signal CKA M) from a first oscillator (e.g., the first oscillator 210), and the inverters 532 and 534 are configured to buffer a second clock signal (e.g., the second clock signal CKB M) from a second oscillator (e.g., the second oscillator 220).

[0062] In this example, the D-type flip-flop 510 includes a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the D-type flip-flop 510 is configured to receive a first signal corresponding to the first clock signal CKA M from the first buffer stage. In some embodiments, the CLK terminal of the D-type flip-flop 510 is configured to receive a second signal that is inverted based on a signal from the second buffer stage and corresponds to the second clock signal CKB M. In some embodiments, the Q terminal of the D-type flip-flop 510 is configured to output a third signal corresponding to the detection signal HITB. In this example, the inverter 542 receives the third signal from the Q terminal of the D-type flip-flop 510 and outputs the detection signal HITB. In some embodiments, the CD terminal of the D-type flip-flop 510 is configured to receive a reset signal RST, has no effect on the operation of the D-type flip-flop 510 in response to the reset signal RST being in a first logic state (e.g., low), and causes the D-type flip-flop 510 to reset the output at the Q terminal of the D-type flip-flop 510 in response to the reset signal RST being in a second logic state (e.g., high).

[0063] FIG. 6A is a circuit diagram of a clock gating circuit example 600 according to some embodiments. In some embodiments, the clock gating circuit 600 is a non-limiting example of the clock gating circuit 250 in FIG. 2

[0064] In FIG. 6A ​In this example, the clock gating circuit 600 includes a first D-type flip-flop 610, a second D-type flip-flop 620, a first buffer stage including series-coupled inverters 632 and 634, a second buffer stage including inverter 642, and an output stage including NAND gate 644. In this example, each of the first D-type flip-flop 610 and the second D-type flip-flop 620 includes a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the first D-type flip-flop 610 is configured to receive a supply voltage (e.g., VDD) representing a second logic state (e.g., high). In some embodiments, the CLK terminal of the first D-type flip-flop 610 is configured to receive a signal that is inverted based on the detection signal H ITB. In some embodiments, the CD terminal of the first D-type flip-flop 610 is configured to receive a reset signal RST that has no effect on the operation of the first D-type flip-flop 610 in response to the reset signal RST being in a first logic state (e.g., low) and causes the first D-type flip-flop 610 to reset the output at the Q terminal of the first D-type flip-flop 610 in response to the reset signal RST being in a second logic state (e.g., high). In some embodiments, the inverters 632 and 634 are configured to buffer the output signal from the Q terminal of the first D-type flip-flop 610 and provide the buffered output signal (labeled “STOP”) to the second D-type flip-flop 620.

[0065] In some embodiments, the D terminal of the second D-type flip-flop 620 is configured to receive the buffered output signal STOP from the inverter 634. In some embodiments, the CLK terminal of the second D-type flip-flop 620 is configured to receive the first buffered clock signal CKA OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the CD terminal of the second D-type flip-flop 620 is configured to receive the reset signal RST that has no effect on the operation of the second D-type flip-flop 620 in response to the reset signal RST being in a first logic state (e.g., low) and causes the second D-type flip-flop 620 to reset the output at the Q terminal of the second D-type flip-flop 620 in response to the reset signal RST being in a second logic state (e.g., high). In some embodiments, the Q terminal of the second D-type flip-flop 620 is configured to output a signal STOP R based on the signal STOP and the first buffered clock signal CKA OUT.

[0066] In this example, the inverter 642 receives the signal STOP R and outputs an inverted signal STOP B. In some embodiments, the NAND gate 644 includes a first input terminal configured to receive the first buffered clock signal CKA OUT and a second input terminal configured to receive the signal STOP B. In some embodiments, in response to the signal STOP B being in a first logic state (e.g., low), the NAND gate 644 outputs a second logic state (e.g., high) at its output terminal as the counter clock signal CKC (e.g., a non-oscillating signal). In some embodiments, in response to the signal STOP B being in a second logic state (e.g., high), the NAND gate 644 outputs an inversion of the first buffered clock signal CKA OUT at its output terminal as the counter clock signal CKC (e.g., an oscillating signal).

[0067] In some other embodiments, the first clock signal CKA M, the second clock signal CKB M, or a second buffered clock signal based on the second clock signal CKB M can be used in place of the first buffered clock signal CKA OUT.

[0068] FIG. 6B is a circuit diagram of a variant example 650A of the clock gating circuit 600 based on FIG. 6A In some embodiments, the combination of the second D-type flip-flop 620, the inverter 642, and the NAND gate 644 can be replaced by the variant example 650A.

[0069] In FIG. 6B In this example, the D-type flip-flop 620A includes a D terminal, a CLK terminal, and a Q terminal. In some embodiments, the D terminal of the D-type flip-flop 620A is configured to receive the signal STOP. In some embodiments, the clock terminal of the D-type flip-flop 620A is configured to receive the first buffered clock signal CKA OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the Q terminal of the D-type flip-flop 620A is configured to output the signal STOP R based on the signal STOP and the first buffered clock signal CKA OUT.

[0070] In FIG. 6B In this example, the first input terminal of the AND gate 646 is configured to receive the signal STOP R, and the second input terminal of the AND gate 644 is configured to receive the first buffered clock signal CKA OUT. In this example, the output terminal of the AND gate 646 is configured to output the counter clock signal CKC.

[0071] FIG. 6C is a circuit diagram of a variant example 650A of the clock gating circuit 600 based on FIG. 6Acircuit diagram of a variant example 650B of the clock gating circuit 600 in FIG. 6. In some embodiments, the combination of the second D-type flip-flop 620, the inverter 642, and the NAND gate 644 can be replaced by the variant example 650A.

[0072] In FIG. 6C In this example, the D-type latch 620B includes a D terminal, an EN terminal, and a Q terminal. In some embodiments, the D terminal of the D-type latch 620B is configured to receive the signal STOP. In some embodiments, the EN terminal of the D-type latch 620B is configured to receive the first buffered clock signal CKA OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the Q terminal of the D-type latch 620B is configured to output a signal STOP R based on the signal STOP and the first buffered clock signal CKA OUT.

[0073] In FIG. 6C In this example, the first input terminal of the AND gate 646 is configured to receive the signal STOP R, and the second input terminal of the AND gate 644 is set to receive the first buffered clock signal CKA OUT. In this example, the output terminal of the AND gate 646 is configured to output the counter clock signal CKC.

[0074] FIG. 7 is a block diagram of a counter example 260 according to some embodiments. In some embodiments, the counter example 260 is a non-limiting example of the counter 200 in FIG. 2. FIG. 2 is a block diagram of a counter example 260 according to some embodiments. In some embodiments, the counter example 260 is a non-limiting example of the counter 200 in FIG. 2.

[0075] In FIG. 7 In this example, the D-type latch 620B includes a D terminal, an EN terminal, and a Q terminal. In some embodiments, the D terminal of the D-type latch 620B is configured to receive the signal STOP. In some embodiments, the EN terminal of the D-type latch 620B is configured to receive the first buffered clock signal CKA OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the Q terminal of the D-type latch 620B is configured to output a signal STOP R based on the signal STOP and the first buffered clock signal CKA OUT.

[0076] In this example, the N-bit output port Q of the N-bit clock buffer 720 is configured to carry a count value TDC_OUT, and the first N-bit input port Ain of the N-bit adder 710 is configured to receive the count value TDC_OUT from the N-bit output port Q of the N-bit clock buffer 720. In this example, the second N-bit input port Bin is configured to receive a binary value of 0001b, and the carry-in terminal Cin is coupled to a supply voltage (e.g., VSS or ground) representing a binary value of Ob. In some embodiments, the N-bit output port S is configured to output a binary value based on a sum of the binary values at the first N-bit input port Ain, the second N-bit input port Bin, and the carry-in terminal Cin. The N-bit input port D of the N-bit clock buffer 720 receives the binary value from the N-bit output port S of the N-bit adder 710.

[0077] In operation, in response to the counter clock signal CKC transitioning from a first logic state (e.g., low) to a second logic state (e.g., high), the N-bit clock buffer 720 updates the count value TDC_OUT at the N-bit output port Q based on the output value of the N-bit adder 710. In response to the updated count value TDC_OUT, the N-bit adder 710 updates the digital value at the N-bit output port S by adding the updated count value TDC_OUT (value at the first N-bit input port Ain) and 1 (value at the second N-bit input port Bin). The updated digital value at the N-bit output port S will be used to update the count value TDC_OUT at the N-bit output port Q the next time the counter clock signal CKC transitions from the first logic state (e.g., low) to the second logic state (e.g., high).

[0078] FIGS. 8A-8D is a time-to-digital conversion session example of a time-to-digital conversion device based on the examples in FIGS. 2-6A and FIG. 7 .

[0079] FIG. 8A includes graphs 801-808. In graphs 801-807, time is represented by the horizontal axis, and voltage levels of various signals are represented by the vertical axis. In graph 808, time is represented by the horizontal axis, and digital values are represented by the vertical axis.

[0080] Graph 801 includes a waveform 812 corresponding to the waveform of the reset signal RST in FIG. 5 , FIG. 6A and FIG. 7 . Graph 802 includes a waveform 822 corresponding to the waveform of the first reference signal START1 in FIG. 2 , and a waveform 824 corresponding to the waveform of the second reference signal START2 in FIG. 2 . Graph 803 includes a waveform 832 corresponding to the waveform of the counter clock signal CKC inFIG. 2 and FIG. 5 corresponding to the waveform of the first clock signal CKA M in FIG. 2 and FIG. 5 corresponding to the waveform of the second clock signal CKB M in FIG. 2 , FIG. 6A and FIG. 7 corresponding to the waveform of the count clock signal CKC in FIG. 2 , FIG. 5 and FIG. 6A corresponding to the waveform of the detection signal HITB in FIG. 6A corresponding to the waveform of the buffer output signal STOP in FIG. 2 and FIG. 7 corresponding to the waveform of the count value TDC OUT in

[0081] In FIG. 8A , the first clock signal CKA M (waveform 832), the second clock signal CKB M (waveform 834), and the count clock signal CKC (waveform 836) oscillate between a high voltage level (e.g., corresponding to a high logic state) and a low voltage level (e.g., corresponding to a low logic state) in response to the first reference signal START1 (waveform 822) and the second reference signal START2 (waveform 824) transitioning from a low voltage level to a high voltage level. In FIG. 8A , the count value TDC OUT (waveform 850) increases when the phase of the second reference signal START2 lags behind the phase of the first reference signal START1. In FIG. 8A , after the detection signal HITB (waveform 842) and the buffer output signal STOP (waveform 844) indicate that the phase of the first reference signal START1 lags behind the phase of the second reference signal START2, the count value TDC OUT (waveform 850) stops increasing, and the first clock signal CKA M (waveform 832), the second clock signal CKB M (waveform 834), and the count clock signal CKC (waveform 836) remain in a fixed logic state (e.g., represented by a low voltage level).

[0082] FIG. 8B the portion of the graphs 801-808 within portion A is further illustrated in FIG. 8C the portion of the graphs 801-808 within portion B is further illustrated in

[0083] FIG. 8B is a zoomed-in view of portion A in FIG. 8A FIG. 8B ​includes graphs 801A-808A corresponding to portions of graphs 801-808 in Part A. In FIG. 8B the same waveforms are assigned the same reference numbers as in FIG. 8A

[0084] In FIG. 8B , before time t0, the reset signal RST (waveform 812) is at a high voltage level (e.g., high) to reset various components of the time-to-digital conversion device (e.g., time-to-digital conversion device 200), which corresponds to stage 310 in FIG. 3 . At time t0, the reset signal RST (waveform 812) transitions from a high voltage level (e.g., high) to a low voltage level (e.g., low) to allow the time-to-digital conversion device to operate in response to various other signals.

[0085] At time t1, the first reference signal START1 (waveform 822) transitions from a low voltage level (e.g., low) to a high voltage level (e.g., high), which corresponds to stage 315 in FIG. 3 . In response to this transition and corresponding to stage 320 in FIG. 3 , the first oscillator (e.g., first oscillator 210) begins to output a first clock signal CKA M (waveform 832) as an oscillating signal that transitions between a low voltage level and a high voltage level after an inherent delay. In addition, a clock counter (e.g., clock counter 240) is started by the first clock signal CKA M, as shown by the count clock signal CKC (waveform 836), which corresponds to stage 325 in FIG. 3 .

[0086] At time t2, the second reference signal START2 (waveform 824) transitions from a low voltage level (e.g., low) to a high voltage level (e.g., high), which corresponds to stage 330 in FIG. 3 . The transition of the second reference signal START2 is delayed from the transition of the first reference signal START1 by a time difference Tsense (e.g., t2-t1 = Tsense). In response to the transition of the second reference signal START2 and corresponding to stage 335 in FIG. 3 , the second oscillator (e.g., second oscillator 220) begins to output a second clock signal CKB M (waveform 834) as an oscillating signal that transitions between a low voltage level and a high voltage level after an inherent delay.

[0087] In some embodiments, the first clock signal CKA M has a first clock period T1 and the second clock signal CKB M has a second clock period T2 that is smaller than the first clock T1 by a period difference AT. In FIG. 8B , the phase of the second clock signal CKB M starts to lag behind the phase of the first clock signal CKA M. In​FIG. 8B In this example, the phase difference between the second clock signal CKB M and the first clock signal CKA M decreases by the period difference AT every clock period of the first clock pulse CKA M or the second clock pulse CKB M. In this example, the counting clock signal CKC (waveform 836) and the first clock pulse CKA M have the same frequency. Thus, the clock counter counts the clock periods of the counting clock signal CKC to represent the number of clock periods that have elapsed for the first clock signal CKA M.

[0088] FIG. 8C is an enlarged view of part B in FIG. 8A FIG. 8C includes graphs 801B-808B corresponding to the parts of the graphs 801-808 in part B. In FIG. 8C FIG. 8A the same waveforms in

[0089] In FIG. 8C In FIG. 3 stage 340 inAt time t4, the phase detector (e.g., the phase detector 230) detects the change in the phase relationship between the first clock signal CKA M and the second clock signal CKB M and outputs the detection signal HITB (waveform 842) that transitions from a high voltage level (e.g., high) to a low voltage level (e.g., low), which corresponds to FIG. 3 stage 345 in

[0090] In response to the detection signal HITB (waveform 842) transitioning from the high voltage level to the low voltage level, and corresponding to FIG. 3 stage 350 inthe buffer output signal STOP (waveform 844) transitions from the low voltage level to the high voltage level, which in turn disables the clock gating circuit (e.g., the clock gating circuit 250) that outputs the counting clock signal CKC (waveform 836). Thereafter, the digital value of the count value TDC OUT (waveform 850) will be read as the conversion result, which corresponds to FIG. 3 stage 355 in

[0091] FIG. 8D is a plot of the relationship between the digital value of the count value TDC OUT (waveform 850) and the time difference (e.g., Tsense) between the first reference signal START1 and the second reference signal START2 according to some embodiments based on the example in FIG. 8A FIG. 8D ​In the diagram, the time difference Tsesne is represented by the horizontal axis, and the numerical values ​​are represented by the vertical axis.

[0092] In this non-limiting example, the time difference Tsesne and the digital value have a linear proportional relationship, as shown by curve 860. In this example, data point 862 represents a count value TDC_OUT with a digital value of 476 in response to a time difference Tsesne of 45.2531 picoseconds (ps). In this example, data point 864 represents a count value TDC_OUT with a digital value of 2876 in response to a time difference Tsesne of 235.4562 ps. Therefore, in this non-limiting example, the resolution of the measured time difference Tsesne is 79.4 fs (per digital value).

[0093] FIG. 9A This is a circuit diagram of an example 900 of a delay circuit based on a phase interpolator according to some embodiments. In some embodiments, the delay circuit 900 can be used as... FIG. 4A An alternative embodiment of the delay circuit 430 in the diagram. FIG. 9A In the delay circuit 900, inverters 912 and 914, capacitors 922 and 924, and a phase interpolator 932 are included. The input terminals of inverters 912 and 914 are adapted to be electrically coupled to... FIG. 4A The second set of inverters 415; and the output terminals of the phase interpolator 932 are adapted to be electrically coupled to FIG. 4A The third inverter group 416 in the middle.

[0094] exist FIG. 9A In this configuration, one terminal of capacitor 922 is coupled to a power node configured to carry a supply voltage (e.g., VSS or ground), and the other terminal is electrically coupled to the output terminal of inverter 912 and the input terminal of phase interpolator 932. Similarly, one terminal of capacitor 924 is coupled to a power node configured to carry a supply voltage (e.g., VSS or ground), and the other terminal is electrically coupled to the output terminal of inverter 912 and another input terminal of phase interpolator 932. In some embodiments, capacitor 922 has a capacitance C1. In some embodiments, capacitor 924 has a capacitance C2 in response to a deceleration control signal SLOW in a first logic state (e.g., low), and a capacitance C2+ΔC in response to a deceleration control signal SLOW in a second logic state (e.g., high). In some embodiments, capacitances C1 and C2 are set to be the same or within a 10% variation range. In some embodiments, capacitor 922 is omitted, and capacitance C1 is considered zero.

[0095] exist FIG. 9AIn this configuration, the signal at the input terminal of the phase interpolator 932 coupled to the output terminal of inverter 912 is labeled PI_IN0; and the signal at another input terminal of the phase interpolator 932 coupled to the output terminal of inverter 914 is labeled PI_IN1. Furthermore, the signal at the output terminal of the phase interpolator 932 is labeled PI_OUT. In some embodiments, the phase interpolator 932 is configured to determine a first time delay of the signal transition of signal PI_IN1 relative to the signal transition of signal PI_IN0, and output a signal PI_OUT, which has a signal transition and a second time delay relative to the signal transition of signal PI_IN0. In some embodiments, the second time delay is a fraction of the first time delay.

[0096] FIG. 9B According to some embodiments FIG. 9A The diagram shows various signals from the delay circuit 900. FIG. 9B In the image, time is represented by the horizontal axis. FIG. 9B In this context, the signal transition of signal PI_IN1 has a first delay TD1 relative to the signal transition of signal PI_IN0. FIG. 9B In this context, the signal transition of signal PI_OUT has a second delay TD2 relative to the signal transition of signal PI_IN0.

[0097] Therefore, the delay circuit 900 can be configured to further reduce the period difference ΔT between the two oscillators without further reducing the difference in the corresponding load capacitance values ​​of the two oscillators. In some embodiments, the period difference ΔT based on the second delay TD2 is in the range of tens of fs to obtain a time-to-digital converter with finer resolution than that based on the first delay TD1.

[0098] FIG. 10A This is a circuit diagram of an example 1000 of a delay circuit based on an adjustable load resistor, according to some embodiments. In some embodiments, the delay circuit 1000 can be used as... FIG. 4A Another alternative embodiment of the delay circuit 430 in the diagram. FIG. 10A In the delay circuit 1000, an inverter 1012, a capacitor 1014, and an adjustable resistor 1016 are included. The input terminals of the inverter 1012 are adapted for electrical coupling to... FIG. 4A The second set of inverters 415; and the output node 1018 of the delay circuit 1000 is adapted to be electrically coupled to FIG. 4A The third inverter group 416 in the middle.

[0099] exist FIG. 10AIn some embodiments, one terminal of the capacitor 1014 is coupled to a power supply node configured to carry a power supply voltage (e.g., VSS or ground), and the other terminal is electrically coupled to the output node 1018. Further, one terminal of the adjustable resistor 1016 is electrically coupled to the output terminal of the inverter 1012, and the other terminal is electrically coupled to the output node 1018. In some embodiments, the time delay between the input terminal of the inverter 1012 and the output node 1018 can be determined based on the resistance of the adjustable resistor 1016, where the greater the resistance value of the adjustable resistor 1016, the greater the delay imposed between the second group of inverters 415 and the third group of inverters 416.

[0100] FIG. 10B is an example of a circuit diagram of a first adjustable resistor 1016A that can be used as the adjustable resistor 1016 in FIG. 10A is an example of a circuit diagram of a first adjustable resistor 1016A that can be used as the adjustable resistor 1016 in FIG. 10A is an example of a circuit diagram of a first adjustable resistor 1016A that can be used as the adjustable resistor 1016 in

[0101] In some embodiments, the bias generator 1030 is configured to generate a first bias voltage Vbiasp provided to the gate terminal of the p-type transistor 1026 and a second bias voltage Vbiasn provided to the gate terminal of the n-type transistor 1028. In some embodiments, the bias generator 1030 is configured to output appropriate voltage levels at the first bias voltage Vbiasp and the second bias voltage Vbiasn in response to the slow-down control signal SLOW to adjust the resistance value between the first terminal 1022 and the second terminal 1024.

[0102] FIG. 10C is an example of a circuit diagram of a first adjustable resistor 1016A that can be used as the adjustable resistor 1016 in FIG. 10A is an example of a circuit diagram of a first adjustable resistor 1016A that can be used as the adjustable resistor 1016 in FIG. 10AThe two terminals of the adjustable resistor 1016 in the first terminal 1042 and the second terminal 1044 correspondingly. The second adjustable resistor 1016B includes a first resistor 1046, a second resistor 1048, and a switch 1050. In this example, the second resistor 1048 is electrically coupled between the first terminal 1042 and the second terminal 1044; and the first resistor 1046 has one end electrically coupled to the second terminal 1044 and another end electrically coupled to the switch 1050.

[0103] In FIG. 10C the switch 1050 is configured to electrically couple the first resistor 1046 to the first terminal 1042 or electrically decouple the first resistor 1042 from the first terminal 1042 in response to an inversion of the slow-down control signal SLOW (labeled “ / SLOW”). Thus, the resistance between the first terminal 1042 and the second terminal 1044 is adjustable based on the slow-down control signal SLOW.

[0104] FIG. 11 is a circuit diagram of an oscillator configured to correspond to different clock periods according to some embodiments. In FIG. 11 the first oscillator 1100A corresponds to FIG. 2 the first oscillator 210 in FIG. 2 the second oscillator 220 in

[0105] In some embodiments, the first oscillator 1100A is a ring oscillator and includes a NAND gate 1102A, a first set of inverters 1104A, a second set of inverters 1106A, and a third set of inverters 1110. A first input terminal of the NAND gate 1102A is electrically coupled to an output terminal of the third set of inverters 1110. A second input terminal of the NAND gate 1102A is configured to receive a reference signal (e.g., a first reference signal START1). In some embodiments, a signal at an output terminal of the first set of inverters 1104A is used as an output clock signal (e.g., a first clock signal CKA_M).

[0106] In some embodiments, the second oscillator 1100B is a ring oscillator and includes a NAND gate 1102B, a first set of inverters 1104B, and a second set of inverters 1106B. A first input terminal of the NAND gate 1102B is electrically coupled to an output terminal of the second set of inverters 1106B. A second input terminal of the NAND gate 1102B is configured to receive another reference signal (e.g., a second reference signal START2). In some embodiments, a signal at an output terminal of the first set of inverters 1104B is used as an output clock signal (e.g., a second clock signal CKB_M).

[0107] In some embodiments, the hardware configuration of NAND gate 1102A, first set of inverters 1104A, and second set of inverters 1106A matches the hardware configuration of NAND gate 1102B, first set of inverters 1104B, and second set of inverters 1106B. In some embodiments, the third set of inverters 1110 includes M stages of inversion. In some embodiments, NAND gate 1102A, first set of inverters 1104A, second set of inverters 1106A, and third set of inverters 1110 are electrically coupled one after another, forming a loop of K+M stages of inversion. In some embodiments, NAND gate 1102B, first set of inverters 1104B, and second set of inverters 1106B are also electrically coupled one after another, forming a loop of K stages of inversion. In some embodiments, K is an odd positive integer, and M is an even positive integer.

[0108] In this example, the additional delay introduced by the third set of inverters 1110 further expands the time period of the first clock signal CKA M relative to the second clock signal CKB M. In some embodiments, because there is no adjustable delay based on the hardware configuration of the first oscillator 1100A and the second oscillator 1100B, the first slow-down control signal SLOW1 and / or the second slow-down control signal SLOW2 as shown in FIG. 2 is omitted.

[0109] FIG. 12 is a flowchart of a method 1200 of generating a count value indicative of a time difference between a first event and a second event, according to some embodiments. In some embodiments, various implementation examples in FIGS. 3-11 are considered, FIG. 2 the time-to-digital conversion device 200 in FIG. 2 performs various operations of the method 1200. As shown in the method 1200 includes blocks 1210-1240.

[0110] FIG. 2 At block 1210, in response to the first event, a first oscillator (e.g., the first oscillator 210 in FIG. 2 outputs a first clock signal (e.g., the first clock signal CKA M of FIG. 3 In some embodiments, the first clock signal has a first clock period. In some embodiments, block 1210 corresponds at least to the operations of stages 315 and 320 in

[0111] In some embodiments, the method 1200 further includes receiving, by the first oscillator, a first reference signal (e.g., the first reference signal REF1 of FIG. 2the first reference signal changes from a first logic state (e.g., low) to a second logic state (e.g., high). In some embodiments, the method 1200 further includes deactivating the first oscillator based on the first reference signal being in the first logic state, and / or activating the first oscillator based on the second reference signal being in the second logic state.

[0112] At block 1220, in response to the second event, the second oscillator (e.g., the second oscillator 220 in FIG. 12A) outputs a second clock signal (e.g., the second clock signal CKB M in FIG. 12B). In some embodiments, the second clock signal has a second clock period. In some embodiments, the first event occurs before the second event (e.g., by a time difference Tsense). In some embodiments, the first clock period is greater than the second clock period by a period difference AT. In some embodiments, block 1220 corresponds at least to the operation of stages 330 and 335 in FIG. 12A. FIG. 2 FIG. 2 At block 1220, in response to the second event, the second oscillator (e.g., the second oscillator 220 in FIG. 12A) outputs a second clock signal (e.g., the second clock signal CKB M in FIG. 12B). In some embodiments, the second clock signal has a second clock period. In some embodiments, the first event occurs before the second event (e.g., by a time difference Tsense). In some embodiments, the first clock period is greater than the second clock period by a period difference AT. In some embodiments, block 1220 corresponds at least to the operation of stages 330 and 335 in FIG. 12A. FIG. 3

[0113] In some embodiments, the method 1200 further includes receiving, by the second oscillator, a second reference signal (e.g., the second reference signal START2 in FIG. 12A), where the second event corresponds to the second reference signal changing from a first logic state (e.g., low) to a second logic state (e.g., high). In some embodiments, the method 1200 further includes deactivating the second oscillator based on the second reference signal being in the first logic state, and / or activating the second oscillator based on the second reference signal being in the second logic state. FIG. 2

[0114] At block 1230, based on a phase relationship between the first clock signal and the second clock signal, a phase detector (e.g., the phase detector 230 in FIG. 12A) generates a detection signal (e.g., the detection signal HITB in FIG. 12B). In some embodiments, block 1230 corresponds at least to the operation of stages 340 and 345 in FIG. 12A. FIG. 2 FIG. 2 At block 1230, based on a phase relationship between the first clock signal and the second clock signal, a phase detector (e.g., the phase detector 230 in FIG. 12A) generates a detection signal (e.g., the detection signal HITB in FIG. 12B). In some embodiments, block 1230 corresponds at least to the operation of stages 340 and 345 in FIG. 12A. FIG. 3

[0115] At block 1240, in response to the detection signal indicating that the phase of the second clock signal lags the phase of the first clock signal, a clock counter (e.g., the clock counter 240 in FIG. 12A) generates a count value (e.g., the count value TDC OUT in FIG. 12B) based on the first clock signal. In some embodiments, block 1240 corresponds to at least part of the operation of stages 325-345 in FIG. 12A. FIG. 2 FIG. 2 At block 1240, in response to the detection signal indicating that the phase of the second clock signal lags the phase of the first clock signal, a clock counter (e.g., the clock counter 240 in FIG. 12A) generates a count value (e.g., the count value TDC_OUT in FIG. 12B) based on the first clock signal. In some embodiments, block 1240 corresponds to at least part of the operation of stages 325-345 in FIG. 12A. FIG. 3

[0116] ​​​​​​​In some embodiments, to generate the count value by the clock counter, the method 1200 further includes generating, by a clock gating circuit (e.g., the clock gating circuit 250 in FIG. 2 ) of the clock counter, a count clock signal (e.g., the count clock signal CKC in FIG. 2 ) based on the first clock signal and the detection signal. In some embodiments, the method 1200 further includes generating, by a counter (e.g., the counter 260 in FIG. 2 ) the count value based on the count clock signal. In some embodiments, the counter is an N-bit counter, where N ranges from 6 to 12, or 8 to 10. In some embodiments, the count value is an N-bit unsigned integer.

[0117] In some embodiments, the method 1200 further includes setting the first oscillator, the second oscillator, or both, such that the second clock period is at least 100 times a period difference AT between the first clock period and the second clock period. In some embodiments, the first oscillator is a first ring oscillator, and the second oscillator is a second ring oscillator. In some embodiments, the method 1200 further includes setting a first configurable delay of the first oscillator based on configuring one or more of a first load capacitance, a first load resistance, or a first phase interpolator between successive inverting stages of the first oscillator, as shown in the examples in FIG. 4A 、 FIG. 4B and FIGS. 9A-10C . In some embodiments, the method 1200 further includes setting a second configurable delay of the second oscillator based on configuring one or more of a second load capacitance, a second load resistance, or a second phase interpolator between successive inverting stages of the second oscillator, as shown in the examples in FIG. 4A 、 FIG. 4B and FIGS. 9A-10C .

[0118] In some aspects, a time-to-digital conversion device includes a first oscillator configured to output a first clock signal in response to a first event, the first clock signal having a first clock period, and a second oscillator configured to output a second clock signal in response to a second event. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is greater than the second clock period. The time-to-digital conversion device further includes a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. The count value represents a time difference between the first event and the second event.

[0119] In some embodiments, the first event corresponds to the first reference signal changing from the first logic state to the second logic state, and the second event corresponds to the second reference signal changing from the first logic state to the second logic state.

[0120] In some embodiments, the first oscillator is configured to be disabled based on the first reference signal being in the first logic state, and to be enabled based on the first reference signal being in the second logic state, and the second oscillator is configured to be disabled based on the second reference signal being in the first logic state, and to be enabled based on the second reference signal being in the second logic state.

[0121] In some embodiments, the first oscillator is a first ring oscillator including one or more of a first load capacitance between two consecutive inverting stages of the first oscillator, a first load resistance, or a first phase interpolator, and is configured to set a first configurable delay of the first oscillator, and the second oscillator is a second ring oscillator including one or more of a second load capacitance between two consecutive inverting stages of the second oscillator, a second load resistance, or a second phase interpolator, and is configured to set a second configurable delay of the second oscillation.

[0122] In some embodiments, the first load capacitance or the second load capacitance is based on a NAND gate or a NOR gate.

[0123] In some embodiments, the phase detector includes a D-type flip-flop, a D terminal of the D-type flip-flop is configured to receive a first signal corresponding to the first clock signal, a clock terminal of the D-type flip-flop is configured to receive a second signal corresponding to an inversion of the second clock signal, and a Q terminal of the D-type flip-flop is configured to output a third signal corresponding to the detection signal.

[0124] In some embodiments, the clock counter includes: a clock gating circuit configured to generate a counting clock signal based on the first clock signal and the detection signal; and a counter configured to generate a count value based on the counting clock signal.

[0125] In some embodiments, the clock gating circuit is based on a D-type flip-flop or a D-type latch, and has a NAND gate or an AND gate.

[0126] In some embodiments, the counter is an N-bit counter, N ranges from 6 to 12.

[0127] In some embodiments, the second clock period is at least 100 times of a period difference between the first clock period and the second clock period.

[0128] In some aspects, a method of generating a count value indicative of a time difference between a first event and a second event includes, in response to the first event, outputting, by a first oscillator, a first clock signal, the first clock signal having a first clock period. In response to the second event, outputting, by a second oscillator, a second clock signal, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period. The method further includes generating, by a phase detector, a detection signal based on a phase relationship between the first clock signal and the second clock signal, and in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal, generating, by a clock counter, the count value based on the first clock signal.

[0129] In some embodiments, the method further includes receiving, by the first oscillator, a first reference signal, the first event corresponding to the first reference signal changing from a first logic state to a second logic state, and receiving, by the second oscillator, a second reference signal, the second event corresponding to the second reference signal changing from the first logic state to the second logic state.

[0130] In some embodiments, the method further includes disabling the first oscillator based on the first reference signal being in the first logic state, enabling the first oscillator based on the first reference signal being in the second logic state, disabling the second oscillator based on the second reference signal being in the first logic state, or enabling the second oscillator based on the second reference signal being in the second logic state.

[0131] In some embodiments, the method further includes setting a first configurable delay of the first oscillator based on configuring one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two consecutive inverting stages of the first oscillator, and setting a second configurable delay of the second oscillator based on configuring one or more of a second load capacitance, a second load resistance, or a second phase interpolator between two consecutive inverting stages of the second oscillator, wherein the first oscillator is a first ring oscillator and the second oscillator is a second ring oscillator.

[0132] In some embodiments, generating, by the clock counter, the count value includes generating, by a clock gating circuit of the clock counter, a count clock signal based on the first clock signal and the detection signal, and generating, by a counter, the count value based on the count clock signal.

[0133] In some embodiments, the count value is an N-bit unsigned integer, and N ranges from 6 to 12.

[0134] In some embodiments, the method further includes setting the first oscillator, the second oscillator, or both, such that the second clock period is at least 100 times a period difference between the first clock period and the second clock period.

[0135] In some aspects, an integrated circuit die includes one or more digital circuit blocks configured to output a first reference signal and a second reference signal, and a time-to-digital conversion device configured to output a count value indicative of a time difference between a first event and a second event. The time-to-digital conversion device includes a first oscillator configured to output a first clock signal in response to the first event based on the first reference signal. A second oscillator is configured to output a second clock signal based on the second event in response to the second reference signal. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is greater than the second clock period. The time-to-digital conversion device further includes a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate the count value based on the first clock signal in response to the detection signal indicative of a phase of the second clock signal lagging behind a phase of the first clock signal.

[0136] In some embodiments, the first oscillator is a first ring oscillator including one or more of a first load capacitance between two consecutive inverting stages of the first oscillator, a first load resistance, or a first phase interpolator, and is configured to set a first configurable delay of the first oscillator, and the second oscillator is a second ring oscillator including one or more of a second load capacitance between two consecutive inverting stages of the second oscillator, a second load resistance, or a second phase interpolator, and is configured to set a second configurable delay of the second oscillation.

[0137] In some embodiments, the clock counter includes a clock gating circuit configured to generate a count clock signal based on the first clock signal and the detection signal, and a counter configured to generate the count value based on the count clock signal.

[0138] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will readily understand that they can readily employ the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same results as the embodiments introduced herein. Those skilled in the art will also readily appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A time-to-digital converter, comprising: A first oscillator is configured to output a first clock signal in response to a first event, the first clock signal having a first clock period; A second oscillator is configured to output a second clock signal in response to a second event, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; A phase detector is configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal; as well as A clock counter is configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal, the count value indicating the time difference between the first event and the second event.

2. The time-to-digital converter according to claim 1, wherein, The first event corresponds to the first reference signal changing from a first logic state to a second logic state, and The second event corresponds to the second reference signal changing from the first logic state to the second logic state.

3. The time-to-digital converter according to claim 2, wherein, The first oscillator is configured to deactivate based on the first reference signal being in the first logic state, and to activate based on the first reference signal being in the second logic state. The second oscillator is configured to be deactivated based on the second reference signal being in the first logic state, and to be activated based on the second reference signal being in the second logic state.

4. The time-to-digital converter according to claim 1, wherein, The first oscillator is a first ring oscillator, including one or more of a first load capacitor, a first load resistor, or a first phase interpolator between two consecutive inverting stages of the first oscillator, and is configured to set a first configurable delay for the first oscillator. The second oscillator is a second ring oscillator, including one or more of a second load capacitor, a second load resistor, or a second phase interpolator between two consecutive inverting stages of the second oscillator, and is configured to set a second configurable delay for the second oscillator.

5. The time-to-digital converter according to claim 4, wherein, The first load capacitor or the second load capacitor is based on a NAND gate or a NOR gate.

6. The time-to-digital converter according to claim 1, wherein, The phase detector includes a D-type trigger. The D terminal of the D-type flip-flop is configured to receive a first signal corresponding to the first clock signal. The clock terminal of the D-type flip-flop is configured to receive a second signal that is inversely corresponding to the second clock signal, and The Q terminal of the D-type trigger is configured to output a third signal corresponding to the detection signal.

7. The time-to-digital converter according to claim 1, wherein, The clock counter includes: A clock gating circuit is configured to generate a counting clock signal based on the first clock signal and the detection signal; and A counter is configured to generate the count value based on the count clock signal.

8. The time-to-digital converter according to claim 7, wherein, The clock gating circuit is based on a D-type flip-flop or a D-type latch and has NAND gates or AND gates.

9. A method for generating a count value indicating the time difference between a first event and a second event, comprising: In response to the first event, a first clock signal is output by a first oscillator, the first clock signal having a first clock period; In response to the second event, a second clock signal is output by a second oscillator, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; A detection signal is generated by a phase detector based on the phase relationship between the first clock signal and the second clock signal; as well as In response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal, the clock counter generates the count value based on the first clock signal.

10. An integrated circuit die, comprising: One or more digital circuit blocks are configured to output a first reference signal and a second reference signal; as well as A time-to-digital converter configured to output a count value indicating the time difference between a first event and a second event, the time-to-digital converter comprising: A first oscillator is configured to output a first clock signal in response to a first event based on the first reference signal, the first clock signal having a first clock period; A second oscillator is configured to output a second clock signal based on a second event in response to a second reference signal, the second clock having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; A phase detector is configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal; and A clock counter is configured to generate a count value based on the first clock signal in response to a detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal.

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