Nor flash chip erasure frequency recording method, device and equipment and storage medium

Abstract

The invention provides a Nor flash chip erasure frequency recording method, device and equipment and a storage medium, and is applied to the technical field of semiconductor integrated circuits. When an erasure instruction is received, current erasure frequency information of a target minimum erasure unit is read to a temporary storage unit to be temporarily stored; then, executing erasing operation on the target minimum erasing unit, clearing internal data of the target minimum erasing unit and counting old erasing frequency information in the storage area; generating updated erasure frequency information according to the temporarily stored current erasure frequency information; and finally, writing the updated erasure frequency information into a counting storage area of the target minimum erasure unit which is erased. According to the internal recording mode, the integrity and the accuracy of the data can be ensured even under the condition of power failure, so that the reliability and the accuracy of recording the erasing times of the Nor flash chip are remarkably improved, and the service life of the Nor flash chip is effectively prolonged.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a method, apparatus, device and storage medium for recording the number of erase cycles of a Nor flash chip. Background Technology

[0002] NOR Flash chips, as a type of non-volatile memory, are widely used in various electronic devices. However, the memory cells of NOR Flash chips have an inherent limitation on the number of erase cycles. Typically, there is an upper limit to the number of erase cycles, for example, generally no more than 100,000. Exceeding this limit may lead to erase operation failures, which in turn seriously affects the reliability and lifespan of the chip. Therefore, during the use of NOR Flash chips, users need to effectively monitor the number of erase cycles to ensure that the chip operates within the specified upper limit, thereby improving its overall reliability.

[0003] In existing technologies, a common method for recording erase counts is through an external controller for the NOR Flash chip. While this external recording method provides erase count monitoring, it has significant limitations. Specifically, using an external controller to record erase counts not only requires processing and storing large amounts of complex data, increasing the design and management burden of the external system, but its biggest challenge lies in the fact that the recorded erase count information is easily lost when the system loses power. This power-loss loss problem makes the erase count recording unreliable and unsustainable, failing to provide users with continuous and accurate erase count data, thus hindering the effective improvement of the overall reliability of the NOR Flash chip.

[0004] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0005] In view of the shortcomings of the prior art, this application provides a method, apparatus, device and storage medium for recording the erase count of a Nor flash chip, which is applied to the field of semiconductor integrated circuit technology. It solves the problems of easy loss of erase count information and heavy external recording burden in the prior art. It realizes internal recording and management of erase count information, improves the reliability and accuracy of Nor flash chip erase count recording, and effectively extends the chip's service life.

[0006] Firstly, a method for recording the number of erase cycles of a Nor flash chip is provided, applied to a memory, wherein the memory includes multiple minimum erase units, each of which has an independent counting storage area for storing the number of erase cycles of that minimum erase unit. The method includes the following steps: S1: In response to the erase command for the target minimum erase unit, the current erase count information in the count storage area of ​​the target minimum erase unit is read into the temporary storage unit; S2: Perform an erasure operation on the target minimum erasure unit according to the erasure instruction. The erasure operation is used to clear the data in the target minimum erasure unit and the current erasure count information in the counting storage area. S3: Generate updated erase count information based on the current erase count information in the temporary storage unit; S4: Write the updated erasure count information into the count storage area of ​​the target minimum erasure unit that has been erased.

[0007] Furthermore, the counting storage area is a word line allocated within the address space of the minimum erase unit, and step S1 includes: S11: In response to an erase instruction for a target minimum erase unit, address the word line in the target minimum erase unit that serves as the counting storage area; S12: Transmit the current erase count information stored in the word line to the temporary storage unit.

[0008] Furthermore, step S4 includes: S41: Perform a programming operation on the word line within the target minimum erasure unit to write the updated erasure count information into the word line.

[0009] Furthermore, the method also includes the following steps: S13: In response to an erase command for the target minimum erase unit, detect the data state inside the target minimum erase unit; S14: When the data state is not full FF state, the current erasure count information in the counting storage area of ​​the target minimum erasure unit is read into the temporary storage unit; S15: When the data state is all FF state, perform a pre-programming operation on the target minimum erase unit, and write all the data in the target minimum erase unit and the data in the counting storage area to 0; S16: Perform an erase pulse operation on the pre-programmed target minimum erase unit; S17: Perform an erase verification operation on the target minimum erase unit after the erase pulse operation to confirm that the data in the target minimum erase unit and the data in the counting storage area have become all FF.

[0010] Furthermore, step S3 includes: S31: Obtain the current erase count information temporarily stored in the temporary storage unit; the temporary storage unit is a register or static random access memory integrated inside the Nor flash chip, used to maintain the current erase count information during the erase operation; S32: Increment the current erase count information by one to obtain the updated erase count information.

[0011] Furthermore, in step S1, the erase command includes a first type of command for a single minimum erase unit and a second type of command for multiple minimum erase units, and the step in response to the erase command for the target minimum erase unit includes: S18: When the second type of instruction is received, the address range covered by the second type of instruction is parsed to determine all the smallest erase units contained in the address range; S19: Each of the minimum erase units is taken as the target minimum erase unit, so that the number of erases of each minimum erase unit within the coverage of the second type of instruction is accumulated separately.

[0012] Furthermore, the method also includes: S5: Receive an externally sent erase count read instruction, wherein the read instruction contains address information specifying the minimum erase unit; S6: Address the counting storage area inside the corresponding smallest erasure unit according to the address information; S7: Read the erase count information stored in the counting storage area; S8: Output the erase count information through the data interface of the Nor flash chip.

[0013] Secondly, a device for recording the number of erase cycles of a Nor flash chip, the device comprising: The read module is used to read the current number of erases information in the count storage area of ​​the target minimum erase unit into the temporary storage unit in response to the erase command for the target minimum erase unit; The erasure module is used to perform an erasure operation on the target minimum erasure unit according to the erasure instruction. The erasure operation is used to clear the data in the target minimum erasure unit and the current erasure count information in the counting storage area. The generation module is used to generate updated erase count information based on the current erase count information in the temporary storage unit; The writing module is used to write the updated erase count information into the count storage area of ​​the target minimum erase unit that has been erased.

[0014] Thirdly, this application provides an apparatus including a processor and a memory, the memory storing computer-readable instructions that, when executed by the processor, perform the steps of any of the methods described above.

[0015] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, performs the steps of any of the above methods.

[0016] Beneficial Effects: The method, apparatus, device, and storage medium for recording erase counts of Nor flash chips proposed in this application effectively solves the problems of high system complexity and easy data loss due to power failure in existing technologies where external controllers record erase counts by directly storing the erase count information of each smallest erase unit in its internal independent counting storage area and adopting a "read first, erase then update and write" mechanism. Specifically, upon receiving an erase command, the current erase count information of the target smallest erase unit is first read into a temporary storage unit for temporary storage to ensure that the information is not lost during the erase operation; then, an erase operation is performed on the target smallest erase unit to clear its internal data and the old erase count information in the counting storage area; next, updated erase count information is generated based on the temporarily stored current erase count information; finally, the updated erase count information is written into the counting storage area of ​​the target smallest erase unit that has been erased. This internal recording method avoids dependence on external controllers, reduces the overall complexity of the system, and because the erase count information is stored inside the non-volatile Nor flash chip, the integrity and accuracy of the data can be guaranteed even in the event of power failure. This significantly improves the reliability and accuracy of the erase count recording of the Nor flash chip and effectively extends the service life of the Nor flash chip. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for recording the number of erase cycles of a Nor flash chip as proposed in this application.

[0018] Figure 2 This is a structural diagram of a device for recording the number of erase / write cycles of a NOR Flash chip proposed in this application.

[0019] Figure 3 A schematic diagram of the device provided in this application.

[0020] Labeling explanations: 201, Read module; 202, Erase module; 203, Generate module; 204, Write module; 301, Processor; 302, Memory; 303, Communication bus; 3, Device. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and marked in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] Nor flash memory chips, as a type of non-volatile memory, are widely used in data storage. However, Nor flash chip cells have a limited number of erase cycles, typically capped at 100,000. Exceeding this limit may cause erase operations to fail, impacting reliability and lifespan. To ensure that Nor flash chips do not exceed their specified erase cycle limit in practical applications, users typically need to monitor the erase cycle count. Currently, existing solutions primarily rely on external controllers to record erase cycles. This external recording method has several problems. First, the external controller needs to record a large amount of complex erase cycle information, increasing system complexity. Second, and most critically, the external controller is prone to losing recorded erase cycle information during power outages, making it impossible to accurately track the erase history of the Nor flash chip and thus hindering effective management of its reliability.

[0023] For this, please refer to Figure 1 This application proposes a method for recording the number of erase cycles of a Nor flash chip, applied to a memory. The memory contains multiple minimum erase units, each with an independent counting storage area for storing the number of erase cycles for that minimum erase unit. The method includes the following steps: S1: In response to the erase command for the target minimum erase unit, read the current erase count information in the count storage area of ​​the target minimum erase unit into the temporary storage unit; S2: Perform an erasure operation on the target minimum erasure unit according to the erasure instruction. The erasure operation is used to clear the data in the target minimum erasure unit and the current erasure count information in the count storage area. S3: Generate updated erase count information based on the current erase count information in the temporary storage unit; S4: Write the updated erase count information into the count storage area of ​​the target smallest erase unit that has been erased.

[0024] The process begins when the chip receives an erase command from an external host. This command specifies one or more addresses to be erased. The chip's internal control logic first parses the command to determine which one or more minimum erase units are being targeted. A minimum erase unit is the smallest physical unit in which a Nor flash chip performs an erase operation; it can be a sector or a block. After locking onto the target minimum erase unit, the first step before performing any physical erase operation is data backup. Specifically, the control logic issues an internal read command. The target address of this command is not the user data area, but rather a pre-planned, independent counter memory area located within the target minimum erase unit. This area stores the total number of erases the unit has undergone so far, i.e., the current erase count information. This value, once read, does not disappear directly from the bus but is transferred and temporarily latched into a temporary memory unit located inside the chip. This temporary memory unit is volatile, but its purpose is to safely store this count value, which is about to be erased, during subsequent erase operations.

[0025] After confirming that the current erase count information has been safely backed up, the control logic begins applying the specific voltage and pulses required for the erase operation to the target smallest erase cell. In Nor flash technology, the erase operation typically removes the floating gate electrons from all the storage transistors within the entire cell, restoring it to its initial state of logic 1, which is equivalent to all FF in hexadecimal representation. A key characteristic of this process is its indiscriminate nature; that is, the erase voltage applied to the entire smallest erase cell simultaneously affects both the area storing user data and the count memory area storing erase count information. Therefore, after the erase operation is completed, not only is the user data cleared, but the current erase count information in the count memory area is also erased, becoming all FF. This is precisely the necessity of the first backup operation.

[0026] After the target smallest erase unit is successfully erased, or during the erase operation, the chip's internal control logic accesses the temporary storage unit previously used for backup. From this unit, it retrieves the current erase count information saved just before the erase. Then, the arithmetic logic unit within the control logic increments this value by one. The physical meaning of this simple arithmetic operation is that the target smallest erase unit has just undergone another erase, so its total erase count needs to be increased accordingly. The result of this operation is the updated erase count information.

[0027] After generating the updated erase count information, the control logic initiates an internal programming operation, also known as a write operation. The target address of this programming operation is the counting memory area inside the smallest erase unit that was just erased. The control logic writes the updated erase count information as programming data into this area. Since Norflash programming involves flipping a logic 1 to logic 0, and the erased counting memory area is already in an all-1 state, programming can be performed directly. After programming, the new erase count, incremented by one, is permanently and non-volatilely stored inside the smallest erase unit. This completes a full erase cycle with internal count updates.

[0028] Through this closed-loop process of reading, erasing, updating, and writing back, the method in this application ensures accurate, independent, and power-loss-free recording of the number of erases for each smallest erase unit. External systems do not need to concern themselves with this internal mechanism; they only need to send erase commands as usual. The chip automatically maintains its lifespan information internally, providing a solid data foundation for implementing more advanced wear leveling algorithms, bad block management, and predictive maintenance strategies.

[0029] Furthermore, to make the above scheme more feasible, the physical implementation of the counting storage area was specifically defined. The counting storage area is designed as a word line allocated within the address space of the smallest erase unit. Accordingly, the steps for reading the current erase count information specifically include: S11: In response to an erase instruction targeting the minimum erase unit, address the word line in the minimum erase unit that serves as the counting storage area; S12: Transfer the current erase count information stored in the word line to the temporary storage unit.

[0030] In the array structure of Nor flash, memory cells are arranged in a matrix of interwoven word lines and bit lines. A minimum erase cell, such as a sector, contains hundreds or thousands of word lines, each controlling a row of memory transistors. Specifically representing the counting memory area as a single word line is a highly efficient implementation with minimal changes to the original chip design. This means that within the address space of each minimum erase cell, one or more word lines are reserved not for storing user data, but specifically for storing metadata, such as the erase count. The address of this word line is fixed, or has a fixed offset relative to the starting address of the cell.

[0031] Once the chip's control logic receives an erase command and determines the target smallest erase unit, its internal address decoder directly calculates the physical address of this dedicated word line according to preset rules. For example, if the last word line of each sector is designated as a counting storage, the address decoder, upon receiving an erase command for sector X, will automatically generate an internal control signal to read the last word line of sector X. Subsequently, the chip's sense amplifier and other circuits are activated to read the state of all memory cells on this word line, forming data representing the current erase count, and sending it to a temporary storage unit. This method utilizes the chip's existing addressing and read circuits, eliminating the need for additional complex hardware and enabling fast and accurate access to the counting information.

[0032] Corresponding to the above read operation, the step of writing the updated erase count information into the count storage area is also specified. This step specifically includes: S41: Perform programming operations on the word lines within the target minimum erase unit to write the updated erase count information into the word lines.

[0033] After the erase operation is completed in the target smallest erase unit and the updated erase count information is generated in the internal arithmetic logic unit, the chip control logic initiates an internal programming process. The target address for programming is precisely set to the address of that dedicated word line. The control logic loads the updated erase count information, such as a 32-bit binary number, through the data input buffer and then drives the programming circuit to apply programming voltages to the specified word line and the corresponding bit line. This writes the updated count value bit by bit into the memory cell of that word line. This programming operation is physically identical to writing data to the user data area and also utilizes the chip's existing functionality. By tightly integrating the implementation of the counting memory area with the chip's basic physical structure, namely the word line, this application not only provides a conceptual method but also presents a clear, efficient, and easily implementable technical path in chip design.

[0034] To further improve the stability and reliability of the erasure operation, this method also introduces a preprocessing and verification mechanism before erasure. Specifically, the method includes the following steps: S13: In response to the erase command for the target minimum erase unit, detect the data status inside the target minimum erase unit; S14: When the data state is not full FF, read the current erase count information in the count storage area of ​​the target minimum erase unit to the temporary storage unit; S15: When the data state is all FF, perform a pre-programming operation on the target minimum erase unit, and write all the data in the target minimum erase unit and the data in the counting storage area to 0; S16: Perform an erase pulse operation on the pre-programmed target minimum erase unit; S17: Perform an erase verification operation on the target minimum erase unit after the erase pulse operation to confirm that the data in the target minimum erase unit and the data in the counting storage area have become all FF.

[0035] In some cases, a minimum erase unit may have already been erased, and its internal data is already in a fully FROM (Fail-to-Flash) state. Performing another erase operation on it at this point is not only redundant but may also cause over-erasure damage to the storage unit, accelerating its aging. Therefore, adding a data status check step before performing the erase operation is essential.

[0036] Upon receiving an erase command, the control logic first performs a quick read or verification of the target smallest erase unit to determine if its content is all FF (Full Front End). If the detection result is not all FF, it means that the unit does indeed contain user-programmed data and needs to be erased. At this point, the process proceeds according to the aforementioned standard steps: back up the erase count, perform the erase, update the count, and write back the count.

[0037] However, if the detection result shows that the cell is already in a full FF state, a special processing procedure will be triggered. Skipping the erase operation directly seems feasible, but it may hide potential risks, such as some memory cells being in a critical state of incomplete erasure. To ensure that each erase operation starts from a defined and uniform initial state to achieve the best erase effect, this application adopts a more robust strategy: pre-programming. Specifically, a programming operation is first performed on the cell that is already in a full FF state, forcibly writing all its bits, including the user data area and the counter memory area, to 0. In this way, regardless of the cell's previous state, it is now uniformly set to a fully programmed state. After pre-programming, a standard erase pulse operation is performed to erase it from the all-0 state back to the full FF state. Finally, an erase verification operation is used to strictly confirm that every bit in the cell has successfully changed to the FF state. This seemingly convoluted pre-programming-erase-verification process is actually a reinforcement measure to ensure erasure quality. It can effectively avoid incomplete erasure or erasure failure caused by uncertain initial cell states, thereby significantly improving the overall reliability of the chip.

[0038] The process of generating the updated erase count information is also described in more detail. This step specifically includes: S31: Obtain the current erase count information temporarily stored in the temporary storage unit; the temporary storage unit is a register or static random access memory integrated inside the Norflash chip, used to maintain the current erase count information during the erase operation; S32: Increment the current erase count information by one to obtain the updated erase count information.

[0039] This method clarifies two preferred physical implementations of temporary storage units: registers or static random access memory (SRAM). Both memory devices are integrated within the Nor flash chip as part of its control logic.

[0040] In one specific embodiment, the temporary storage unit can be a single dedicated hardware register or a set of dedicated registers. Registers are the fastest storage elements and are located at the core of the processor or control logic. After the current erase count information is read from the counting memory area, i.e., the dedicated word line, this data can be directly latched into this set of registers. Since the registers are directly connected to the arithmetic logic unit, subsequent increment operations can be completed instantaneously. The advantage of this design is its extremely high speed and minimal latency, making it ideal for applications with stringent requirements on erase operation time.

[0041] In another specific embodiment, the temporary storage unit can be a small piece of on-chip SRAM. Compared to registers, SRAM is slightly slower to access, but it can have a larger capacity and is more flexible. For example, if the chip's control logic is designed for pipelined operation, capable of handling multiple erase requests simultaneously, then a small piece of SRAM can allocate multiple storage locations to temporarily store the current erase count information from different smallest erase units. The control logic manages these SRAM locations by maintaining a pointer or index, ensuring that the count value for each erase task is correctly saved and updated. This design is more advantageous when handling complex concurrent tasks.

[0042] Whether registers or SRAM are used, their core function remains the same: to provide a reliable, volatile data safe haven during the brief window when physical erase operations cause data loss in the counting storage area. The update operation itself uses the chip's internal adder circuit to perform a simple increment operation on the value retrieved from this safe haven, thereby generating a new count value ready for writing back.

[0043] Furthermore, this method also considers compatibility handling for different types of erase commands. In practical applications, the erase commands sent by the host may be divided into two categories: namely, erase commands include a first type of command targeting a single minimum erase unit and a second type of command targeting multiple minimum erase units. The steps in response to an erase command targeting a target minimum erase unit include: S18: When a second type of instruction is received, the address range covered by the second type of instruction is parsed to determine all the smallest erase units contained in the address range; S19: Each minimum erase unit is taken as the target minimum erase unit, so that the number of erases of each minimum erase unit within the coverage of the second type of instruction is accumulated separately.

[0044] To ensure that the erase count of each affected smallest erase unit can be independently accumulated when processing the second type of instruction, the steps for responding to the erase instruction are further refined: when the second type of instruction is received, the address range covered by the instruction is first parsed to determine all the smallest erase units contained in the address range; then, each smallest erase unit is taken as the target smallest erase unit, and the complete count update process is executed in sequence.

[0045] This processing logic ensures that the granularity of erase count recording remains at the level of the smallest erase unit, thus guaranteeing the accuracy of the record. Specifically, when the chip control logic receives an instruction such as a full-chip erase, it does not simply increment a global counter. Instead, the control logic generates a list containing the addresses of all the smallest erase units within the chip, based on the chip's memory mapping. Then, the control logic initiates a loop or iterative process. In each loop, the address of a smallest erase unit is retrieved from the list and set as the current target. Then, for this current target, the aforementioned four steps are executed completely: read its independent current erase count information into a temporary storage unit, erase that unit, increment the count value in the temporary storage unit, and then write the updated count value back to the unit's count storage area. The loop continues until all the smallest erase units in the list have been processed. In this way, even a batch erase triggered by a macroscopic instruction is decomposed into an independent and precise lifetime record for each micro-unit, avoiding the blurring or distortion of count information caused by batch operations.

[0046] To maximize the value of the erase count information for internal records, this application also adds an external query function. The method further includes: S5: Receive an externally sent erase count read instruction, which contains the address information of the specified minimum erase unit; S6: Address the counting storage area inside the corresponding smallest erase unit according to the address information; S7: Read the erase count information stored in the counter storage area; S8: Output the erase count information through the Nor flash chip's data interface.

[0047] This feature provides a query interface for upper-layer applications, such as operating systems, file systems, or specific device drivers, enabling them to proactively obtain the health status of any smallest erase unit within the chip. The workflow is as follows: The external host system can construct and send a special, non-standard, vendor-defined instruction—a erase count read instruction. This instruction includes an address field specifying which smallest erase unit is being queried.

[0048] Upon receiving this instruction, the control logic of the Nor flash chip recognizes it as a query request, not an erase or program request. The control logic parses the address information in the instruction and locates the target smallest erase cell. Then, similar to the first step of the erase process, the control logic addresses the dedicated word line within that cell, which serves as a counting memory area. Next, an internal read operation is performed to retrieve the erase count information stored on that word line. However, unlike the erase process, this time the read data is not sent to a temporary storage unit for updating; instead, it is directly sent to the chip's data output buffer. Finally, this count value is sent as the instruction return value to the external host via the chip's data interface, such as an SPI bus or parallel bus.

[0049] Through this query mechanism, external systems can periodically poll the erase count of each storage cell, thereby implementing a complex wear-leveling strategy. This involves intentionally directing new write operations to cells with fewer erase counts to balance the overall chip wear. Simultaneously, a warning threshold for erase counts can be set. When the erase count of a cell approaches this threshold, the system can preemptively mark it as read-only or perform data migration, thus achieving predictive maintenance and preventing sudden failures at critical moments.

[0050] Accordingly, this application also provides a device for recording the number of erase cycles of a Nor flash chip. Please refer to... Figure 2 The device includes: The reading module 201 is used to read the current number of erases information in the count storage area of ​​the target minimum erase unit into the temporary storage unit in response to the erase command for the target minimum erase unit; Erasing module 202 is used to perform an erasing operation on the target minimum erasing unit according to the erasing instruction. The erasing operation is used to clear the data in the target minimum erasing unit and the current erasing count information in the counting storage area. The generation module 203 is used to generate updated erase count information based on the current erase count information in the temporary storage unit; The writing module 204 is used to write the updated erase count information into the count storage area of ​​the target smallest erase unit that has been erased.

[0051] Specifically, the read module refers to a hardware or firmware logic unit within the Nor flash chip configured to perform read operations. This read module 201 can consist of hardware circuits such as control logic circuits, address decoders, and data transmission paths within the Nor flash chip. It is configured to automatically address and retrieve data from a specified counted memory area upon receiving an erase command. For example, the read module 201 may include a state machine to control the read timing and data flow, its purpose being to safely acquire and temporarily store the current erase count information before the erase operation begins.

[0052] The erase module 202 refers to a hardware or firmware logic unit within the Nor flash chip configured to perform erase operations. This erase module 202 can consist of hardware units such as an erase control circuit, a high-voltage generation circuit, and an erase verification circuit within the Nor flash chip. It is configured to apply erase pulses to the target smallest erase unit according to a preset erase algorithm and perform erase verification upon receiving an erase command. For example, the erase module 202 may include an erase pump to generate the high voltage required for erasure, with the purpose of thoroughly erasing the data and old erase count information within the target smallest erase unit.

[0053] In practical applications, the generation module 203 refers to a hardware or firmware logic unit within the Nor flash chip configured to perform erase count update operations. This generation module 203 can be implemented by the arithmetic logic unit (ALU) or a dedicated counter circuit within the Nor flash chip. It is configured to perform an increment operation or other update operations on the current erase count information obtained from the temporary storage unit to obtain a new erase count value. For example, the generation module 203 could be a simple adder used to increment the binary count, aiming to accurately reflect the latest erase count of the target minimum erase unit.

[0054] Furthermore, the write module 204 refers to a hardware or firmware logic unit within the Nor flash chip configured to perform programming write operations. This write module 204 can be composed of hardware units such as a programming control circuit, a programming voltage generation circuit, and a programming verification circuit within the Nor flash chip. It is configured to program and write the updated erase count information into its counting storage area after the target minimum erase unit has been erased. For example, the write module 204 may include a programming pump to generate the voltage required for programming, and work with a data buffer to write data to the target storage unit. Its purpose is to persistently store the updated erase count information in a non-volatile counting storage area.

[0055] The Nor flash chip erase count recording device proposed in this application achieves accurate and reliable recording of the erase count by transferring the erase count recording function from an external controller to the Nor flash chip itself and configuring an independent counting storage area for each smallest erase unit. Compared with existing technologies that rely on external controllers to record erase counts, this application has significant advantages. Traditional external recording methods not only increase the complexity of system design but also easily lose erase count information during power failure, making it impossible to accurately track the lifespan of the Nor flash chip. This application effectively solves these problems by implementing erase count recording and management internally within the Nor flash chip. Specifically, by setting up a read module 201, an erase module 202, a generate module 203, and a write module 204 inside the Nor flash chip, a closed-loop erase count management mechanism is formed. This internal recording mechanism tightly binds the erase count information to the corresponding smallest erase unit, ensuring that the erase count information is not lost even when the system is powered off, thereby guaranteeing the integrity and accuracy of the Nor flash chip erase history. This device greatly simplifies the design of external controllers, reduces the overall complexity of the system, and significantly improves the reliability and accuracy of the erase count record for Nor flash chips, thereby better managing the lifespan and performance of Nor flash chips.

[0056] Please refer to Figure 3 , Figure 3 This application provides a schematic diagram of the structure of a device 3, comprising a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other via a communication bus 303 and / or other forms of connection mechanism (not shown). The memory 302 stores computer-readable instructions executable by the processor 301. When the device 3 is running, the processor 301 executes the computer-readable instructions to perform the method in any optional implementation of the above embodiments, thereby achieving the following functions: in response to an erase instruction for a target minimum erase unit, reading the current erase count information in the counting storage area of ​​the target minimum erase unit to a temporary storage unit; performing an erase operation on the target minimum erase unit according to the erase instruction, the erase operation being used to clear the data in the target minimum erase unit and the current erase count information in the counting storage area; generating updated erase count information based on the current erase count information in the temporary storage unit; and writing the updated erase count information into the counting storage area of ​​the target minimum erase unit that has been erased.

[0057] This application provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it performs the method in any optional implementation of the above embodiments to achieve the following functions: in response to an erase instruction for a target minimum erase unit, reading the current erase count information in the counting storage area of ​​the target minimum erase unit into a temporary storage unit; performing an erase operation on the target minimum erase unit according to the erase instruction, the erase operation being used to clear the data in the target minimum erase unit and the current erase count information in the counting storage area; generating updated erase count information based on the current erase count information in the temporary storage unit; and writing the updated erase count information into the counting storage area of ​​the target minimum erase unit that has been erased.

[0058] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0059] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0060] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0061] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for recording the number of erase cycles of a Nor flash chip, applied to a memory, wherein the memory comprises a plurality of minimum erase units, each of the minimum erase units having an independent counting storage area for storing the number of erase cycles of that minimum erase unit, characterized in that, The method includes the following steps: S1: In response to the erase command for the target minimum erase unit, the current erase count information in the count storage area of ​​the target minimum erase unit is read into the temporary storage unit; S2: Perform an erasure operation on the target minimum erasure unit according to the erasure instruction. The erasure operation is used to clear the data in the target minimum erasure unit and the current erasure count information in the counting storage area. S3: Generate updated erase count information based on the current erase count information in the temporary storage unit; S4: Write the updated erasure count information into the count storage area of ​​the target minimum erasure unit that has been erased.

2. The method for recording the number of erase cycles of a Nor flash chip according to claim 1, characterized in that, The counting storage area is a word line allocated within the address space of the minimum erase unit. Step S1 includes: S11: In response to an erase instruction for a target minimum erase unit, address the word line in the target minimum erase unit that serves as the counting storage area; S12: Transmit the current erase count information stored in the word line to the temporary storage unit.

3. The method for recording the number of erase cycles of a Nor flash chip according to claim 2, characterized in that, Step S4 includes: S41: Perform a programming operation on the word line within the target minimum erasure unit to write the updated erasure count information into the word line.

4. The method for recording the number of erase cycles of a Nor flash chip according to claim 1, characterized in that, The method also includes the following steps: S13: In response to an erase command for the target minimum erase unit, detect the data state inside the target minimum erase unit; S14: When the data state is not full FF state, the current erasure count information in the counting storage area of ​​the target minimum erasure unit is read into the temporary storage unit; S15: When the data state is all FF state, perform a pre-programming operation on the target minimum erase unit, and write all the data in the target minimum erase unit and the data in the counting storage area to 0; S16: Perform an erase pulse operation on the pre-programmed target minimum erase unit; S17: Perform an erase verification operation on the target minimum erase unit after the erase pulse operation to confirm that the data in the target minimum erase unit and the data in the counting storage area have become all FF.

5. The method for recording the number of erase cycles of a Nor flash chip according to claim 1, characterized in that, Step S3 includes: S31: Obtain the current erase count information temporarily stored in the temporary storage unit; the temporary storage unit is a register or static random access memory integrated inside the Nor flash chip, used to maintain the current erase count information during the erase operation; S32: Increment the current erase count information by one to obtain the updated erase count information.

6. The method for recording the number of erase cycles of a Nor flash chip according to claim 1, characterized in that, In step S1, the erase command includes a first type of command for a single minimum erase unit and a second type of command for multiple minimum erase units. The step in response to the erase command for the target minimum erase unit includes: S18: When the second type of instruction is received, the address range covered by the second type of instruction is parsed to determine all the smallest erase units contained in the address range; S19: Each of the minimum erase units is taken as the target minimum erase unit, so that the number of erases of each minimum erase unit within the coverage of the second type of instruction is accumulated separately.

7. The method for recording the number of erase cycles of a Nor flash chip according to claim 1, characterized in that, The method further includes: S5: Receive an externally sent erase count read instruction, wherein the read instruction contains address information specifying the minimum erase unit; S6: Address the counting storage area inside the corresponding smallest erasure unit according to the address information; S7: Read the erase count information stored in the counting storage area; S8: Output the erase count information through the data interface of the Nor flash chip.

8. A device for recording the number of erase cycles of a Nor flash chip, characterized in that, The device includes: The read module is used to read the current number of erases information in the count storage area of ​​the target minimum erase unit into the temporary storage unit in response to the erase command for the target minimum erase unit; The erasure module is used to perform an erasure operation on the target minimum erasure unit according to the erasure instruction. The erasure operation is used to clear the data in the target minimum erasure unit and the current erasure count information in the counting storage area. The generation module is used to generate updated erase count information based on the current erase count information in the temporary storage unit; The writing module is used to write the updated erase count information into the count storage area of ​​the target minimum erase unit that has been erased.

9. A device, characterized in that, It includes a processor and a memory, the memory storing computer-readable instructions that, when executed by the processor, perform the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-7.

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