Interconnection system between HSIC type chips

Abstract

The invention discloses an HSIC type inter-chip interconnection system, which is characterized in that a clock module, an RX elastic buffer area, an SYNC detection area, an NRZI decoding area, a bit filling area and an RX conversion and maintenance area are designed, so that a receiving circuit and a transmitting circuit are designed, a receiving state machine and a transmitting state machine are influenced, the transmission power consumption is reduced, the occupied area of chips is reduced, the compatibility is strong, the transmission is reliable, and the cost is low. On the premise of keeping compatibility with the USB2.0 protocol, the power consumption and the chip area are remarkably reduced, and meanwhile, the data transmission rate of 480Mb / s is supported.

Description

Technical Field

[0001] This invention belongs to the field of digital integration technology, specifically relating to an HSIC type chip interconnect system, used to design a physical layer interface circuit for high-speed inter-chip communication, based on a fully digital physical layer implementation scheme of high-speed chip interconnect standards, suitable for low-power, small-size data interconnection between system-level chips. Background Technology

[0002] Currently, in mobile devices, IoT terminals, and wearable devices, chip interconnection commonly uses standards such as USB 2.0, I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), or PCIe (peripheral component interconnect express), as shown in Table 1.

[0003] Table 1 Comparison of Inter-chip Interconnection Standards

[0004] While USB 2.0 offers high transfer rates, its physical layer includes analog transceiver circuitry, resulting in high power consumption and a large chip area, making it difficult to meet high integration requirements. Protocols like I2C and SPI require fewer pins and are simpler to implement, but their low transfer rates fail to meet the demands of high-speed data transmission. PCIe offers high transfer rates, but its large pin count leads to high power consumption. Summary of the Invention

[0005] The objective of this invention is to significantly reduce power consumption and chip area while maintaining compatibility with the USB 2.0 protocol, and simultaneously support a data transfer rate of 480Mb / s.

[0006] To achieve the above-mentioned objectives, the present invention provides an HSIC-type inter-chip interconnection system, comprising: The analog module obtains the Strobe signal clock by sampling DATA according to the HSIC specification and transmits it to the RX elastic buffer. The RX elastic buffer also receives the input clock data from the clock module and performs frequency compensation on the Strobe signal clock based on the input clock data. The SYNC detection area acquires frequency-compensated data for synchronization sequence detection, and generates an indication signal upon detecting the SYNC sequence. The NRZI decoding area acquires the SYNC sequence and corresponding indicator signal detected by the SYNC detection area, and performs NRZI decoding. The bit de-padded region obtains the decoded data and corresponding indication signal from the NRZI decoding region. Based on the indication signal, the decoded data is bit aligned, and the aligned data is de-padded. The amount of padding is recorded to affect the receiver state machine. The RX conversion and holding area completes the serial-to-parallel conversion based on the padded data and saves the last data byte before outputting it to the UTMI+ parallel output port. The clock module divides the frequency to generate output clock data, and the UTMI+ parallel output port performs timing control based on the output clock data. The UTMI+ parallel output port transmits parallel data to the TX conversion and holding area, converts the parallel data in the TX conversion and holding area into serial data, and holds the next set of data to be converted. The bit stuffing area stuffs bits according to the serial data, and the number of bits stuffed affects the transmission state machine. The NRZI encoding area performs NRZI encoding based on the padded data, and then transmits the NRZI-encoded data to the analog module.

[0007] Preferably, the input clock data is 240MHz fclk.

[0008] Preferably, the NRZI encoding rule of the NRZI decoding area is to flip 0s and leave 1s unchanged.

[0009] Preferably, the bit de-stuffing area includes an Unstuffed counter and a Bit counter. The Unstuffed counter records the number of "0"s used for padding. When 8 de-stuffing data are accumulated, the receiving state machine will pull utmi_rxvalid_o low for one clock cycle to align the clock. The Unstuffed counter records the number of consecutively received "1"s. When the count reaches 6, the next data is detected. If it is "0", it is considered a padding bit, which is removed, the Bit counter is cleared, and the Unstuffed counter is incremented by one.

[0010] Preferably, the RX conversion and holding area includes a Shift register for performing serial-to-parallel conversion and a Hold register for storing the last data byte.

[0011] Preferably, bit stuffing is not performed in the bit stuffing area during high-speed EOP transmission.

[0012] Preferably, the input clock data is a 60MHz phyclk.

[0013] Preferably, the NRZI encoding rule is as follows: when the current bit of the input source code is 0, NRZI encoding will flip the level; when the current bit of the source code is 1, NRZI encoding will maintain the original level state.

[0014] This invention provides an HSIC-type chip interconnection system. By designing a clock module, RX elastic buffer, SYNC detection area, NRZI decoding area, bit de-stuffing area, and RX conversion and holding area, the receiving and transmitting circuits are designed, influencing the receiving and transmitting state machines. This reduces transmission power consumption, reduces chip area, and provides strong compatibility and reliable transmission. It achieves significant reduction in power consumption and chip area while maintaining compatibility with the USB 2.0 protocol, and supports a data transmission rate of 480Mb / s. Attached Figure Description

[0015] Figure 1 A schematic diagram of a USB PHY digital core provided for the implementation of this invention; Figure 2 A flowchart of the data receiving path provided for the implementation of this invention; Figure 3 A schematic diagram of the receiving state machine during data reception is provided for the implementation of this invention; Figure 4 A flowchart of the data transmission path provided for the implementation of this invention; Figure 5 This is a schematic diagram of the data transmission state machine provided for the implementation of the present invention. Detailed Implementation

[0016] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0017] like Figure 1 As shown, an embodiment of the present invention provides an HSIC-type chip interconnection system, comprising: like Figure 2 As shown, the analog module performs DATA sampling based on the HSIC specification to obtain the Strobe signal clock, which is then transmitted to the RX elastic buffer. The RX elastic buffer simultaneously receives input clock data from the clock module and performs frequency compensation on the Strobe signal clock based on the input clock data.

[0018] The SYNC detection area acquires frequency-compensated data for synchronization sequence detection, and generates an indication signal upon detecting the SYNC sequence.

[0019] The NRZI decoding area acquires the SYNC sequence and corresponding indicator signal detected by the SYNC detection area and performs NRZI decoding.

[0020] The bit de-padded area obtains the decoded data and corresponding indication signal from the NRZI decoding area. Based on the indication signal, the decoded data is bit aligned, and the aligned data is de-padded. The amount of padding is recorded, which affects the receiver state machine.

[0021] The RX conversion and hold area completes the serial-to-parallel conversion based on the padded data and saves the last data byte, outputting it to the UTMI+ parallel output port. At this point, the receiver has seven states: Reset, RX Wait, RX Data, Strip SYNC, RX DataWait, Strip EOP, and Error. The state transition diagram is shown below. Figure 3 As shown.

[0022] The input clock data is fclk_i at 240MHz.

[0023] The RX elastic buffer, as a small FIFO (first in first out), is mainly used to buffer and adjust the output timing of the received signal. It compensates the Strobe signal clock output by the analog receiver with the fclk frequency, eliminates clock deviation, and improves tolerance to clock jitter.

[0024] The SYNC detection area detects a 32-bit synchronization sequence and supports two SYNC modes after NRZI decoding. Upon detecting a SYNC sequence, this module provides an indication signal, which is used for bit alignment.

[0025] The NRZI encoding rule in the NRZI decoding area is to flip 0s and leave 1s unchanged.

[0026] The bit de-stuffing area includes an Unstuffed counter and a Bit counter. The Unstuffed counter records the number of "0"s that were filled in. When 8 de-stuffing data are accumulated, the receiver state machine will pull utmi_rxvalid_o low for one clock cycle to align the clock. The Unstuffed counter records the number of consecutive "1"s received. When it counts to 6, it checks the next data. If it is "0", it is considered that this data is a filling bit, which is removed, the Bit counter is cleared, and the Unstuffed counter is incremented by one.

[0027] The RX conversion and holding area includes the Shift register, which performs the serial-to-parallel conversion, and the Hold register, which stores the last data byte.

[0028] The clock module divides the frequency to generate output clock data, and the UTMI+ parallel output port performs timing control based on the output clock data.

[0029] The UTMI+ parallel output port transmits parallel data to the TX conversion and holding area, which converts the parallel data into serial data and holds the next set of data to be converted.

[0030] The bit stuffing area is stuffed with bits according to the serial data, and the number of bits stuffed affects the transmission state machine.

[0031] The NRZI encoding area performs NRZI encoding based on the padded data and transmits the NRZI-encoded data to the analog module. At this point, the transmit state machine contains six states: Reset, TX Wait, Send SYNC, TX Data Load, TX Data Wait, and Send EOP. The state transition diagram is shown below. Figure 5 As shown.

[0032] The input clock data is phyclk at 60MHz.

[0033] The TX conversion and holding area includes the Shift register, which completes the parallel-to-serial conversion, and the Hold register, which buffers the next set of data to be converted.

[0034] The bit stuffing module forces a flip by adding a 0 to every 6 consecutive 1s in the serial data. Similar to the transmitting module, the bit stuffing module also requires two counters: a stuff counter and a bit counter. The stuff counter records the number of inserted 0s. When 8 stuffed data bits have accumulated, the transmitting state machine pulls `utmi_txready_o` low for one clock cycle to align the clock. The other counter, the bit counter, records the number of consecutive received 1s. When 6 1s are received, a 0 is inserted into the data stream, the bit counter is cleared, and the stuffed counter is incremented. Bit stuffing is not performed during high-speed EOP transmission.

[0035] The NRZI encoding area performs NRZI encoding on the padded data. The NRZI encoding rule is as follows: when the current bit of the input source code is 0, NRZI encoding will flip the level; when the current bit of the source code is 1, NRZI encoding will maintain the original level state.

[0036] The beneficial effects of the embodiments of the present invention are as follows: 1. Reduced power consumption: Due to the use of a fully digital circuit design, no analog transceiver is required, resulting in approximately 50% lower power consumption compared to traditional USB 2.0 PHYs; 2. Reduced area: High digital logic integration reduces chip area by approximately 75%; 3. Strong compatibility: Supports the UTMI+ interface protocol, allowing direct driving without modifying the host controller; 4. Reliable transmission: Clock skew is compensated by an elastic buffer, and signal integrity is improved by NRZI encoding and bit stuffing mechanisms.

Claims

1. An HSIC-type chip interconnection system, characterized in that, include: The analog module obtains the Strobe signal clock by sampling DATA according to the HSIC specification and transmits it to the RX elastic buffer. The RX elastic buffer also receives the input clock data from the clock module and performs frequency compensation on the Strobe signal clock based on the input clock data. The SYNC detection area acquires frequency-compensated data for synchronization sequence detection, and generates an indication signal upon detecting the SYNC sequence. The NRZI decoding area acquires the SYNC sequence and corresponding indicator signal detected by the SYNC detection area, and performs NRZI decoding. The bit de-padded region obtains the decoded data and corresponding indication signal from the NRZI decoding region. Based on the indication signal, the decoded data is bit aligned, and the aligned data is de-padded. The amount of padding is recorded to affect the receiver state machine. The RX conversion and holding area completes the serial-to-parallel conversion based on the padded data and saves the last data byte before outputting it to the UTMI+ parallel output port. The clock module divides the frequency to generate output clock data, and the UTMI+ parallel output port performs timing control based on the output clock data. The UTMI+ parallel output port transmits parallel data to the TX conversion and holding area, converts the parallel data in the TX conversion and holding area into serial data, and holds the next set of data to be converted. The bit stuffing area stuffs bits according to the serial data, and the number of bits stuffed affects the transmission state machine. The NRZI encoding area performs NRZI encoding based on the padded data, and then transmits the NRZI-encoded data to the analog module.

2. The HSIC-type inter-chip interconnection system as described in claim 1, characterized in that, The input clock data is fclk at 240MHz.

3. The HSIC-type chip interconnection system as described in claim 1, characterized in that, The NRZI encoding rule for the NRZI decoding area is to flip 0s and leave 1s unchanged.

4. The HSIC type chip interconnection system as described in claim 3, characterized in that, The bit de-stuffing area includes an Unstuffed counter and a Bit counter. The Unstuffed counter records the number of "0"s used for padding. When 8 padding data entries are accumulated, the receiving state machine will pull utmi_rxvalid_o low for one clock cycle to align the clock. The Unstuffed counter records the number of consecutive "1"s received. When the count reaches 6, the next data is checked. If it is "0", it is considered a padding bit, removed, the Bit counter is cleared, and the Unstuffed counter is incremented by one.

5. The HSIC type chip interconnection system as described in claim 1, characterized in that, The RX conversion and holding area includes a Shift register that performs serial-to-parallel conversion and a Hold register that stores the last data byte.

6. The HSIC type chip interconnection system as described in claim 1, characterized in that, No bit stuffing is performed in the bit stuffing area during high-speed EOP transmission.

7. The HSIC type chip interconnection system as described in claim 1, characterized in that, The input clock data is 60MHz phyclk.

8. The HSIC type chip interconnection system as described in claim 1, characterized in that, The NRZI encoding rule is as follows: when the current bit of the input source code is 0, NRZI encoding will flip the level; when the current bit of the source code is 1, NRZI encoding will maintain the original level state.

Images