Automatic verification method and system for through hole density and connectivity of multi-layer interconnection structure of integrated circuit

Abstract

The invention provides an automatic verification method and system for through hole density and connectivity of a multilayer interconnection structure of an integrated circuit. The method comprises the following steps: inputting data; defining a connection area; defining a through hole coverage area; calculating a missing region; fine filtering is applied; and outputting a final report. The technical problems that in the prior art, an intelligent exemption mechanism is lacked, cross-layer connection inspection is insufficient, and the inspection granularity is rough are solved. According to the method, electrical connectivity judgment, refined graph filtering and an intelligent exemption mechanism are introduced, the false alarm rate is remarkably reduced, cross-layer connection errors can be effectively captured, and therefore the reliability and verification efficiency of chip design are improved.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided design technology for integrated circuits, and specifically relates to an automated verification method and system for the via density and connectivity of multilayer interconnect structures in integrated circuits. It is used to automatically check the via density and connectivity correctness of multilayer metal interconnect structures in chip layouts during the physical verification stage. Background Technology

[0002] As integrated circuit process nodes continue to advance, the number of metal wiring layers inside chips increases, and wiring density rises dramatically. The complexity of interconnect structures has become a key factor affecting chip performance, reliability, and manufacturing yield. Vias, as crucial structures connecting different metal layers, directly determine circuit connectivity depending on their correct and sufficient placement. Insufficient or absent via density can lead to increased contact resistance or even open circuits, while improper via placement can cause short circuits. These problems cannot be repaired after chip manufacturing and will directly lead to chip malfunction.

[0003] While existing commercial design rule checking tools possess basic via presence detection capabilities, they suffer from the following technical challenges when handling complex, high-density design scenarios using advanced processes:

[0004] 1. Lack of intelligent exemption mechanism: Traditional geometric calculation checks cannot effectively distinguish between ordinary interconnect areas and special device areas (such as MIM capacitors, high-voltage devices, etc.). In these special structures, the overlapping metal layers may not be used for signal interconnection, and therefore vias are unnecessary. Existing tools will falsely report "missing vias" in large numbers in such areas, greatly increasing the workload of manual investigation and exemption by designers and reducing verification efficiency.

[0005] 2. Insufficient inspection of cross-layer connections: Modern designs often employ direct connection structures that skip intermediate metal layers to optimize performance and area. Traditional methods typically only inspect vias between adjacent layers. For such cross-layer connections, it is difficult to accurately determine the completeness of via placement, easily overlooking potential open circuit risks caused by the lack of cross-layer vias.

[0006] 3. Coarse-grained inspection: Traditional methods are usually based on simple Boolean operations and lack fine-grained filtering of candidate error regions. It reports all geometrically uncovered areas, including a large number of non-critical "pseudo-errors" that do not affect electrical performance due to graphic edge effects, tiny gaps, etc. These massive amounts of low-priority errors drown out the truly critical defects that affect yield, making it difficult for designers to focus. Summary of the Invention

[0007] The purpose of this invention is to provide an automated verification method and system for the via density and connectivity of multilayer interconnect structures in integrated circuits, in order to solve the technical problems of existing technologies such as lack of intelligent exemption mechanisms, insufficient cross-layer connection checks, and coarse check granularity.

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions.

[0009] An automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits includes:

[0010] Step 1: The data acquisition module acquires the integrated circuit layout data and inputs it into the geometry calculation engine. The layout data includes graphic information of multiple metal layers and one or more via layers.

[0011] Step 2: The geometry calculation engine judges the acquired layout data by expanding the size and combining electrical continuity, and defines the connection area and the via coverage area as the first region and the second region respectively; at the same time, Boolean operations are performed on the first region and the second region to obtain candidate regions for possible missing vias.

[0012] Step 3: The filtering analysis module applies fine-grained filtering to the candidate regions, eliminating false errors and focusing on critical errors.

[0013] Step 4: The report generation module outputs the final error report based on the filtered information.

[0014] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, prior to step two, uses an electrical rule checker to determine the electrical connectivity of the graphic information, thereby assisting the geometric calculation engine in defining the actual connection areas.

[0015] In the aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, the first region is the area where two target metal layers intersect and are electrically connected, as identified by a geometric calculation engine.

[0016] The second region is obtained by expanding the size of the through-hole layer pattern connecting the two target metal layers using a geometric calculation engine.

[0017] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, wherein the amount of size expansion is set based on design rules or process tolerances.

[0018] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits includes fine-grained filtering, which includes width filtering and special structure exemptions.

[0019] The width filtering refers to filtering out graphic fragments in the candidate region whose width is greater than a predetermined threshold.

[0020] The special structure exemption is to exclude areas containing known special device structures from the screening results.

[0021] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits uses a predetermined threshold set as the minimum linewidth or determined according to the semiconductor fabrication process employed, to filter out minute gaps and non-critical areas at the edges of the pattern. The final determination of the threshold needs to be further supplemented based on the requirements of the circuit design. For special device structures, the threshold requirements will be correspondingly increased.

[0022] In the aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, during the special structure exemption step, the filtering analysis module expands the size of the pattern of the special device structure to form an exemption region, which is used to exclude false errors that may be caused by alignment deviations at the structure edges.

[0023] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits includes error reports that identify, after being graphically or textually marked and filtered, areas of actual via missing or insufficient density that require designer intervention.

[0024] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits is characterized by further including: a step of verifying cross-layer connections;

[0025] Step 1: Identify the connection region between two non-adjacent metal layers that are directly connected across at least one intermediate metal layer.

[0026] Step 2: Calculate the merged expansion area of ​​all via layers required to connect two non-adjacent metal layers by identifying via layers, merging via patterns using Boolean merging, and expanding the merged pattern size.

[0027] Step 3: After the data acquisition module reads the layout data, the geometry calculation engine, electrical rule checker, and filter analysis module obtain the size expansion area of ​​the intermediate metal layer pattern during the execution of via-related rules.

[0028] Step 4: Subtract the merged extended area of ​​the via layer and the extended area of ​​the intermediate metal layer from the connection area to accurately identify the area where the via is missing only due to the cross-layer connection, and avoid misjudgment due to the obstruction of the intermediate metal layer.

[0029] The path via layer identification in step two includes identifying all via layers that must be traversed to connect the starting metal layer and the target metal layer based on semiconductor process design rules; wherein the starting metal layer and the target metal layer are non-adjacent metal layers.

[0030] Step two involves Boolean merging of the through-hole patterns, which includes performing a Boolean OR operation on the pattern data of all identified through-hole layers to obtain a merged through-hole pattern region.

[0031] Step two, merging graphic size expansion, includes performing a size expansion operation on the obtained merged hole graphic area according to the expansion amount specified in the process design rules; the size expansion operation is to translate each edge of the merged through-hole graphic area outward along its normal direction by the expansion amount.

[0032] An automated verification system for via density and connectivity of multilayer interconnect structures in integrated circuits includes: a data acquisition module, a geometric calculation engine, an electrical rule checker, a filtering analysis module, and a report generation module.

[0033] The output of the data acquisition module is connected to the geometric calculation engine and the electrical rule checker, respectively. The outputs of the geometric calculation engine and the electrical rule checker are connected to the filtering analysis module, and the output of the filtering analysis module is connected to the report generation module.

[0034] The data acquisition module is used to read and parse the layout data file.

[0035] The geometry operation engine is used to perform Boolean operations and size expansion.

[0036] The electrical rule checker is used to determine the electrical connectivity of the graphic and assist in defining the actual connection area.

[0037] The filtering analysis module is used to perform refined analysis, including width filtering, special structure identification, and exemption.

[0038] The report generation module is used to generate a visual error marker layer, text logs, and summary reports.

[0039] The beneficial effects of this invention are as follows: This invention provides an automated verification method and system for the via density and connectivity of multilayer interconnect structures in integrated circuits, solving the technical problems of existing technologies such as lack of intelligent exemption mechanisms, insufficient cross-layer connection checks, and coarse inspection granularity. By introducing electrical connectivity judgment and width-based fine-grained filtering, this invention effectively filters out minute gaps and non-critical errors at the edges of patterns, significantly reducing the false alarm rate. This allows designers to focus on solving truly critical issues affecting the circuit, achieving high accuracy and low false alarms. Through a built-in special structural exemption mechanism, this invention deeply integrates process knowledge and design intent, automatically avoiding invalid checks in areas where vias are unnecessary, greatly reducing manual intervention, improving verification efficiency, and enhancing the intelligence of verification. The invention's unique cross-layer connection verification logic systematically solves the connection scenarios that skip intermediate layers, which are difficult for traditional tools to handle. It can effectively capture potential connectivity errors in complex designs, improving chip design reliability and expanding the application scenarios. The entire process of this invention can be automatically executed by EDA tools and seamlessly integrated into existing physical verification processes, greatly improving verification speed and consistency, shortening chip design cycles, and increasing the automation level of the verification process. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the overall process of an automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits according to the present invention.

[0041] Figure 2 This is a schematic diagram of the inspection of through-holes in adjacent metal layers in this invention;

[0042] Figure 3 This is a schematic diagram of the inspection of cross-layer connection through holes in this invention;

[0043] Figure 4 This is a schematic diagram of the module composition of an automated verification system for the via density and connectivity of a multilayer interconnect structure of an integrated circuit according to the present invention. Detailed Implementation

[0044] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0045] Example 1: As Figure 4 As shown, this embodiment provides an automated verification system for the via density and connectivity of multilayer interconnect structures in integrated circuits, including: a data acquisition module, a geometric calculation engine, an electrical rule checker, a filtering analysis module, and a report generation module.

[0046] The output of the data acquisition module is connected to the geometric calculation engine and the electrical rule checker, respectively. The outputs of the geometric calculation engine and the electrical rule checker are connected to the filtering analysis module, and the output of the filtering analysis module is connected to the report generation module.

[0047] The data acquisition module is used to read and parse the layout data file.

[0048] The geometry engine is used to perform Boolean operations, size expansion, and graphic clipping.

[0049] The electrical rule checker is used to determine the electrical connectivity of the graphic and assist in defining the actual connection area.

[0050] The filtering analysis module is used to perform refined analysis, including width filtering, special structure identification, and exemption.

[0051] The report generation module is used to generate a visual error marker layer, text logs, and summary reports.

[0052] like Figure 1 As shown, based on the system described above, this embodiment also provides an automated verification method for the via density and connectivity of multilayer interconnect structures in integrated circuits, including:

[0053] Step 1: The data acquisition module acquires the integrated circuit layout data and inputs it into the geometry calculation engine. The layout data includes graphic information of multiple metal layers and one or more via layers.

[0054] Step 2: The geometry calculation engine judges the acquired layout data by expanding the size and combining electrical continuity, and defines the connection area and the via coverage area as the first region and the second region respectively; at the same time, Boolean operations are performed on the first region and the second region to obtain candidate regions for possible missing vias.

[0055] Step 3: The filtering analysis module applies fine-grained filtering to the candidate regions, eliminating false errors and focusing on critical errors.

[0056] Step 4: The report generation module outputs the final error report based on the filtered information.

[0057] By introducing electrical connectivity checks and width-based fine-grained filtering, minor gaps and non-critical errors at the edges of graphics are effectively filtered out, significantly reducing the false alarm rate and allowing designers to focus on solving critical issues that truly affect the circuit.

[0058] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, prior to step two, uses an electrical rule checker to determine the electrical connectivity of the graphic information, thereby assisting the geometric calculation engine in defining the actual connection areas.

[0059] In the aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, the first region is the area where two target metal layers intersect and are electrically connected, as identified by a geometric calculation engine.

[0060] The second region is obtained by expanding the size of the through-hole layer pattern connecting the two target metal layers using a geometric calculation engine.

[0061] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, wherein the amount of size expansion is set based on design rules or process tolerances.

[0062] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits includes fine-grained filtering, which includes width filtering and special structure exemptions.

[0063] The width filtering refers to filtering out graphic fragments in the candidate region whose width is greater than a predetermined threshold.

[0064] The special structure exemption is to exclude areas containing known special device structures from the screening results.

[0065] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits uses a predetermined threshold set as the minimum linewidth or determined according to the semiconductor fabrication process employed, to filter out minute gaps and non-critical areas at the edges of the pattern. The final determination of the threshold needs to be further supplemented based on the requirements of the circuit design. For special device structures, the threshold requirements will be correspondingly increased.

[0066] In the aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, during the special structure exemption step, the filtering analysis module expands the size of the pattern of the special device structure to form an exemption region, which is used to exclude false errors that may be caused by alignment deviations at the structure edges.

[0067] Through a built-in special structural exemption mechanism, it deeply integrates process knowledge and design intent, automatically avoids invalid inspections in areas where through holes are not needed, greatly reduces manual intervention, and improves verification efficiency.

[0068] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits includes error reports that identify, after being graphically or textually marked and filtered, areas of actual via missing or insufficient density that require designer intervention.

[0069] The aforementioned automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits is characterized by further including: a step of verifying cross-layer connections;

[0070] Step 1: Identify the connection region between two non-adjacent metal layers that are directly connected across at least one intermediate metal layer.

[0071] Step 2: Calculate the merged expansion area of ​​all via layers required to connect two non-adjacent metal layers by identifying via layers, merging via patterns using Boolean merging, and expanding the merged pattern size.

[0072] Step 3: After the data acquisition module reads the layout data, the geometry calculation engine, electrical rule checker, and filter analysis module obtain the size expansion area of ​​the intermediate metal layer pattern during the execution of via-related rules.

[0073] Step 4: Subtract the merged extended area of ​​the via layer and the extended area of ​​the intermediate metal layer from the connection area to accurately identify the area where the via is missing only due to the cross-layer connection, and avoid misjudgment due to the obstruction of the intermediate metal layer.

[0074] By using cross-layer connection verification logic, the system systematically solves the connection scenarios that skip intermediate layers, which are difficult for traditional tools to handle. It can effectively capture potential connectivity errors in complex designs and improve the reliability of chip design.

[0075] Example 2: As Figure 2 and Figure 3 As shown, based on Embodiment 1, this embodiment provides an application of the method and system to check the Via1 connectivity between Metal1 and Metal2.

[0076] S1: Data Input: The system reads the layout GDSII file containing layers such as Metal1, Metal2, and Via1.

[0077] S2: Define the connection region: Use the geometry calculation engine and electrical rule checker to find the region where Metal1 and Metal2 intersect and are electrically connected.

[0078] a1 = metal1 AND metal2 INTERACT CONNECTED / / Get the first region a1

[0079] S3: Define via coverage area: Extend the Via1 pattern outward by a certain distance (e.g., 0.03 micrometers) to cover the alignment tolerance between the via and the metal line.

[0080] a2 = SIZE via1 BY 0.03 / / Get the second region a2

[0081] S4: Calculate missing regions: Calculate the regions in a1 that are not covered by a2.

[0082] candidate = a1 NOT a2 / / Get the initial candidate error region candidate

[0083] S5: Applying refined filtration:

[0084] Width filtering: Only retain graphic fragments with a width greater than 0.28 micrometers in the candidate region, and filter out edge burrs.

[0085] wide_candidate = candidate WITH WIDTH > 0.28

[0086] Special structure exemption: The MIM capacitor is excluded from the above results after the pattern is expanded by 0.5 micrometers.

[0087] mim_region = SIZE MIM BY 0.5

[0088] final_errors = wide_candidate NOT mim_region

[0089] S6: Output the final report: The graphs in final_errors represent the final confirmed errors. The report generation module will highlight these areas on the layout view and generate a list report for designers to modify.

[0090] Example of cross-layer connection check (taking Metal1 directly connecting to Metal3 as an example)

[0091] Identify the connected region: conn_area = metal1 AND metal3 INTERACT CONNECTED

[0092] Calculate the required via coverage: Via1 and Via2 need to be checked.

[0093] via_cover = (SIZE via1 BY 0.03) OR (SIZE via2 BY 0.03)

[0094] Calculate the occlusion area of ​​the intermediate layer Metal2: metal2_cover = SIZE metal2 BY 0.05

[0095] Calculate the region where vias are missing purely due to interlayer connections:

[0096] jump_errors = conn_area NOT (via_cover OR metal2_cover)

[0097] Applying similar fine-grained filtering (width filtering, special structure exemptions) to jump_errors yields the final error.

[0098] The entire process can be automated by EDA tools and seamlessly integrated into the existing physical verification process, greatly improving verification speed and consistency and shortening the chip design cycle.

Claims

1. An automated verification method for via density and connectivity of multilayer interconnect structures in integrated circuits, characterized in that, include: Step 1: The data acquisition module acquires integrated circuit layout data and inputs it into the geometry calculation engine. The layout data includes graphic information of multiple metal layers and one or more via layers. Step 2: The geometry calculation engine judges the acquired layout data by expanding the dimensions and combining electrical continuity, and defines the connection area and the via coverage area as the first region and the second region respectively; at the same time, Boolean operations are performed on the first region and the second region to obtain candidate regions for possible missing vias; Step 3: The filtering and analysis module applies fine-grained filtering to the candidate regions, eliminating false errors and focusing on critical errors; Step 4: The report generation module outputs the final error report based on the filtered information.

2. The method according to claim 1, characterized in that, Before step two, the electrical connectivity of the graphic information is determined by an electrical rule checker to assist the geometry calculation engine in defining the actual connection area.

3. The method according to claim 1, characterized in that, The first region is the area where two target metal layers intersect and are electrically connected, as identified by the geometry calculation engine; the second region is the area obtained by expanding the size of the via layer pattern connecting the two target metal layers using the geometry calculation engine.

4. The method according to claim 3, characterized in that, The amount of dimensional expansion is set based on design rules or process tolerances.

5. The method according to claim 1, characterized in that, The refined filtering includes: width filtering and special structure exemption; the width filtering refers to filtering out graphic fragments in the candidate region whose width is greater than a predetermined threshold; the special structure exemption is to exclude the region where a known special device structure is located in the layout from the filtering results.

6. The method according to claim 5, characterized in that, The predetermined threshold is set as the minimum linewidth or depends on the semiconductor manufacturing process used, and is used to filter out small gaps and non-critical areas at the edges of the pattern. The final determination of the threshold needs to be supplemented in combination with the requirements of the circuit design. For special device structures, the threshold requirements will be increased accordingly.

7. The method according to claim 5, characterized in that, In the special structure exemption step, the filtering analysis module expands the size of the graphic of the special device structure to form an exemption area, which is used to exclude false errors that may be caused by alignment deviations at the edge of the structure.

8. The method according to claim 1, characterized in that, The error reports include areas with actual missing or insufficient density vias that are identified graphically or textually marked and filtered, requiring designer intervention.

9. The method according to claim 1, characterized in that, Also includes: Steps for verifying cross-layer connections; Step 1: Identify the connection region between two non-adjacent metal layers that are directly connected across at least one intermediate metal layer; Step 2: Calculate the merged expansion area of ​​all via layers required to connect two non-adjacent metal layers by identifying via layers, Boolean merging of via patterns, and expanding the size of the merged pattern; Step 3: After the data acquisition module reads the layout data, the geometry calculation engine, electrical rule checker, and filter analysis module obtain the size expansion area of ​​the intermediate metal layer pattern during the execution of via-related rules; Step 4: Subtract the merged extended area of ​​the via layer and the extended area of ​​the intermediate metal layer from the connection area to accurately identify the area where the via is missing only due to the cross-layer connection, and avoid misjudgment due to the obstruction of the intermediate metal layer.

10. An automated verification system for via density and connectivity of multilayer interconnect structures in integrated circuits, characterized in that, include: The system includes a data acquisition module, a geometric calculation engine, an electrical rule checker, a filtering analysis module, and a report generation module. The output of the data acquisition module is connected to the geometric calculation engine and the electrical rule checker, respectively. The outputs of the geometric calculation engine and the electrical rule checker are connected to the filtering analysis module, and the output of the filtering analysis module is connected to the report generation module. The data acquisition module is used to read and parse the layout data file; The geometry operation engine is used to perform Boolean operations and size expansion; The electrical rule checker is used to determine the electrical connectivity of the graphic and assist in defining the actual connection area; The filtering and analysis module is used to perform refined analysis, including width filtering, special structure identification, and exemption. The report generation module is used to generate a visual error marker layer, text logs, and summary reports.

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