A method, system and apparatus for designing a sigma-delta modulator based on a 180 nm process

Abstract

This invention belongs to the field of integrated circuit design technology, specifically relating to a design method, system, and device for a Sigma-Delta modulator based on a 180nm process. First, the noise transfer function of the modulator is parameterized to minimize in-band quantization noise power, while simultaneously applying composite constraints on stability and realizability. A covariance matrix strategy is used to optimize under these constraints, obtaining the optimal transfer function and feedforward coefficients. Based on these coefficients, a switched-capacitor circuit is designed. Random mismatch noise is shaped to out-of-band by modulating cyclic selection logic with a high-pass dithering signal. Based on the quantizer output, the inherent bias of each capacitor is estimated and compensated, breaking periodic locking to suppress coherent spurious emissions. This invention achieves a close connection between theoretical design and physical implementation and possesses excellent voltage and temperature robustness.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a design method, system and device for a Sigma-Delta modulator based on a 180nm process. Background Technology

[0002] In modern integrated circuit design, high-precision analog-to-digital converters (ADCs) are core components connecting the physical world and digital signal processing. ADCs, through oversampling and noise shaping techniques, can achieve high intra-bandwidth resolution at moderate clock frequencies and power consumption, making them widely used in low-bandwidth sensing applications. Among various discrete-time topologies, cascaded feedback integrator architectures are ideal for compact, energy-efficient sensor readout circuits because they can reduce the signal swing of internal nodes while maintaining a near-unity-gain signal transfer function, thus relaxing the requirements for operational amplifier margin and linearity.

[0003] Current technologies still face two major technical bottlenecks: First, the comprehensive design of the noise transfer function is extremely difficult, requiring manual configuration of zeros and poles using a toolbox. However, when dealing with high-order loops, there is a strong nonlinear coupling relationship between the zero and pole parameters, making manual tuning difficult to reproduce and highly dependent on experience. Second, component mismatch in switched-capacitor circuits can severely affect the modulator's accuracy, especially when the input signal is close to DC or a slowly varying signal. This nonlinear error can easily be converted into significant harmonic distortion and in-band spurious signals, severely reducing the modulator's signal-to-noise ratio. Summary of the Invention

[0004] The purpose of this invention is to provide a design method, system and device for a Sigma-Delta modulator based on a 180nm process.

[0005] A design method for a Sigma-Delta modulator based on a 180nm process, the modulator mainly consists of a loop filter, a quantizer, and a feedback digital-to-analog converter circuit. The loop filter includes a quantization noise function, a signal transfer function, and a noise transfer function, and includes the following steps:

[0006] S1. Perform zero-pole parameterization on the noise transfer function of the modulator to obtain the parameterized expression of the noise transfer function;

[0007] S2. Quantify the noise power within the signal band by parameterizing the noise transfer function and integrating it, establish the objective function, and apply upper limits of power gain and voltage to the noise transfer function.

[0008] S3. Obtain all candidate solutions that satisfy the objective function. Establish a fitness function based on the objective function, power gain upper limit constraint, and voltage upper limit constraint. Set the search center, search step size, and covariance matrix to search for all candidate solutions. Calculate the fitness function corresponding to the searched candidate solutions and sort them by feasibility according to the fitness function corresponding to the searched candidate solutions. Update the search center, search step size, and covariance matrix based on the sorting results. Repeat the search process based on the updated search center, search step size, and covariance matrix until the convergence condition is met. Use the search center that meets the convergence condition as the pole configuration of the parameterized expression of the noise transfer function to obtain the final noise transfer function.

[0009] S4. In the existing N capacitors, construct a jitter signal in each clock cycle, and update the selection pointer based on the jitter signal;

[0010] Calculate the error proxy signal for each capacitor, estimate the deviation of each capacitor based on the error proxy signal, obtain the deviation estimate, and map the deviation estimate to the selection weight;

[0011] For all capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to their selection weights, thereby realizing the final noise transfer function and completing the modulator design.

[0012] In S4, the selection pointer is updated based on the jitter signal, specifically as follows:

[0013] ,

[0014] ,

[0015] in, For limited decorrelation delay, Where ρ is the sampling time, ρ is the fixed step size, and δ[n] is the jitter signal. To perform a modulo operation on N, This is the binary selection vector generated at sampling time n. This is the initial window function containing M consecutively selected capacitors.

[0016] In S4, the deviation of each capacitor is estimated based on the error proxy signal of each capacitor, and the deviation estimate is obtained:

[0017] ,

[0018] in, Let be the estimated deviation value of the i-th capacitor at sampling time n+1. Let be the estimated deviation value of the i-th capacitor at sampling time n. To learn step length, For error proxy signal, This represents the selection state of the i-th capacitor at sampling time n. The number of capacitors selected for each clock cycle This represents the number of capacitors contained in the array. For small orthogonal perturbations, The sampling time.

[0019] In S4, for all capacitors, the updated selection pointer selects M capacitors to be connected in parallel based on their selection weights. Specifically, an accumulated usage counter is established for each capacitor to record the number of times the capacitor has been selected in the current clock cycle. After the update, the selection pointer moves forward one position every clock cycle. For the currently pointed-to capacitor, if the accumulated usage counter is less than the selection weight, the capacitor is selected; if the accumulated usage counter is greater than or equal to the selection weight, the capacitor is skipped, and the pointer continues to move, repeating until M capacitors are selected and connected in parallel to the circuit to realize the final noise transfer function, thus completing the modulator design.

[0020] The upper limit constraint of voltage in S2 is as follows: Based on the feedforward coefficients of the parameterized expression of the noise transfer function, a state-space model of the output voltage is established. An input signal that enables the voltage of the integrator inside the modulator to reach the maximum amplitude is set. The state-space model is simulated in the time domain to obtain the output voltage, which serves as the upper limit constraint of voltage.

[0021] In S2, the integral over the signal band is parameterized using the noise transfer function, the in-band noise power is quantized, and the objective function is established, specifically:

[0022] ,

[0023] in, Let be the objective function. This represents the normalized cutoff frequency of the signal band. This represents the frequency weighting function. Represents the noise transfer function at frequency The power gain at point x is the decision vector.

[0024] The fitness function in S3 is as follows:

[0025] ,

[0026] in, For the fitness function, Let A1, A2, and A3 be the objective function. = Constraints A1, A2, and A3, i.e., A1, A2, and A3 constraints respectively, represent the upper limit constraint on power gain, There is a solution, and the voltage upper limit constraint applies; otherwise... = , The feedforward coefficients and transformation matrix are the parameterized expressions of the noise transfer function. , To optimize the coefficients, The objective function is denoted as .

[0027] The upper limit constraint on power gain in S2 is as follows:

[0028] ,

[0029] in, This represents the maximum absolute value of the noise transfer function. For amplitude frequency response, It is a preset stability constant.

[0030] A Sigma-Delta modulator design system based on a 180nm process, used to implement the aforementioned Sigma-Delta modulator design method based on a 180nm process, includes:

[0031] The parameterization module performs zero-pole parameterization on the noise transfer function of the modulator to obtain a parameterized expression of the noise transfer function.

[0032] The constraint module quantifies the noise power within the signal band by parameterizing the noise transfer function as an integral, establishes the objective function, and applies upper limits of power gain and voltage to the noise transfer function.

[0033] The noise transfer function solving module obtains all candidate solutions that satisfy the objective function. Based on the objective function, power gain upper limit constraint, and voltage upper limit constraint, it establishes a fitness function, sets the search center, search step size, and covariance matrix, and searches for all candidate solutions. It calculates the fitness function corresponding to the searched candidate solutions and sorts them by feasibility according to the fitness function. Based on the sorting results, it updates the search center, search step size, and covariance matrix. Based on the updated search center, search step size, and covariance matrix, it repeats the search process until the convergence condition is met. The search center that meets the convergence condition is used as the pole configuration of the parameterized expression of the noise transfer function to obtain the final noise transfer function.

[0034] The capacitor selection module generates a jitter signal in each clock cycle from the existing N capacitors and updates the selection pointer based on the jitter signal.

[0035] Calculate the error proxy signal for each capacitor, estimate the deviation of each capacitor based on the error proxy signal, obtain the deviation estimate, and map the deviation estimate to the selection weight;

[0036] For all capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to their selection weights, thereby realizing the final noise transfer function and completing the modulator design.

[0037] A design method and apparatus for a Sigma-Delta modulator based on a 180nm process includes a processor and a memory, wherein the processor executes a computer program stored in the memory to implement a design method for a Sigma-Delta modulator based on a 180nm process.

[0038] Compared with the prior art, the beneficial effects of this application are as follows:

[0039] This invention solves the problems of debugging difficulty in traditional manual tuning of noise transfer function and periodic locking problem of data weighted averaging, and can ultimately improve the actual performance of sigma-delta modulator;

[0040] The actual performance of the sigma-delta modulator of the present invention has a smaller error compared with the theoretical performance during design, which improves the accuracy and precision of the sigma-delta modulator and reduces the difficulty of design and debugging.

[0041] The sigma-delta modulator of the present invention maintains high performance and strong reliability over a wide range of power supply voltage and temperature while suppressing spurious noise.

[0042] The present invention is reasonably designed, and the hardware overhead of the hybrid mismatch elimination scheme is small. It can be implemented without making complex changes to the circuit structure, making it suitable for widespread application in high-performance sensor interfaces and easy to promote and implement. Attached Figure Description

[0043] Figure 1 It is the basic architecture for improving the Sigma-Delta modulator;

[0044] Figure 2 This is a schematic diagram of a dynamic comparator circuit with an RS latch applicable to the present invention.

[0045] Figure 3 This is the output power spectral density diagram from the pre-layout simulation based on the present invention.

[0046] Figure 4 It is a graph showing the changes in SNR and SNDR as a function of the input signal amplitude, as measured according to the present invention;

[0047] Figure 5 This is a performance curve diagram of the present invention under simulated power supply voltage variation;

[0048] Figure 6 The graphs are performance curves of the present invention at different operating temperatures. Detailed Implementation

[0049] Example 1

[0050] To further understand the content of this invention, the invention will be described in detail with reference to the embodiments.

[0051] This invention relates to a design method for a Sigma-Delta modulator based on a 180nm process, referring to... Figure 1 The modulator architecture shown mainly consists of a loop filter and a quantizer. It consists of a feedback digital-to-analog converter (DAC) circuit.

[0052] The loop filter consists of three cascaded integrators, and its output transfer function Y(z) can be expressed as:

[0053] ,

[0054] in, It is the input signal. It is quantization noise. It is a signal transfer function. Let z be the noise transfer function, and z be the complex variable of the transformation. This expression can be derived as:

[0055] ,

[0056] ,

[0057] a1, a2, a3 are as follows: Figure 1 The feedforward coefficients of the Sigma-Delta modulator shown are designed with the core objective of minimizing in-band quantization noise by optimizing the NTF while satisfying stability and realizability constraints.

[0058] S1. Perform zero-pole parameterization on the noise transfer function of the modulator to obtain the parameterized expression of the noise transfer function.

[0059] To implement the NTF design of the modulator, it is first parameterized.

[0060] To ensure third-order noise suppression near DC and maintain STF characteristics, the NTF molecule is fixed at... The three zeros at the denominator determine the pole locations, which in turn determine the stability of the loop. The characteristic equation of the NTF denominator is parameterized as three poles: a pair of complex conjugate poles. and a real pole j is the imaginary unit, that is, satisfying j 2 =-1.

[0061] Define the decision vector as:

[0062] ,

[0063] Among them, and Let be the radius and angle of the complex conjugate poles. Let be the radius of the real pole. .

[0064] According to Z-field theory, the denominator polynomial It can be written as a product in pole form:

[0065] ,

[0066] Furthermore, standards can be obtained. Polynomial form:

[0067] ,

[0068] Among them, the optimization coefficient With decision vector The relationship is an explicit operation:

[0069] ,

[0070] ,

[0071] ,

[0072] The candidate solution NTF can be written as:

[0073] ,

[0074] By comparison The coefficients of the terms are used to establish a matrix equation:

[0075] ,

[0076] Wherein, the transformation matrix Defined as:

[0077] ,

[0078] Establish a coefficient mapping equation in order to map the decision vector generated by the algorithm. Mapped to feedforward coefficients in actual circuits Therefore, it is necessary to solve the system of linear uniformity equations.

[0079] Feasible solution to this system of equations These are the actual parameters required by the circuit. If the system of equations has no solution or the coefficients obtained do not satisfy the causality of the circuit, then it is determined that... Or the decision vector invalid.

[0080] S2. Quantify the noise power within the signal band by parametrically expressing the noise transfer function as an integral, establish the objective function, and impose upper limits of power gain and voltage on the noise transfer function.

[0081] The design objective is to minimize the in-band quantization noise power. The objective function is defined as the integral of the NTF amplitude-frequency response over the signal band, i.e., over a given decision vector. Below, after noise shaping, the total noise energy remaining and falling within the effective signal bandwidth. The core task of optimization is to find the objective function that makes the objective function... Minimized .

[0082] ,

[0083] in, This represents the normalized angular frequency, with units of rad / sample. The normalized cutoff frequency, representing the signal bandwidth, is calculated using the following formula: OSR is the oversampling rate (in this embodiment) This integration interval This represents the effective signal bandwidth; This represents the frequency weighting function, which is typically taken as... , indicating uniform weighting of in-band quantization noise; Represents the noise transfer function at frequency Power gain at that point.

[0084] To limit peak values ​​and maintain stability margin, and to prevent the modulator from entering an unstable state due to excessive out-of-band gain (i.e., quantizer overload), upper limits of power gain and voltage are applied, restricting the upper limit of NTF power gain across the entire frequency band.

[0085] ,

[0086] in, (Infinite norm) represents the maximum absolute value of the function, here referring to the NTF amplitude-frequency response over the entire frequency range. The maximum peak value, This indicates that the algorithm will scan the entire frequency band. To determine the amplitude-frequency response, find the point where the gain is highest. It is a preset stability constant, which typically ranges from 1.5 to 2.0 for a third-order system with 1-bit quantization.

[0087] If the optimized NTF peak value exceeds This set of parameters will be deemed unstable and will be directly removed during the optimization process.

[0088] Even if the noise and stability requirements are met, it is still necessary to ensure that the output voltage of the integrator inside the circuit does not exceed the linear output range of the op-amp; otherwise, clipping distortion will occur. Therefore, the upper limit constraint of the voltage is as follows: Since the feedforward coefficients of the parameterized expression of the noise transfer function are the specific manifestation of the integrator inside the modulator, a state-space model of the output voltage is established based on the feedforward coefficients of the parameterized expression of the noise transfer function. An input signal that enables the voltage of the integrator inside the modulator to reach the maximum amplitude is set, and the state-space model is simulated in the time domain to obtain the output voltage, which serves as the upper limit constraint of the voltage.

[0089] Based on feedforward coefficients Establish the state-space model of the output voltage of the CIFF structure:

[0090] ,

[0091] ,

[0092] in These are state vectors, representing the states of the three integrators in the circuit. Output voltage value at time , It is the input signal sequence, usually a full-scale sine wave signal is used for worst-case testing, and the specific values ​​of the state matrix are:

[0093] ,

[0094] ,

[0095] ,

[0096] ,

[0097] Based on this model, a time-domain simulation is performed, with the following upper voltage constraint applied:

[0098] ,

[0099] That is, during the simulation period Inside, check the output status of all integrators. The modulus value is set to ensure that its maximum value does not exceed the voltage margin of the circuit design. If the value exceeds a certain threshold, it indicates that the set of coefficients cannot achieve linear operation in the physical circuit, and the determination is made accordingly. invalid.

[0100] S3. Obtain all candidate solutions that satisfy the objective function. Establish a fitness function based on the objective function, power gain upper limit constraint, and voltage upper limit constraint. Set the search center, search step size, and covariance matrix to search for all candidate solutions. Calculate the fitness function corresponding to the searched candidate solutions and rank them according to their feasibility. Update the search center, search step size, and covariance matrix based on the ranking results. Repeat the search process based on the updated search center, search step size, and covariance matrix until the convergence condition is met. Use the search center that meets the convergence condition as the pole configuration of the parameterized expression of the noise transfer function to obtain the final noise transfer function.

[0101] First, we need to clarify that we are looking for the optimal placement of the poles of the noise transfer function, i.e., the decision vector. Under this pole configuration, the modulator can minimize the in-band quantization noise power / objective function while satisfying all hard physical constraints, including the upper limit of power gain and the upper limit of voltage.

[0102] The optimal solution is hidden in a high-dimensional, nonlinear parameter space with complex constraints. There is no simple analytical relationship between the pole parameters (r1, θ1, r0) and the objective function; rather, there is a strong nonlinear coupling between them. Adjusting the complex pole radius r1 affects the peak gain of the NTF, thus impacting stability. Adjusting the complex pole angle θ1 affects the depth and bandwidth of noise shaping. The real pole radius r0, coupled with the former two, collectively determines the overall shape of the NTF. Changing one parameter will cause the optimal values ​​of the others to drift. Furthermore, the constraint boundaries are not regular geometric shapes.

[0103] This application proposes maintaining a multivariate normal distribution N(m,σ). 2 C) As a sampler. Obtain all candidate solutions that satisfy the objective function. This distribution is an ellipsoid in the parameter space. Set the search center m, search step size σ, and covariance matrix C of the multivariate normal distribution to search for all candidate solutions. The mean of the distribution represents the current search center, which is currently considered the most likely location to contain the optimal solution; The global step size controls the search range; the covariance matrix is ​​the overall size of the ellipsoid. The symmetric positive definite property determines the shape and orientation of the ellipsoid for the search distribution. In each iteration, a batch of candidate solutions is sampled from this ellipsoid, evaluated, and then the center, shape, and orientation of the ellipsoid are updated using the best-performing solutions.

[0104] Based on this distribution, generate The decision vector, the th decision vector Decision vectors The formula for generating it is:

[0105] ,

[0106] in This indicates that the mean is 0 and the covariance is... A random vector.

[0107] Mathematically, this mechanism is achieved through anisotropic evolutionary pathways. Implementation. Each update:

[0108] ,

[0109] ;

[0110] Among them, the updated mean , The preset weighting coefficients satisfy... and Secondly, update the covariance matrix. This step utilizes evolutionary path information to improve the algorithm's convergence speed under ill-conditioned conditions. The normalization step size is defined; and These are rank 1 update and rank update respectively. Updated learning rate, here To effectively select quality, This is the time constant of the path.

[0111] The intuitive meaning of this formula is that, Preserve historical shapes to prevent abrupt changes in the search direction. Lengthen the ellipsoid according to the evolutionary path to enhance the continuously favorable direction. Adjust the shape of the ellipsoid based on the distribution of the current best samples.

[0112] The result is that no matter how the parameter space is distorted, the search ellipsoid can always be rotated, stretched, or compressed, and it learns how to search in the face of strongly correlated parameters.

[0113] Having the right direction is one thing, but controlling the size of each step is another. Controlling the step size σ occurs through another evolutionary path. accomplish:

[0114] ,

[0115] ,

[0116] If evolutionary path The length is greater than the expected length of the random walk. This indicates that the search direction is consistent, and the step size should be increased to accelerate the process; conversely, the step size should be decreased if the direction is divergent. This mechanism prevents stagnation in a wide region and also prevents skipping over areas near the optimal solution due to an excessively large step size.

[0117] Now, we introduce the problem of ensuring that sampling points fall within the feasible region during the search process. Our solution is to prioritize feasibility. Define the fitness function:

[0118] ,

[0119] in, For the fitness function, Let A1, A2, and A3 be the objective function. = Constraints A1, A2, and A3, i.e., A1, A2, and A3 constraints respectively, represent the upper limit constraint on power gain, There is a solution, and the voltage upper limit constraint applies; otherwise... = , The feedforward coefficients and transformation matrix are the parameterized expressions of the noise transfer function. , To optimize the coefficients, The objective function is denoted as .

[0120] according to Sort and keep the best A feasible decision vector Its weight is , This means that if this generation of sampling contains both feasible and infeasible solutions, all feasible solutions are ranked first, and all infeasible solutions are ranked last, updating the distribution (m, σ). 2 In case C), only the first feasible solution is used, and infeasible solutions are completely ignored.

[0121] If no feasible solution is found in this generation of sampling, it means the current search region is completely infeasible. The search direction needs to be adjusted based on the distribution information of infeasible solutions. The final effect is that the search ellipsoid is forcibly pulled towards the feasible region while avoiding the infeasible region. Over time, the entire distribution N(m, σ) 2 C) It will be attracted to the feasible region.

[0122] In summary, the entire convergence process is as follows: An initial center, initial step size, and covariance matrix are set. At this point, the search ellipsoid is a large sphere covering the entire parameter space. Candidate solutions are sampled from this large sphere. Due to the large step size, the sampling points are scattered throughout the parameter space. After feasibility-based prioritization, solutions falling within the feasible region are selected for updating the distribution.

[0123] At this point, the evolutionary path begins to accumulate information, and the evolutionary path will point towards the feasible region. The covariance matrix begins to stretch along this direction, and the search ellipsoid changes from a sphere to an elongated ellipsoid, extending along the feasible region. At the same time, the step size may remain large or increase slightly, quickly covering the feasible region.

[0124] As the search iterates, the evolutionary path becomes increasingly clear, pointing in a dominant direction. The covariance matrix is ​​stretched sufficiently, and the shape of the search ellipsoid closely matches the geometry of the feasible region. At this point, as the length of the evolutionary path begins to shorten, the step size automatically decreases.

[0125] The search ellipsoid gradually shrinks, the center moves slowly, and eventually stabilizes near a point. The eigenvalues ​​of the covariance matrix become very small, indicating that sampling only occurs in a very small region, and the step size σ also decreases to below the threshold.

[0126] At this point, check the convergence condition:

[0127] or ,

[0128] If the improvement in the optimal fitness over several consecutive generations is less than a preset threshold, then convergence is determined, and the current center is output as the optimal solution.

[0129] Furthermore, to enhance global search capabilities, population size... Set with dimension Logarithmic functions:

[0130] ,

[0131] If the search does not converge to a satisfactory level, the population size λ is increased exponentially, and the search is restarted. A larger population means stronger global exploration capabilities, allowing the search to escape possible local optima and find better solutions.

[0132] The S3 step of this application exhibits excellent global convergence properties. Under appropriate conditions, it can be proven to converge to the global optimum of the problem. Premature convergence is avoided by using adaptive step size and covariance matrix to maintain exploratory capability when needed. Covariance matrix learning can decouple strongly correlated parameters, transforming ill-conditioned problems into isotropic ones. The evolutionary path accumulates directional information from multiple generations, making it more robust than simply relying on current-generation samples.

[0133] Through zero-pole optimization, the modulator's transfer function is finally determined: the in-band signal transfer function is flat, meaning it is flat within the signal band. The amplitude-frequency response within the range approaches unity gain; on the other hand, the noise transfer function, by imposing constraints during the optimization process, achieves a maximum peak value at all frequencies. Strictly limited to the preset maximum allowable gain The following range ensures that the third-order loop does not experience overload oscillation under full-amplitude input, while minimizing in-band noise and achieving a higher effective bit count.

[0134] S4. In the existing N capacitors, construct a jitter signal in each clock cycle, and update the selection pointer based on the jitter signal;

[0135] The error proxy signal for each capacitor is calculated based on the quantizer and narrowband low-pass filter. Based on the error proxy signal for each capacitor, the deviation of each capacitor is estimated to obtain the deviation estimate. The deviation estimate is then mapped to the selection weight.

[0136] For all capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to their selection weights, thereby realizing the final noise transfer function and completing the modulator design.

[0137] Specifically, in the circuit-level implementation of the improved modulator, the integration and addition coefficients are determined by the ratio between capacitors. In this improved modulator, the thermal noise of the sampling switch and the operational amplifier in the first-stage integrator reaches the output directly without attenuation, just like the input signal, thus limiting the resolution of the converted signal. The thermal noise of the sampling capacitor in the first-stage integrator is the bottleneck of system accuracy; its power spectral density can be derived as follows:

[0138] ,

[0139] in Boltzmann's constant, Absolute temperature For sampling capacitance value, This represents the noise factor of the operational amplifier; and It is a two-phase non-overlapping clock, which controls switches F1 and F2 respectively. Phase, the integrator samples, in Phase integration is performed by the integrator. To suppress the thermal noise of the first-stage integrator, a 5.6pF sampling capacitor is used in this embodiment.

[0140] The voltage difference between the subtractor and the reference level is amplified to a digital logic level, typically one of the supply voltages. or ). Figure 3 The diagram shows a dynamic comparator whose output is controlled by a clock signal. When the input clock (CLK) is low, the output is reset to high. When the input clock (CLK) is high, the differential pair composed of N1 and N2 adjusts the output to the two input voltages. and After comparison and latching, the output level is pulled up to the positive power supply voltage according to the input level. or negative power supply voltage ).

[0141] To suppress non-ideal effects in circuit implementation, especially capacitor mismatch, this invention employs a hybrid mismatch elimination scheme, which includes two working layers: a rotation layer and a background correlation layer.

[0142] The CIFF coefficients and DAC in the mismatch model are implemented using a capacitor array. Assume a certain coefficient has N values... The capacitors are connected in parallel, and the relative error of each capacitor is... Let the first... i-th The actual value of each capacitor is:

[0143] ,

[0144] ,

[0145] At sampling time n A binary selection vector choose M One capacitor ( The effective coefficient value generated at this time is , This refers to the instantaneous error term introduced by capacitor mismatch, which directly translates into nonlinear distortion of the circuit.

[0146] ,

[0147] in To eliminate random mismatches, dynamic rotation is used to shift the error spectrum to a higher frequency.

[0148] Define a numeric index pointer k[n] to control the starting position of the selection window, and its update rule includes a high-pass dithering term. :

[0149] ,

[0150] ,

[0151] in, For limited decorrelation delay, The sampling time is ρ, where ρ is a fixed step size. To perform a modulo operation on N, This is the binary selection vector generated at sampling time n. Let Π(⋅) be the initial window function containing M consecutive selected capacitors, and let Π(⋅) be the cyclic shift operation. The jitter signal δ[n] is generated by a first-order digital ΔΣ modulator and is a zero-mean jitter signal with high-pass spectrum characteristics.

[0152] ,

[0153] in Indicates quantification, It is white noise excitation. The leakage factor (pole coefficient) of the filter is used to adjust the shape of the jitter spectrum. W(z) represents the transfer function of the noise shaping filter. After this operation, the residual mismatch noise power in the band is reduced. It is significantly attenuated, and its value is inversely proportional to the cube of the oversampling rate:

[0154] ,

[0155] in, It is the variance of capacitor mismatch. These are CIFF feedforward coefficients. This characterizes the theoretical minimum limit achievable for broadband noise floor caused by random mismatch under ideal first-order shaping. It demonstrates that statistical random mismatch noise power can be suppressed to below the system's allowable noise floor level simply by using a rotation layer. Although this significantly reduces the contribution of random mismatch, short-period locking can still occur under near-DC excitation, resulting in discrete in-band spectral lines. The background layer addresses this problem.

[0156] The background correlation layer extracts in-band error information from the quantizer output, breaks the periodic selective lock caused by a specific input signal, and thus suppresses coherent spurious noise.

[0157] While rotating layers can effectively handle random mismatches, they can still produce periodic locking problems under certain inputs, leading to coherent spurious noise. The role of the background correlation layer is to break this periodicity through a slow adaptive feedback loop, and its working principle is as follows:

[0158] Inject a very small, orthogonal perturbation To each capacitor i In the selection preference, a 1-bit quantizer is used for output. This forms a band-limited error proxy:

[0159] ,

[0160] in, It is a narrowband low-pass filter. kIt is a finite decorrelation delay, bias estimation, using the Sign-LMS algorithm to iteratively estimate the inherent bias of each capacitor. In order to detect a specific capacitance The contribution to the error is achieved by injecting small orthogonal perturbations into the selection logic. The deviation estimate is obtained as follows:

[0161] ,

[0162] in, Let be the estimated deviation value of the i-th capacitor at sampling time n+1. Let be the estimated deviation value of the i-th capacitor at sampling time n. To learn step length, For error proxy signal, This represents the selection state of the i-th capacitor at sampling time n. The number of capacitors selected for each clock cycle This represents the number of capacitors contained in the array. For small orthogonal perturbations, The sampling time.

[0163] If selected capacitor At that time, error If the tendency is to increase, the update term will be negative, leading to a negative estimated bias value. If the value of capacitor i increases, subsequent algorithms will reduce its weight. Conversely, if the error tends to decrease when capacitor i is selected, the update term will be positive, and the algorithm will increase its weight. If the selection of capacitor i is unrelated to the change in error, the statistical average of the update term will be zero. It remains unchanged.

[0164] Finally, the estimated bias is transformed into selection weights using the Softmax function. Used to correct selection logic and break periodicity:

[0165] ,

[0166] An accumulated usage counter is established for each capacitor to record the number of times the capacitor has been selected in the current clock cycle. After updating, the selection pointer moves forward one position every clock cycle. For the currently pointed-to capacitor, if the accumulated usage counter is less than the selection weight, the capacitor is selected; if the accumulated usage counter is greater than or equal to the selection weight, the capacitor is skipped, and the pointer continues to move. This process is repeated until M capacitors are selected and connected in parallel to the circuit to realize the final noise transfer function, thus completing the modulator design.

[0167] The pointer cycles forward, prioritizing capacitors whose instantaneous quotas have not yet been met. Define a digital pointer that cycles between 0 and N-1. Each clock cycle, the pointer scans forward, and for each capacitor scanned, checks if its current accumulated usage is below its target quota. If yes, the capacitor is selected; otherwise, if the capacitor has exceeded its usage limit, it is skipped, and the pointer continues searching for the next one. This mechanism breaks the fixed periodic selection pattern on a macroscopic level, forcing the frequency of capacitor use to conform to the correction requirements of its physical deviation.

[0168] This invention specifically applies the above-mentioned hybrid mismatch elimination scheme to the implementation of feedforward coefficients. In the feedforward capacitor array and the feedback capacitor array of the 1-bit DAC, it combines out-of-band shaping rotation with low-rate background correlation to suppress random and coherent mismatch, maintain the in-band noise floor, and prevent periodic lock-in.

[0169] A Sigma-Delta modulator design system based on a 180nm process, used to implement the aforementioned Sigma-Delta modulator design method based on a 180nm process, includes:

[0170] The parameterization module performs zero-pole parameterization on the noise transfer function of the modulator to obtain a parameterized expression of the noise transfer function.

[0171] The constraint module quantifies the noise power within the signal band by parameterizing the noise transfer function as an integral, establishes the objective function, and applies upper limits of power gain and voltage to the noise transfer function.

[0172] The noise transfer function solving module obtains all candidate solutions that satisfy the objective function. Based on the objective function, power gain upper limit constraint, and voltage upper limit constraint, it establishes a fitness function, sets the search center, search step size, and covariance matrix, and searches for all candidate solutions. It calculates the fitness function corresponding to the searched candidate solutions and sorts them by feasibility according to the fitness function. Based on the sorting results, it updates the search center, search step size, and covariance matrix. Based on the updated search center, search step size, and covariance matrix, it repeats the search process until the convergence condition is met. The search center that meets the convergence condition is used as the pole configuration of the parameterized expression of the noise transfer function to obtain the final noise transfer function.

[0173] The capacitor selection module generates a jitter signal in each clock cycle from the existing N capacitors and updates the selection pointer based on the jitter signal.

[0174] Calculate the error proxy signal for each capacitor, estimate the deviation of each capacitor based on the error proxy signal, obtain the deviation estimate, and map the deviation estimate to the selection weight;

[0175] For all capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to their selection weights, thereby realizing the final noise transfer function and completing the modulator design.

[0176] A design method and apparatus for a Sigma-Delta modulator based on a 180nm process includes a processor and a memory, wherein the processor executes a computer program stored in the memory to implement a design method for a Sigma-Delta modulator based on a 180nm process.

[0177] Example 2

[0178] This embodiment illustrates the performance verification results of S4 in Embodiment 1.

[0179] This embodiment performs pre-layout simulation of the designed circuit under the conditions of a sampling frequency of 32kHz and an oversampling rate (OSR) of 128. (See attached document.) Figure 3 , Figure 3 The output power spectral density is shown when a 27Hz sine wave signal is input. The third-order noise shaping characteristics are clearly visible in the figure; in-band noise is effectively suppressed, and there is no significant harmonic distortion. (See also...) Figure 4 , Figure 4 The measured SNR and SNDR curves as a function of the input signal amplitude are shown. The peak SNR and SNDR reached 99.9 dB and 94.0 dB, respectively, equivalent to 15.3 effective bits, proving that the invention achieves extremely high conversion accuracy. To verify the robustness of the design, simulations were performed under different power supply voltages and temperatures. (See reference...) Figure 5 When the simulated power supply voltage undergoes a ±5% change, the SNDR fluctuation is less than 0.5dB. (See [reference needed]) Figure 6 SNDR also maintains high stability over a wide temperature range of -40°C to 100°C, with fluctuations of less than 1.0 dB.

Claims

1. A design method for a Sigma-Delta modulator based on a 180nm process, wherein the modulator mainly consists of a loop filter, a quantizer, and a feedback digital-to-analog converter circuit, and the loop filter includes quantization noise, signal propagation, and noise propagation components, characterized in that... Includes the following steps: S1. Perform zero-pole parameterization on the noise transfer function of the modulator to obtain the parameterized expression of the noise transfer function; S2. Quantify the noise power within the signal band by parameterizing the noise transfer function and integrating it, establish the objective function, and apply upper limits of power gain and voltage to the noise transfer function. S3. Obtain all candidate solutions that satisfy the objective function. Establish a fitness function based on the objective function, power gain upper limit constraint, and voltage upper limit constraint. Set the search center, search step size, and covariance matrix to search for all candidate solutions. Calculate the fitness function corresponding to the searched candidate solutions and sort them by feasibility according to the fitness function corresponding to the searched candidate solutions. Update the search center, search step size, and covariance matrix based on the sorting results. Repeat the search process based on the updated search center, search step size, and covariance matrix until the convergence condition is met. Use the search center that meets the convergence condition as the pole configuration of the parameterized expression of the noise transfer function to obtain the final noise transfer function. S4. In the existing N capacitors, construct a jitter signal in each clock cycle, and update the selection pointer based on the jitter signal; Calculate the error proxy signal for each capacitor, estimate the deviation of each capacitor based on the error proxy signal, obtain the deviation estimate, and map the deviation estimate to the selection weight; For all capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to their selection weights, thereby realizing the final noise transfer function and completing the modulator design.

2. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, In S4, the selection pointer is updated based on the jitter signal, specifically as follows: ， ， in, For limited decorrelation delay, Where ρ is the sampling time, ρ is the fixed step size, and δ[n] is the jitter signal. To perform a modulo operation on N, This is the binary selection vector generated at sampling time n. This is the initial window function containing M consecutively selected capacitors.

3. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, In S4, the deviation of each capacitor is estimated based on the error proxy signal of each capacitor, and the deviation estimate is obtained: ， in, Let be the estimated deviation value of the i-th capacitor at sampling time n+1. Let be the estimated deviation value of the i-th capacitor at sampling time n. To learn step length, For error proxy signal, This represents the selection state of the i-th capacitor at sampling time n. The number of capacitors selected for each clock cycle This represents the number of capacitors contained in the array. For small orthogonal perturbations, The sampling time.

4. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, In S4, for all capacitors, the updated selection pointer selects M capacitors to be connected in parallel based on their selection weights. Specifically, an accumulated usage counter is established for each capacitor to record the number of times the capacitor has been selected in the current clock cycle. After the update, the selection pointer moves forward one position every clock cycle. For the currently pointed-to capacitor, if the accumulated usage counter is less than the selection weight, the capacitor is selected; if the accumulated usage counter is greater than or equal to the selection weight, the capacitor is skipped, and the pointer continues to move, repeating until M capacitors are selected and connected in parallel to the circuit to realize the final noise transfer function, thus completing the modulator design.

5. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, The upper limit constraint of voltage in S2 is as follows: Based on the feedforward coefficients of the parameterized expression of the noise transfer function, a state-space model of the output voltage is established. An input signal that enables the voltage of the integrator inside the modulator to reach the maximum amplitude is set. The state-space model is simulated in the time domain to obtain the output voltage, which serves as the upper limit constraint of voltage.

6. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, In S2, the integral over the signal band is parameterized using the noise transfer function, the in-band noise power is quantized, and the objective function is established, specifically: ， in, Let be the objective function. This represents the normalized cutoff frequency of the signal band. This represents the frequency weighting function. Represents the noise transfer function at frequency The power gain at point x is the decision vector.

7. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, The fitness function in S3 is as follows: ， in, For the fitness function, Let A1, A2, and A3 be the objective function. = Constraints A1, A2, and A3, i.e., A1, A2, and A3 constraints respectively, represent the upper limit constraint on power gain, There is a solution, and the voltage upper limit constraint applies; otherwise... = , The feedforward coefficients and transformation matrix are the parameterized expressions of the noise transfer function. , To optimize the coefficients, The objective function is denoted as .

8. The design method for a Sigma-Delta modulator based on a 180nm process according to claim 1, characterized in that, The upper limit constraint on power gain in S2 is as follows: ， in, This represents the maximum absolute value of the noise transfer function. For amplitude frequency response, It is a preset stability constant.

9. A Sigma-Delta modulator design system based on a 180nm process, used to implement the Sigma-Delta modulator design method based on a 180nm process as described in any one of claims 1-8, characterized in that, include: The parameterization module performs zero-pole parameterization on the noise transfer function of the modulator to obtain a parameterized expression of the noise transfer function. The constraint module quantifies the noise power within the signal band by parameterizing the noise transfer function as an integral, establishes the objective function, and applies upper limits of power gain and voltage to the noise transfer function. The noise transfer function solving module obtains all candidate solutions that satisfy the objective function. Based on the objective function, power gain upper limit constraint, and voltage upper limit constraint, it establishes a fitness function, sets the search center, search step size, and covariance matrix, and searches for all candidate solutions. It calculates the fitness function corresponding to the searched candidate solutions and sorts them by feasibility according to the fitness function. Based on the sorting results, it updates the search center, search step size, and covariance matrix. Based on the updated search center, search step size, and covariance matrix, it repeats the search process until the convergence condition is met. The search center that meets the convergence condition is used as the pole configuration of the parameterized expression of the noise transfer function to obtain the final noise transfer function. The capacitor selection module generates a jitter signal in each clock cycle from the existing N capacitors and updates the selection pointer based on the jitter signal. Calculate the error proxy signal for each capacitor, estimate the deviation of each capacitor based on the error proxy signal, obtain the deviation estimate, and map the deviation estimate to the selection weight; For all capacitors, the updated selection pointer selects M capacitors to be connected in parallel according to their selection weights, thereby realizing the final noise transfer function and completing the modulator design.

10. A design method and apparatus for a Sigma-Delta modulator based on a 180nm process, characterized in that, It includes a processor and a memory, wherein the processor executes a computer program stored in the memory to implement a Sigma-Delta modulator design method based on a 180nm process as described in any one of claims 1-8.

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