Netlist extraction method and device, equipment and medium

Abstract

The invention relates to the technical field of chips, and discloses a netlist extraction method and device, equipment and a medium, and the method comprises the steps: determining an overall contour boundary adaptive to a chip based on the projection of a plurality of crystal grains in the chip on a preset shared plane; wherein the plurality of crystal grains are stacked in a direction perpendicular to the preset sharing plane; determining a reference partition of the overall contour boundary, and dividing a density partition of the overall contour boundary according to density information of each crystal grain in the reference partition; aiming at each density partition obtained by division, extracting a unit netlist of each crystal grain in the density partition; and based on the extracted unit netlists, combining the unit netlists to obtain a chip netlist of the chip. According to the technical scheme provided by the invention, netlist extraction can be efficiently and accurately carried out, and coordination and connectivity between different crystal grains are ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a netlist extraction method, apparatus, device and medium. Background Technology

[0002] In 3DIC (three-dimensional integrated circuit) design, the challenges of netlist extraction are mainly reflected in two aspects: First, because the top die and bottom die use different local coordinate systems, their netlists cannot be effectively connected; second, the traditional two-dimensional partitioning method is no longer applicable in vertical stacking designs, the partitioning rules are inconsistent, the partition size and number are inconsistent, and the netlist density distribution after stacking is uneven, which affects the accuracy of the entire netlist extraction.

[0003] Therefore, how to efficiently and accurately extract netlists in 3DIC design and ensure the coordination and connectivity between different chips is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a netlist extraction method, apparatus, device, and medium, which achieves the technical effect of efficient and accurate netlist extraction, ensuring the coordination and connectivity between different grains.

[0005] To achieve the above objectives, the main technical solution adopted in this application includes a netlist extraction method, the method comprising: The overall contour boundary of the chip is determined based on the projection of multiple dies within the chip onto a preset shared plane; wherein the multiple dies are stacked in a direction perpendicular to the preset shared plane. Determine the reference partition of the overall contour boundary, and divide the density partition of the overall contour boundary according to the density information of each grain within the reference partition; For each density partition obtained, the cell netlist of each grain in that density partition is extracted. Based on the extracted unit netlists, the chip netlist of the chip is obtained by merging them.

[0006] This application provides a netlist extraction method that determines the overall chip outline boundary based on the projection of multiple dies onto a preset shared plane, ensuring physical layout coordination between different dies. Next, by dividing the chip into baseline and density partitions and combining die density information, the partitioning method is optimized to improve computational efficiency and avoid design bottlenecks caused by density unevenness. This partitioning method helps improve the stability and efficiency of EDA tools when processing different regions. The netlists of the dies are extracted according to the density partitions and merged into a unified chip netlist, ensuring the accuracy of electrical connections and cross-layer coordination, avoiding signal interference and delay issues, while reducing computation and resource consumption. Overall, this method can improve the coordination, connectivity, and computational efficiency of 3DIC designs, thereby effectively optimizing resource utilization. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0008] Figure 1 This application provides schematic diagrams of different grain extraction techniques in the prior art. Figure 2 A flowchart of a netlist extraction method provided in this application embodiment; Figure 3 A schematic diagram of density partitioning provided in an embodiment of this application; Figure 4 A schematic diagram illustrating the creation of associated nodes provided in an embodiment of this application; Figure 5 A schematic diagram illustrating the determination of the overall contour boundary provided in an embodiment of this application; Figure 6 This is a top-view diagram illustrating the relationships in an embodiment of this application. Figure 7 A schematic diagram of density partitioning in step S20 provided in an embodiment of this application; Figure 8 This application provides schematic diagrams of embodiments and scenarios. Figure 9 A block diagram of a chip netlist extraction device provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0010] Netlist extraction is a crucial step in chip back-end design, its core task being to transform complex physical metal wiring into a network of resistors and capacitors. This process simplifies the originally lengthy and complex metal wiring into nodes and connections in the circuit diagram through abstract modeling. In this way, the electrical characteristics of the physical layer can be analyzed at the logic layer, providing important foundational data for subsequent design steps such as timing simulation and functional verification. With the development of integrated circuit technology, especially in multi-layer 3DIC design, the size of netlists continues to expand, and extraction technology faces enormous computational and storage pressures.

[0011] To cope with the ever-growing size of netlists, EDA tools commonly employ a partitioned parallel approach for netlist extraction. This involves dividing the chip's physical area into multiple smaller partitions, extracting the netlist from each partition independently, and then merging the boundary nodes to accelerate the entire extraction process. While this method works well in 2D scenarios, its complexity increases significantly in 3D dicing design. In 3D dicing, multiple dies are stacked vertically, making traditional two-dimensional partitioning methods unsuitable; vertical coupling and coordination must be considered.

[0012] like Figure 1As shown, in 3DIC design, since both the top die and bottom die use their own local coordinate systems, and these coordinate systems are only rigidly offset through stacking alignment without coordinate system normalization in the EDA data model, their netlists cannot be effectively connected. Secondly, the partitioning rules of the top and bottom dies may be inconsistent. They each perform 2D uniform mesh partitioning (perhaps 4×4 or 5×5, etc.), meaning that traditional 2D partitioning thinking is directly applied to 3D, directly causing inconsistencies in partition size and number. For example, the red area in the figure represents the projection outline of the top die onto the bottom die. This red area spans three vertical mesh boundaries of the bottom die and three horizontal mesh boundaries, resulting in four partitions in the top die corresponding to six partitions in the bottom die, leading to a one-to-many phenomenon. Furthermore, even if the partition density within each die is uniform, the density distribution of the stacked netlist in the vertical direction may be uneven. For example, in the figure, the mesh density outside the top die projection area (several meshes to the lower left of the bottom) is significantly lower, while the density in the projection overlap area is higher. This results in uneven density after merging meshes across dies.

[0013] Therefore, how to efficiently and accurately extract netlists in 3DIC design and ensure the coordination and connectivity between different chips is a technical problem that urgently needs to be solved.

[0014] To address the aforementioned technical problems, an embodiment of the netlist extraction method is provided according to the present application. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0015] This embodiment provides a netlist extraction method. Figure 2 A flowchart of a netlist extraction method provided in this application embodiment is shown below. Figure 2 As shown, the process includes the following steps: Step S1: Based on the projection of multiple dies within the chip onto a preset shared plane, determine the overall contour boundary adapted to the chip; wherein, the multiple dies are stacked in a direction perpendicular to the preset shared plane.

[0016] Specifically, each die is projected onto the same pre-defined shared plane. This process transforms 3D projection into 2D projection, simplifying the complexity of spatial layout and providing a foundation for subsequent coordinate normalization. Since each die may have different sizes and shapes in space, 2D projection ensures that the footprint of each die reflects its physical size and position. When normalizing the projection, any location within the pre-defined shared plane is chosen as the global origin, and a known offset is applied to unify the coordinate system. This process ensures that the coordinate system of all dies is consistent, thus avoiding calculation errors and layout conflicts caused by coordinate system differences. By obtaining the extreme coordinates (minimum and maximum values) of all projections, the overall chip outline boundary can be determined. This overall outline boundary is the physical outline of the chip design and fully considers the actual footprint of each die. Determining the overall outline boundary provides a clear and unified reference framework for subsequent density partitioning and baseline region division.

[0017] Step S3: Determine the reference partition of the overall contour boundary, and divide the density partition of the overall contour boundary according to the density information of each grain in the reference partition.

[0018] Specifically, after determining the overall contour boundary, the region is first partitioned into reference zones according to a preset mesh granularity. A reference zone can be understood as a coordinate system that provides a uniform density scale for each grain; that is, the dimensions of each reference zone are consistent. By dividing these meshes, a foundation can be effectively provided for subsequent density partitioning, ensuring the physical and logical consistency of each zone.

[0019] Furthermore, based on the projection of the die onto a preset shared plane, it is mapped to a baseline partition, and density partitioning is performed according to the number, distribution, and location of patterns within each baseline partition. By setting a pattern number threshold, the number of patterns in each density partition is ensured to be as balanced as possible, reducing the occurrence of density hotspots. Density partitioning can effectively eliminate design problems caused by overly concentrated or dispersed dies. Reasonable density partitioning can significantly reduce performance bottlenecks caused by excessive memory peaks when using EDA backend tools for design verification. By optimizing density partitioning, ensuring that the difference in the number of patterns in each partition is small, the computational bottleneck of EDA tools when dealing with uneven density is avoided, improving the processing efficiency and verification speed of the tools.

[0020] Step S5: For each density partition obtained, extract the cell netlist of each grain within that density partition.

[0021] Specifically, the cell netlist can also be called a partitioned netlist or a density-partitioned netlist. After density partitioning, the cell netlist for each die is extracted independently. The cell netlist contains the die's input ports, output ports, connections, logic elements, and electrical connections with other cells. This ensures that the electrical behavior of each cell is completely and independently represented, providing fundamental data for overall chip analysis. While maintaining independence, the extracted cell netlists are combined with the connections between different dies to form a complete chip netlist. The chip netlist integrates the connections and electrical characteristics of all dies, reflecting the overall electrical architecture of the chip. By using appropriate netlist extraction and merging methods, wasted computational resources can be reduced. Parallel extraction of cell netlists throughout the design process can effectively optimize efficiency.

[0022] Step S7: Based on the extracted cell netlists, merge them to obtain the chip netlist of the chip.

[0023] Specifically, after the parallel extraction of each die by density partitioning is completed, all cell netlists within the same partition are merged. Then, the overlapping area is scanned at the boundary layer of adjacent dies: for each pair of patterns with overlapping areas, an associated node located at the geometric center of the pattern is added and an interconnected electrical connection is established, thereby mapping the originally independent 3D nodes to the same 2D network label; finally, a complete chip netlist that can be used directly is output, realizing seamless dimensionality reduction from 3DIC physical stack to 2D circuit model.

[0024] This embodiment provides a netlist extraction method that determines the overall chip outline boundary based on the projection of multiple dies onto a preset shared plane, ensuring physical layout coordination between different dies. Next, by dividing the chip into baseline and density partitions and combining die density information, the partitioning method is optimized to improve computational efficiency and avoid design bottlenecks caused by density unevenness. This partitioning method helps improve the stability and efficiency of EDA tools when processing different regions. The netlists of the dies are extracted according to the density partitions and merged into a unified chip netlist, ensuring the accuracy of electrical connections and cross-layer coordination, avoiding signal interference and latency issues, while reducing computation and resource consumption. Overall, this method can improve the coordination, connectivity, and computational efficiency of 3DIC designs, thereby effectively optimizing resource utilization.

[0025] In one embodiment, the process may include the following steps: Step S51: For each density partition obtained, extract the cell netlist of each grain in the density partition according to the graphic information of the pattern falling in the density partition; wherein, the pattern in a grain represents the metal wiring used for interconnection inside the grain; the graphic information of the pattern indicates the position of the metal wiring represented by the pattern in the grain.

[0026] Specifically, each die contains a series of patterns, which typically represent the metal wiring within the die. Pattern information refers to the detailed description (including location) of these patterns falling within specific density zones within the die. The netlist of each die is a collection containing all pattern information, defining the topology and connectivity of the various components within that die. By extracting the cell netlist, the specific structural data of each die can be obtained, preparing for the next step of chip design and integration.

[0027] Preferably, in this embodiment, multiple dies can be concurrently extracted during cell netlist extraction. This parallel processing significantly improves the netlist extraction speed and reduces latency caused by serial processing. Netlist extraction can be performed simultaneously between different dies, and through concurrent extraction, the cell netlists of these dies can be generated simultaneously. Furthermore, each die contains multiple density partitions, and the netlists of these density partitions can also be processed in parallel, thereby maximizing extraction efficiency. For example, please refer to... Figure 3 , Figure 3 In the image, (a) represents the projection of the bottom die. Figure 3 In diagram (b), the projection of the top die is shown. Each die contains multiple density partitions. That is, the bottom die contains part0, part1, part2, part3, part4, and part5. Part0 on the bottom die can be extracted simultaneously with any other part on that bottom die because there is no direct dependency between the extraction of these parts. Not only can different parts within the same die be extracted in parallel, but part0 on the bottom die and any part on the top die can also be extracted in parallel. Although these two dies may be located at different levels or modules of the chip, their extraction processes are independent and therefore can be processed in parallel.

[0028] This embodiment optimizes the density partitioning method by extracting the cell netlist based on the pattern information within the die, reducing computational complexity while improving accuracy. Furthermore, the optimized partitioning method not only improves computational efficiency but also reduces resource consumption, thereby saving computational resources and improving efficiency when handling large-scale designs. This method is particularly suitable for 3D IC design, enabling precise handling of connections between multiple stacked layers and ensuring smooth signal and power transmission.

[0029] In one embodiment, a grain comprises at least one metal layer; the process may include the following steps: Step S71: If there is a pattern with an overlapping region in the boundary layer of any two adjacent grains, then create an associated node and a connection relationship between the associated nodes for the two adjacent grains respectively.

[0030] Specifically, an interface layer refers to a metal layer between two adjacent dies that are interconnected. The design of this region plays a crucial role in circuit performance, power consumption, interconnection, and layout. An overlapping region graphically refers to a physical connection between two dies' metal traces at the interface. For example, the metal traces of two dies at the interface may share some connections, or their trace paths may partially overlap. This situation typically affects signal integrity, electrical performance, and routing optimization. When there is an overlapping region at the interface layer of two adjacent dies, it means that there is a certain physical connection between the two dies. In this case, to accurately describe the interconnection relationship and electrical behavior between the two dies, associated nodes need to be created at these interfaces. Associated nodes are logical nodes used in physical design to represent the connection between two dies or regions. They typically represent interconnection points, shared resources of the interface layer, or interfaces for signal transmission.

[0031] Electrical connection refers to linking two or more associated nodes through the transmission of electrical parameters such as current, signal, and power. After creating associated nodes, electrical connections (such as ideal resistors) are established for the corresponding associated nodes of each die, thereby establishing physical electrical connections between the associated nodes.

[0032] Step S73: Merge the connection relationships and cell netlists into a chip netlist for the chip.

[0033] Specifically, the cell netlist of a die is comprised of the cell netlists within each density partition. By merging these cell netlists and their associated node connections, the entire chip netlist can be generated. The chip netlist is a logical description of the entire circuit design, containing information on all electrical connections, including nodes, wires, and ports. After merging the cell netlists of all dies to form the chip netlist, it can be used for subsequent chip simulation, optimization, verification, and other processes.

[0034] A chip netlist is a higher-level netlist formed by merging all cell netlists, representing the circuit topology of the entire chip. A chip netlist includes not only the structural information within each die but also the connections between these dies. When merging cell netlists from multiple dies, the resulting chip netlist is still a 3D netlist, describing the connections between dies at different levels and physical locations. For further processing and optimization, 3D netlists typically need to be converted to 2D netlists. In a 2D netlist, all dies are flattened onto a plane, and all connections are presented in two dimensions. EDA tools usually provide instructions (e.g., 3D-aware floorplan → 2D placement conversion instructions) that allow users to convert 3D netlists to 2D netlists, facilitating subsequent placement, routing, and optimization operations.

[0035] This embodiment effectively maps the physical contact points between multiple dies to logical connection points by creating associated nodes at the interface boundaries, thereby ensuring electrical compatibility and connectivity between different dies. This not only improves the stability of 3DIC design but also avoids electrical failures caused by connection errors. Furthermore, by determining the connection relationships of the associated nodes and merging them into the cell netlist to generate a complete chip netlist, the electrical connections between dies can be accurately reflected, ensuring that the chip's electrical performance is accurately represented.

[0036] In one embodiment, the process may include the following steps: Step S731: At the boundary layer of any two adjacent grains, detect the pattern located in different grains but with overlapping regions, and create associated nodes for the geometric center of the pattern respectively.

[0037] Specifically, in 3D IC design, multiple dies (i.e., different top dies and bottom dies) are typically electrically connected through physically overlapping patterns. These patterns are usually metal wirings, which may overlap at the boundaries between two dies. This overlap indicates the need for electrical connections; that is, in this region, two different dies need to be connected to transmit signals or current. For example, the overlapping area between the metal layers of the top die and the bottom die needs to be connected, which is typically achieved by creating corresponding associated nodes.

[0038] Step S733: For any two graphics with overlapping areas, establish an electrical connection to represent the interconnection between the coordinate positions of the two associated nodes, so as to obtain the connection relationship of the associated nodes.

[0039] Specifically, in 3DIC design, a node is an abstract representation of a circuit connection point. In this step, an associated node refers to an electrical connection point created at the die-interface boundary for a pattern with overlapping areas. Each boundary may have multiple nodes, representing connections that need to be established between different dies. These associated nodes ensure that the electrical connections between different dies are correctly established.

[0040] Although nodes on different grains (top die and bottom die) are located in different physical spaces, their electrical connections can be confirmed through overlapping areas. Therefore, after creating associated nodes, conductive paths (such as ideal resistors) are added to establish connections between the associated nodes.

[0041] For example, please refer to Figure 4 In the physical cross-sectional diagram of the 3D chip, the top die and bottom die each display three metal layers as examples. All rectangular block graphics represent metal wiring, and the netlist extracts this metal wiring information to form several abstract nodes. On the interface top_layer_1 of the top die, additional associated nodes are created at the center of each graphic, such as the red nodes node5 and node7 in the diagram. Similarly, on the bottom_die's bottom_layer_1 layer, associated nodes node8 and node9 are also created for each graphic. It is particularly important to note that node7 of the top die and node9 of the bottom die coincide in physical coordinates. Although their actual positions are the same, they still represent two independent associated nodes. The creation of these associated nodes ensures the correctness and integrity of the electrical connections.

[0042] Next, an electrical connection is established between the coordinates of the associated nodes. This connection can be represented by adding an ideal resistor (i.e., an idealized connection with a very small resistance value) between them. The introduction of this resistor ensures that the associated nodes can still be electrically connected through the ideal resistor, even though their positions are different, thus ensuring that current can flow between the two associated nodes. Therefore, this approach ensures that the electrical connections between different grain layers are not affected, while also simplifying the design and calculation process.

[0043] This embodiment effectively identifies patterns requiring electrical connections between different dies by recognizing patterns with overlapping regions at die boundaries. Then, corresponding associated nodes are created for each pattern with overlapping regions, abstracting physical layer connections into logical layer nodes and electrical connections, improving accuracy and operability. Electrical connections are established between these associated nodes. This makes netlist extraction more efficient and accurate, while optimizing the partitioning method and reducing computational resource consumption. In this way, not only is the coordination and connectivity between different dies ensured, but computational efficiency and design quality are also significantly improved.

[0044] In one embodiment, the process may include the following steps: Step S11: For the projection of any grain onto the preset shared plane, determine the offset parameters and boundary parameters of the projection of each grain in the specified coordinate system.

[0045] Specifically, in 3DIC design, a preset shared plane needs to be defined. This preset shared plane is usually the basis for the projection of each die. For multiple stacked dies, their projections are typically mapped onto this plane. Let's assume the XY plane is used as the shared plane. Set the lower left corner of the preset shared plane as the origin (0,0) of the specified coordinate system, with the X-axis to the right and the Y-axis to the top. The projections of all dies need to be described within this unified specified coordinate system to avoid confusion caused by different origins for each die.

[0046] The projection of each grain requires an offset from the origin of the specified coordinate system to determine its position within that system. This offset is typically represented as (Δx, Δy). For example, see [link to relevant documentation]. Figure 5 In (a), assume both the bottom and top dies are rectangular. For the bottom die, the lower left corner of its projection is located at (10, 0) in the specified coordinate system. This means its lower left corner is offset by 10 units in the X-axis direction and 0 units in the Y-axis direction from the origin of the specified coordinate system. The offset parameters are (Δx = 10, Δy = 0). For the top die, the lower left corner of its projection is located at (20, 40) in the specified coordinate system. This means its lower left corner is offset by 20 units in the X-axis direction and 40 units in the Y-axis direction from the origin of the specified coordinate system. The offset parameters are (Δx = 20, Δy = 40).

[0047] Boundary parameters refer to the minimum bounding box of the grain projection in a specified coordinate system. This bounding box is determined by the minimum and maximum X and Y values ​​of the grain projection. (See also...) Figure 5In (b), for the bottom die, its projection range is: X-axis range is [10, 50], indicating that the projection of the bottom die is from x=10 to x=50. Y-axis range is [0, 80], indicating that the projection of the bottom die is from y=0 to y=80. Therefore, the boundary parameters of the bottom die are: x∈[10, 50], y∈[0, 80]. For the top die, its projection range is: X-axis range is [20, 60], indicating that the projection of the top die is from x=20 to x=60. Y-axis range is [40, 90], indicating that the projection of the top die is from y=40 to y=90. Therefore, the boundary parameters of the top die are: x∈[20, 60], y∈[40, 90].

[0048] Step S13: Determine the overall contour boundary adapted to the chip based on the offset parameter and boundary parameter.

[0049] Specifically, the boundary parameters of each die are precisely mapped using offset parameters, ensuring that the positional information of each die can be calibrated within a unified, specified coordinate system. This precise mapping provides a clear spatial framework for subsequent design, clarifying the relative position of each die and thus avoiding potential overlap and conflict issues. Next, by extracting extreme coordinates from the global boundary coordinate set, the overall layout range of the chip can be further clarified. These extreme coordinates reveal the limiting boundaries of the die distribution, ensuring that the design boundaries are clear and conform to actual layout requirements. Finally, by enclosing the contour region formed by these extreme coordinates, the overall contour boundary of the chip can be precisely determined. This contour boundary not only defines the overall shape of the chip but also provides an accurate basis for subsequent space allocation and partitioning, ensuring a reasonable layout between subsequent dies and avoiding resource waste.

[0050] This embodiment analyzes the projections of multiple dies onto a preset shared plane to determine the offset and boundary parameters of each die, thereby accurately mapping the spatial position and geometry of each die to a specified coordinate system. This provides a clear spatial framework for subsequent layout optimization. Based on the offset and boundary parameters, an overall outline boundary adapted to the chip is determined, providing a clear shape boundary for chip design. This helps optimize chip space utilization, accurately determine die layout, optimize resource allocation, and ensure effective connection between dies, thereby improving the accuracy and efficiency of the overall design.

[0051] In one embodiment, the process may include the following steps: Step S131: Map the boundary parameters of each grain to a specified coordinate system according to the offset parameters to obtain the global boundary coordinate set of each grain.

[0052] Specifically, for each grain, the x and y coordinates of the boundary parameters need to be adjusted according to the offset parameters. Assume the boundary parameters of a grain are x∈[x... min ,x max ] and y∈[y min ,y max The offset parameter is (△x, △y). After mapping to the specified coordinate system, the new boundary will be: x∈[x min +△x,x max +△x],y∈[y min +△y,y max In this way, the global boundary parameters of all grains projected onto the specified coordinate system are determined. After the above mapping, a set containing the global boundary coordinates of all grains is obtained.

[0053] Step S133: Extract extreme value coordinates from the global boundary coordinate set.

[0054] Specifically, extreme coordinates refer to the minimum and maximum values ​​on the X and Y axes among the boundary coordinates of all grains. These extreme coordinates determine the outermost boundary of the entire chip. For the set of x-coordinates of all grains, the minimum x' is found. min and the largest x' max For the set of y-coordinates of all grains, find the smallest y'. min and the largest y' max .

[0055] Step S135: Determine the contour region enclosed by the extreme coordinates as the overall contour boundary adapted to the chip.

[0056] Specifically, the extreme coordinates [x' min ,x' max ,y' min ,y' max The outer boundary of the chip was determined. By connecting these coordinates into a rectangle, the enclosed area represents the overall outline boundary of all grain projections. See also... Figure 5 In (b), the outline region enclosed by the extreme coordinates (10, 60, 0, 90) is the overall outline boundary of the chip.

[0057] This embodiment maps the boundary parameters of the dies to a specified coordinate system to ensure the precise location of each die. This provides a clear spatial framework for subsequent design and partitioning. Extracting the extreme values ​​of the global boundary coordinates further clarifies the overall chip outline. This facilitates subsequent overall optimization and partitioning, ensuring coordination and connectivity between different dies while avoiding design conflicts and resource waste.

[0058] In one embodiment, any two reference partitions have the same size but different location information; the process may include the following steps: Step S10: For each reference partition, determine the density of the reference partition based on the number of patterns of each grain within the reference partition.

[0059] Specifically, the overall outline boundary refers to the area within the chip that needs to be partitioned. The overall outline boundary can be a chip die or the chip itself; that is, the size of the overall outline boundary can be smaller than or equal to the size of the chip. It is worth noting that the projection pattern of the overall outline boundary onto the die in a top-view can be either a regular or irregular shape.

[0060] Determining the relative positional relationship between the overall contour boundary and the chip allows us to determine the positional information of the overall contour boundary within the die. Specifically, along the top view direction of the die, the projection pattern of any overall contour boundary in this top view direction falls within the projection pattern of the chip in this top view direction. Therefore, if we establish an x-axis coordinate system along the length of the chip and a y-axis coordinate system along the width of the chip, the positional information of the overall contour boundary can be described as the set of x-axis coordinates of the overall contour boundary in the x-axis coordinate system and the set of y-axis coordinates of the overall contour boundary in the y-axis coordinate system.

[0061] In this step, the size of the reference partition refers to the size of the projected pattern of the reference partition in the top view direction of the die. For ease of reference partitioning and description, generally speaking, the length direction of the reference partition is parallel to the length direction of the chip, and the width direction of the reference partition is parallel to the width direction of the chip.

[0062] Generally, to facilitate partitioning and subsequent merging, the projection pattern of the reference partition in the top view of the grain is a regular shape, such as a rectangle. The size of the reference partition can be selected according to actual needs. Typically, the width of the reference partition is less than or equal to 1000 micrometers, and the length of the reference partition is less than or equal to 1000 micrometers. The length and width of the reference partition can be the same or different.

[0063] It is worth mentioning that the reference partition is the lowest level of the hierarchical design of the entire grain as defined in this application. That is, the reference partition is a statistical object of the pattern density or the total number of patterns in the overall outline boundary. Furthermore, the reference partition is the smallest mergeable module in the hierarchical design of the entire grain as defined in this application.

[0064] It should be noted that during the actual division of the overall contour boundary, the size of the overall contour boundary on the x-axis coordinate system (i.e., the length of the overall contour boundary) may not be divisible by the length of the reference partition. In this case, it is necessary to perform a rounding process on the overall contour boundary.

[0065] For example, if the length of the overall outline boundary is x11 and the length of the reference partition is x21, the calculated value is x11 / x21 = 6.3. Therefore, in the x-axis direction, the overall outline boundary is divided into 7 consecutive reference partitions. Similarly, if the width of the overall outline boundary is y11 and the width of the reference partition is y21, the calculated value is y11 / y21 = 4.6. Therefore, in the y-axis direction, the overall outline boundary is divided into 5 consecutive reference partitions. It is worth noting that the above example only rounds down the number of reference partitions obtained. In the subsequent steps of this embodiment, the statistical calculation of the number of reference partitions will still be based on the actual dimensions of the overall outline boundary on the x-axis and the actual dimensions on the y-axis.

[0066] Step S20: Based on the density of each reference partition, the overall contour boundary is divided to obtain the density partition of the overall contour boundary.

[0067] Specifically, the threshold value for the number of patterns can be preset according to actual needs. Once the position information of the overall contour boundary and the size of the reference partition are determined, the position information of each first position (i.e., the position information of the reference partition within the die) can be determined. Since the position information of the overall contour boundary describes the relative positional relationship between the overall contour boundary and the chip, for a reference partition, its position information within the chip can be determined based on its position information within the overall contour boundary and the position information of the overall contour boundary within the chip.

[0068] Using the chip as a reference, the first location information describes the x-axis coordinate set of the corresponding reference partition in the x-axis coordinate system and the y-axis coordinate set in the y-axis coordinate system. At least one of the x-axis coordinate set and y-axis coordinate set of any two reference partitions is different.

[0069] Since the die design file details the location information of all die patterns within the chip, once the first location information is determined, the number of patterns corresponding to that first location information can be obtained from the design file. It is worth noting that because the distribution of patterns within the die is not uniform, the number of patterns in any two reference partitions may differ.

[0070] Compared to related technologies that divide the overall outline boundary of a grain into multiple reference partitions of the same size based only on a fixed length and fixed width, the grain partitioning method provided in this embodiment, based on step S20, reduces the difference in the number of patterns in any two density partitions determined by density partitioning, or even makes the number of patterns comparable. This improves the uniformity of the distribution of the number of patterns in each density partition in the overall outline boundary. As a result, during the calculation of the grain using EDA back-end verification design tools, the difference in the amount of computation caused by extracting the resistor network of each density partition is reduced, or even made comparable. This can effectively reduce the phenomenon of excessive peak memory and solve the problem that the overall performance of EDA back-end verification design tools is affected by excessive peak memory.

[0071] Further, in one embodiment, step S20 includes the following steps: Step S21: Determine multiple first reference partition groups based on the first location information.

[0072] In this configuration, multiple first reference partition groups are arranged along a first direction, and each first reference partition group includes multiple reference partitions arranged sequentially along a second direction, wherein the first and second directions intersect. For example, please refer to... Figure 6 Taking the overall outline boundary S1 as a regular rectangular shape as an example, the overall outline boundary S1 is divided into multiple reference partitions B101 arranged in an array. Figure 6 The x-axis shown is the length direction in the top view projection of the grain. Figure 6 The y-axis shown represents the width direction in the top view projection of the grain. Figure 6 The z-axis shown is the thickness direction in the top view projection of the grain.

[0073] For ease of explanation, Figure 6 The y-axis direction is the first direction indicated in step S21. Figure 6 The x-axis direction is the second direction indicated in step S21. Figure 6 The rectangular pattern formed by single-point lines shown is a projection pattern on the top view of the TopBlock grain. Figure 6 The rectangular pattern shown in the figure, formed by dashed and solid lines, or by dashed and dashed lines, serves as the base partition.

[0074] Figure 6 The number shown for each reference partition B101 indicates the number of graphics included in that reference partition B101 obtained from the design file. For example, if the number shown in reference partition B101 located in the first row and first column of the overall outline boundary B1 is "10", it means that reference partition B101 with position information [(x0,x0+x1),(y0,y0+y1)] contains 10 graphics.

[0075] For any two reference partitions in the first reference partition group, their position information in the y-axis direction (i.e. Figure 6 The y-axis coordinate set is the same as the position information in the x-axis direction (i.e., Figure 6 The x-axis coordinate sets in the reference partitions are different. For two reference partitions located in different first reference partition groups, their position information in the y-axis direction will necessarily be different.

[0076] Therefore, the step S21 of "determining multiple first reference partition groups based on the first position information" can be specifically defined as: determining reference partitions with the same y-axis coordinate set based on the first position information, and dividing the reference partitions with the same y-axis coordinate set into the same first reference partition group.

[0077] Step S22: Determine the total number of first graphics in each first reference partition group based on the number of graphics in each reference partition in the first reference partition group.

[0078] Since step S10 has obtained the number of graphics in each reference partition from the design file, when the first position information is determined, the total number of graphics in all reference partitions belonging to the same first reference partition group is determined as the first total number of graphics in this first reference partition group.

[0079] Step S23: Determine the density partition based on the total number of first graphics, the threshold number of first graphics, and the first benchmark partition group.

[0080] Wherein, the first graphic quantity threshold is the graphic quantity threshold corresponding to the first direction. In one embodiment, the first graphic quantity threshold is related not only to the number of first reference partition groups divided by the overall contour boundary in the first direction, but also to the total number of first graphics in each first reference partition group. The specific value of the first graphic quantity threshold can be the average value of the total number of first graphics, the mode or median of the total number of first graphics, or the variance value calculated based on the total number of all first graphics.

[0081] Furthermore, in one embodiment, step S23 specifically includes the following steps: Step S231: Based on the total number of first graphics, the first graphics quantity threshold, and the first baseline partition group, multiple first merged module groups are obtained.

[0082] Each first merge module group includes at least one first baseline partition group.

[0083] Step S232: Determine density partitions based on the first merging module group.

[0084] Based on the density partitions obtained from steps S231 to S232 provided in this embodiment, the difference in the number of graphics presented along the first direction of the overall outline boundary is adjusted by determining the first merging module group.

[0085] Further, in one embodiment, step S232 specifically includes: determining the set of first position information arranged along the first direction in the first merging module group as the position information of density partition.

[0086] In another embodiment, step S232 specifically includes: determining the total number of graphics in the reference partitions arranged along the first direction in the first merging module group as the graphic quantity information of the density partition. In yet another embodiment, step S232 specifically includes: determining the set of first position information arranged along the first direction in the first merging module group as the position information of the density partition, and determining the total number of graphics in the reference partitions arranged along the first direction in the first merging module group as the graphic quantity information of the density partition.

[0087] like Figure 7 As shown in (a) and (b), the first merged module group, counting from bottom to top along the first direction, includes eight density partitions. Figure 7 In (b), the first density partition counting from left to right along the second direction is Figure 7 (a) shows the set of the first reference partitions arranged along the first direction in the first to third first reference partition groups, that is, Figure 7 (b) shows the first density partition by Figure 7 (a) The first reference partition in the first first reference partition group, the first reference partition in the second first reference partition group, and the first reference partition in the third first reference partition group together constitute the first reference partition.

[0088] Specifically, the position information of the first reference partition in the first reference partition group is ((x0,x0-x1),(y0,y0+y1)), the position information of the first reference partition in the second reference partition group is ((x0,x0-x1),(y0+y1,y0+2y1)), and the position information of the first reference partition in the third reference partition group is ((x0,x0-x1),(y0+2y1,y0+3y1)). Therefore, the position information of the first density partition is ((x0,x0+x1),(y0,y0-3y1)). Similarly, since the number of graphics in the first reference partition in each of the first to third reference partition groups is 10, the number of graphics in the first density partition is 30.

[0089] Specifically, in one embodiment, step S231 further includes: Step S2311: Determine the current first reference partition group as the first initial module group.

[0090] In this step, the current first reference partition group can be any of the selected first reference partition groups. If it is necessary to traverse each first reference partition group along the first direction, then the current first reference partition group is either the first first reference partition group from top to bottom along the first direction, or the first first reference partition group from bottom to top along the first direction.

[0091] Step S2312: Determine the current total amount of the first graphic as the first initial total amount of the graphic.

[0092] In this step, the current total number of first graphics is the sum of the number of graphics in each base partition of the current first base partition group.

[0093] Step S2313: Determine whether the total number of the first initial graphics is greater than or equal to the threshold number of the first graphics.

[0094] If so, after step S2313, step S231 further includes step S2314, determining a first merged module group from the first initial module group. That is, if the total number of the first initial graphics is greater than or equal to the first graphics quantity threshold, then the current first baseline partition group is a first merged module group, and merging is unnecessary. If the total number of the first initial graphics is less than the first graphics quantity threshold, after step S2313, step S231 further includes: Step S2315: Determine whether the first initial module group includes the last first baseline partition group.

[0095] In this step, the location information of the first initial module group and the last first reference partition group are obtained to determine whether the first initial module group includes the last first reference partition group. If the location information of the first initial module group includes the location information of the last first reference partition group, then the first initial module group includes the last first reference partition group; otherwise, the first initial module group does not include the last first reference partition group. If it does not include the last first reference partition group, then step S2316 is executed to merge the current first initial module group and the next first reference partition group to obtain the updated first initial module group.

[0096] In this step, the updated location information of the first initial module group includes the location information of the current first reference partition group and the location information of another first reference partition group adjacent to the current first reference partition group.

[0097] And execute step S2317, merging the current first initial graphic total and the next first graphic total to obtain the updated first initial graphic total.

[0098] In this step, the updated first initial graphic total value is the sum of the first initial graphic total before the update (i.e., the current first graphic total) and the next first graphic total.

[0099] It should be noted that steps S2316 and S2817 can be executed sequentially or simultaneously, and this application does not impose any restrictions on this.

[0100] After steps S2316 and S2317 are completed, return to step S2313.

[0101] It should be noted that when returning to step S2313, the updated total number of the first initial graphics is compared with the first graphics quantity threshold.

[0102] Furthermore, in one embodiment, if the determination result of step S2315 is that the first initial module group includes the last first reference partition group, then after step S2315, step S231 further includes: step S2318, determining the first initial module group as a first merged module group.

[0103] The following will combine Figure 7 Steps S2311 to S2318 described above will be explained by example. Figure 7 In the example, the overall contour boundary B1 includes 8 rows and 8 columns, totaling 64 baseline partitions B101. For example... Figure 7 As shown, taking the current first reference partition group as the first reference partition group S_L1 from bottom to top along the first direction as an example.

[0104] Step S2311 specifically involves determining the first first baseline partition group S_L1 as the first initial module group.

[0105] Step S2312 specifically involves determining the first total graphic quantity of the first first reference partition group S_L1 as the first initial total graphic quantity.

[0106] Based on the position information of the first first reference partition group, the number of graphics in the first to eighth reference partitions of the first first reference partition group can be determined as 10, 10, 10, 10, 20, 20, 20, 20, respectively. Therefore, the total number of graphics in the first first set is calculated as: 10 + 10 + 10 + 10 + 20 + 20 + 20 + 20 = 120. Thus, the total number of graphics in the first initial set is 120. Similarly, as... Figure 6 As shown, the total number of the first graphic in the second to fourth figures is 120, and the total number of the first graphic in the fifth to eighth figures is 240.

[0107] Step S2313 specifically involves determining whether the total number of the first initial graphics (120) is greater than or equal to the threshold number of the first graphics (360).

[0108] Since the judgment result at this time is that the total number of the first initial graphics is less than the threshold number of the first graphics, step S2315 is executed after step S2313. Step S2315 specifically involves: determining whether the first initial module group (the first first reference partition group) includes the last first reference partition group.

[0109] Since the judgment result at this time is that the first initial module group is not the last first reference partition group, steps S2316 and S2317 are executed after step S2315.

[0110] Step S2316 specifically involves merging the current first initial module group (i.e., the first first base partition group S_L1) and the next first base partition group (i.e., the second first base partition group S_L2) to obtain the first initial module group after one update.

[0111] After step S2316 is completed, the updated position information of the first initial module group includes the position information of the first to second first reference partition groups.

[0112] Step S2817 specifically involves merging the current total amount of the first initial graphic (i.e., the first total amount of the first first graphic) and the total amount of the next first graphic (i.e., the second total amount of the first first graphic) to obtain the total amount of the first initial graphic after one update.

[0113] After step S2317 is completed, the total number of the first initial graphics after one update is 240.

[0114] After steps S2317 and S2316 are completed, the process returns to step S2313. In step S2313, which is executed again, the total number of the first initial graphics after the update is compared with the first graphics quantity threshold.

[0115] Since the total number of initial graphics after the update is still less than the threshold for the number of initial graphics, step S2315 needs to be executed again after step S2313. In this re-executed step S2315, the position information of the updated first initial module group is compared with the position information of the last first reference partition group.

[0116] Since the first initial module group after the update still does not include the last first reference partition group, steps S2316 and S2317 need to be executed again after step S2315.

[0117] In step S2316, which is executed again, the current first initial module group (i.e., the first to second base partition group) and the next first base partition group (i.e., the third first base partition group) are merged to obtain the first initial module group after being updated twice.

[0118] In step S2317, which is executed again, the current first initial graphic total (i.e., the first initial graphic total updated once) and the next first graphic total (i.e., the third first graphic total) are merged to obtain the first initial graphic total after being updated twice.

[0119] After completing steps S2316 and S2317 for the second time, the process returns to step S2313. In step S2313, which is executed for the third time, the total number of the first initial graphics after the two updates is compared with the first graphics quantity threshold 360.

[0120] Since the total number of the first initial graphics after two updates is equal to the threshold number of the first graphics, step S2314 is executed after step S2313. Specifically, step S2314 involves determining the first initial module group updated twice as a first merged module group.

[0121] In summary, the first to third first baseline partition groups together constitute the first first merge module group.

[0122] Next, the fourth first benchmark partition group is determined as the current first benchmark partition group, and a new round of steps S2311 to S2318 is executed. Referring to the example above, ultimately, the fourth and fifth first benchmark partition groups together form the second first merge module group. Next, the sixth first benchmark partition group is determined as the current first benchmark partition group, and a new round of steps S2311 to S2318 is executed. Referring to the example above, ultimately, the sixth and seventh first benchmark partition groups together form the third first merge module group. Next, the eighth first benchmark partition group is determined as the current first benchmark partition group, and a new round of steps S2311 to S2318 is executed. (The rest of the text is missing.) Figure 7 As shown, since the total number of the first initial graphics at this time is the eighth total number of the first graphics (240), after step S2313, step S2315 is executed. The current first initial module group is the last first reference partition group, so after step S2315, step S2318 is executed. The last first reference partition group is determined as the fourth first merge module group.

[0123] In conclusion, in Figure 7 In the overall contour boundary B1 shown, along the first direction, based on steps S2311 to S2318, the eight first reference partitions are finally combined into four first merged module groups.

[0124] In another embodiment, step S232 specifically includes the following steps.

[0125] Step S2321: Determine multiple second reference partition groups based on the first location information.

[0126] In this configuration, multiple second reference partition groups are arranged along a second direction, and each second reference partition group includes multiple reference partitions arranged along a first direction. Step S2322 involves determining the total number of second graphics in each second reference partition group based on the number of graphics in each reference partition within the second reference partition group.

[0127] Given the first location information, the total number of graphics in all reference partitions belonging to the same second reference partition group is determined as the second total number of graphics in this second reference partition group.

[0128] Step S2323: Determine the density partition based on the total amount of the second graphic, the threshold number of the second graphic, the second benchmark partition group, and the first merging module group.

[0129] The second graphic quantity threshold is a graphic quantity threshold corresponding to the second direction. In one embodiment, the second graphic quantity threshold is related not only to the number of second reference partition groups divided by the overall contour boundary in the second direction, but also to the total number of second graphics in each second reference partition group. The specific value of the second graphic quantity threshold can be the average value of the total number of second graphics, the mode or median of the total number of second graphics, or the variance value calculated based on the total number of second graphics.

[0130] Furthermore, in one embodiment, step S2323 specifically includes the following steps: Step S23231: Based on the total amount of the second graphics, the threshold number of the second graphics, and the second benchmark partition group, multiple second merged module groups are obtained.

[0131] Each second merge module group includes at least one second baseline partition group.

[0132] Step S23282: Determine density partitions based on the second merging module group and the first merging block group.

[0133] Based on the density partitions obtained in steps S23231 and S23232 provided in this embodiment, the difference in the number of graphics presented along the first direction of the overall outline boundary is adjusted by determining the first merging module group, and the difference in the number of graphics presented along the second direction of the overall outline boundary is adjusted by determining the second merging module group.

[0134] Furthermore, in one embodiment, step S23232 specifically includes the following steps: Step S23232a: Determine the overlapping area of ​​the second merged module group and the first merged module group.

[0135] Step S23232b: Determine the location information of the overlapping region as the location information of the density partition, and / or determine the total number of graphics in the reference partition located in the overlapping region as the number of graphics in the density partition.

[0136] Please continue reading. Figure 7 , Figure 7 As shown in (c), counting from bottom to top along the first direction, the overall contour boundary B1 includes four first merging module groups; counting from left to right along the second direction, the overall contour boundary B1 includes four second merging module groups. Thus, the four second merging module groups and the four first merging module groups form a total of 16 overlapping regions. Each overlapping region is a density partition, and therefore the positional information of each overlapping region is the positional information of the corresponding density partition. The sum of the number of graphics in the reference partition of each overlapping region is the positional information of the corresponding density partition.

[0137] Specifically, in one embodiment, step S23231 further includes: Step S23231a: Determine the current second reference partition group as the second initial module group.

[0138] In this step, the current second reference partition group can be any of the selected second reference partition groups. If it is necessary to traverse each second reference partition group along the second direction, then the current second reference partition group is either the first second reference partition group from left to right along the second direction, or the first second reference partition group from right to left along the second direction.

[0139] Step S23231b: Determine the current total amount of the second graphic as the total amount of the second initial graphic.

[0140] In this step, the current total number of second graphics is the sum of the number of graphics in each base partition of the current second base partition group.

[0141] Step S23231c: Determine whether the total number of the second initial graphics is greater than or equal to the threshold number of the second graphics.

[0142] If so, after step S23231c, step S23231 further includes step S23231d, which determines the second initial module group as a second merged module group. That is, if the total number of second initial graphics is greater than or equal to the second graphics quantity threshold, then the current second baseline partition group is a second merged module group, and no merging is required. If the total number of second initial graphics is greater than or equal to the second graphics quantity threshold, after step S23231c, step S23231 further includes: Step S23231e: Determine whether the second initial module group includes the last second baseline partition group.

[0143] In this step, the location information of the second initial module group and the last second reference partition group are obtained to determine whether the second initial module group includes the last second reference partition group. If the location information of the second initial module group includes the location information of the last second reference partition group, then the second initial module group includes the last second reference partition group; otherwise, the second initial module group does not include the last second reference partition group.

[0144] If not included, proceed to step S23231f to merge the current second initial module group and the next second baseline partition group to obtain the updated second initial module group.

[0145] In this step, the updated position information of the second initial module group includes the position information of the current second reference partition group and the position information of another second reference partition group adjacent to the current second reference partition group. Step S23231g is then executed to merge the current total amount of the second initial graphics and the total amount of the next second graphics to obtain the updated total amount of the second initial graphics.

[0146] In this step, the updated second initial graphic total is the sum of the previous second initial graphic total (i.e., the current second graphic total) and the next second graphic total.

[0147] In this embodiment, in conjunction with steps S23231c, S23231e, and S23231h, it can be seen that when the second initial module group includes at least two second reference partition groups, even if the total number of second initial graphics corresponding to the second initial module group is less than the second graphics quantity threshold, as long as the position information of the second initial module group includes the position information of the last second unit module group, the merging operation ends.

[0148] The following is still combined Figure 6 Steps S23231a to S23231h described above are illustrated by example. See details [link to documentation]. Figure 6 In (a), the current second reference partition group is the first second reference partition group S_W1 from left to right along the second direction.

[0149] Step S23231a specifically involves determining the first second baseline partition group S_W1 as the second initial module group.

[0150] Step S23231b specifically involves determining the second total amount of the second graphics in the first second baseline partition group S_W1 as the second initial total amount of the graphics.

[0151] For details, please refer to Figure 7 In (a), based on the position information of the first second reference partition group, the number of graphics in the first to eighth reference partitions of the first second reference partition group can be determined as: 10, 10, 10, 10, 20, 20, 20, 20. Therefore, the total number of the first second graphics is calculated as: 10 + 10 + 10 + 10 + 20 + 20 + 20 + 20 = 120. Thus, the total number of the first initial graphics is 120. Similarly, as... Figure 7 As shown, the total number of the second to fourth second figures is 120, and the total number of the fifth to eighth first figures is 240.

[0152] Step S23231c specifically involves determining whether the total number of the second initial graphics (120) is greater than or equal to the threshold number of the second graphics (assuming the threshold number of the second graphics is 360).

[0153] Since the judgment result at this time is that the total number of the second initial graphics is less than the threshold of the number of the second graphics, step S23231e is executed after step S23231c. Step S23231e specifically means: determining whether the second initial module group (the first second reference partition group) includes the last second reference partition group.

[0154] Since the judgment result at this time is that the second initial module group is not the last second reference partition group, steps S23151f and S23151g are executed after step S23151e.

[0155] Step S23151f specifically involves merging the current second initial module group (i.e., the first second base partition group S_W1) and the next second base partition group (i.e., the second second base partition group S_W2) to obtain the second initial module group after one update.

[0156] After step S23151f is completed, the updated position information of the second initial module group includes the position information of the first to the second second reference partition groups.

[0157] Step S23151g specifically involves merging the current total amount of the second initial graphic (i.e., the first total amount of the second graphic) and the total amount of the next second graphic (i.e., the second total amount of the second graphic) to obtain the total amount of the second initial graphic after one update.

[0158] After step S23151g is completed, the total number of the second initial graphics after one update is 240.

[0159] After steps S23151f and S23151g are completed, the process returns to step S23151c. In step S23151c, which is executed again, the total number of the second initial graphics after the update is compared with the threshold number of the second graphics.

[0160] Since the total number of the second initial graphics after the update is still less than the threshold for the number of second graphics, step S23151e needs to be executed again after step S23151c. In this re-executed step S23151e, the position information of the updated second initial module group is compared with the position information of the last second reference partition group.

[0161] Since the second initial module group after the update still does not include the last second reference partition group, steps S23151f and S23151g need to be executed again after step S23151e.

[0162] In step S23151f, which is executed again, the current second initial module group (i.e., the first to the second second base partition group) and the next first base partition group (i.e., the third second base partition group) are merged to obtain the second initial module group after being updated twice.

[0163] In step S23151g, which is executed again, the current total amount of the second initial graphic (i.e., the total amount of the second initial graphic updated once) and the next total amount of the second graphic (i.e., the third total amount of the second graphic) are merged to obtain the total amount of the first initial graphic after being updated twice.

[0164] After the second execution of steps S23151f and S23151g, the execution returns to step S23151c. At this time, in the third execution of step S23151c, the total number of stars (360) of the second initial graphic after the two updates is compared with the second graphic quantity threshold (360).

[0165] Since the total number of the second initial graphics after two updates is equal to the threshold number of the second graphics, step S23151d is executed after step S23151c. Specifically, step S23151d involves determining the second initial module group that has been updated twice as a second merged module group.

[0166] In summary, the first to third second baseline partition groups together constitute the first second merge module group.

[0167] Next, the fourth second reference partition group is determined as the current second reference partition group, and a new round of steps S23151a to S23151g is executed. Referring to the example above, ultimately, the fourth to fifth second reference partition groups together form the second second merge module group.

[0168] Next, the sixth second reference partition group is determined as the current second reference partition group, and a new round of steps S23151a to S23151g is executed. Referring to the example above, ultimately, the sixth to seventh second reference partition groups together form the third second merge module group.

[0169] Next, the eighth second reference partition group is determined as the current second reference partition group, and a new round of steps S23151a to S23151g is executed. Figure 7 As shown, since the total amount of the second initial graphics at this time is the eighth total amount of the second graphics (240), after step S23151c, step S23151e is executed. The current second initial module group is the last second reference partition group. Therefore, after step S23151e, step S23151g is executed to determine the last second reference partition group as the fourth second merge module group.

[0170] In conclusion, in Figure 7 In the overall contour boundary B1 shown in (b) and (c), along the first direction, based on steps S23151a to S23151g, the eight second reference partitions are finally combined into four second merged module groups.

[0171] For example, such as Figure 7 As shown in (c), after merging, a total of 16 density partitions are obtained. Among the 5 density partitions with a target pattern count greater than or equal to 100, the difference in the number of patterns between any two density partitions ranges from a maximum of 40 to a minimum of 0, which is within a controllable range. In this way, the number of patterns in the density partitions obtained based on the partitioning method provided in this embodiment is balanced and reasonable, thereby ensuring that the resistor network size of each density partition is relatively uniform. When using EDA back-end verification design tools to calculate integrated circuits, this significantly reduces the phenomenon of excessive peak memory usage and enables the EDA back-end verification design tools to achieve good concurrent acceleration efficiency, solving the problem that the overall performance of EDA back-end verification design tools is affected by excessive peak memory usage.

[0172] It should be noted that, although the above embodiments are mainly based on Figure 8 The following example, scenario (a) 1, is used to illustrate the application. Scenario 1 includes a combination of bottom and top dies, but the scope of this application is not limited to this. In fact, Figure 8 Other scenarios were also shown, such as Figure 8 Scene (b) 2 and Figure 8 Scenario (c) 3. These scenarios may include different grain configurations or structures, achieving the technical effects described in this embodiment. Therefore, the application and implementation of this embodiment can flexibly adapt to a variety of different design requirements and actual situations, aiming to provide broader applicability and flexibility.

[0173] Accordingly, please refer to Figure 9 A block diagram of a netlist extraction device provided in this application embodiment, the device comprising: Boundary determination unit 101 is used to determine the overall contour boundary adapted to the chip based on the projection of multiple dies in the chip onto a preset shared plane; wherein, the multiple dies are stacked in a direction perpendicular to the preset shared plane. Boundary division unit 103 is used to determine the reference partition of the overall contour boundary and to divide the density partition of the overall contour boundary according to the density information of each grain in the reference partition. The netlist extraction unit 105 is used to extract the cell netlist of each grain in each density partition for each density partition. The netlist merging unit 107 is used to merge the extracted netlists of each unit to obtain the chip netlist.

[0174] In some alternative implementations, the netlist extraction unit 105 includes: For each density partition obtained, the cell netlist of each grain in that density partition is extracted based on the graphic information of the pattern falling into that density partition in each grain. In this context, the pattern in a grain represents the metal wiring used for interconnection within that grain; the pattern information indicates the location of the metal wiring represented by the pattern within its respective grain.

[0175] In some alternative implementations, a grain comprises at least one metal layer; the netlist merging unit 107 includes: If there is a pattern with an overlapping region in the boundary layer of any two adjacent grains, then for the two adjacent grains, an associated node and the connection relationship of the associated node are created respectively. The connection relationships and cell netlists are merged into the chip netlist of the chip.

[0176] In some alternative implementations, associated nodes and their connection relationships are obtained in the following ways: At the interface between any two adjacent grains, detect patterns located in different grains but with overlapping regions, and create associated nodes for the geometric center of each pattern. For any two graphs with overlapping areas, establish an electrical connection to represent the interconnection between the coordinate positions of the two graphs, so as to obtain the connection relationship between the graphs.

[0177] In some optional implementations, the boundary determination unit 101 includes: For any grain's projection onto a preset shared plane, determine the offset parameters and boundary parameters of each grain's projection in a specified coordinate system; Based on the offset parameters and boundary parameters, determine the overall contour boundary that fits the chip.

[0178] In some alternative implementations, the overall contour boundary adapted to the chip is determined based on offset parameters and boundary parameters, including: The boundary parameters of each grain are mapped to a specified coordinate system based on the offset parameter to obtain the global boundary coordinate set of each grain; Extract extreme value coordinates from the global boundary coordinate set; The contour region enclosed by the extreme coordinates is defined as the overall contour boundary that fits the chip.

[0179] In some optional implementations, any two reference partitions have the same size but different location information; the boundary partitioning unit 103 includes: For each reference partition, the density of that reference partition is determined based on the number of patterns of each grain within that reference partition. Based on the density of each reference zone, the overall contour boundary is divided to obtain the density zones of the overall contour boundary.

[0180] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0181] In this embodiment, a chip netlist extraction device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0182] Please see Figure 10 , Figure 10 This application provides a schematic diagram of the structure of a computer device, as shown in the embodiment of the present application. Figure 10As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 10 Take a processor 10 as an example.

[0183] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0184] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0185] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0186] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0187] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0188] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0189] The apparatus, module, or unit described in the above embodiments can be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0190] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0191] Those skilled in the art will understand that the embodiments of this application can be provided as methods or apparatus. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0192] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, and devices according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0193] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0194] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0195] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0196] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0197] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0198] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for extracting netlists, characterized in that, The method includes: The overall contour boundary of the chip is determined based on the projection of multiple dies within the chip onto a preset shared plane; wherein the multiple dies are stacked in a direction perpendicular to the preset shared plane. Determine the reference partition of the overall contour boundary, and divide the density partition of the overall contour boundary according to the density information of each grain within the reference partition; For each density partition obtained, the cell netlist of each grain in that density partition is extracted. Based on the extracted unit netlists, the chip netlist of the chip is obtained by merging them.

2. The method according to claim 1, characterized in that, For each density partition obtained, extracting the cell netlist of each grain within that density partition includes: For each density partition obtained, the cell netlist of each grain in the density partition is extracted based on the graphic information of the pattern falling into the density partition in each grain. In this context, a pattern in a grain represents the metal wiring used for interconnection within that grain; the pattern information indicates the location of the metal wiring represented by the pattern within its respective grain.

3. The method according to claim 1, characterized in that, A grain contains at least one metal layer; The process of merging the extracted cell netlists to obtain the chip netlist includes: If there is a pattern with an overlapping region in the interface layer of any two adjacent grains, then for the two adjacent grains, an associated node and the connection relationship of the associated node are created respectively. The connection relationships are merged with the cell netlist to form the chip netlist of the chip.

4. The method according to claim 3, characterized in that, The associated nodes and their connection relationships are obtained in the following way: At the interface layer between any two adjacent grains, detect patterns located in different grains but with overlapping regions, and create associated nodes for the geometric center of each pattern. For any two graphs with overlapping regions, establish an electrical connection to represent the interconnection between the coordinate positions of the two graphs, so as to obtain the connection relationship between the graphs.

5. The method according to claim 1, characterized in that, The determination of the overall contour boundary adapted to the chip includes: For any grain's projection onto a preset shared plane, determine the offset parameters and boundary parameters of each grain's projection in a specified coordinate system; Based on the offset parameter and the boundary parameter, the overall contour boundary adapted to the chip is determined.

6. The method according to claim 5, characterized in that, The step of determining the overall contour boundary adapted to the chip based on the offset parameter and the boundary parameter includes: The boundary parameters of each grain are mapped to the specified coordinate system according to the offset parameter to obtain the global boundary coordinate set of each grain; Extract extreme value coordinates from the global boundary coordinate set; The contour region enclosed by the extreme coordinates is defined as the overall contour boundary adapted to the chip.

7. The method according to claim 1, characterized in that, Any two of the reference partitions have the same size but different positional information; the step of dividing the overall contour boundary into density partitions based on the density information of each grain within the reference partition includes: For each reference partition, the density of the reference partition is determined based on the number of patterns of each grain within that reference partition. Based on the density of each reference partition, the overall contour boundary is divided to obtain the density partition of the overall contour boundary.

8. A netlist extraction device, characterized in that, The device includes: A boundary determination unit is used to determine an overall contour boundary adapted to the chip based on the projection of multiple dies within the chip onto a preset shared plane; wherein the multiple dies are stacked in a direction perpendicular to the preset shared plane; A boundary division unit is used to determine the reference partition of the overall contour boundary and to divide the overall contour boundary into density partitions based on the density information of each grain within the reference partition. The netlist extraction unit is used to extract the cell netlist of each grain in each density partition for each density partition obtained; The netlist merging unit is used to merge the extracted unit netlists to obtain the chip netlist of the chip.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the netlist extraction method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the netlist extraction method according to any one of claims 1 to 7.

Images