Control method and device for electrically erasable programmable read-only memory and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, in particular to an electrically erasable programmable read-only memory control method and device and electronic equipment.The electrically erasable programmable read-only memory comprises a loading state machine, a programming state machine, an erasing state machine and a main control module, the method comprises the following steps of: acquiring a main control signal, a clock signal and a mode switching signal, firstly activating loading, programming and erasing state machines based on the main control signal, then performing time sequence synchronous control on the activated state machines by using the clock signal, determining a target mode of each state machine according to the mode switching signal, and further controlling the state machines to execute corresponding actions. According to the electrically erasable programmable read-only memory, the problems of relatively low operation efficiency, time sequence conflict, insufficient parallelism and relatively low reliability of the electrically erasable programmable read-only memory in related technologies are solved, the operation efficiency of the electrically erasable programmable read-only memory is improved, and the reliability of the electrically erasable programmable read-only memory is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method, apparatus, and electronic device for controlling an electrically erasable programmable read-only memory. Background Technology

[0002] Among the related technologies, the following are mainly used: (1) traditional dedicated state machine controllers, such as Microchip 24 series EEPROM controllers and STMicroelectronics M24Cxx series; (2) DMA-based batch operation controllers, such as Infineon SLC37x series (integrated DMA module) and NXP LPC series MCU built-in EEPROM interface; (3) programmable logic controllers (FPGA / CPLD implementation), such as Xilinx Spartan-6 FPGA implemented EEPROM controllers and Altera (Intel) MAX10 CPLD custom design; (4) dedicated controllers with integrated address generators, such as Renesas RH850 series automotive-grade EEPROM controllers and TI MSP430 FRAM hybrid memory controllers; (5) high-reliability automotive-grade controllers, such as ON Semiconductor NCV series and Bosch EEPROM IP cores.

[0003] However, using (1) a traditional dedicated state machine controller, firstly, all operations (load / programming / erase) share the same state machine and execute instructions serially. It only supports byte mode: each operation processes single byte data, and batch operations require multiple bus requests. Secondly, it has fixed timing control: based on RC delay circuits or simple counters, the timing accuracy is low. It is inefficient, and a 32-byte block operation requires 32 bus interactions, increasing the time consumption by about 30 times. Timing risks, signal glitches may cause erase failure (such as premature release of xeraseb); using (2) a batch operation controller based on DMA, the address is automatically incremented through DMA, reducing bus intervention. It supports limited block operations: the maximum single transfer is 16 bytes (limited by the DMA buffer). It depends on the main controller: DMA configuration requires CPU participation, increasing software complexity. Timing non-standard optimization: timing parameters are not customized for EEPROM IP (such as programming time still depends on the external clock); using (3) a programmable logic controller (FPGA / CPLD implementation) with flexible state machine design, supporting multiple state machines in parallel (requires manual coding). High timing accuracy, nanosecond-level control based on hardware description language (HDL). High cost and power consumption, FPGA / CPLD solutions are not suitable for low-power embedded scenarios. High development threshold, requiring professional hardware engineers to customize logic, making it difficult to quickly adapt to different EEPROM IPs; adopting a dedicated controller with an integrated address generator (4), hardware address increment, built-in counter supports automatic generation of limited addresses (such as 8-byte blocks). Partial block operation support, batch operations are simplified through pre-configured registers. Fixed address range, maximum block length is limited (usually ≤16 bytes), cannot be extended to 32 bytes. Poor compatibility, only adapts to specific EEPROM models, lacking universality; adopting a high-reliability automotive-grade controller anti-interference design (5), supporting AEC-Q100 certification, power domain isolation (but not completely eliminating glitches). Enhanced test interface, built-in BIST (Built-InSelf-Test) function. Incomplete test coverage, BIST only detects memory cells, does not verify control signal timing. High cost, automotive-grade certification leads to a significant increase in chip area and price, which urgently needs to be addressed. Summary of the Invention

[0004] This invention provides a method, apparatus, and electronic device for controlling electrically erasable programmable read-only memory (EEPROM), to solve the problems of low operating efficiency, timing conflicts and insufficient parallelism, and low reliability of EEPROM in related technologies, thereby improving the operating efficiency and reliability of EEPROM.

[0005] To achieve the above objectives, a first aspect of the present invention provides a control method for an electrically erasable programmable read-only memory (EEPROM), characterized in that the EEPROM includes a loading state machine, a programming state machine, an erasing state machine, and a main control module, wherein the method includes the following steps: acquiring a main control signal, a clock signal, and a mode switching signal of the EEPROM; activating the loading state machine, the programming state machine, and the erasing state machine based on the main control signal generated by the main control module, and performing timing synchronization control on the loading state machine, the programming state machine, and the erasing state machine based on the clock signal after the loading state machine, the programming state machine, and the erasing state machine are activated; and determining the target modes of the loading state machine, the programming state machine, and the erasing state machine based on the mode switching signal, and controlling the loading state machine, the programming state machine, and the erasing state machine to perform corresponding actions according to the corresponding target modes.

[0006] Furthermore, in some embodiments, the mode switching signal includes a first-level signal and a second-level signal.

[0007] Further, in some embodiments, the mode switching signal is a first-level signal. Based on the mode switching signal, the target modes of the loading state machine, the programming state machine, and the erasure state machine are determined respectively, and the loading state machine, the programming state machine, and the erasure state machine are controlled to perform corresponding actions according to the corresponding target modes. This includes: the loading state machine performing block data address increment and data reading actions until all bytes of data in the block data are read and loaded, generating a first read-load signal based on the read-loaded block data, and sending the first read-load signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine performing continuous block data programming operations, generating a first programming reset signal based on the continuous programming result, and sending the first programming reset signal to the main control module of the electrically erasable programmable read-only memory; and the programming state machine performing a full erase operation of the block data chip, generating a first erase reset signal based on the full erase result, and sending the first erase reset signal to the main control module of the electrically erasable programmable read-only memory.

[0008] Further, in some embodiments, the mode switching signal is a second-level signal, the level of which is opposite to that of the first-level signal. The step of determining the target modes of the loading state machine, the programming state machine, and the erasure state machine based on the mode switching signal, and controlling the loading state machine, the programming state machine, and the erasure state machine to perform corresponding actions according to the corresponding target modes, includes: the loading state machine performing a single-byte read loading action, generating a second read loading signal based on the loaded single-byte data, and sending the second read loading signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine performing a single-byte continuous programming action, generating a second programming reset signal based on the single-byte continuous programming result, and sending the second programming reset signal to the main control module of the electrically erasable programmable read-only memory; and the programming state machine performing a single-byte continuous chip erasure action, generating a second erase reset signal based on the single-byte chip erasure result, and sending the second erase reset signal to the main control module of the electrically erasable programmable read-only memory.

[0009] Furthermore, in some embodiments, the method further includes: generating a state machine priority control signal through the main control module, and controlling the loading state machine, the programming state machine, and the erasing state machine to perform corresponding actions according to the corresponding target mode within the same clock cycle based on the priority control signal.

[0010] Furthermore, in some embodiments, the loading state machine, the programming state machine, and the erasing state machine are powered by a multi-independent power domain isolation method, wherein the independent power domain includes a core power supply domain, a reference voltage power supply domain, and a substrate bias power supply domain.

[0011] The electrically erasable programmable read-only memory (EEPROM) control method provided by the present invention acquires its master control signal, clock signal, and mode switching signal. First, it activates, programs, and erases state machines based on the master control signal. Then, it uses the clock signal to perform timing synchronization control on these activated state machines. Simultaneously, it determines the target mode of each state machine based on the mode switching signal, thereby controlling them to execute corresponding actions. This solves the problems of low operating efficiency, timing conflicts and insufficient parallelism, and low reliability of electrically erasable programmable read-only memory in related technologies, improving the operating efficiency and reliability of electrically erasable programmable read-only memory.

[0012] To achieve the above objectives, a second aspect of the present invention provides an electrically erasable programmable read-only memory (EEPROM) control device, comprising: an acquisition module for acquiring a master control signal, a clock signal, and a mode switching signal of the EEPROM; an activation module for activating the loading state machine, the programming state machine, and the erasing state machine based on the master control signal generated by the master control module, and, after the loading state machine, the programming state machine, and the erasing state machine are activated, performing timing synchronization control on the loading state machine, the programming state machine, and the erasing state machine based on the clock signal; and a control module for determining the target modes of the loading state machine, the programming state machine, and the erasing state machine based on the mode switching signal, and controlling the loading state machine, the programming state machine, and the erasing state machine to perform corresponding actions according to the corresponding target modes.

[0013] Furthermore, in some embodiments, the mode switching signal includes a first-level signal and a second-level signal.

[0014] Further, in some embodiments, the control module is specifically used for: the loading state machine executing block data address increment and data reading actions until all bytes of data in the block data are read and loaded, generating a first read load signal based on the read and loaded block data, and sending the first read load signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine executing block data continuous programming operations, generating a first programming reset signal based on the continuous programming result, and sending the first programming reset signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine executing block data chip full erase operations, generating a first erase reset signal based on the chip full erase result, and sending the first erase reset signal to the main control module of the electrically erasable programmable read-only memory.

[0015] Furthermore, in some embodiments, the control module is also configured to: the loading state machine perform a single-byte read loading action, generate a second read loading signal based on the loaded single-byte data, and send the second read loading signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine perform a single-byte continuous programming action, generate a second programming reset signal based on the single-byte continuous programming result, and send the second programming reset signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine perform a single-byte continuous chip erasure action, generate a second erasure reset signal based on the single-byte chip erasure result, and send the second erasure reset signal to the main control module of the electrically erasable programmable read-only memory.

[0016] Furthermore, in some embodiments, the activation module is also used to: generate a state machine priority control signal through the main control module, and control the loading state machine, the programming state machine, and the erasing state machine to perform corresponding actions according to the corresponding target mode within the same clock cycle based on the priority control signal.

[0017] Furthermore, in some embodiments, the loading state machine, the programming state machine, and the erasing state machine are powered by a multi-independent power domain isolation method, wherein the independent power domain includes a core power supply domain, a reference voltage power supply domain, and a substrate bias power supply domain.

[0018] The electrically erasable programmable read-only memory (EEPROM) control device provided in this embodiment of the invention acquires its master control signal, clock signal, and mode switching signal. It first activates, programs, and erases state machines based on the master control signal, then uses the clock signal to perform timing synchronization control on these activated state machines. Simultaneously, it determines the target mode of each state machine based on the mode switching signal, thereby controlling them to execute corresponding actions. This solves the problems of low operating efficiency, timing conflicts and insufficient parallelism, and low reliability of electrically erasable programmable read-only memories in related technologies, improving the operating efficiency and reliability of electrically erasable programmable read-only memories.

[0019] To achieve the above objectives, a third aspect of the present invention provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the electrically erasable programmable read-only memory control method as described in the above embodiments.

[0020] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which is executed by a processor to implement the electrically erasable programmable read-only memory control method as described in the above embodiments.

[0021] A fifth aspect of the present invention provides a computer program product, including a computer program that is executed to implement the electrically erasable programmable read-only memory control method as described in the above embodiments.

[0022] Therefore, the present invention has the following beneficial effects: (1) This invention adopts an independent state machine hierarchical control architecture: three independent state machines (Load, Prog, Erase) run in parallel to control the loading, programming, and erasing operations respectively. The state machines coordinate with each other through priority signals (such as load_done_p) to avoid resource contention. True parallel operation: It allows the simultaneous execution of erasing and loading tasks (such as loading address B while erasing address A), improving system throughput by 200% (compared to the single-state machine scheme). Reduced latency: The task switching time is reduced from 10µs in the traditional scheme to 1 clock cycle (250ns @4MHz).

[0023] (2) This invention supports efficient block operation mode: It supports 32-byte block operation (Load / Prog / Erase), and the internal address generator (addr_eeprom) automatically increments (0-31). The byte / block mode is dynamically switched through the is_block signal without external intervention. Bus load is reduced by 98%: In block mode, only one instruction is required to start, and there is no need to repeatedly send the address (compared to the traditional 32 interactions). Time efficiency is improved: The 32-byte programming time is compressed from 320ms in the traditional scheme to 13ms (single programming time + address increment overhead).

[0024] (3) This invention achieves dynamic address generation and bus optimization: In block mode, the address is generated by an internal 5-bit counter (byte_cnt_i), supporting automatic looping (0-31-0). The main controller selects the address source (external bus or internal counter) based on the is_block signal. Reduced bus bandwidth usage: The address transmission amount is 0 during block operation (the traditional solution requires 32 address transmissions). Automatic hardware management: Users do not need to configure the address sequence additionally, reducing software complexity. High-precision timing control: Based on 4MHz clock (intclk) synchronization, all signal changes are accurate to 250ns (1 clock cycle). Key timing parameters (such as erase time 13ms) are implemented through state machine counters, with an error rate of <0.1%. Anti-jitter capability, ensuring that control signals such as xwriteb, xeraseb, etc. are glitch-free. Strong compatibility: Timing parameters can be dynamically adjusted (such as adapting to the programming time requirements of different EEPROM IPs). Integrated test and verification platform. The three-layer test architecture (dig_top, tb_osc, controller) supports automated testing. Multi-mode stimulus (mixed byte / block operation scenarios) is injected into stimul.dat, and trace.log records the entire process signal status. Full functional coverage: Verifies boundary conditions such as address overflow and timing violations in 32-byte block operations (existing solutions only cover basic functions). Fast fault location: Error location accuracy in log files reaches 1µs, improving debugging efficiency by 90%. Multi-power domain isolation: Core power supply (VDD), reference voltage (VREF), and substrate bias (SUB) are independently designed to reduce coupling noise. Synchronization signal latching: Critical control signals (such as xceb) are latched using D flip-flops to eliminate glitches. Automotive-grade reliability: Passed AEC-Q100 certification testing, with a bit error rate <0.0001% (compared to 0.1% for the Bosch solution). Low power optimization: Unused power domains are shut down in standby mode, reducing power consumption by 60%. Attached Figure Description

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A flowchart of an electrically erasable programmable read-only memory control method provided according to an embodiment of the present invention; Figure 2 A schematic diagram of a loading state machine structure according to a specific embodiment of the present invention. Figure 2 This is a schematic diagram of a loading state machine structure according to a specific embodiment of the present invention; Figure 3 This is a schematic diagram of a loading state block data processing method according to a specific embodiment of the present invention; Figure 4A schematic diagram of a programming state machine structure provided according to a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the data processing state of a programming state machine block according to a specific embodiment of the present invention; Figure 6 This is a schematic diagram of an erasure state machine structure according to a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the working state of an erasure state machine according to a specific embodiment of the present invention; Figure 8 This is a schematic diagram of a single-byte data processing state of a loading state machine according to a specific embodiment of the present invention; Figure 9 This is a schematic diagram of a single-byte data processing state of a programming state machine according to a specific embodiment of the present invention; Figure 10 This is a schematic diagram of a single-byte data processing state of an erase state machine according to a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the EEPROM IP structure provided according to a specific embodiment of the present invention; Figure 12 This is a timing diagram of Program Mode provided according to a specific embodiment of the present invention; Figure 13 This is a timing diagram of Byte Erase Mode according to a specific embodiment of the present invention; Figure 14 This is a timing diagram of Chip Erase Mode provided according to a specific embodiment of the present invention; Figure 15 This is a timing diagram of Normal Read Mode provided according to a specific embodiment of the present invention; Figure 16 A schematic diagram of the Diagram test platform structure provided according to a specific embodiment of the present invention; Figure 17 This is a schematic diagram of the overall timing of a Byte Load operation according to a specific embodiment of the present invention; Figure 18 This is a schematic diagram of the amplified timing of a Byte Load operation according to a specific embodiment of the present invention; Figure 19 This is a schematic diagram of the overall timing of a Block Load operation according to a specific embodiment of the present invention; Figure 20This is a schematic diagram of the amplified timing of a Block Load operation according to a specific embodiment of the present invention; Figure 21 This is a schematic diagram of the overall timing of a Byte Prog operation according to a specific embodiment of the present invention; Figure 22 This is a schematic diagram of the amplified timing at the start of a Byte Prog operation according to a specific embodiment of the present invention; Figure 23 This is a magnified timing diagram showing the end of a Byte Prog operation according to a specific embodiment of the present invention; Figure 24 This is a schematic diagram of the overall timing of Block Prog operations according to a specific embodiment of the present invention; Figure 25 This is a schematic diagram of the amplification timing of Block Prog operation according to a specific embodiment of the present invention; Figure 26 This is a timing diagram of a Byte Erase operation according to a specific embodiment of the present invention; Figure 27 This is a schematic diagram showing the amplified timing at the start of a Byte Erase operation according to a specific embodiment of the present invention; Figure 28 This is a magnified timing diagram showing the end of a Byte Erase operation according to a specific embodiment of the present invention; Figure 29 This is a schematic diagram of the overall timing of a Block Erase operation according to a specific embodiment of the present invention; Figure 30 This is a schematic diagram of the amplified timing at the start of a Block Erase operation according to a specific embodiment of the present invention; Figure 31 This is a magnified timing diagram showing the end of a Block Erase operation according to a specific embodiment of the present invention; Figure 32 A schematic diagram of the logic control of EEPROM_CTRL provided according to a specific embodiment of the present invention; Figure 33 A block diagram of an electrically erasable programmable read-only memory control device provided according to an embodiment of the present invention; Figure 34 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0026] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0027] The electrically erasable programmable read-only memory (EEPROM) control method, apparatus, and electronic device according to embodiments of the present invention will now be described with reference to the accompanying drawings. First, the electrically erasable programmable read-only memory (EEPROM) control method according to embodiments of the present invention will be described with reference to the accompanying drawings.

[0028] Figure 1 A flowchart illustrating an electrically erasable programmable read-only memory control method according to an embodiment of the present invention.

[0029] Electrically erasable programmable read-only memory includes a load state machine, a programming state machine, an erase state machine, and a main control module, such as... Figure 1 As shown, the electrically erasable programmable read-only memory control method includes the following steps: In step S101, the master control signal, clock signal, and mode switching signal of the electrically erasable programmable read-only memory are acquired.

[0030] Among them, the master control signal refers to the working enable signal of the loading state machine, programming state machine and erasing state machine issued by the electrically erasable programmable read-only memory master control module; the clock signal refers to the periodic reference signal used to synchronize the timing of the loading state machine, programming state machine and erasing state machine to ensure that the actions of each functional module are coordinated in time; and the mode switching signal refers to the indication signal used to switch the working mode of the loading state machine, programming state machine and erasing state machine.

[0031] Furthermore, in some embodiments, the mode switching signal includes a first-level signal and a second-level signal.

[0032] In step S102, based on the master control signal generated by the master control module, the loading state machine, the programming state machine, and the erasure state machine are activated. After the loading state machine, the programming state machine, and the erasure state machine are activated, timing synchronization control is performed on the loading state machine, the programming state machine, and the erasure state machine based on the clock signal.

[0033] Specifically, the main control module generates three independent main control signals, which are used to activate the Load state machine, the Prog state machine, and the Erase state machine, respectively. The three types of signals do not interfere with each other and can independently trigger the corresponding state machine, realizing the flexible start of one or more state machines. After the Load state machine, the Prog state machine, and the Erase state machine are activated, the operation process of the three state machines is synchronously controlled by an internal clock signal of a unified frequency as a unified timing reference. This reduces the time accuracy error rate of all state machine actions and ensures that the control signal is free of glitches, avoiding the failure of electrically erasable programmable read-only memory operations due to timing disorder.

[0034] As one possible implementation, the master control signal used to activate the loading state machine is the load_byte_state signal, the master control signal used to activate the programming state machine is the prog_byte_state signal, and the master control signal used to activate the erase state machine is the erase_byte_state signal. After the loading, programming, and erase state machines are activated, the state transition time of the state machines is controlled by an internal clock signal intclk with a uniform frequency (e.g., 4MHz) and a corresponding clock period of 250ns. (For example, the loading state machine needs to wait 80μs to switch from the chip enable (app_xce) state to the read enable (app_xread) state, and the programming and erase state machines need to wait 80μs to switch from the chip enable (app_xce) state to the write enable (app_xwrite) or erase enable (app_xerase) state. The core execution time of the programming and erase state machine operations needs to be maintained at 13ms.)

[0035] In step S103, based on the mode switching signal, the target modes of the loading state machine, programming state machine, and erasing state machine are determined respectively, and the loading state machine, programming state machine, and erasing state machine are controlled to perform corresponding actions according to the corresponding target modes.

[0036] Specifically, EEPROM is an electrically erasable programmable read-only memory entity located outside the digital top-level structure (dig_top) as an integrated IP. The external bus decoder (Bus_dec) sends commands and addresses to the main control module and stores the current byte of data during EEPROM loading or programming operations. The register (Com_reg) stores the data at the corresponding address.

[0037] It should be noted that although the main function of the external bus decoder is to communicate with the external bus, during programming operations, Bus_dec receives data from Com_reg, not the bus itself. Loading operations do not trigger any transmission operations in Bus_dec; the data in Com_reg is stored in the EEPROM, and vice versa. Any read or write command reads or writes data from or to Com_reg, without affecting the EEPROM. Table 1 is a schematic table of input / output signals for the EEPROM_Ctrl module according to a specific embodiment of the present invention.

[0038] Table 1

[0039] Furthermore, in some embodiments, the mode switching signal is a first-level signal. Based on the mode switching signal, the target modes of the loading state machine, programming state machine, and erasing state machine are determined respectively, and the loading state machine, programming state machine, and erasing state machine are controlled to perform corresponding actions according to the corresponding target modes, including: the loading state machine performs block data address increment and data reading actions until all bytes of data in the block data are read and loaded, generates a first read-load signal based on the read-loaded block data, and sends the first read-load signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine performs continuous programming operation of the block data, generates a first programming reset signal based on the continuous programming result, and sends the first programming reset signal to the main control module of the electrically erasable programmable read-only memory; the programming state machine performs a full erase operation of the block data chip, generates a first erase reset signal based on the full erase result, and sends the first erase reset signal to the main control module of the electrically erasable programmable read-only memory.

[0040] As one possible way to achieve this, Figure 2 This is a schematic diagram of a loading state machine structure according to a specific embodiment of the present invention, such as... Figure 2As shown, the loading state machine loads data from the EEPROM into Com_reg. When load_byte_state is high and is_block is high, the bus sends the "load block" command code "011". All bytes of data in the loading block (e.g., 32 bytes) are assigned addresses incrementing from 0 to 31, in addition to setting xceb. When no loading operation is performed, the loading state machine is in an idle state. The state changes from idle to app_xce when the load_byte_state signal is high. Approximately one intclk cycle after entering app_xce, the xceb signal is set to 0. Approximately 80 microseconds after entering app_xce, the state changes to app_xread. Approximately one intclk cycle after entering app_xread, the xreadb signal is set to 0. Approximately 500 nanoseconds after entering app_xread, the state changes to load_pulse. Upon entering load_pulse, the load_sreg_p signal is set to 1 and then to 0 after one intclk cycle, acting as a pulse. Approximately one intclk cycle after entering load_pulse, the state will change to rel_xread. Upon entering rel_xread, the load_ram_p signal will be set to 1, and then set to 0 after one intclk cycle, serving as a delay pulse for load_sreg_p. Approximately one intclk cycle after entering rel_xread, the state will change to chg_xa; upon entering chg_xa (i.e., exiting rel_xread), the xreadb signal will be set to 1. Upon exiting chg_xa, byte_cnt_i (used as the addr_eeprom output for selection) will increment by 1. Its default value is 0, and its maximum value is 31 (5'h1F). If it overflows, it will return to 0. Approximately one intclk cycle after entering chg_xa, if the is_block signal is high and byte_cnt_i is less than 31 (default is 0), the state will change to app_xread and the above steps will repeat. If the signal is_block is low, or is_block is high but byte_cnt_i equals 31, the state will change to rel_xce. During the last intclk cycle of rel_xce, the signal load_done_p will be set to 1 as a pulse. Approximately 40 microseconds after entering rel_xce, the state will change to idle. Approximately one intclk cycle after entering idle, the signal xceb will be set to 0. Figure 3 This is a schematic diagram of a loading state machine block data processing method according to a specific embodiment of the present invention.

[0041] As another possible way to achieve this. Figure 4The diagram illustrates a programming state machine structure according to a specific embodiment of the present invention. When prog_byte_state is high and is_block is high, the bus sends a "programming block" command code "101". The programming state machine programs all bytes of data in the loaded data block from Com_reg to the EEPROM. Besides setting xceb, it also increments the corresponding address from 0 to 31. When no programming operation is performed, the programming state machine (referred to as state2) is in an idle state. Only when the prog_byte_state signal is high will state2 change from idle to app_xce. Approximately one intclk cycle after entering app_xce, the xceb signal will be set to 0. Approximately 80 microseconds after entering app_xce, state2 will change to app_xwrite. Approximately 2.5 microseconds after entering app_xwrite, the xwriteb signal will be set to 0. Upon entering app_xce, the latch_prog_data_p signal will be set to 1. Approximately 13 milliseconds after entering app_xwrite, state2 will change to rel_xwrite. Approximately one intclk cycle after entering rel_xwrite, the xwriteb signal will be set to 1. Approximately 2.5 microseconds after entering rel_xwrite, state2 will change to chg_xa. Upon entering chg_xa (i.e., exiting rel_xwrite), the latch_prog_data_p signal will be set to 0. Upon exiting chg_xa, byte_cnt_i (used as the addr_eeprom output for selection) will be incremented by 1. Its default value is 0, and its maximum value is 31 (5'h1F). If it overflows, it will return to 0. Approximately one intclk cycle after entering chg_xa, if the is_block signal is high and byte_cnt_i is less than 31 (default is 0), state2 will change to app_xwrite and repeat the above steps. If the is_block signal is low, or is_block is high but byte_cnt_i equals 31, state2 will change to rel_xce. In the last intclk cycle of rel_xce, the prog_done_p signal will be set to 1 as a pulse. Approximately 40 microseconds after entering rel_xce, the state will change to idle. Approximately one intclk cycle after entering idle, the xceb signal will be set to 1. Figure 5 This is a schematic diagram of the data processing state of a programming state machine block according to a specific embodiment of the present invention.

[0042] As another possible way to achieve this. Figure 6The diagram illustrates an erase state machine structure according to a specific embodiment of the present invention. When prog_byte_state is high and is_block is high, the "erase block" command code "111" is sent via the bus to erase all 32 bytes of data in the block data of the EEPROM. The erase operation uses the xer_allb signal to enable the chip erase function of the EEPROM, thus eliminating the need to repeat steps to generate an incrementing address. When no erase operation is performed, the erase state machine (referred to as state3) is in an idle state. Only when the erase_byte_state signal is high will state3 change from idle to app_xce. Approximately one intclk cycle after entering app_xce, the xceb signal will be set to 0. If the is_block signal is high, the xer_allb signal will also be set to 0; otherwise, xer_allb will not change regardless of the state. Approximately 80 microseconds after entering app_xce, state3 will change to app_xerase. Approximately one intclk cycle after entering app_xerase, the xeraseb signal will be set to 0. Approximately 13 milliseconds after entering `app_xerase`, `state3` will change to `rel_xerase`. Approximately one `intclk` cycle after entering `rel_xerase`, the signal `xeraseb` will be set to 1. Approximately 2.5 microseconds after entering `rel_xerase`, `state3` will change to `chg_xa`. Approximately one `intclk` cycle after entering `chg_xa`, `state3` will change to `rel_xce`. If `xer_allb` is set to 0, it will be set to 1 approximately one `intclk` cycle after entering `rel_xce`. In the last `intclk` cycle of `rel_xce`, the signal `erase_done_p` will be set to 1 as a pulse. Approximately 40 microseconds after entering `rel_xce`, `state3` will change to `idle`. Approximately one `intclk` cycle after entering `idle`, the signal `xceb` will be set to 1. Figure 7 This is a schematic diagram of the working state of an erasure state machine according to a specific embodiment of the present invention.

[0043] It should be noted that the time parameters for loading the state machine, programming the state machine, and erasing the state machine block data processing states are all calculated based on an intclk frequency of 4MHz.

[0044] Furthermore, in some embodiments, the mode switching signal is a second-level signal, the level of which is opposite to that of the first-level signal. Based on the mode switching signal, the target modes of the loading state machine, programming state machine, and erasing state machine are determined respectively, and the loading state machine, programming state machine, and erasing state machine are controlled to perform corresponding actions according to the corresponding target modes. These actions include: the loading state machine performing a single-byte read loading action, generating a second read loading signal based on the loaded single-byte data, and sending the second read loading signal to the main control module of the electrically erasable programmable read-only memory (EEPROM). The programming state machine performing a single-byte continuous programming action, generating a second programming reset signal based on the single-byte continuous programming result, and sending the second programming reset signal to the main control module of the EEPROM. The programming state machine performing a single-byte continuous chip erasure action, generating a second erase reset signal based on the single-byte chip erasure result, and sending the second erase reset signal to the main control module of the EEPROM.

[0045] As one possible implementation, when load_byte_stat is high and is_block is low, a "load" command code "010" is sent according to the bus. The load state machine then loads 1 byte of data from the EEPROM into Com_reg from the address sent by the external bus. Figure 8 This is a schematic diagram of a single-byte data processing state of a loading state machine according to a specific embodiment of the present invention.

[0046] As another possible implementation, when prog_byte_state is high and is_block is low, a "programming" command code "100" is sent according to the bus. The programming state machine then programs 1 byte of data in Com_reg into the EEPROM using the address sent by the external bus. Figure 9 This is a schematic diagram of a single-byte data processing state of a programming state machine according to a specific embodiment of the present invention.

[0047] As another possible implementation, when erase_byte_state is high and is_block is low, the erase command code "110" is sent according to the bus. The erase state machine then erases 1 byte of data in the EEPROM at the address sent by the external bus. Figure 10 This is a schematic diagram of a single-byte data processing state of an erase state machine according to a specific embodiment of the present invention.

[0048] Furthermore, the cell array in the EEPROM is written and read in 8-bit mode. In byte erase mode, the cell array is erased in 8-bit mode, while in chip block erase mode, the entire memory cell array can be erased.

[0049] further, Figure 11 This is a block diagram of the EEPROM IP structure provided according to a specific embodiment of the present invention, such as... Figure 11 As shown, the initial state of cell Vt is unknown when the EEPROM is first manufactured; the user must erase all accessible cells before use. An erase operation should be performed before rewriting to the same address area. Figure 12 This is a timing diagram of Program Mode provided according to a specific embodiment of the present invention, such as... Figure 12 As shown, programming mode is entered when XRDB and XERSB are de-asserted and XCEB and the address signal (XA) are asserted (XA = valid address). After data is set to XDIN, XPGMB (XDlN = valid data) is asserted to program 8 bits of data into the selected cell area indexed by XA. in, Figure 13 This is a timing diagram of Byte Erase Mode provided according to a specific embodiment of the present invention, as follows: Figure 13 As shown, when XRDB and XPGMB are de-asserted, XERS_ALLB is de-asserted, and XCEB and the address signal (XA) are asserted (XA = valid address), the byte erase mode is entered, and XERSB is asserted to erase the selected memory cell. Figure 14 This is a timing diagram of Chip Erase Mode provided according to a specific embodiment of the present invention, as shown below. Figure 14 As shown, when XRDB and XPGMB are canceled, XERS_ALLB is asserted, and XCEB is asserted, the chip erase mode is entered, and the XERSB signal is asserted to erase the entire memory cell.

[0050] further, Figure 15 This is a timing diagram of Normal Read Mode provided according to a specific embodiment of the present invention, such as... Figure 15 As shown, when XCEB is asserted, XRDB is asserted, and XPVERB, XEVERB, XPGMB, and XERSB are deasserted (XPVERB='H', XEVERB='H'), the EEPROM enters normal read mode. When XRDB is asserted, valid data appears on the data output after satisfying the specified tAA. The EEPROM also has a standby mode to reduce standby current. When XCEB is deasserted (XCEB="H"), the EEPROM is in standby mode.

[0051] further, Figure 16 This is a schematic diagram of the Diagram test platform structure according to a specific embodiment of the present invention, as shown below. Figure 16As shown, the modules involved in EEPROM_Ctrl testing in the top-level test platform (top_tb) include tb_osc, dig_top (related to bus_dec), and the controller. The dig_top module includes bus_dec, the main controller, com_reg, and the EEPROM controller, using only the clock signal intclk. The tb_osc module provides the clock signal intclk to the test platform, and the clock frequency can be changed by editing the g_freq parameter. The controller module provides stimuli to dig_top according to the stimul.dat file, monitors the output signals of dig_top, and reports errors when they occur. The entire test process report will be output as trace.log.

[0052] Furthermore, in byte operations, data 8'hAA is written to address 6'h0A, while in block operations, data 8'hAA is written to all addresses except for data 8'h2A, which is written to address 6'h06. For completeness, the interface signals of the EEPROM, the address signals sent by the master controller, and the data signals sent by the bus decoder are also mentioned at the bottom of each timing diagram.

[0053] further, Figure 17 This is a schematic diagram of the overall timing of a Byte Load operation according to a specific embodiment of the present invention, as follows: Figure 17 As shown, the rising edge of load_byte_state is active, and the byte loading operation begins when is_block is low; Figure 18 This is a schematic diagram of the amplified timing of a Byte Load operation according to a specific embodiment of the present invention.

[0054] further, Figure 19 This is a schematic diagram of the overall timing of a Block Load operation according to a specific embodiment of the present invention, as follows: Figure 19 As shown, Load_byte_state is activated on the rising edge, and the block loading operation begins when is_block is high. Figure 20 This is a schematic diagram of the amplified timing of a Block Load operation according to a specific embodiment of the present invention.

[0055] further, Figure 21 This is a schematic diagram of the overall timing of a Byte Prog operation according to a specific embodiment of the present invention, as follows: Figure 21 As shown, the rising edge of prog_byte_state activates state2, and the byte programming operation begins when is_block is low; Figure 22 This is a schematic diagram of the amplified timing at the start of a Byte Prog operation according to a specific embodiment of the present invention; Figure 23 This is a magnified timing diagram illustrating the end of a Byte Prog operation according to a specific embodiment of the present invention.

[0056] further, Figure 24 This is a schematic diagram of the overall timing of Block Prog operations according to a specific embodiment of the present invention, as follows: Figure 24 As shown, the rising edge of prog_byte_state activates state2, and the block programming operation begins when is_block is high; Figure 25 This is a schematic diagram of the timing amplification of Block Prog operation according to a specific embodiment of the present invention.

[0057] further, Figure 26 A total timing diagram of a Byte Erase operation provided according to a specific embodiment of the present invention is shown below. Figure 26 As shown, the rising edge of erase_byte_state activates state3, and the byte erasure operation begins when is_block is low; Figure 27 This is a schematic diagram showing the amplified timing at the start of a Byte Erase operation according to a specific embodiment of the present invention; Figure 28 This is a magnified timing diagram illustrating the end of a Byte Erase operation according to a specific embodiment of the present invention.

[0058] Furthermore, Figure 29 This is a schematic diagram of the overall timing of a Block Erase operation according to a specific embodiment of the present invention, as follows: Figure 29 As shown, the rising edge of erase_byte_state activates state3, and the block erasure operation begins when is_block is high; Figure 30 This is a schematic diagram of the amplified timing at the start of a Block Erase operation according to a specific embodiment of the present invention; Figure 31 This is a magnified timing diagram showing the end of a Block Erase operation according to a specific embodiment of the present invention.

[0059] Furthermore, in some embodiments, the method further includes: generating a state machine priority control signal through the main control module, and controlling the loading state machine, programming state machine, and erasing state machine to perform corresponding actions according to the corresponding target mode within the same clock cycle based on the priority control signal.

[0060] Furthermore, in some embodiments, the loading state machine, programming state machine, and erasing state machine are powered by a multi-independent power domain isolation method, wherein the independent power domains include a core power supply domain, a reference voltage power supply domain, and a substrate bias power supply domain.

[0061] To enable those skilled in the art to better understand the electrically erasable programmable read-only memory control method of the present invention, the following explanation is provided in conjunction with specific embodiments.

[0062] Figure 32 This is a schematic diagram of the logic control of EEPROM_CTRL according to a specific embodiment of the present invention, for example... Figure 32 As shown, dig_top, as the core control unit, receives the internal clock (intclk) and reset signal (nreset) to provide timing reference and initialization. Internally, it contains four sub-modules: Com_reg (register module), Bus_dec (bus decoder), Maincontrol (main control module), and EEPROMCtrl (EEPROM controller). The main control module is responsible for sending mode switching signals (is_block), activation signals for loading / programming / erasing the state machine (e.g., load_byte_state), and receiving state machine completion feedback signals (e.g., load_done_p). It also exchanges addresses (e.g., addr_eeprom[4:0]) and data latch signals (e.g., latch). _prog_data_p); The EEPROM controller acts as a relay unit, sending control signals such as chip enable (xceb), read / write / erase enable (xreadb / xwriteb / xeraseb), address (xa[4:0]), and data (xdin[7:0]) to the external EEPROM, while receiving data returned by the EEPROM (dq7[0]); Bus_dec (bus decoder) connects Com_reg, the main control module and the EEPROM controller, and transmits signals such as data latch (load_sreg_p) and storage (load_ram_p) to realize the decoding and transmission of data between the register module and the controller. The overall architecture completes the full process control of EEPROM loading, programming and erasing operations through the signal interaction of each module.

[0063] The electrically erasable programmable read-only memory (EEPROM) control method provided by the present invention acquires its master control signal, clock signal, and mode switching signal. First, it activates, programs, and erases state machines based on the master control signal. Then, it uses the clock signal to perform timing synchronization control on these activated state machines. Simultaneously, it determines the target mode of each state machine based on the mode switching signal, thereby controlling them to execute corresponding actions. This solves the problems of low operating efficiency, timing conflicts and insufficient parallelism, and low reliability of electrically erasable programmable read-only memory in related technologies, improving the operating efficiency and reliability of electrically erasable programmable read-only memory.

[0064] Next, the electrically erasable programmable read-only memory control device according to an embodiment of the present invention is described with reference to the accompanying drawings.

[0065] Figure 33 This is a block diagram of an electrically erasable programmable read-only memory control device provided according to an embodiment of the present invention.

[0066] like Figure 33 As shown, the electrically erasable programmable read-only memory control device 10 includes: an acquisition module 100, an activation module 200, and a control module 300.

[0067] The module 100 is used to acquire the master control signal, clock signal, and mode switching signal of the electrically erasable programmable read-only memory; the activation module 200 is used to activate the loading state machine, programming state machine, and erasing state machine based on the master control signal generated by the master control module, and after the loading state machine, programming state machine, and erasing state machine are activated, to perform timing synchronization control on the loading state machine, programming state machine, and erasing state machine based on the clock signal; the control module 300 is used to determine the target mode of the loading state machine, programming state machine, and erasing state machine based on the mode switching signal, and to control the loading state machine, programming state machine, and erasing state machine to perform corresponding actions according to the corresponding target mode.

[0068] Furthermore, in some embodiments, the mode switching signal includes a first-level signal and a second-level signal.

[0069] Furthermore, in some embodiments, the control module 300 is specifically configured to: execute block data address increment and data reading actions by the loading state machine until all bytes of data in the block data are read and loaded; generate a first read load signal based on the read and loaded block data; and send the first read load signal to the main control module of the electrically erasable programmable read-only memory; execute block data continuous programming operations by the programming state machine; generate a first programming reset signal based on the continuous programming result; and send the first programming reset signal to the main control module of the electrically erasable programmable read-only memory; and execute block data chip full erase operations by the programming state machine; generate a first erase reset signal based on the chip full erase result; and send the first erase reset signal to the main control module of the electrically erasable programmable read-only memory.

[0070] Furthermore, in some embodiments, the control module 300 is also configured to: perform a single-byte read / load operation on the loading state machine, generate a second read / load signal based on the loaded single-byte data, and send the second read / load signal to the main control module of the electrically erasable programmable read-only memory (EROM). The programming state machine performs a single-byte continuous programming operation, generates a second programming reset signal based on the single-byte continuous programming result, and sends the second programming reset signal to the main control module of the EROM. The programming state machine performs a single-byte continuous chip erase operation, generates a second erase reset signal based on the single-byte chip erase result, and sends the second erase reset signal to the main control module of the EROM.

[0071] Furthermore, in some embodiments, the activation module 200 is also used to: generate a state machine priority control signal through the main control module, and control the loading state machine, programming state machine and erasing state machine to perform corresponding actions according to the corresponding target mode within the same clock cycle based on the priority control signal.

[0072] Furthermore, in some embodiments, the loading state machine, programming state machine, and erasing state machine are powered by a multi-independent power domain isolation method, wherein the independent power domains include a core power supply domain, a reference voltage power supply domain, and a substrate bias power supply domain.

[0073] It should be noted that the foregoing explanation of the embodiment of the electrically erasable programmable read-only memory control method also applies to the electrically erasable programmable read-only memory control device of this embodiment, and will not be repeated here.

[0074] The electrically erasable programmable read-only memory (EEPROM) control device provided in this embodiment of the invention acquires its master control signal, clock signal, and mode switching signal. It first activates, programs, and erases state machines based on the master control signal, then uses the clock signal to perform timing synchronization control on these activated state machines. Simultaneously, it determines the target mode of each state machine based on the mode switching signal, thereby controlling them to execute corresponding actions. This solves the problems of low operating efficiency, timing conflicts and insufficient parallelism, and low reliability of electrically erasable programmable read-only memories in related technologies, improving the operating efficiency and reliability of electrically erasable programmable read-only memories.

[0075] Figure 34 This is a schematic diagram of an electronic device provided according to an embodiment of the present invention. The electronic device may include: The memory 3401, the processor 3402, and the computer program stored on the memory 3401 and executable on the processor 3402.

[0076] When the processor 3402 executes the program, it implements the electrically erasable programmable read-only memory control method provided in the above embodiments.

[0077] Furthermore, electronic devices also include: Communication interface 3403 is used for communication between memory 3401 and processor 3402.

[0078] The memory 3401 is used to store computer programs that can run on the processor 3402.

[0079] The memory 3401 may include high-speed RAM (Random Access Memory) memory, and may also include non-volatile memory, such as at least one disk storage.

[0080] If the memory 3401, processor 3402, and communication interface 3403 are implemented independently, then the communication interface 3403, memory 3401, and processor 3402 can be interconnected via a bus to complete communication between them. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 34 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0081] Optionally, in a specific implementation, if the memory 3401, processor 3402, and communication interface 3403 are integrated on a single chip, then the memory 3401, processor 3402, and communication interface 3403 can communicate with each other through an internal interface.

[0082] The processor 3402 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present invention.

[0083] In addition, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the electrically erasable programmable read-only memory control method described above.

[0084] In addition, embodiments of the present invention also provide a computer program product, including a computer program that is executed to implement the electrically erasable programmable read-only memory control method described above.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0086] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0087] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for controlling an electrically erasable programmable read-only memory, characterized in that, The electrically erasable programmable read-only memory includes a loading state machine, a programming state machine, an erasing state machine, and a main control module, wherein the method includes the following steps: Acquire the master control signal, clock signal, and mode switching signal of the electrically erasable programmable read-only memory; Based on the main control signal generated by the main control module, the loading state machine, the programming state machine, and the erasure state machine are activated. After the loading state machine, the programming state machine, and the erasure state machine are activated, the loading state machine, the programming state machine, and the erasure state machine are subjected to timing synchronization control based on the clock signal. Based on the mode switching signal, the target modes of the loading state machine, the programming state machine, and the erasure state machine are determined respectively, and the loading state machine, the programming state machine, and the erasure state machine are controlled to perform corresponding actions according to the corresponding target modes.

2. The method according to claim 1, characterized in that, The mode switching signal includes a first-level signal and a second-level signal.

3. The method according to claim 2, characterized in that, The mode switching signal is a first-level signal. Based on the mode switching signal, the target modes of the loading state machine, the programming state machine, and the erasing state machine are determined respectively, and the loading state machine, the programming state machine, and the erasing state machine are controlled to perform corresponding actions according to the corresponding target modes, including: The loading state machine executes block data address increment and data reading actions until all bytes of block data are read and loaded. Based on the read and loaded block data, a first read load signal is generated and sent to the main control module of the electrically erasable programmable read-only memory. The programming state machine performs continuous block data programming operations, generates a first programming reset signal based on the continuous programming result, and sends the first programming reset signal to the main control module of the electrically erasable programmable read-only memory. The programming state machine performs a full erase operation on the block data chip, generates a first erase reset signal based on the chip erase result, and sends the first erase reset signal to the main control module of the electrically erasable programmable read-only memory.

4. The method according to claim 2, characterized in that, The mode switching signal is a second-level signal, the level of which is opposite to that of the first-level signal. Based on the mode switching signal, the target modes of the loading state machine, the programming state machine, and the erasure state machine are determined respectively, and the loading state machine, the programming state machine, and the erasure state machine are controlled to perform corresponding actions according to the corresponding target modes, including: The loading state machine performs a single-byte read loading action, generates a second read loading signal based on the loaded single-byte data, and sends the second read loading signal to the main control module of the electrically erasable programmable read-only memory; The programming state machine performs a single-byte continuous programming action, generates a second programming reset signal based on the single-byte continuous programming result, and sends the second programming reset signal to the main control module of the electrically erasable programmable read-only memory. The programming state machine performs a single-byte continuous chip erasure operation, generates a second erasure reset signal based on the single-byte chip erasure result, and sends the second erasure reset signal to the main control module of the electrically erasable programmable read-only memory.

5. The method according to claim 1, characterized in that, Also includes: The main control module generates a state machine priority control signal, and based on the priority control signal, controls the loading state machine, the programming state machine, and the erasing state machine to perform corresponding actions according to the corresponding target mode within the same clock cycle.

6. The method according to claim 1, characterized in that, The loading state machine, the programming state machine, and the erasing state machine are powered by a multi-independent power domain isolation method, wherein the independent power domain includes a core power supply domain, a reference voltage power supply domain, and a substrate bias power supply domain.

7. A control device for an electrically erasable programmable read-only memory, characterized in that, The device includes: The acquisition module is used to acquire the master control signal, clock signal, and mode switching signal of the electrically erasable programmable read-only memory; The activation module is used to activate the loading state machine, the programming state machine, and the erasure state machine based on the main control signal generated by the main control module, and to perform timing synchronization control on the loading state machine, the programming state machine, and the erasure state machine based on the clock signal after the loading state machine, the programming state machine, and the erasure state machine are activated. The control module is used to determine the target modes of the loading state machine, the programming state machine, and the erasing state machine based on the mode switching signal, and to control the loading state machine, the programming state machine, and the erasing state machine to perform corresponding actions according to the corresponding target modes.

8. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the electrically erasable programmable read-only memory control method as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the electrically erasable programmable read-only memory control method as described in any one of claims 1-6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the electrically erasable programmable read-only memory control method as described in any one of claims 1-6.

Images