Parallel read operation speed test circuit, parallel read operation speed test method and chip
By combining a multiplexer and SPI interface circuit with the SPI interface and read commands of NOR flash, the complexity of testing the parallel read operation speed of EF flash was solved, achieving the test effect of simplifying control logic and reducing costs.
Patent Information
- Application Number
- CN202512013373.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-07
AI Technical Summary
In the existing technology, the parallel read operation speed test method of eflash requires additional pins and complex control logic, resulting in high test costs and increased chip area, and lacks a simple and effective test method.
Using a multiplexer and SPI interface circuit, the parallel read operation speed of eflash is tested by utilizing the SPI interface of NOR flash and read commands. The SPI interface circuit is connected to the eflash storage module, and the multiplexer is used to switch interfaces, simplifying the control logic and reusing existing test equipment.
It simplifies the control logic, reduces testing costs, minimizes redundant development overhead, meets testing requirements, and simplifies the test design process.
Smart Images
Figure CN121811952A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of flash memory testing technology, and in particular to a method and circuit for testing the parallel read operation speed of embedded flash (eflash). Background Technology
[0002] Currently, NOR flash with an SPI interface (Serial Peripheral Interface) has advantages in system design complexity and cost compared to NOR flash with a parallel interface. However, in embedded flash applications, increasing the bus width can significantly improve data throughput. Therefore, EFlash read operations still use a parallel interface, and the bit width of EFlash IP read operations can reach 128 bits or even more, while the bit width of NOR flash with a parallel interface is generally 8 bits or 16 bits. Therefore, the read operation speed of NOR flash with a parallel interface can be directly tested, but other methods are needed to test the parallel read operation speed of EFlash IP.
[0003] Currently, the most direct method for testing the parallel read speed of EF Flash is to connect the EF Flash port to external pins. This increases the number of pins used, the complexity of the control logic and the corresponding test environment, and the chip area, leading to increased testing costs. Some tests also use serial ports, but this also requires the introduction of complex serial port logic. Summary of the Invention
[0004] The technical problem to be solved by this disclosure is to overcome the defects in the prior art and provide a test circuit, test method and chip for testing the parallel read operation speed of eflash using the existing NOR flash SPI interface and read commands.
[0005] This disclosure solves the above-mentioned technical problems by providing a test circuit for parallel read operation speed.
[0006] The test circuit includes a multiplexer and an SPI interface circuit.
[0007] The SPI interface circuit is a serial NOR flash SPI interface circuit. The SPI interface circuit includes an electrically connected SPI interface unit and a control logic unit. The SPI interface unit includes a serial data input interface SI, a serial data output interface SO, and a serial clock interface SCLK.
[0008] The eflash under test includes a storage module and a parallel interface. The storage module includes a first address bus ADD<23:0>, a first control signal Ctrl, and a first sensitive amplifier output bus SAOUT<127:0>.
[0009] The control logic unit is electrically connected to the first address bus ADD<23:0>, the first control signal Ctrl, and the first sensitive amplifier output bus SAOUT<127:0> of the storage module via the multiplexer;
[0010] The test circuit performs parallel read operation speed tests on the eflash under test through the SPI interface circuit.
[0011] Optionally, the storage module of the eflash under test is connected to the parallel interface through the multiplexer;
[0012] Based on the enable signal of the multiplexer, the connection between the storage module of the eflash under test and the SPI interface circuit or the parallel interface is switched.
[0013] Optionally, the control logic unit includes a second address bus, a second control signal, and a data input bus;
[0014] The second address bus, the second control signal, and the data input bus are connected to the first address bus, the first control signal, and the first sensitive amplifier output bus respectively via the multiplexer.
[0015] This disclosure also provides a method for testing the speed of parallel read operations, wherein the method employs the test circuit described in any one of the above-mentioned methods, and specifically includes the following steps:
[0016] The first signal is generated based on the SPI interface circuit, and a read operation is started on the preset address of the storage module of the EFlash under test; the preset address of the storage module of the EFlash under test stores preset data.
[0017] Based on the second signal generated by the SPI interface circuit, the data obtained from the read operation of the storage module of the eflash under test is sampled.
[0018] The reading operation and the sampling start operation are separated by one serial clock cycle of the SPI interface circuit.
[0019] Adjust the serial clock period of the SPI interface circuit until the serial data output interface of the SPI interface circuit outputs the preset data. At this time, the serial clock period of the SPI interface circuit is the parallel read operation speed of the eflash under test.
[0020] Optionally, the first signal generated by the SPI interface circuit is used to perform a read operation on a preset address of the storage module of the eflash under test; specifically, this includes:
[0021] The control logic unit based on the SPI interface circuit generates the first signal and sends the first signal as a trigger signal for the read operation of the eflash under test to the first control signal (Ctrl); at the same time, it sends the preset address to the first address bus (ADD<23:0>) of the eflash under test.
[0022] Optionally, sampling the data obtained from the read operation of the storage module of the eflash under test based on the second signal generated by the SPI interface circuit specifically includes:
[0023] The control logic unit based on the SPI interface circuit generates a second signal to sample the data obtained from the read operation in the storage module of the eflash under test, and then the data is processed by the logic control unit and converted into serial data output.
[0024] Optionally, the first signal is the rising edge of the sensitive amplifier enable signal (saen_logic) of the control logic unit of the SPI interface circuit that triggers SPI read, and the second signal is the falling edge of the sampled parallel output data signal (saoe_logic) of the control logic unit of the SPI interface circuit.
[0025] Optionally, the first signal and the second signal are generated by the read operation instruction 03H of the SPI interface circuit.
[0026] Optionally, adjusting the serial clock period of the SPI interface circuit until the serial data output interface of the SPI interface circuit outputs the preset data includes:
[0027] Adjust the serial clock period of the SPI interface circuit from low to high frequency and / or from high to low frequency until the serial data output interface of the SPI interface circuit outputs the preset data.
[0028] In another aspect of this disclosure, a chip is provided, characterized by including a test circuit as described above.
[0029] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.
[0030] The positive and progressive effects of this disclosure are as follows: This disclosure directly adopts the mature NOR flash SPI interface and directly reuses the SPI read command to test the speed of parallel read operation of EF flash, which can simplify the control logic, reduce the cost of repeated development, and reuse existing SPI flash test equipment, simplify the test design process, reduce test costs, and at the same time meet the test requirements. Attached Figure Description
[0031] Figure 1 This is a block diagram of the SPI interface circuit in an existing NOR flash memory.
[0032] Figure 2 Here is a structural block diagram of an existing eflash;
[0033] Figure 3 Timing diagram for existing internal read operations of eflash;
[0034] Figure 4 This is a timing diagram of the read 03H command from the existing SPI interface NOR flash user manual.
[0035] Figure 5 This is a schematic diagram of a parallel read operation speed test circuit provided in Embodiment 1 of this disclosure;
[0036] Figure 6 This is a flowchart illustrating a parallel read operation speed testing method provided in Embodiment 2 of this disclosure;
[0037] Figure 7 For based on Figure 4 Parallel read operation speed test circuit and Figure 5 The timing diagram for testing the parallel read operation speed of eflash is shown in the parallel read operation speed test method. Detailed Implementation
[0038] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.
[0039] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the context of the embodiments, and the use of such prefixes should not constitute unnecessary restrictions. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.
[0040] Figure 1 This is a block diagram of an existing NOR flash SPI interface circuit. The SPI interface circuit includes an SPI interface unit and a control logic unit. The SPI interface unit includes a serial input interface SI, a serial output interface SO, and a serial clock interface SCLK. The output of the SPI interface unit is connected to the control logic unit. The output of the control logic unit is electrically connected to the address bus ADD<23:0> and the sensitive amplifier saenamp of the flash memory. This address bus is connected to the X-direction address decoders (X decoders) and the Y-direction address decoders (Y decoders). The data bus of the sensitive amplifier of the flash memory is connected to the control logic unit.
[0041] During a read operation, the address is input serially via the serial input interface SI of the SPI interface unit. The serially input address signal is converted into a parallel signal by the control logic unit and sent to the address bus, which in turn sends it to the X decoders and Y decoders. The read data is a parallel signal output from the Data Path, which is converted into a serial signal by the control logic unit and sent to the SPI interface unit. The data is output serially via the serial output interface SO. Therefore, the SPI architecture of traditional NOR flash memory actually includes a parallel data path.
[0042] like Figure 2 The diagram shown is a schematic of the existing eflash structure. The eflash includes a storage module and a parallel interface electrically connected to the storage module. The storage module includes a storage array, a first address bus ADD<23:0>, a first control signal Ctrl, and a first sensitive amplifier output bus SAOUT<127:0>. The first address bus ADD<23:0>, the first control signal Ctrl, and the first sensitive amplifier output bus SAOUT<127:0> are all connected to the parallel interface.
[0043] Figure 3 This is a timing diagram of the existing internal read operation of EFASH. As shown in the figure, ADD is the parallel address signal. The changes of RCLK and ADD are synchronized, and it is the trigger signal for the read operation. The trigger signal of the read operation can trigger the internal EFASH to generate the enable signal SAENB of the sensitive amplifier and the output enable signal SAOE of the sensitive amplifier. SAOUT<127:0> is a 128-bit wide data output signal.
[0044] Tacc is defined as the parallel read speed, which is the time from when the eflash receives the read trigger signal to when it outputs the read parallel data. It consists of the sum of two time intervals, T1 and T2. T1 is the setup time of the decoding circuit, which is the interval between the trigger signal RCLK of the read operation and the generation of the sensitive amplifier enable signal SAENB. T2 is the working time of the sensitive amplifier, which represents the time interval between the generation of the sensitive amplifier enable signal SAENB and the generation of the output enable signal SAOE that controls the sensitive amplifier. T1 and T2 are generated by the internal delay circuit and their duration can be adjusted.
[0045] Figure 4 This is a timing diagram for the read operation instruction 03H in the existing NOR flash datasheet (user manual). The address is serially input via port SI, and the data is serially output via port SO. After receiving the operation instruction 03H at the serial input interface SI, the address to be read is followed by a 24-bit encoded address. The address data is sampled on the rising edge of the clock SCLK, and the data is output sequentially from the serial output interface SO on the falling edge of the clock SCLK.
[0046] Example 1
[0047] like Figure 5 The diagram shown is a schematic representation of the test circuit according to an embodiment of this disclosure. The test circuit includes a multiplexer (MUX) and an SPI interface circuit; the SPI interface circuit is a serial NOR flash SPI interface circuit, as shown... Figure 1 and Figure 5 As shown, the SPI interface circuit includes an electrically connected SPI interface unit and a control logic unit. The SPI interface unit includes a serial data input interface SI, a serial data output interface SO, and a serial clock interface SCLK.
[0048] The eflash under test includes a storage module and a parallel interface. The storage module includes a storage array, a first address bus ADD<23:0>, a first control signal Ctrl, and a first sensitive amplifier output bus SAOUT<127:0>. The control logic unit of the SPI interface circuit is electrically connected to the first address bus ADD<23:0>, the first control signal Ctrl, and the first sensitive amplifier output bus SAOUT<127:0> of the storage module via the multiplexer.
[0049] Specifically, the control logic unit of the SPI interface circuit further includes a second address bus, a second control signal, and a data input bus; the second address bus, the second control signal, and the data input bus are connected to the first address bus, the first control signal, and the first sensitive amplifier output bus respectively via the multiplexer.
[0050] Meanwhile, the storage module of the eflash under test is connected to the parallel interface through the multiplexer. The parallel interface includes a read operation trigger signal interface RCLK, an address interface ADD<23:0>, and a data interface Data<127:0>. The operation trigger signal interface RCLK, the address interface ADD<23:0>, and the data interface Data<127:0> of the parallel interface are connected to the first control signal, the first address bus, and the first sensitive amplifier output bus respectively through the multiplexer.
[0051] Based on the enable signal of the multiplexer, the connection between the storage module of the eflash under test and the SPI interface circuit or the parallel interface is switched.
[0052] The test circuit performs parallel read operation speed tests on the EFASH under test through the SPI interface circuit. Specifically, by inputting a read operation trigger signal to the EFASH under test through the SPI interface circuit, the data reading and output of the EFASH can be triggered, thereby testing the parallel read operation speed of the EFASH.
[0053] The parallel read operation test circuit of this embodiment directly adopts the mature NOR flash SPI interface circuit and reuses the SPI read command to test the speed of parallel read operations of EF flash. This simplifies the control logic, reduces redundant development costs, and therefore allows reuse of existing SPI interface Flash test benches and other equipment, simplifying the test design process, reducing test costs, and still meeting test requirements. The parallel read operation test circuit of this embodiment can also be used in IP-level testing.
[0054] Example 2
[0055] This embodiment is a test method based on Embodiment 1 described above. For example... Figure 6 As shown, the specific steps include:
[0056] S10, a first signal is generated based on the SPI interface circuit to perform a read operation on the preset address of the storage module of the eflash under test; the preset address of the storage module of the eflash under test stores preset data;
[0057] S20, based on the second signal generated by the SPI interface circuit, sample the data obtained from the read operation of the storage module of the eflash under test;
[0058] The first signal and the second signal are separated by one serial clock cycle of the SPI interface circuit.
[0059] S30, adjust the serial clock period of the SPI interface circuit until the serial data output interface of the SPI interface circuit outputs preset data. At this time, the serial clock period of the SPI interface circuit is the parallel read speed of the EFASH under test. That is, the parallel read operation speed of the EFASH under test can be calculated by obtaining the serial clock period of the SPI interface circuit.
[0060] The first signal generated by the SPI interface circuit is used to perform a read operation on the preset address of the storage module of the EFlash under test. Specifically, the control logic unit of the SPI interface circuit generates the first signal and sends it as a trigger signal for the read operation of the EFlash under test to the first control signal Ctrl; simultaneously, the preset address is sent to the first address bus ADD<23:0> of the EFlash under test, thereby triggering the SAENB and SAOE signals inside the EFlash. Figure 7 As shown, the first signal is equivalent to the RCLK signal of eflash and is input to the first control signal Ctrl of the eflash under test.
[0061] The second signal generated by the SPI interface circuit is used to sample the data obtained from the read operation of the storage module of the eflash under test, specifically including:
[0062] The control logic unit based on the SPI interface circuit generates a second signal to sample the data obtained from the read operation of the storage module of the eflash under test, and then processes it through the control logic unit to convert it into serial data output.
[0063] As an optional implementation, on the SPI interface circuit side, the first signal is the rising edge of the sensitive amplifier enable signal saen_logic of the control logic unit of the SPI interface circuit, which triggers SPI read operations, and thus can be used as the read operation trigger signal for eflash, i.e., the RCLK signal. The second signal is the falling edge of the sampling parallel output data signal saoe_logic of the control logic unit of the SPI interface circuit, and thus can be used to sample the data read from the memory module. The difference between these two signals is exactly one serial clock cycle SCLK of the SPI interface circuit. Of course, those skilled in the art will understand that the first and second signals can also be formed using the rising or falling edges of other signals.
[0064] like Figure 7As shown, in the SPI interface circuit, the rising edges of the `saen_logic` and `saoe_logic` signals are the same. The rising and falling edges of the `saen_logic` and `saoe_logic` signals differ by one SPI interface circuit serial clock cycle (SCLK). That is, the difference between performing a read operation and starting a sampling operation is exactly one SPI interface circuit serial clock cycle (SCLK). The `saoe_logic` signal, as a sampling signal, samples and outputs data on the falling edge, and outputs it via the data output bus `SAOUT<127:0>`. In the SPI interface circuit, after sampling, the Control Logic converts this parallel data and outputs it through the serial data output interface of the SPI interface circuit. Furthermore, the interval between the rising and falling edges of the `saen_logic` and `saoe_logic` signals can be synchronously changed by adjusting the serial clock cycle.
[0065] As an optional implementation, the first and second signals are generated by the read operation instruction 03H of the SPI interface circuit. That is, the first and second signals can be generated simply by using the read operation instruction 03H of the SPI interface circuit. Furthermore, adjusting the clock period SCLK of the SPI interface circuit allows adjustment of the interval between the rising edge of the first signal and the falling edge of the second signal.
[0066] Specifically, such as Figure 5 , 6 As shown in Figure 7, the SPI interface circuit inputs the read operation command 03H. Along with the serial clock cycle signal input at the serial clock interface SCLK, on the rising edge of the serial clock cycle SCLK, the control logic unit of the SPI interface circuit generates a saen_logic signal. The rising edge of the saen_logic signal is then sent to the first control signal Ctrl of the EFASH under test, and simultaneously, a preset address is sent to the first address bus of the EFASH under test, thereby triggering the SAENB and SAOE signals inside the EFASH. The rising edge of this saen_logic signal is equivalent to... Figure 2 , 3 The RCLK signal is the trigger signal for the read operation, i.e., the first signal. That is, the above process involves performing a read operation from a preset address in the EFASH memory module under test. This preset data is pre-stored data at the preset address of the EFASH memory under test.
[0067] Similarly, the saoe_logic signal generated by the control logic unit of the SPI interface circuit serves as a sampling signal. It samples the output bus SAOUT<127:0> of the first sensitive amplifier on the falling edge, marking the start of sampling the parallel data of the read operation. In the SPI interface circuit, after sampling, the Control Logic converts this parallel data and outputs it through the serial data output interface SO of the SPI interface unit. The falling edge of this saoe_logic signal is the second signal, from which sampling of the data obtained from the read operation of the EFASH memory module under test begins. In the EFASH memory under test, the memory module outputs parallel data on the rising edge of SAOE.
[0068] Therefore, by adjusting the SCLK frequency, i.e., the serial clock period of the SPI interface circuit, as the frequency is adjusted from low to high or from high to low, the interval between the falling edge of the saoe_logic signal and the rising edge of the sae_logic signal can be adjusted synchronously, gradually making the falling edge of saoe_logic approach the rising edge of SAOE. By determining whether the serial data output from the serial data output interface SO is correct, and based on the frequency of the SCLK signal when the data is exactly correct, the parallel read speed Tacc of the eflash under test can be obtained. If the frequency when the data obtained from the serial data output interface SO by the read03H command is correct is f, then the parallel read operation speed Tacc = 1 / f.
[0069] Preferably, the step S30 of adjusting the clock period of the SPI interface until the serial output interface of the SPI interface circuit outputs the preset data includes adjusting the serial clock period of the SPI interface circuit from low to high frequency and / or adjusting the serial clock period of the SPI interface circuit from high to low frequency until the serial data output interface of the SPI interface unit outputs the preset data.
[0070] Furthermore, as an optional implementation, the test eflash can be switched to either the test phase or the normal operation phase based on the enable signal of the multiplexer.
[0071] During testing, when the multiplexer's enable signal TEST_EN equals 1, the SPI interface circuit generates the signal saen_logic after passing through Controllogic, which is equivalent to the eflash read operation trigger signal RCLK. During normal operation, the multiplexer's enable signal TEST_EN equals 0, and the RCLK signal is generated by the parallel interface.
[0072] The parallel read operation speed testing method disclosed in this embodiment directly adopts the mature NOR flash SPI interface and reuses SPI read commands to test the parallel read operation speed of EF flash. This simplifies the control logic, reduces redundant development costs, and allows reuse of existing NOR flash test benches and other equipment with SPI interfaces, simplifying the test design process and meeting testing requirements. Furthermore, it can also be used in IP-level testing.
[0073] Example 3
[0074] This embodiment also provides a chip, which includes the test circuit of Embodiment 1 above.
[0075] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.
Claims
1. A parallel read operation speed testing circuit, characterized in that, The test circuit includes a multiplexer and an SPI interface circuit. The SPI interface circuit is a serial NOR flash SPI interface circuit. The SPI interface circuit includes an electrically connected SPI interface unit and a control logic unit. The SPI interface unit includes a serial data input interface, a serial data output interface and a serial clock interface. The eflash under test includes a storage module and a parallel interface. The storage module includes a storage array, a first address bus, a first control signal, and a first sensitive amplifier output bus. The control logic unit is electrically connected to the first address bus, the first control signal, and the first sensitive amplifier output bus of the storage module via the multiplexer. The test circuit performs parallel read operation speed tests on the eflash under test through the SPI interface circuit.
2. The parallel read operation speed testing circuit as described in claim 1, characterized in that, The storage module of the eflash under test is connected to the parallel interface through the multiplexer; Based on the enable signal of the multiplexer, the connection between the storage module of the eflash under test and the SPI interface circuit or the parallel interface is switched.
3. The parallel read operation speed testing circuit as described in claim 1 or 2, characterized in that, The control logic unit includes a second address bus, a second control signal, and a data input bus; The second address bus, the second control signal, and the data input bus are connected to the first address bus, the first control signal, and the first sensitive amplifier output bus respectively via the multiplexer.
4. A method for testing the speed of parallel read operations, characterized in that, The method employs the test circuit described in any one of claims 1-3, and specifically includes the following steps: The first signal is generated based on the SPI interface circuit, and a read operation is performed on the preset address of the storage module of the EFlash under test; the preset address of the storage module of the EFlash under test stores preset data. Based on the second signal generated by the SPI interface circuit, the data obtained from the read operation of the storage module of the eflash under test is sampled. The first signal and the second signal are separated by one serial clock cycle of the SPI interface circuit; Adjust the serial clock period of the SPI interface circuit until the serial data output interface of the SPI interface circuit outputs the preset data. At this time, the serial clock period of the SPI interface circuit is the parallel read operation speed of the eflash under test.
5. The parallel read operation speed testing method as described in claim 4, characterized in that, The first signal generated by the SPI interface circuit is used to perform a read operation on a preset address of the eflash memory module under test; specifically, this includes: The control logic unit based on the SPI interface circuit generates the first signal and sends the first signal as a trigger signal for the read operation of the eflash under test to the first control signal; at the same time, it sends the preset address to the first address bus of the eflash under test.
6. The parallel read operation speed testing method as described in claim 4, characterized in that, The sampling operation for the data obtained from the read operation of the storage module of the eflash under test based on the second signal generated by the SPI interface circuit specifically includes: The control logic unit based on the SPI interface circuit generates a second signal to sample the data obtained from the read operation in the storage module of the eflash under test, and then the data is processed by the control logic unit and converted into serial data output.
7. The parallel read operation speed testing method as described in claim 4, characterized in that, The first signal is the rising edge of the sensitive amplifier enable signal that triggers SPI read in the control logic unit of the SPI interface circuit, and the second signal is the falling edge of the sampled parallel output data signal of the control logic unit of the SPI interface circuit.
8. The parallel read operation speed testing method as described in claim 4, characterized in that, The first signal and the second signal are generated by the read operation instruction 03H of the SPI interface circuit.
9. The parallel read operation speed testing method as described in claim 4, characterized in that, Adjusting the serial clock period of the SPI interface circuit until the serial data output interface of the SPI interface circuit outputs the preset data includes, Adjust the serial clock period of the SPI interface circuit from low to high frequency and / or from high to low frequency until the serial data output interface of the SPI interface circuit outputs the preset data.
10. A chip, characterized in that, Includes the test circuit as described in any one of claims 1-3.