Quick comparison circuit, comparator and automobile power system

Abstract

The invention discloses a rapid comparison circuit, a comparator and an automobile power system, and belongs to the technical field of comparators. The fast comparison circuit comprises at least two signal channels; the signal channel comprises a signal input end and a signal output end; the comparison module is used for comparing a signal accessed by the sampling input end with a signal accessed by the reference input end and outputting a comparison result to the comparison result output end; the channel selection module is respectively connected with each signal channel and the comparison module and is used for switching the signal channels communicated with the comparison module; at the same time, the channel selection module selects one of the signal channels as a target signal channel, communicates a signal input end in the target signal channel with the sampling input end, communicates a signal output end in the target signal channel with the comparison result output end, and provides a reference signal corresponding to the target signal channel to the reference input end. According to the embodiment of the invention, the area and cost of the quick comparison circuit can be reduced on the basis of meeting the multi-channel comparison requirement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of comparators, in particular to a fast comparison circuit, a comparator and an automotive power system. BACKGROUND

[0002] In the related art, for the comparison requirement of two or more channels, a comparison structure needs to be independently set for each channel, which results in high circuit area occupation and cost. Another solution in the related art is to add a selector after the input end, and a selection signal is configured by a register, so that comparison of each channel can be selected, which can save area. However, in fact, the channel selection is the result of static configuration, and after the configuration is completed, only the input signal of one channel can be compared and processed, and the comparison requirement of multiple channels cannot be met at the same time. Therefore, the related art cannot meet the comparison requirement of multiple channels and reduce the circuit area. SUMMARY

[0003] The present application provides a fast comparison circuit, a comparator and an automotive power system to reduce the area and cost of the fast comparison circuit while meeting the comparison requirement of multiple channels.

[0004] In a first aspect, an embodiment of the present application provides a fast comparison circuit, comprising:

[0005] at least two signal channels; the signal channel comprises a signal input end and a signal output end;

[0006] a comparison module comprising a sampling input end, a reference input end and a comparison result output end; the comparison module is used for comparing the signal input into the sampling input end with the signal input into the reference input end, and outputting the comparison result to the comparison result output end;

[0007] a channel selection module connected to each of the signal channels and the comparison module; the channel selection module is used for switching the signal channel connected to the comparison module; wherein at the same time, the channel selection module selects one of the signal channels as a target signal channel, connects the signal input end in the target signal channel to the sampling input end, connects the signal output end in the target signal channel to the comparison result output end, and provides the reference signal corresponding to the target signal channel to the reference input end.

[0008] Optionally, the channel selection module controls each of the signal channels to be connected to the comparison module in turn, and switches one of the signal channels to be connected to the comparison module every interval of a switching period; the switching period is greater than or equal to the comparison period of the comparison module.

[0009] Optionally, the channel selection module comprises:

[0010] a first selector, a plurality of inputs of the first selector are connected with the signal inputs one by one, and an output of the first selector is connected with the sampling input;

[0011] a second selector, an input of the second selector is connected with the comparison result output, and a plurality of outputs of the second selector are connected with the signal outputs one by one;

[0012] a channel selection unit, connected with the first selector and the second selector respectively, the channel selection unit is used for controlling the input of the first selector connected with the signal input in the target signal channel to be in communication with the output of the first selector, and controlling the input of the second selector to be in communication with the output of the second selector connected with the signal output in the target signal channel;

[0013] a reference signal generation unit, connected with the reference input, used for providing the reference signal corresponding to the target signal channel to the reference input.

[0014] Optionally, the comparison module further comprises a result flag output, the comparison module is further used for outputting a result valid flag from the result flag output while outputting the comparison result from the comparison result output; the reference signal generation unit stores the reference signal corresponding to each signal channel;

[0015] the channel selection unit is further connected with the result flag output and the reference signal generation unit; the channel selection unit is used for switching the signal channel in communication with the comparison module when the result valid flag is received, and controlling the reference signal generation unit to output the reference signal corresponding to the signal channel in communication with the comparison module.

[0016] Optionally, the fast comparison circuit further comprises a flip-flop; the flip-flop outputs a trigger signal when a trigger condition is met, and a trigger period of the flip-flop is greater than or equal to a comparison period of the comparison module;

[0017] wherein, the output of the flip-flop is connected with the channel selection unit and the reference signal generation unit respectively; the channel selection unit is used for switching the signal channel in communication with the comparison module when the trigger signal is received, and the reference signal generation unit is used for switching the output reference signal when the trigger signal is received;

[0018] or,

[0019] The output of the trigger is connected to the channel selection unit, and the channel selection unit is connected to the reference signal generation unit. The channel selection unit is used to switch the signal channel connected to the comparison module when the trigger signal is received, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

[0020] Optionally, the output of the trigger is connected to the channel selection unit, and the channel selection unit is connected to the reference signal generation unit; the comparison module further includes a result flag output terminal, and the comparison module is also used to output a result validity flag from the result flag output terminal while outputting the comparison result from the comparison result output terminal;

[0021] The channel selection unit is also connected to the result flag output terminal; the channel selection unit is used to switch the signal channel connected to the comparison module when it receives the result valid flag for the first time after receiving the trigger signal, and control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

[0022] Optionally, the channel selection unit is also connected to the processor; the channel selection unit is also used to output a trigger loss alarm signal to the processor when it receives more than or equal to three trigger signals within a comparison period.

[0023] Optionally, the channel selection unit is configured with a counter, the reference signal generation unit stores reference signals corresponding to each of the signal channels, and the channel selection unit is also connected to the reference signal generation unit;

[0024] The channel selection unit is used to switch the signal channel connected to the comparison module when the counter count reaches the counting threshold, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module; wherein, the counter is cleared and starts counting again after the count reaches the counting threshold, and the duration of the counter count reaching the counting threshold is greater than or equal to the comparison period of the comparison module.

[0025] Optionally, the comparison module further includes a result flag output terminal, and the comparison module is further configured to output a result validity flag from the result flag output terminal while outputting the comparison result from the comparison result output terminal;

[0026] The channel selection unit is also connected to the result flag output terminal; the channel selection unit is used to switch the signal channel connected to the comparison module when the result valid flag is received for the first time after the counter count reaches the counting threshold, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

[0027] Optionally, the comparison module includes an analog comparator, wherein the first input terminal of the analog comparator serves as the sampling input terminal, the second input terminal of the analog comparator serves as the reference input terminal, and the output terminal of the analog comparator serves as the comparison result output terminal; the reference signal output by the reference signal generation unit is a digital signal;

[0028] The channel selection module further includes a digital-to-analog converter connected between the reference signal generation unit and the reference input terminal, used to convert the reference signal into a digital signal and then provide it to the reference input terminal.

[0029] Optionally, the channel selection module further includes: at least two comparison result processing units corresponding one-to-one with the signal channels; each comparison result processing unit is connected one-to-one between each output terminal of the second selector and the corresponding signal output terminal;

[0030] And / or, the fast comparison circuit further includes: at least two result registers connected in a one-to-one correspondence with each of the signal output terminals;

[0031] And / or, both the channel selection unit and the reference signal generation unit are connected to the configuration bus and receive corresponding configuration information from the configuration bus.

[0032] Optionally, the reference signal generation unit includes:

[0033] At least two reference signal processing units, each corresponding to one of the aforementioned signal channels, are provided. Each reference signal processing unit includes a first calculation subunit, a second calculation subunit, and a third selector. The first and second calculation subunits are respectively connected to the two input terminals of the third selector, and the control terminal of the third selector is connected to the signal output terminal of the corresponding signal channel. Specifically, the first calculation subunit generates a high-hysteresis reference signal based on a reference value, the second calculation subunit generates a low-hysteresis reference signal based on the reference value, and the third selector selects one input terminal of the third selector to be connected to its output terminal based on the signal from its control terminal. The high-hysteresis reference signal is greater than the reference value, and the low-hysteresis reference signal is less than the reference value.

[0034] The fourth selector is connected to the control terminal and the output terminal of the reference signal generation unit, as well as the output terminal of each of the third selectors; the fourth selector is used to select one of the output terminals of the third selector to be connected to the output terminal of the reference signal generation unit according to the signal of its control terminal.

[0035] Secondly, embodiments of the present invention also provide a comparator, comprising: at least one fast comparison circuit as provided in any embodiment of the present invention.

[0036] Thirdly, embodiments of the present invention also provide an automotive powertrain system, including a comparator as provided in any embodiment of the present invention.

[0037] The fast comparison circuit provided in this embodiment of the invention includes a comparison module, a channel selection module, and at least two signal channels. Each signal channel is independently configured, with a signal input terminal and a corresponding signal output terminal, and the output signals of each signal channel are decoupled. The channel selection module provides a corresponding reference signal while switching signal channels. The comparison module compares the received sampled signal with the sampled signal and provides the comparison result to the corresponding signal output terminal. Each signal output terminal can be connected to the subsequent processing circuit corresponding to its respective signal channel. Therefore, this fast comparison circuit can support channel switching and comparison processing for multiple signal channels based on a single comparison module. By reasonably configuring the channel switching to switch each signal channel, real-time comparison processing of multiple signal channels can be supported. Therefore, this embodiment of the invention can reduce the number of comparison modules, significantly reduce the circuit area required for fast comparison of multiple channels, and reduce costs, achieving a reduction in the area and cost of the fast comparison circuit while meeting the requirements of multi-channel comparison.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a fast comparison circuit provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention;

[0043] Figure 4This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of the structure of a reference signal generation unit provided in an embodiment of the present invention;

[0047] Figure 8 This is a schematic diagram of a hysteresis band processing procedure provided in an embodiment of the present invention;

[0048] Figure 9 This is a schematic diagram of a comparator provided in an embodiment of the present invention;

[0049] Figure 10 This is a schematic diagram of the structure of an automotive power system provided in an embodiment of the present invention. Detailed Implementation

[0050] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0052] This invention provides a fast comparison circuit that supports fast comparison of two or more signal channels, with each channel's comparison result processed and output independently. Especially for large-scale system applications, achieving similar functionality with a smaller area can reduce costs.

[0053] Figure 1 This is a schematic diagram of a fast comparison circuit provided in an embodiment of the present invention. See also... Figure 1The fast comparison circuit FC includes at least two signal channels, a comparison module 10, and a channel selection module 20. Each signal channel includes a signal input terminal and a signal output terminal. Figure 1 The example shows a first signal channel including a first signal input terminal IN1 and a first signal output terminal OUT1, a second signal channel including a second signal input terminal IN2 and a second signal output terminal OUT2, and so on. The comparison module 10 includes a sampling input terminal N1, a reference input terminal N2, and a comparison result output terminal N3; the comparison module 10 compares the signal input to the sampling input terminal N1 with the signal input to the reference input terminal N2, and outputs the comparison result to the comparison result output terminal N3. The channel selection module 20 connects each signal channel to the comparison module 10; the channel selection module 20 switches the signal channels connected to the comparison module 10; wherein, at any given time, the channel selection module 20 selects one of the signal channels as the target signal channel, connects the signal input terminal of the target signal channel to the sampling input terminal N1, connects the signal output terminal of the target signal channel to the comparison result output terminal N3, and provides the reference signal corresponding to the target signal channel to the reference input terminal N2.

[0054] For example, the signal input terminal can be an I / O interface, such as connecting to the sampling signal of a sampling point in the circuit under test; the signal output terminal is used to output the comparison result, and can be connected to subsequent processing circuitry. The subsequent processing circuitry may include a demand module, which, for example, controls the operation of the circuit under test based on the comparison result. The demand module includes, but is not limited to, controllers, latches, and switching elements. Alternatively, the subsequent processing circuitry can also be connected to a register, where the comparison result is stored. The demand module can also call the comparison result in the register and perform corresponding processing. The comparison frequency of the comparison module 10 is, for example, in the MHz range, to support the comparison requirements of sampled signals at MSPS-level signal channel sampling rates, providing sufficient comparison speed. The channel selection module 20 can specifically be connected to each signal input terminal, each signal output terminal, sampling input terminal N1, reference input terminal N2, and comparison result output terminal N3 respectively. In practical applications, the channel selection module 20 can be configured to switch signal channels according to actual needs. For example, it can control each signal channel to cyclically connect to the comparison module 10 at a certain frequency and in a certain order to achieve real-time comparison of each signal channel, or it can control the signal channel with sampling signal access to connect to the comparison module 10 to achieve real-time comparison of signal channels with comparison requirements. For example, the sampling signal can be used to characterize the current at the sampling point. This fast comparison circuit can be applied to application scenarios such as overcurrent detection, current limiting control, and peak current control.

[0055] The fast comparison circuit FC provided in this embodiment of the invention includes a comparison module 10, a channel selection module 20, and at least two signal channels. Each signal channel is independently configured, with a signal input terminal and a corresponding signal output terminal, and the output signals of each signal channel are decoupled. The channel selection module 20 provides a corresponding reference signal while switching signal channels. The comparison module 10 compares the received sampled signal with the sampled signal and provides the comparison result to the corresponding signal output terminal. Each signal output terminal can be connected to the subsequent processing circuit corresponding to its respective signal channel. Therefore, this fast comparison circuit FC can support channel switching and comparison processing for multiple signal channels based on a single comparison module 10. By reasonably configuring the channel switching 20 to switch each signal channel, real-time comparison processing of multiple signal channels can be supported. Therefore, this embodiment of the invention can save the number of comparison modules 10, significantly reduce the circuit area required for fast comparison of multiple channels, and reduce costs, achieving a reduction in the area and cost of the fast comparison circuit FC while meeting the requirements of multi-channel comparison.

[0056] Based on the above embodiments, optionally, the channel selection module 20 sequentially controls each signal channel to connect with the comparison module 10, and switches the connection of one signal channel with the comparison module 10 every switching cycle. In this way, by controlling each signal channel to compare alternately in a time-division manner, each signal channel can be compared at the same frequency, saving area while realizing the comparison and result processing of multiple signal channels independently, thereby reducing costs.

[0057] The switching period is the time interval between two adjacent signal channel switchings. The switching period is greater than or equal to the comparison period of the comparison module to ensure that at least one comparison can be completed when a single signal channel is connected to the comparison module 10, guaranteeing that each signal channel can obtain a valid comparison result. For example, the switching period can be set to an integer multiple of the comparison period to ensure that each signal channel, when connected to the comparison module 10, can switch to the next signal channel for comparison processing after completing a full comparison. More specifically, the switching period can be set equal to the comparison period of the comparison module. This maximizes the comparison frequency of each signal channel. For instance, if the fast comparison circuit FC includes n signal channels, where n is a positive integer greater than 1, and the comparison frequency of the comparison module 10 is kMHz, then when the n signal channels alternately perform comparisons, the comparison frequency of each signal channel can reach k / nMHz.

[0058] It is understandable that the fast comparison circuit FC supports both single-channel and multi-channel modes, which can be configured according to actual needs. In single-channel mode, only one signal channel can be connected to the comparison module 10. In this case, since the comparison module 10 only needs to support the comparison requirements of one signal channel, the same comparison frequency as the comparison module 10 can be provided to that signal channel. In multi-channel mode, at least two signal channels can be alternately connected to the comparison module 10. In this case, since the comparison module 10 needs to support the comparison requirements of at least two signal channels, a lower comparison frequency can be provided to any one signal channel. In practical applications, the number of signal channels can be set according to the comparison frequency of the comparison module 10 and the comparison frequency requirements of each signal channel. For example, taking the fast comparison circuit FC, which includes two signal channels, as an example, the design of this embodiment realizes the dual-channel switching of front-end sampling and the dual-channel switching of back-end comparison results. It can support single and dual-channel modes. For example, the sampling rate in single-channel mode can reach 5MSPS, while the sampling rate in dual-channel mode can reach 2.5MSPS. In this way, while meeting the performance requirements of comparison speed, area optimization can be achieved, saving the area of ​​the comparison structure of one signal channel and reducing costs.

[0059] The following description provides an example of the possible structures that the channel selection module 20 may have, but it is not intended to limit the invention.

[0060] Figure 2 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention. See also... Figure 2 In one embodiment, the channel selection module 20 may optionally include: a first selector MUX1, a second selector MUX2, a channel selection unit 210, and a reference signal generation unit 220.

[0061] The first selector MUX1 is a multiplexer that can select one from multiple signals. It may include at least two input terminals and one output terminal. The number of input terminals of the first selector MUX1 is greater than or equal to the number of signal input terminals. The multiple input terminals of the first selector MUX1 are connected one-to-one with each signal input terminal, and the output terminal of the first selector MUX1 is connected to the sampling input terminal N1. The second selector MUX2 is a one-to-many selector that can select one from multiple signals. It may include one input terminal and at least two output terminals. The number of output terminals of the second selector MUX2 is greater than or equal to the number of signal output terminals. The input terminal of the second selector MUX2 is connected to the comparison result output terminal N3, and the multiple output terminals of the second selector MUX2 are connected one-to-one with each signal output terminal. The channel selection unit 210 is connected to the first selector MUX1 and the second selector MUX2 respectively. The channel selection unit 210 is used to control the input terminal of the first selector MUX1 connected to the signal input terminal in the target signal channel to be connected to the output terminal of the first selector MUX1, and to control the input terminal of the second selector MUX2 to be connected to the output terminal of the second selector MUX2 connected to the signal output terminal in the target signal channel. The reference signal generation unit 220 is connected to the reference input terminal N2 and is used to provide the reference signal corresponding to the target signal channel to the reference input terminal N2. The reference signal generation unit 220 can store the reference signals corresponding to each signal channel. The reference signals corresponding to different signal channels can be the same or different, depending on the actual requirements, and are not limited here. For example, after being enabled, the comparison module 10 starts comparing signals at a preset comparison period, which can be set and adjusted according to actual needs. Furthermore, the fast comparison circuit FC can be configured to have a signal channel that is connected to the comparison module 10 by default when enabled.

[0062] This embodiment includes a first selector MUX1, a second selector MUX2, a channel selection unit 210, and a reference signal generation unit 220 in the channel selection module 20. Based on the control of the first selector MUX1 and the second selector MUX2 by the channel selection unit 210, the selection of the target signal channel can be realized, so that the corresponding signal input terminal and signal output terminal are connected to the comparison module 10. Based on the reference signal generation unit 220, the reference signal corresponding to the connected target signal channel can be provided to the comparison module 10, thereby realizing the function of the channel selection module 20.

[0063] It is important to emphasize that this embodiment supports multi-channel comparison requirements through a comparison module 10 and two selectors for channel switching. Compared to the traditional structure that configures a comparison module for each signal channel separately, this embodiment does not require significantly more circuit area. Furthermore, in related technologies, the solution that only adds a selector at the input end directly stores the result of one channel in a register and sends it to the back end, which cannot process signals from two channels simultaneously. Compared to this solution, this embodiment also sets up multiple decoupled signal channels with signal output terminals corresponding one-to-one with the signal input terminals. A second selector MUX2 is also set after the comparison result output terminal N3 of the comparison module 10. This supports independent comparison processing for each signal channel, allows storage of comparison result information from different signal channels, and enables subsequent processing circuits and other applications to simultaneously respond to the output signals of different signal channels for corresponding processing.

[0064] Based on the above implementation methods, there are multiple ways to trigger the channel selection module 20 to switch channels, which will be described below.

[0065] Figure 3 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention. See also... Figure 3 In one embodiment, optionally, the comparison module 10 further includes a result flag output terminal N4. The comparison module 10 is also configured to output a result valid flag from the result flag output terminal N4 while outputting the comparison result from the comparison result output terminal N3; that is, the comparison module 10 outputs a result valid flag each time it completes a comparison (or outputs a comparison result each time), for example, at the end of each comparison cycle. For example, the result valid flag can be a rising edge. Furthermore, the reference signal generation unit 220 can store reference signals corresponding to each signal channel. The channel selection unit 210 is also connected to the result flag output terminal N4 and the reference signal generation unit 220. Based on this, the channel selection unit 210 is configured to switch the signal channel connected to the comparison module 10 when a result valid flag is received, and control the reference signal generation unit 220 to output the reference signal corresponding to the signal channel connected to the comparison module 10.

[0066] In this embodiment, the channel selection unit 210 automatically triggers the switching of signal channels and switching of reference signals by acquiring the comparison result flag, so that the switching period is equal to the comparison period of the comparison module 10, thereby realizing the automatic and fast switching of signal channels.

[0067] In this embodiment, taking a fast comparison circuit FC that includes two signal channels and a rising edge as an example, the data and control flow triggered by the result validity flag to switch channels and reference signals are as follows: When the result validity flag output by the comparison module 10 is high, the channel selection unit 210 controls the two selectors to switch channels alternately, for example, from the first signal channel to the second signal channel, and correspondingly controls the reference signal generation unit to switch to output the reference signal corresponding to the second signal channel, realizing a one-to-one correspondence between signal channels and reference signals. Specifically, when the result validity flag output by the comparison module 10 is high, the channel selection unit 210 can provide a first selection signal to the first selector MUX1, a second selection signal to the second selector MUX2, and a third selection signal to the reference signal generation unit 220. The specific processing flow of this circuit is as follows:

[0068] 1. When the first selector MUX1 receives the first selection signal, it controls the input terminal connected to the output terminal of the first selector MUX1 according to the first selection signal. For example, it connects the input terminal connected to the second input signal terminal IN2 of the first selector MUX1 to the output terminal of the first selector MUX1, so that the second sampling signal connected to the second input signal terminal IN2 is selected and output to the sampling input terminal N1 of the comparison module 10 through the first selector MUX1.

[0069] 2. When the reference signal generation unit 220 receives the third selection signal, it outputs the second reference signal corresponding to the second signal channel; the comparison module 10 receives the second sampling signal and the second reference signal and compares them, outputs the comparison result to the input terminal of the second selector MUX2, and outputs the result valid flag to the channel selection unit 210.

[0070] 3. When the second selector MUX2 receives the second selection signal, it outputs the comparison result to the corresponding signal output terminal for result processing. For example, the input terminal of the second selector MUX2 is connected to the output terminal of the second selector MUX2 that is connected to the second signal output terminal OUT2, so that the comparison result is output to the second signal output terminal OUT2, thereby achieving decoupling and independent processing and output of the two channels.

[0071] In this embodiment, upon completion of a comparison, the comparison module 10 outputs a valid result flag again, triggering the next channel switching and comparison. The comparison process repeats steps 1-3. In this implementation, the comparison module 10 performs a signal channel switching and comparison each time it outputs a valid result flag. The channel switching in this embodiment depends on the output of the comparison module 10. Since the channel selection unit 210 cannot prepare for the reference signal and other control logic in advance, a counter or trigger can be added to initiate control and reference signal preparation earlier.

[0072] Figure 4 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention. See also... Figure 4 In another implementation, channel switching can optionally be performed via an external hardware trigger channel selection module 20. Specifically, the fast comparison circuit FC also includes a trigger 30; the trigger 30 outputs a trigger signal when the trigger condition is met, and the trigger period of the trigger 30 is greater than or equal to the comparison period of the comparison module 10.

[0073] Among them, see Figure 4 The output of trigger 30 can be connected to channel selection unit 210 and reference signal generation unit 220 respectively. Channel selection unit 210 is used to switch the signal channel connected to comparison module 10 when a trigger signal is received. Reference signal generation unit 220 is used to switch the output reference signal when a trigger signal is received, specifically switching to the reference signal corresponding to the signal channel connected to comparison module 10, so as to achieve a one-to-one correspondence between signal channels and reference signals. Channel selection unit 210 and reference signal generation unit 220 can be configured with the same switching order so that the target signal channel and the reference signal corresponding to the target signal channel are switched synchronously when a trigger signal arrives.

[0074] Or see Figure 5 The output of trigger 30 can be connected to channel selection unit 210, which in turn is connected to reference signal generation unit 220. Channel selection unit 210 switches the signal channel connected to comparison module 10 upon receiving a trigger signal and controls reference signal generation unit 220 to output the reference signal corresponding to the signal channel connected to comparison module 10. In this way, by controlling the operating state of each selector and the output of reference signal generation unit 220 through channel selection unit 210, a one-to-one correspondence between signal channels and reference signals can be ensured, and only the channel selection order needs to be configured on channel selection unit 210.

[0075] Further, see Figure 5The comparison module 10 also includes a result flag output terminal N4. The comparison module 10 is further configured to output a result validity flag from the result flag output terminal N4 while simultaneously outputting the comparison result from the comparison result output terminal N3. Based on the connection of the channel selection unit 210 to the output terminal of the trigger 30 and the connection of the channel selection unit 210 to the reference signal generation unit 220, the channel selection unit 210 is also connected to the result flag output terminal N4. Correspondingly, the channel selection unit 210 is configured to switch the signal channel connected to the comparison module 10 and control the reference signal generation unit 220 to output the reference signal corresponding to the signal channel connected to the comparison module when it first receives the result validity flag after receiving the trigger signal. In this embodiment, the channel selection unit 210 waits to receive the result validity flag after receiving the trigger signal before switching channels. This ensures that the current comparison is completed before switching channels, allowing each comparison to proceed completely and avoiding the impact of asynchronous trigger signal and result validity flag on the circuit output.

[0076] Based on the above embodiments, optionally, the triggering condition of the trigger 30 can be configured according to actual needs, and the triggering period of the trigger 30 can be considered as the time interval between two consecutive trigger signals issued by the trigger 30, which is the switching period. For example, the trigger can be connected to a GTM (Generic Timer Module), and when the timing time of the GTM reaches the triggering period, a timing signal can be provided to the trigger 30. Upon receiving the timing signal, the trigger 30 can consider that the triggering condition has been met and output a trigger signal.

[0077] by Figure 5 Taking the structure shown as an example, and using a fast comparison circuit FC that includes two signal channels, with the result validity flag being a rising edge as an example, the data and control flow for triggering channel switching and reference signal switching based on the trigger signal and the result validity flag are as follows: When the trigger signal arrives and the result validity flag output by the comparison module 10 is high, the channel selection unit 210 controls the two selectors to alternately switch channels, for example, switching from the first signal channel to the second signal channel, and correspondingly controls the reference signal generation unit to switch to outputting the reference signal corresponding to the second signal channel, realizing a one-to-one correspondence between the signal channels and the reference signals. Specifically, when the trigger signal arrives and the result validity flag output by the comparison module 10 is high, the channel selection unit 210 can provide a first selection signal to the first selector MUX1, a second selection signal to the second selector MUX2, and a third selection signal to the reference signal generation unit 220. The specific processing flow of this circuit is as follows:

[0078] 1. When the first selector MUX1 receives the first selection signal, it controls the input terminal connected to the output terminal of the first selector MUX1 according to the first selection signal. For example, it connects the input terminal connected to the second input signal terminal IN2 of the first selector MUX1 to the output terminal of the first selector MUX1, so that the second sampling signal connected to the second input signal terminal IN2 is selected and output to the sampling input terminal N1 of the comparison module 10 through the first selector MUX1.

[0079] 2. When the reference signal generation unit 220 receives the third selection signal, it outputs the second reference signal corresponding to the second signal channel; the comparison module 10 receives the second sampling signal and the second reference signal and compares them, outputs the comparison result to the input terminal of the second selector MUX2, and outputs the result valid flag to the channel selection unit 210.

[0080] 3. When the second selector MUX2 receives the second selection signal, it outputs the comparison result to the corresponding signal output terminal for result processing. For example, the input terminal of the second selector MUX2 is connected to the output terminal of the second selector MUX2 that is connected to the second signal output terminal OUT2, so that the comparison result is output to the second signal output terminal OUT2, thereby achieving decoupling and independent processing and output of the two channels.

[0081] When the channel selection unit 210 receives the trigger signal again, it receives a result valid flag, indicating that the comparison is over and the next channel switching and comparison can be performed. The comparison process repeats the above steps 1-3.

[0082] In the above embodiments, optionally, the channel selection unit 210 is also connected to a processor; the processor is, for example, a CPU (Central Processing Unit). The channel selection unit 210 is also used to output a trigger loss alarm signal to the processor when it receives more than or equal to three trigger signals within a comparison cycle. As can be seen from the above analysis, the trigger cycle of the trigger 30 is greater than or equal to the comparison cycle. If a second trigger signal is received within a comparison cycle, the trigger signal can be recorded and the comparison can continue to be performed normally after waiting for the result validity flag, thus avoiding occasional interference affecting the comparison progress. However, if three or more trigger signals are received within a comparison cycle, it indicates an abnormality, and a trigger loss alarm needs to be issued to inform the processor to perform corresponding fault handling in order to achieve fault protection for the fast comparison circuit FC.

[0083] Figure 6 This is a schematic diagram of another fast comparison circuit provided in an embodiment of the present invention. See also... Figure 6In another embodiment, optionally, automatic channel switching can be triggered by a counter built into the channel selection module 20. Specifically, the channel selection unit 210 is equipped with a counter CNT, and the reference signal generation unit 220 stores reference signals corresponding to each signal channel. The channel selection unit 210 is also connected to the reference signal generation unit 220. The channel selection unit 210 is used to switch the signal channel connected to the comparison module 10 when the counter CNT reaches a counting threshold, and controls the reference signal generation unit 220 to output the reference signal corresponding to the signal channel connected to the comparison module 10. The counter CNT is reset to zero and restarts counting after reaching the counting threshold, and the duration for the counter CNT to reach the counting threshold is greater than or equal to the comparison period of the comparison module 10. The duration for the counter CNT to reach the counting threshold from zero is the switching period. For example, the channel switching time can be calculated based on the comparison time required by the comparison module 10, and the counting threshold of the counter CNT can be set accordingly.

[0084] In this embodiment, automatic switching of signal channels can be achieved by configuring a counter CNT inside the channel selection unit 210. Taking a fast comparator circuit FC with two signal channels as an example, the data and control flow for triggering channel switching and reference signal switching using the counter CNT is as follows: When the count value of the counter CNT reaches the counting threshold, the channel selection unit 210 controls the two selectors to alternately switch channels, for example, from the first signal channel to the second signal channel, and correspondingly controls the reference signal generation unit to switch to outputting the reference signal corresponding to the second signal channel, thus achieving a one-to-one correspondence between signal channels and reference signals. Specifically, when the count value of the counter CNT reaches the counting threshold, the channel selection unit 210 can provide a first selection signal to the first selector MUX1, a second selection signal to the second selector MUX2, and a third selection signal to the reference signal generation unit 220. The specific processing flow of this circuit is as follows:

[0085] 1. When the first selector MUX1 receives the first selection signal, it controls the input terminal connected to the output terminal of the first selector MUX1 according to the first selection signal. For example, it connects the input terminal connected to the second input signal terminal IN2 of the first selector MUX1 to the output terminal of the first selector MUX1, so that the second sampling signal connected to the second input signal terminal IN2 is selected and output to the sampling input terminal N1 of the comparison module 10 through the first selector MUX1.

[0086] 2. When the reference signal generation unit 220 receives the third selection signal, it outputs the second reference signal corresponding to the second signal channel; the comparison module 10 receives the second sampling signal and the second reference signal and compares them, and outputs the comparison result to the input terminal of the second selector MUX2.

[0087] 3. When the second selector MUX2 receives the second selection signal, it outputs the comparison result to the corresponding signal output terminal for result processing. For example, the input terminal of the second selector MUX2 is connected to the output terminal of the second selector MUX2 that is connected to the second signal output terminal OUT2, so that the comparison result is output to the second signal output terminal OUT2, thereby achieving decoupling and independent processing and output of the two channels.

[0088] When the counter reaches the counting threshold again after being cleared, the channel switching and comparison can be performed again. The comparison process repeats steps 1-3 above.

[0089] For example, the counter CNT can be set to automatically reset to zero after the count reaches the counting threshold, or it can be reset under the control of the channel selection unit 210. For example, the channel selection unit controls the counter CNT to reset to zero while switching signal channels.

[0090] Furthermore, the comparison module 10 also includes a result flag output terminal N4. The comparison module 10 is also used to output a result validity flag from the result flag output terminal N4 while outputting the comparison result from the comparison result output terminal N3. The channel selection unit 210 is also connected to the result flag output terminal N4. The channel selection unit 210 is used to switch the signal channel connected to the comparison module 10 and control the reference signal generation unit 220 to output the reference signal corresponding to the signal channel connected to the comparison module 10 when the counter CNT reaches the counting threshold for the first time and receives the result validity flag.

[0091] When channel switching is triggered solely by the counter CNT, the accuracy of the switching cycle depends on the accuracy of the threshold calculation. If the counting threshold is smaller than the actual switching cycle, errors may occur. In this embodiment, the channel selection unit 210 waits for a valid result flag to be received after the counter CNT reaches the counting threshold before switching channels. This ensures that the current comparison is completed before switching channels, allowing each comparison to be performed completely and avoiding the impact of counting threshold deviation on the circuit output.

[0092] See also Figures 3-6Based on the above embodiments, optionally, the comparison module 10 includes an analog comparator 110, with its first input terminal serving as a sampling input terminal N1, its second input terminal serving as a reference input terminal N2, and its output terminal serving as a comparison result output terminal N3; the reference signal output by the reference signal generation unit 220 is a digital signal. Therefore, the channel selection module 20 further includes a digital-to-analog converter 230, connected between the reference signal generation unit 220 and the reference input terminal N2, specifically connected between the output terminal of the reference signal generation unit 220 and the second input terminal of the analog comparator 110. The digital-to-analog converter 230 is used to convert the reference signal from digital to analog and then provide it to the reference input terminal N2. The sampling signal input to the signal input terminal can be an analog signal. Specifically, both the sampling signal and the reference signal can be voltage signals; for example, the sampling signal is a sampled voltage signal obtained by converting the sampled current at the sampling point in the circuit under test.

[0093] See also Figures 3-6 Based on the above embodiments, the channel selection module 20 may optionally include at least two comparison result processing units corresponding to the signal channels; each comparison result processing unit is connected to each output terminal of the second selector MUX and the corresponding signal output terminal. Figures 3-6 The example provides two comparison result processing units: a first comparison result processing unit 241, which is configured for the first signal channel; and a second comparison result processing unit 242, which is configured for the second signal channel.

[0094] The comparison result processing unit can perform filtering, noise reduction, polarity selection, and voltage conversion on the comparison result, thereby generating a boundary marker signal based on the comparison result, improving the reliability of the output signal at the signal output terminal, and ensuring that the high or low level represented by the output signal at the signal output terminal can be correctly identified by the subsequent processing circuit.

[0095] Based on the above embodiments, optionally, the fast comparison circuit FC further includes at least two result registers connected one-to-one with each signal output terminal. The result registers are used to store the signals output by the connected signal output terminals. If a module subsequently needs to retrieve the comparison result of any channel, it can access the corresponding result register to read the result. This embodiment achieves independent storage of the comparison results for each signal channel by configuring result registers one-to-one with each signal channel.

[0096] See also Figures 3-6Based on the above embodiments, optionally, both the channel selection unit 210 and the reference signal generation unit 220 are connected to a configuration bus and receive corresponding configuration information from the configuration bus. The configuration information of the channel selection unit 210 may include, for example, the channel switching order, and the configuration information of the reference signal generation unit 220 may include, for example, reference values ​​related to the reference signal. Specifically, the configuration bus may be an AHB bus (Advanced High-performance Bus), and both the channel selection unit 210 and the reference signal generation unit 220 may be connected to the processor via the AHB bus.

[0097] In summary, the fast comparison circuit FC provided in this embodiment of the invention adds a first selector MUX1 after each signal input terminal to achieve channel selection of analog inputs; the switching control is flexibly configurable, and can be triggered by the detection of the result validity flag to switch the channel to an automatic trigger continuous operation mode, or by a trigger signal to switch the channel to a hardware trigger mode, or by a counter to switch the channel to a counting trigger mode, realizing real-time comparison of each channel; the reference signal generation unit 220 can flexibly generate reference signals according to user needs, and the channel selection unit 210 controls the selection of the required reference signal for the channel; a second selector MUX2 is connected after the output of the comparison module 10 and before the comparison result processing unit, so that the signal output terminals are decoupled, and the required channel can be selected to output the comparison result based on the control of the channel selection unit 210. This embodiment can significantly reduce the analog and digital area required for multi-channel fast comparison, thereby reducing costs.

[0098] Based on the above embodiments, optionally, the comparison results of each signal channel can be processed independently for hysteresis band, hysteresis comparison can be completed, and the stability of each signal channel can be improved.

[0099] Figure 7 This is a schematic diagram of a reference signal generation unit provided in an embodiment of the present invention. See also... Figure 7 Specifically, the reference signal generation unit 220 includes at least two reference signal processing units 221 corresponding to each signal channel, and a fourth selector MUX4. Each reference signal processing unit 221 includes a first calculation subunit 2211, a second calculation subunit 2212, and a third selector MUX3. The first calculation subunit 2211 and the second calculation subunit 2212 are respectively connected to the two input terminals of the third selector MUX3, and the control terminal of the third selector MUX3 is connected to the signal output terminal of the signal channel corresponding to the reference signal processing unit 221. For example, Figure 7The two reference signal processing units 221, from top to bottom, correspond to the first signal channel and the second signal channel, respectively. The control terminal of the upper third selector MUX3 is connected to the first signal output terminal, receiving the first result signal rslt1 output from the first signal output terminal. The control terminal of the lower third selector MUX3 is connected to the second signal output terminal, receiving the second result signal rslt2 output from the second signal output terminal. The first calculation subunit 2211 generates a high-hysteresis reference signal based on the reference value vref0, the second calculation subunit 2212 generates a low-hysteresis reference signal based on the reference value vref0, and the third selector MUX3 selects one input terminal of the third selector MUX3 to be connected to its output terminal based on the signal from its control terminal. The high-hysteresis reference signal is greater than the reference value vref0, and the low-hysteresis reference signal is less than the reference value vref0; that is, the high-hysteresis reference signal and the low-hysteresis reference signal constitute a hysteresis band including the reference value vref0. The fourth selector MUX4 is connected to the control terminal and output terminal of the reference signal generation unit 220, as well as the output terminal of each of the third selectors MUX3. The fourth selector MUX4 is used to select a third selector MUX3 to connect to the output terminal of the reference signal generation unit 220 based on the signal from its control terminal. The third selector MUX3 is, for example, a 2-to-1 selector, and the fourth selector MUX4 is, for example, a multiple-to-1 selector. The control terminal of the fourth selector MUX4 is connected to the control terminal of the reference signal generation unit 220, and then to the channel selection unit 210, receiving the third selection signal sel. The output terminal of the fourth selector MUX4 is connected to the output terminal of the reference signal generation unit 220.

[0100] According to such Figure 7 The reference signal generation unit 220 shown, for any signal channel, the reference signal processing unit 221 calculates high hysteresis and low hysteresis for the configured reference value vref0, respectively, to obtain the high hysteresis reference voltage and low hysteresis reference voltage corresponding to that signal channel. Specifically, in a single reference signal processing unit 221, the output of the third selector MUX3 is controlled by the result signal at the signal output terminal, thereby selecting the reference signal corresponding to that signal channel; between different reference signal processing units 221, the reference signal output of the corresponding target signal channel is selected by the third selection signal sel provided by the channel selection unit 210. It should be noted that the reference value vref0 of different reference signal processing units 221 can be as follows: Figure 7 The settings shown can be the same or different, depending on the actual requirements. The reference value vref0 and the calculation method of each calculation subunit can be configured via the AHB bus. For example, the first calculation subunit 2211 can be an adder, and the second calculation subunit 2212 can be a subtractor.

[0101] Comparison module 10, for example, outputs 0 when the sampled signal is less than the reference signal and outputs 1 when the sampled signal is greater than the reference signal. The third selector MUX3, for example, outputs a high-hysteresis reference signal when the result signal characterization comparison module 10 outputs 0 and a low-hysteresis reference signal when the result signal characterization comparison module 10 outputs 1. Therefore, for any signal channel, its hysteresis band processing is as follows: Figure 8 As shown, Figure 8 In this diagram, vref0 represents the reference value, VH represents the high-hysteresis reference signal, and VL represents the low-hysteresis reference signal. Each dot represents a sampled signal at a different time point. Taking the initially provided reference signal as the high-hysteresis reference signal VH as an example, looking from left to right, when the sampled signal is lower than the high-hysteresis reference signal VH (see the first four solid dots), the comparison result is 0, and the third selector MUX3 selects to output the high-hysteresis reference signal VH. The output signal is also 0, allowing the current at the sampling point of the circuit under test to continue increasing, thus raising the sampled signal. When the sampled signal is higher than the reference signal (see the first hollow dot), the comparison result becomes 1, and the third selector MUX3 selects to output the low-hysteresis reference signal VL. Since the reference signal has changed to the low-hysteresis reference signal VL... This ensures that the sampling signals corresponding to the subsequent four hollow white dots remain higher than the reference signal. The third selector MUX3 maintains the output of the low-hysteresis reference signal VL. In this case, the output signal is also 1, which can continue to control the current of the sampling point of the circuit under test to decrease, so that the sampling signal continues to decrease. When the sampling signal decreases to the next solid dot, it indicates that the sampling signal is lower than the reference signal (in this case, lower than the low-hysteresis reference signal VL). The third selector MUX3 then switches to select the output of the high-hysteresis reference signal VH. This cycle repeats to complete the hysteresis comparison function and outputs the result signal to the subsequent processing circuit (such as GTM or MOS transistor control module). The subsequent processing circuit controls the operation of the circuit under test accordingly, and finally maintains the sampling signal of the sampling point in the hysteresis band.

[0102] The fast comparison circuit FC provided in this embodiment of the invention can realize independent hysteresis band processing for each signal channel. For any signal channel, feedback adjustment is performed according to the different comparison results of the signal channel, and different reference signals are output to the comparison module. In this way, the sampled signals of each signal channel can be stabilized independently in their respective hysteresis bands.

[0103] In summary, this invention provides a fast comparison control implementation scheme based on a channel switching structure, which can be specifically used in MCU product lines. This fast comparison circuit divides the switching cycle: that is, it alternately switches each signal channel and independently processes the comparison results of each channel. This saves area while enabling each signal channel to perform its own comparison and result processing, ensuring the real-time comparison requirements of each signal channel, and reducing costs.

[0104] This fast comparison circuit can be used in application scenarios such as current limiting control and peak current control.

[0105] In a specific application scenario, this fast comparison circuit can be used for current limiting control. Specifically, current limiting control is a basic and crucial protective control strategy. Its core principle is to ensure that the current of the system does not exceed a preset safety threshold. Current limiting control is usually not an independent working mode, but a protective layer superimposed on other control strategies (such as speed control, torque control). Its working process is as follows:

[0106] 1. Current sampling: The current flowing through the motor or power switch tube (such as MOSFET) is monitored in real time through a sampling resistor or Hall current sensor.

[0107] 2. Comparison and judgment: The sampled current value is compared with the preset current limit value (denoted as I_max).

[0108] 3. Trigger protection:

[0109] If the measured current < I_max, the system operates normally according to the established strategy (such as PWM speed regulation).

[0110] If the measured current ≥ I_max, the current limiting controller immediately intervenes to force a change in the system behavior to reduce the current. The most common practices include: 1) Reducing the PWM duty cycle: Immediately reducing the duty cycle of the drive signal, thereby reducing the average voltage applied to the motor and causing the current to drop. 2) Entering the current limiting mode: The system temporarily abandons the original control goal (such as maintaining a certain speed) and instead mainly aims to maintain the current near I_max.

[0111] Current limiting control is mainly applied to power system collapse: Sudden large currents can pull down the vehicle power grid voltage, affecting the normal operation of other electronic devices, and may even cause battery discharge or generator failure in severe cases. And this fast comparison circuit is the core component of the comparison and judgment link.

[0112] In another specific application scenario, this fast comparison circuit can be used for Peak Current Mode Control (PCMC). PCMC is a very popular and efficient switching power supply and motor drive control technology, belonging to current control type technology. Its core idea is to directly control the peak current in the power switch tube within each switching cycle to make it follow a reference signal.

[0113] A typical PCMC system (such as for a DC-DC converter or motor H-bridge drive) includes the following key components and steps:

[0114] 1. Current detection: Use a small sampling resistor or current sensor to detect the instantaneous current in the power inductor or power switching transistor.

[0115] 2. Generate control signal:

[0116] Current reference signal (denoted as I_ref): This signal comes from the outer loop controller. For a motor, it may be the output of a speed loop or torque loop, determining the desired current magnitude.

[0117] Current ramp signal: That is, the instantaneous value of the detected current.

[0118] 3. Comparator and latch:

[0119] Send the detected current ramp signal to the non-inverting input terminal of the comparator, and send I_ref to the inverting input terminal of the comparator.

[0120] When the current ramp signal < I_ref, the comparator outputs a low level, and the power switching transistor (such as a MOSFET) remains conducting, and the current can increase linearly.

[0121] When the current ramp signal ≥ I_ref, the comparator outputs a high level, and this signal will immediately reset an RS latch, for example, to turn off the power switching transistor.

[0122] In this application scenario, the fast comparison circuit is the core component in the comparator.

[0123] Through the above technical means, the fast comparison circuit provided by the embodiment of the present invention realizes that the drive source supports flexible switching of a trigger, a counter, and a result valid flag. Based on the measured results of the dual signal channels, real-time comparison of the dual channels can be achieved in 410 ns, which is further beneficial to realizing the overcurrent detection function.

[0124] Compared with the related technology, the beneficial effects of the embodiment of the present invention are as follows:

[0125] 1. Significant cost-effectiveness: The embodiment of the present invention adopts a multi-channel real-time comparison method. Only one analog comparator, one digital control module (i.e., a channel selection unit), and one digital-to-analog converter are required to realize overcurrent detection of multiple channels. This method significantly reduces the area of analog and digital circuits required for fast comparison of multiple channels, thereby reducing the hardware cost and improving the space utilization rate.

[0126] 2. Simple implementation: The multi-channel real-time comparison method of the embodiment of the present invention realizes automatic control of multiple signal channels through the channel selection module, simplifies the implementation process, and reduces the workload of programming and debugging.

[0127] 3. Multi-channel real-time response: Real-time comparison of multiple channels is achieved by rapidly switching between signal channels.

[0128] 4. High flexibility: The multi-channel real-time comparison method of this invention can flexibly adapt to different overcurrent detection requirements by adjusting the switching period, comparison period and reference signal, and has strong adaptability and flexibility; moreover, different signal channels have their own result processing and hysteresis band processing, making the hysteresis band processing of this invention more flexible.

[0129] 5. Improved reliability: Due to the reduction of at least one channel of comparison circuitry, the possibility of errors is smaller, and the system reliability is better.

[0130] 6. Optimize user experience: For users, fast comparison of multi-channel switching means saving the configuration of control signals for at least one channel.

[0131] In summary, the embodiments of the present invention have significant advantages over existing technologies in terms of cost, area, power consumption, and implementation complexity. This fast comparator circuit can be applied in fields such as industrial control, medical equipment, and environmental monitoring. Overcurrent detection based on this fast comparator circuit can promptly detect abnormalities, ensuring the normal operation of equipment. This fast comparator circuit has broad application prospects.

[0132] This invention also provides a comparator, including the fast comparison circuit provided in any embodiment of this invention, which has corresponding beneficial effects.

[0133] Figure 9 This is a schematic diagram of a comparator provided in an embodiment of the present invention. See also... Figure 9 The comparator 100 may include at least one fast comparison circuit. For example, the number of signal channels required can be determined based on the actual number of sampling points required by the circuit under test, and the number of fast comparison circuits in the comparator 100 can be set accordingly. Figure 9 The example provided includes a first fast comparison circuit FC1, a second fast comparison circuit FC2, and a third fast comparison circuit FC3; subsequent fast comparison circuits are omitted. For example, the comparator 100 may include ten fast comparison circuits. The comparator 100 can be applied to applications such as current limiting control and peak current control, as well as in industrial control, medical equipment, and environmental monitoring.

[0134] This invention also provides an automotive powertrain system, including a comparator as provided in any embodiment of this invention, which has corresponding beneficial effects.

[0135] Figure 10 This is a schematic diagram of the structure of an automotive powertrain system provided in an embodiment of the present invention. See also... Figure 10The automotive powertrain system may include: a circuit under test 200, a current detection module 300, a comparator 100, and a processor 400. Specifically, the circuit under test 200 may include, for example, a motor drive circuit. The current detection module 300 is used to detect the current at each key sampling point in the circuit under test 200 and generate a sampling signal. The comparator 100 is used to receive the sampling signals of different key sampling points through different signal channels and compare them with the corresponding reference signals. The processor 400 is used to adjust the operating state of the circuit under test 200 when the comparison result of any signal channel indicates an overcurrent, so that the current at the key sampling point corresponding to that signal channel is reduced, thereby achieving overcurrent protection.

[0136] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0137] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A fast comparator circuit, characterized in that, include: At least two signal channels; The signal channel includes a signal input terminal and a signal output terminal; The comparison module includes a sampling input terminal, a reference input terminal, and a comparison result output terminal; The comparison module is used to compare the signal accessed at the sampling input terminal with the signal accessed at the reference input terminal, and output the comparison result to the comparison result output terminal. A channel selection module is connected to each of the signal channels and the comparison module respectively; the channel selection module is used to switch the signal channels connected to the comparison module; wherein, at the same time, the channel selection module selects one of the signal channels as the target signal channel, connects the signal input terminal of the target signal channel to the sampling input terminal, connects the signal output terminal of the target signal channel to the comparison result output terminal, and provides the reference signal corresponding to the target signal channel to the reference input terminal.

2. The fast comparison circuit according to claim 1, characterized in that, The channel selection module sequentially controls each signal channel to connect with the comparison module, and switches one signal channel to connect with the comparison module every switching cycle; the switching cycle is greater than or equal to the comparison cycle of the comparison module.

3. The fast comparison circuit according to claim 1 or 2, characterized in that, The channel selection module includes: A first selector, wherein multiple input terminals of the first selector are connected one-to-one with each of the signal input terminals, and the output terminal of the first selector is connected to the sampling input terminal; The second selector has its input terminal connected to the comparison result output terminal, and its multiple output terminals are connected one-to-one with each of the signal output terminals. A channel selection unit is connected to the first selector and the second selector respectively; the channel selection unit is used to control the input terminal of the first selector connected to the signal input terminal of the target signal channel to be connected to the output terminal of the first selector, and to control the input terminal of the second selector to be connected to the output terminal of the second selector connected to the signal output terminal of the target signal channel; A reference signal generation unit, connected to the reference input terminal, is used to provide the reference signal corresponding to the target signal channel to the reference input terminal.

4. The fast comparison circuit according to claim 3, characterized in that, The comparison module further includes a result flag output terminal, and the comparison module is also used to output a result validity flag from the result flag output terminal while outputting the comparison result from the comparison result output terminal; the reference signal generation unit stores reference signals corresponding to each of the signal channels; The channel selection unit is also connected to the result flag output terminal and the reference signal generation unit; the channel selection unit is used to switch the signal channel connected to the comparison module when the result valid flag is received, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

5. The fast comparison circuit according to claim 3, characterized in that, Also includes: trigger; The trigger outputs a trigger signal when the trigger condition is met, and the trigger period of the trigger is greater than or equal to the comparison period of the comparison module. The output of the trigger is connected to the channel selection unit and the reference signal generation unit respectively; the channel selection unit is used to switch the signal channel connected to the comparison module when the trigger signal is received, and the reference signal generation unit is used to switch the output reference signal when the trigger signal is received. or, The output of the trigger is connected to the channel selection unit, and the channel selection unit is connected to the reference signal generation unit. The channel selection unit is used to switch the signal channel connected to the comparison module when the trigger signal is received, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

6. The fast comparison circuit according to claim 5, characterized in that, The output of the trigger is connected to the channel selection unit, and the channel selection unit is connected to the reference signal generation unit; the comparison module also includes a result flag output terminal, and the comparison module is further used to output a result validity flag from the result flag output terminal while outputting the comparison result from the comparison result output terminal; The channel selection unit is also connected to the result flag output terminal; the channel selection unit is used to switch the signal channel connected to the comparison module when it receives the result valid flag for the first time after receiving the trigger signal, and control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

7. The fast comparison circuit according to claim 5, characterized in that, The channel selection unit is also connected to the processor; the channel selection unit is also used to output a trigger loss alarm signal to the processor when it receives more than or equal to three trigger signals within a comparison period.

8. The fast comparison circuit according to claim 3, characterized in that, The channel selection unit is equipped with a counter, and the reference signal generation unit stores the reference signal corresponding to each signal channel. The channel selection unit is also connected to the reference signal generation unit. The channel selection unit is used to switch the signal channel connected to the comparison module when the counter count reaches the counting threshold, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module; wherein, the counter is cleared and starts counting again after the count reaches the counting threshold, and the duration of the counter count reaching the counting threshold is greater than or equal to the comparison period of the comparison module.

9. The fast comparison circuit according to claim 8, characterized in that, The comparison module further includes a result flag output terminal, and the comparison module is also used to output a result validity flag from the result flag output terminal while outputting the comparison result from the comparison result output terminal. The channel selection unit is also connected to the result flag output terminal; the channel selection unit is used to switch the signal channel connected to the comparison module when the result valid flag is received for the first time after the counter count reaches the counting threshold, and to control the reference signal generation unit to output the reference signal corresponding to the signal channel connected to the comparison module.

10. The fast comparison circuit according to claim 3, characterized in that, The comparison module includes an analog comparator, wherein the first input terminal of the analog comparator serves as the sampling input terminal, the second input terminal of the analog comparator serves as the reference input terminal, and the output terminal of the analog comparator serves as the comparison result output terminal; The reference signal output by the reference signal generation unit is a digital signal; The channel selection module further includes a digital-to-analog converter connected between the reference signal generation unit and the reference input terminal, used to convert the reference signal into a digital signal and then provide it to the reference input terminal.

11. The fast comparison circuit according to claim 3, characterized in that, The channel selection module further includes: at least two comparison result processing units corresponding to each of the signal channels; each of the comparison result processing units is connected to each output terminal of the second selector and the corresponding signal output terminal. And / or, the fast comparison circuit further includes: at least two result registers connected in a one-to-one correspondence with each of the signal output terminals; And / or, both the channel selection unit and the reference signal generation unit are connected to the configuration bus and receive corresponding configuration information from the configuration bus.

12. The fast comparison circuit according to claim 3, characterized in that, The reference signal generation unit includes: At least two reference signal processing units, each corresponding to one of the aforementioned signal channels, are provided. Each reference signal processing unit includes a first calculation subunit, a second calculation subunit, and a third selector. The first and second calculation subunits are respectively connected to the two input terminals of the third selector, and the control terminal of the third selector is connected to the signal output terminal of the corresponding signal channel. Specifically, the first calculation subunit generates a high-hysteresis reference signal based on a reference value, the second calculation subunit generates a low-hysteresis reference signal based on the reference value, and the third selector selects one input terminal of the third selector to be connected to its output terminal based on the signal from its control terminal. The high-hysteresis reference signal is greater than the reference value, and the low-hysteresis reference signal is less than the reference value. The fourth selector is connected to the control terminal and output terminal of the reference signal generation unit, and the output terminal of each of the third selectors; the fourth selector is used to select an output terminal of the third selector to be connected to the output terminal of the reference signal generation unit according to the signal of its control terminal.

13. A comparator, characterized in that, include: At least one fast comparison circuit as described in any one of claims 1-12.

14. A vehicle powertrain system, characterized in that, Includes the comparator as described in claim 13.

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