Turning voltage self-protection thyristor and manufacturing method thereof

Abstract

The invention relates to a breakover voltage self-protection thyristor and a manufacturing method thereof. Belongs to the technical field of power semiconductor devices. The IGBT or IGCT collector voltage protection circuit mainly solves the technical problems that self-protection safe conduction can be ensured when the IGBT or IGCT collector voltage reaches a preset value, and energy generated by the voltage in the release process can be used for protecting a device from being damaged. The amplifier is mainly characterized in that an annular auxiliary cathode and an amplification gate pole circular ring are respectively arranged between a central gate pole and an annular cathode of the semiconductor chip, and the annular auxiliary cathode and the amplification gate pole circular ring are provided with metal layers which are electrically connected to form an amplification gate pole metal layer; a sunken circular ring abrupt change junction is arranged in the forward blocking region corresponding to the lower part of the annular auxiliary cathode; and the amplifying gate electrode, the annular cathode and the electrode anode form a main thyristor. The device has the characteristics of being simple in structure and capable of achieving self-protection when the breakover voltage is reached, and is mainly applied to an IGBT or an IGCT used in the fields of rail transit, flexible direct-current transmission converter valves and industrial transmission.

Description

Technical Field

[0001] The present invention belongs to the technical field of the design and manufacture of power semiconductor devices, and particularly relates to a turn-off voltage self-protected thyristor and a manufacturing method thereof. Background Art

[0002] IGCT (Integrated Gate Commutated Thyristors) or IGBT (Insulated Gate Bipolar Transistor) is a turn-off power semiconductor device, which has the advantages of low on-state voltage drop, small switching loss and large current density, and is widely used in the fields of rail transit, flexible DC transmission converter valves and industrial drives. However, in practical applications, as Figure 1 shown, the core converter devices IGBT modules or IGCT devices in the circuit are relatively sensitive to overvoltage and are prone to damage if lack of protection measures or improper use. For example, during the turn-off process of the IGBT module or IGCT, due to the rapid decrease of its collector current, a very high spike overvoltage often occurs between the collector and emitter of the IGBT or IGCT under the action of circuit stray inductance and load inductance; or in the application of high-voltage circuits such as flexible DC transmission, due to system errors or lightning strike factors, spike overvoltage is generated, and the IGBT or IGCT is extremely easy to be broken down, thus causing device damage, affecting the normal operation of the system and increasing costs.

[0003] To avoid the damage of the spike overvoltage to the IGBT or IGCT, the current main methods include: Reducing the stray inductance and parasitic inductance in the loop at the design level, optimizing the internal structure of the IGBT module or the recovery characteristics of the freewheeling diode supporting the IGCT, optimizing the main circuit structure, and reducing the stray inductance. Although it can relieve the pressure caused by overvoltage to the IGBT module or IGCT, its effect is limited.

[0004] While reducing the loop stray inductance, designing an external protection circuit for the IGBT module or IGCT at the circuit design level. The protection circuit adopted by this method needs a large number of electronic components and connection lines to implement, has a relatively complex structure and is slow in response, has losses and line inductance, and this protection method has deficiencies; that is, to protect the IGBT module or IGCT device from being damaged by the reverse spike voltage, it is also necessary to release the energy generated by the overvoltage, which is very likely to cause the IGBT module or IGCT device to be damaged due to overheating.

[0005] Therefore, how to realize a power semiconductor device with a simple structure and overvoltage protection function so that the IGBT or IGCT collector voltage can self-protect when reaching a predetermined value has become an urgent technical problem to be solved. Summary of the Invention

[0006] The technical problem to be solved by the present invention is how to realize a power semiconductor device with a simple structure and overvoltage self-protection function, so as to protect the IGBT or IGCT from damage when the collector voltage of the IGBT or IGCT reaches a predetermined value, thereby solving the shortcomings of existing protection circuits such as poor reliability and high cost.

[0007] The technical solution for the thyristor of this invention is: a turnaround voltage self-protected thyristor, comprising an anode electrode, a cathode electrode, a gate electrode, and a semiconductor chip. The semiconductor chip has a four-layer, three-terminal structure, including a central gate electrode and a central gate electrode metal layer, an amplifying gate electrode and an amplifying gate electrode surface metal layer, and a surrounding annular cathode electrode and a cathode metal layer. The amplifying gate electrode has an auxiliary cathode N+. The central gate electrode metal layer is electrically connected to the gate electrode, and the cathode metal layer is electrically connected to the cathode electrode. The amplifying gate electrode includes an amplifying gate electrode ring outside the auxiliary cathode N+. The auxiliary cathode N+ portion of the amplifying gate electrode is a lower... The structure comprises a recessed annular groove structure, or a recessed disk structure for the auxiliary cathode N+ portion and the central gate of the amplifying gate; the positive blocking region below the auxiliary cathode N+ portion or the central gate of the amplifying gate is provided with a recessed annular abrupt junction or a recessed disk abrupt junction; the recessed annular abrupt junction is aluminum ion doped and has abrupt junction width and depth, and controlling the abrupt junction width and / or depth can control the size of the current passage channel; the amplifying gate, the cathode, and the anode constitute the main thyristor; the central gate, the auxiliary cathode N+, and the anode constitute the auxiliary thyristor.

[0008] In the technical solution of the thyristor of this invention, the auxiliary cathode N+ is a spaced double-ring structure with an auxiliary cathode P-type short-circuit point between them; the amplifying gate surface metal layer includes amplifying gate extension section distributed in a scattering pattern and amplifying gate extension branch at its outer end, which is electrically connected to the auxiliary cathode N+, the auxiliary cathode P-type short-circuit point, and the amplifying gate ring metal layer; the annular cathode includes inner, middle, and outer annular cathode N+ and a cathode P-type short-circuit point between them; a first isolation groove is provided between the central gate and the auxiliary cathode N+; and second isolation grooves are provided between the amplifying gate ring and the cathode N+, and between the cathode metal layer and the surface metal layer.

[0009] In the technical solution of the thyristor of the present invention, the first isolation trench is formed by etching a trench, the trench width is 0.5-0.7 mm, and the depth from the auxiliary cathode N+ surface is 8.0-12.0 µm; the second isolation trench is formed by etching a trench, the trench width is 0.5-0.7 mm, and the depth from the cathode N+ surface is 8.0-12.0 µm.

[0010] In the technical solution of the thyristor of this invention, the cathode metal layer and the amplification gate surface metal layer are made of aluminum electrode material, and the amplification gate surface metal layer is lower than the cathode metal layer; the second isolation trench has a width of 0.5-0.7 mm and a depth of 8.0-40.0 µm; the amplification gate extension section consists of 6 P-type segments, with a width of 1.8-2.8 mm near the amplification gate and connected to the P-type ring of the amplification gate, and the width gradually decreases; at the end of the amplification gate extension section, it is divided into a V-shaped amplification gate extension branch, and the P-type doping width gradually decreases from 1.6-2.4 mm to 0.6-1.2 mm; aluminum electrode material is covered on the amplification gate extension section and the amplification gate extension branch, and connected to the aluminum electrode material of the amplification gate ring.

[0011] In the technical solution of the thyristor of the present invention, the semiconductor chip is provided with a mesa; the central gate, the amplifying gate, the cathode N+, and the mesa constitute the transverse structure of the cathode.

[0012] The semiconductor chip in the technical solution of the thyristor of the present invention includes an anode P1 conductive layer and a cathode P2 conductive layer made of a first type of conductivity material, an N1 substrate conductive layer made of a second type of conductivity material, and an emitter region conductive layer cathode N+ on the cathode P2 conductive layer; the anode P1 conductive layer has an anode metal layer as an electrode anode, a cathode metal layer as an electrode cathode, and a central gate metal layer as an electrode gate on the side away from the N1 substrate conductive layer.

[0013] In the thyristor technical solution of this invention, the semiconductor chip diameter is Φ38~Φ146; the anode P1 conductive layer is composed of an anode P+ layer, an anode P layer, and an anode P- buffer layer; the cathode P2 conductive layer is composed of a cathode P- buffer layer, a cathode P layer, a cathode P+ short-circuit point surrounded by cathode N+, an auxiliary cathode P+ short-circuit point surrounded by auxiliary cathode N+, an amplifying gate ring P+, and a central gate P+; the cathode P+ short-circuit point, the auxiliary cathode P+ short-circuit point, the amplifying gate ring P+, and the central gate P+ are respectively nested in the cathode P-type short-circuit point, the auxiliary cathode P-type short-circuit point, the amplifying gate ring, and the central gate; the cathode P- buffer layer or the cathode P layer creates a P-buffer layer-type recessed circular abrupt junction and a P-layer-type recessed concentration distribution layer in the positive blocking region below the auxiliary cathode N+ and auxiliary cathode P-type short-circuit point regions; the surface concentration of the anode P+ layer is 0.6~8.0×10⁻⁶. 20 / cm 3 The junction depth is 5–15 μm; the surface concentration of the anode P layer and cathode P layer is 0.5–6.0 × 10⁻⁶. 18 / cm 3 The depth is 40–75 µm; the surface concentration of the anode P-buffer layer and the cathode P-buffer layer is 0.22–6.3 × 10⁻⁶. 16 / cm3 The junction depth is 90–110 μm or 110–130 μm; the surface concentration of N+ in the cathode and auxiliary cathode is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 15–25 μm; the surface concentrations of P+ at the cathode short-circuit point, auxiliary cathode P+ short-circuit point, amplification gate ring P+, and center gate P+ are 0.4–3.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5–10 μm; the cathode P+ short-circuit point or auxiliary cathode P+ short-circuit point is cylindrical with a diameter of 100–300 μm; the width of the recessed annular abrupt junction is 2–4 cm and the depth is 10–20 µm; the auxiliary cathode N+ or cathode N+ is an N-type doped region, and cathode P-type short-circuit points or auxiliary cathode P-type short-circuit points with a diameter of 0.10–0.30 mm are uniformly distributed in the N+ doped region, which are connected to the cathode P2 conductive layer under the cathode N+ doped region; cathode P+ short-circuit points or auxiliary cathode P+ short-circuit points are distributed in the P-type short-circuit points, and the amplification gate annular P+ and amplification gate extension P+ are embedded in the amplification gate P-type doped region to form a P-type low-resistance current channel.

[0014] The technical solution for the thyristor of this invention includes a lower sealing component, a lower molybdenum wafer, a potting ring, an upper molybdenum wafer, a gate assembly, and an upper sealing component; the semiconductor chip is mounted between the lower molybdenum wafer and the upper molybdenum wafer.

[0015] The technical solution of the manufacturing method of the present invention is: a method for manufacturing a self-protected thyristor with a breakover voltage, characterized by comprising the following steps: (1) Select type N <100> or <111> High-resistivity single-crystal silicon wafers, used as N-region substrate materials, have a thickness of 700–970 μm or 1050–1300 μm, a resistivity of 160–200 Ω•cm or 300–450 Ω•cm, and undergo double-sided chemical etching or phosphorus absorption treatment. (2) Etching trench: Selectively trench on one side of the central area of ​​the cathode surface of the silicon wafer, with an inner diameter of 3.6-4 mm and a width of 2-4 mm for the trench, or a diameter of 4-8 mm for the trench disc; trench depth of 10-20 μm; (3) P-diffusion: After cleaning the silicon wafer, double-sided aluminum pre-deposition is performed on the silicon wafer at a temperature of 950–1150℃. Then, the aluminum impurities are diffused and oxidized at a low concentration distribution on both sides at a temperature of 1200–1250℃ for 10–30 hours. The resulting P-structures in the P1 and P2 regions have a junction depth of 80–100 μm or 100–120 μm, and the surface impurity concentration is 0.35–8.5 × 10⁻⁶. 16 / cm 3 ; (4) P-diffusion oxidation: After cleaning the silicon wafer, the silicon wafer is pre-deposited with high-concentration aluminum on both sides at a temperature of 950–1150℃; then, the aluminum impurities on both sides are diffused and oxidized at a low concentration distribution at a temperature of 1200–1250℃ for 4–8 hours. The resulting P-structures in the P1 and P2 regions have a junction depth of 30–60 μm and a surface impurity concentration of 0.65–8.5 × 10⁻⁶ μm. 18 / cm 3 ; (5) N+ photolithography: Coating photoresist on the cathode surface of the silicon wafer, photolithographically ... (6) N+ diffusion: After cleaning the silicon wafer, the cathode surface of the silicon wafer is subjected to low-temperature phosphorus pre-deposition or phosphorus ion implantation at a temperature of 1000–1125℃; then, diffusion and oxidation are carried out at a temperature of 1120–1240℃ for 8–12 hours to form a P1-N1-P2-N+ structure, with an N+ impurity concentration of 0.58–8.0 × 10⁻⁶. 20 / cm 3 The cathode N+ depth is 12–20 μm; (7) P+ photolithography: Coating photoresist on the cathode surface of the silicon wafer, photolithographically tracing the P+ region, exposing, developing, removing the oxide layer in the cathode window area, and removing the oxide layer on the anode surface; (8) P+ diffusion: After cleaning the silicon wafer, boron is sprayed onto the anode surface of the silicon wafer. After boron diffusion, an anode P+ layer and a cathode P+ short-circuit point are formed. The depth of the anode P+ layer is 5–15 μm and the depth of the cathode P+ short-circuit point is 5–10 μm. The impurity concentration on the surface of the anode P+ layer is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration of the cathode P+ layer is 0.4–3.0 × 10⁻⁶. 20 / cm 3 The anode P+ is formed by high-concentration boron diffusion, and the cathode P+ is formed by reverse diffusion from the anode boron source. The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source. The silicon wafer is diffused by boron spraying source and constant surface source on both sides. Propulsion conditions: 1180~1250℃, N2=6L / min, O2=0.5L / min, time 60~200min; (9) A metal conductive layer is deposited on both surfaces of the silicon wafer by evaporation. The thickness of the metal conductive layer is 15-30 μm. The metal layers of the central gate and the amplification gate are removed by photolithography on the cathode surface of the electrode. The metal layers of the cathode and the anode of the electrode are formed. A metal conductive layer is deposited on the cathode surface of the silicon wafer. The thickness of the metal conductive layer is 8-20 μm. The metal layer of the isolation region between the central gate and the amplification gate, and between the amplification gate and the electrode cathode is removed by photolithography to form the metal layer of the electrode gate and the amplification gate, while retaining the metal layer of the electrode cathode. (10) Chip surface design, with a double positive angle or double negative angle design; (11) Chemical etching of the chip mesa, followed by passivation and adhesive coating of the mesa edge surface; (12) Final testing of semiconductor chip product parameters.

[0016] Between steps (9) and (10) of the manufacturing method of the present invention, an isolation channel is formed by etching grooves; an oxide layer is provided in the area corresponding to the isolation channel.

[0017] The present invention has the following advantages or beneficial effects: 1. Since the auxiliary cathode N+ portion of the amplifying gate has a recessed annular groove structure, or the auxiliary cathode N+ portion and the central gate of the amplifying gate have a recessed disk structure, it is convenient to form a recessed annular abrupt junction or a recessed disk abrupt junction in the positive blocking region corresponding to the auxiliary cathode N+ portion or the central gate of the amplifying gate. This not only simplifies the process steps, but also facilitates the formation of the recessed annular abrupt junction or the recessed disk abrupt junction, and at the same time reduces the distance between the auxiliary cathode N+ and the recessed annular abrupt junction or the recessed disk abrupt junction.

[0018] 2. Because the auxiliary cathode N+ adopts an alternating double ring structure with an auxiliary cathode P-type short-circuit point between them, it is beneficial for precise control.

[0019] 3. After creating a P2 layer recessed circular abrupt junction or a recessed disk abrupt junction in the forward blocking region below the auxiliary cathode region, when the device reaches the forward breakover voltage, the space charge region of the reverse bias junction expands to the abrupt junction for preferential punch-through. The punch-through current is equal to the trigger current entering the amplification gate, which turns on the auxiliary thyristor. Then, the large current after turn-on is quickly introduced to the amplification gate and the extension line, which is sufficient to enable the main thyristor to achieve strong triggering and achieve self-protection function. By controlling the width L and / or depth of the recessed circular abrupt junction, or by controlling the diameter and / or depth of the recessed disk abrupt junction, the size of the current punch-through channel in the central gate region is controlled, which determines the magnitude of the turn-on extension protection short-circuit current and the turn-on extension sensitivity of the self-protected thyristor, thus realizing the safe conduction of the self-protected thyristor.

[0020] 4. This invention integrates a self-protection function that can trigger the auxiliary thyristor to turn on in advance when the transition voltage is applied inside the device. This eliminates the need for cumbersome external protection and triggering circuits, simplifies the thyristor application circuit, saves costs, and improves reliability.

[0021] 5. The present invention also designs a center gate electrode, which can realize the self-protection function of the transition voltage and the gate-triggered turn-on before the transition voltage, so as to realize the controllable turn-on of the thyristor.

[0022] 6. The thyristor described in this invention is used to protect the IGBT module or IGCT device when used in parallel. When the collector voltage of the IGBT module or IGCT device reaches a predetermined value, the thyristor can be triggered to turn on without an external trigger signal, causing the collector voltage of the IGBT module or IGCT device to drop rapidly, thereby protecting the IGBT module and IGCT device from damage by system overvoltage. After the self-protection thyristor is turned on, it serves as a current path in the main circuit, further releasing the energy generated by system overvoltage.

[0023] 7. The semiconductor chip of the present invention can have a diameter of Φ38 to Φ146, its product blocking voltage reaches 4000 to 8500V, self-protection turn-on extended response time is 5.0 to 20μS, and surge current reaches 150KA.

[0024] This invention features a simple structure and self-protection when the collector voltage of the IGBT or IGCT reaches a predetermined value. It is mainly used in IGBTs or IGCTs applied in rail transit, flexible DC transmission converter valves, and industrial transmission fields. Attached Figure Description

[0025] The accompanying drawings are used to provide a further understanding of the technical solutions of this application or the prior art, and constitute a part of the specification. The accompanying drawings illustrating the embodiments of this application are used together with the embodiments of this application to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0026] Figure 1 This is a schematic diagram of a self-protected thyristor and an IGBT module connected in parallel according to an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of the packaging structure of the self-protected thyristor with transition voltage of the present invention.

[0028] Figure 3 This is a schematic diagram of the chip structure of the self-protected thyristor with transition voltage of the present invention.

[0029] Figure 4 This is a schematic diagram of the magnified gate of the self-protected thyristor with transition voltage of the present invention.

[0030] Figure 5 This is a schematic diagram of the doping concentration distribution structure of the self-protected thyristor with transition voltage according to an embodiment of the present invention.

[0031] Figure 6This is a schematic diagram of the center gate depression structure of the self-protected thyristor with transition voltage according to an embodiment of the present invention.

[0032] Figure 7 This is a schematic diagram of the slotted structure of the self-protected thyristor isolation groove according to an embodiment of the present invention.

[0033] Figure 8 This is a schematic diagram of the isolation groove structure with the center gate of the self-protected thyristor recessed in an embodiment of the present invention.

[0034] In the diagram: A-Anode electrode, K-Cathode electrode, G-Gate electrode, 1-Lower sealant, 2-Lower molybdenum wafer, 3-Glue ring, 4-Semiconductor chip, 5-Upper molybdenum wafer, 6-Gate assembly, 7-Upper sealant, 8-Damped annular abrupt junction, 9-P-layer recessed concentration distribution layer, 40-Anode metal layer, 41-Anode P1 conductive layer, 42- N1 substrate conductive layer, 43-cathode P2 conductive layer, 44-cathode N+, 45-cathode metal layer, 46-amplifier gate, 47-center gate metal layer, 48-cathode P-type short circuit point, 49-mesa, 61-center gate, 62-auxiliary cathode N+, 63-auxiliary cathode P-type short circuit point, 64-amplifier gate ring, 65-first isolation trench, 66-second isolation trench, 411-anode P+ layer, 412-anode P layer, 413-anode P- buffer layer, 431-cathode P- buffer layer, 432-cathode P layer, 433-cathode P+ short circuit point, 610-center gate P+, ​​630-auxiliary anode P+ short circuit point, 640-amplifier gate ring P+, 650-first isolation trench, 660-second isolation trench, G' - Amplify the gate surface metal layer, G'2a - Amplify the gate extension segment, G'2b - Amplify the gate extension branch, L - Abrupt junction width. Detailed Implementation

[0035] The following is combined Figures 2 to 8 The embodiments of the present invention will be described in full here. Obviously, the described embodiments are only a part of the present invention, and not all of them. Any other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0036] Embodiment 1 of the present invention provides a self-protected thyristor with a breakover voltage, as follows: Figure 2 As shown, the turnaround voltage self-protected thyristor consists of a lower sealing component 1, a lower molybdenum wafer 2, a potting ring 3, a semiconductor chip 4, an upper molybdenum wafer 5, a gate assembly 6, and an upper sealing component 7; Figure 3As shown, the semiconductor chip 4 has an anode P1 conductive layer 41 and a cathode P2 conductive layer 43 made of a first type of conductive material, an N1 substrate conductive layer 42 made of a second type of conductive material, and an emitter region conductive layer cathode N+44 on the cathode P2 conductive layer 43. An anode metal layer 40 is disposed on the side of the anode P1 conductive layer 41 away from the N1 substrate conductive layer 42 as an electrode anode A. A cathode metal layer 45 is disposed on the surface of the cathode P2 conductive layer 43 away from the substrate, corresponding to the emitter region conductive layer cathode N+44, as an electrode cathode K. A central gate metal layer 47 is disposed on the surface of the central gate 61 of the central region of the N+44 electrode as the gate electrode G; an auxiliary cathode N+62 and an amplifying gate ring 64 are disposed sequentially at the outer end of the central gate 61 to form an amplifying gate 46; the auxiliary cathode N+62 surrounds the auxiliary cathode P-type short circuit point 63 and is connected to the amplifying gate ring 64 through the amplifying gate surface metal layer G'; the cathode N+44 region is uniformly surrounded by the cathode P-type short circuit point 48; the central gate 61, the amplifying gate 46, the cathode N+44 and the mesa 49 constitute the transverse structure of the cathode. A first isolation groove 65 is provided between the central gate 61 and the auxiliary cathode N+62; a second isolation groove 66 is provided between the amplifying gate ring 64 and the cathode N+44; the auxiliary cathode N+62 and the auxiliary cathode P-type short circuit point 63 are configured as a recessed ring groove, and a P2 layer recessed ring abrupt junction 8 is created in the positive blocking region below the auxiliary cathode N+62 region. The recessed ring abrupt junction 8 is aluminum ion doped. By controlling the width L or depth of the recessed ring abrupt junction 8, the size of the current passage can be controlled.

[0037] like Figure 3 , Figure 4As shown, the amplifying gate 46 is composed of an auxiliary cathode N+62, an amplifying gate ring 64, an amplifying gate extension segment G'2a, and an amplifying gate extension branch G'2b. The amplifying gate 46 is covered with aluminum electrode material that is lower than the height of the cathode metal layer 45, forming an amplifying gate surface metal layer G' formed by the electrical connection between the auxiliary cathode N+62 and the auxiliary cathode P-type short circuit point 63 it surrounds, the amplifying gate ring 64, the amplifying gate extension segment G'2a, and the amplifying gate extension branch G'2b. A second isolation groove 66 is provided between the amplifying gate ring 64, the amplifying gate extension segment G'2a, and the amplifying gate extension branch G'2b and the cathode metal layer 45. The isolation groove has a width of 0.5 to 0.7 mm and a depth of 8.0 to 40.0 µm. The amplification gate extension segment G'2a consists of 6 P-type segments. The width of the segment near the amplification gate 46 is 1.8 to 2.8 mm, and it is connected to the P-type ring of the amplification gate 46. The width gradually decreases. At the end of the amplification gate extension segment G'2a, it is divided into a V-shaped amplification gate extension branch G'2b. The width of the P-type doped segment gradually decreases from 1.6 to 2.4 mm to 0.6 to 1.2 mm. The amplification gate extension segment G'2a and the amplification gate extension branch G'2b are covered with aluminum electrode material and connected to the aluminum electrode material of the amplification gate ring 64.

[0038] like Figure 5 As shown, the anode P1 conductive layer 41 is composed of an anode P+ layer 411, an anode P layer 412, and an anode P- buffer layer 413; the cathode P2 conductive layer 43 is composed of a cathode P- buffer layer 431, a cathode P layer 432, a cathode P+ short-circuit point 433 surrounded by a cathode N+44, an auxiliary cathode P+ short-circuit point 630 surrounded by an auxiliary cathode N+62, an amplification gate ring P+640, and a central gate P+610; the cathode P+ short-circuit point 433, the auxiliary cathode... The P+ short-circuit point 630, the amplifying gate ring P+640, and the center gate P+610 are respectively nested in the cathode P-type short-circuit point 48, the auxiliary cathode P-type short-circuit point 63, the amplifying gate ring 64, and the center gate 61; the cathode P-buffer layer 431 or the cathode P layer 432 creates a P-buffer layer sunken ring abrupt junction 8 and a P-layer sunken concentration distribution layer 9 in the positive blocking region below the auxiliary cathode N+62 and the auxiliary cathode P-type short-circuit point 63 region.

[0039] The auxiliary cathode N+62 or cathode N+44 is an N-type doped region. Within the N+ doped region, cathode P-type short-circuit points 48 or auxiliary cathode P-type short-circuit points 63 with diameters of 0.10–0.30 mm are uniformly distributed, and are connected to the cathode P2 conductive layer 43 under the cathode N+44 doped region. Within the P-type short-circuit points, cathode P+ short-circuit points 433 or auxiliary anode P+ short-circuit points 630 are distributed. Within the P-type doped region of the amplification gate 46, amplification gate ring P+640 and amplification gate extension P+ are embedded, forming a P-type low-resistance current channel.

[0040] The anode P1 conductive layer 41 and the cathode P2 conductive layer 43 are doped with the same impurity aluminum element, the cathode N+44 conductive layer is doped with phosphorus element, and the N1 substrate conductive layer 42 is a high-resistivity N-type silicon single crystal with a resistivity of 160–200 Ω•cm or 300–450 Ω•cm; a thickness of 720–840 µm or 970–1120 µm, and a crystal orientation of [missing information]. <100> The surface concentration of the 411 P+ layer at the anode is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5–15 μm; the surface concentration of the anode P-layer 412 and the cathode P-layer 432 is 0.5–6.0 × 10⁻⁶. 18 / cm 3 The depth is 40–75 µm; the surface concentration of the anode P-buffer layer 413 and the cathode P-buffer layer 431 is 0.22–6.3 × 10⁻⁶. 16 / cm 3 The junction depth is 90–110 μm or 110–130 μm; the surface concentrations of cathode N+44 and auxiliary cathode N+62 are 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 15–25 μm; the surface concentrations of cathode P+ short-circuit point 433, auxiliary cathode P+ short-circuit point 630, amplification gate ring P+640, and center gate P+610 are 0.4–3.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5–10 μm; the cathode P+ short-circuit point 433 or the auxiliary cathode P+ short-circuit point 630 is cylindrical with a diameter of 100–300 μm; the recessed circular abrupt junction 8 has a width of 2–4 cm and a depth of 10–20 µm.

[0041] The working principle of the self-protected thyristor with a breakover voltage according to the present invention is as follows: When a forward voltage is applied to the thyristor, junction j1 ​​is forward biased, and the direction of the applied electric field is opposite to that of the built-in electric field, so the space charge region is shortened here; the direction of the applied electric field is the same as that of the built-in electric field of junction j2, so the space charge region is widened here; when the avalanche breakdown voltage (i.e., the breakover voltage) of junction j2 is applied, a breakover conduction will occur in the weak region of junction j2, causing a negative resistance effect and forming a strong short-circuit current. If this current cannot spread out quickly to reduce the current density, the thyristor will be burned out.

[0042] When a forward voltage is applied to the cathode K of the amplifying gate G', the j3 junction is forward biased. With the thyristor polarity being positive at the bottom and negative at the top, the gate current Ig is forced to flow laterally into the lower end of the cathode, forming a closed loop through the cathode short-circuit point and cathode K. Due to the lateral resistance of the short base region of P2, the gate current density is highest near the gate's N+ region and lowest further away. As the gate voltage and gate current Ig increase, when the threshold voltage for the forward bias j3 junction to turn on is reached, the N+ region near the amplifying gate reaches its turn-on voltage earliest, introducing the short-circuit current of the auxiliary thyristor into the amplifying gate G', causing a strong triggering of the amplifying gate and forming the normal triggering mode of the thyristor, allowing the thyristor to conduct safely.

[0043] After creating a P2 layer with a drooping abrupt junction in the forward blocking region below the auxiliary cathode region, when the device reaches the forward breakover voltage, the space charge region of the reverse bias junction expands to the abrupt junction for preferential punch-through. The punch-through current under the auxiliary cathode is equivalent to the trigger current entering the amplification gate, enabling the auxiliary thyristor to turn on quickly. Then, the large current after turn-on is rapidly introduced to the amplification gate and the extension line, which is sufficient to enable the main thyristor to achieve strong triggering and achieve self-protection function. By controlling the width (L) or depth of the drooping circular abrupt junction, the size of the current punch-through channel in the central gate region is controlled, which determines the magnitude of the turn-on extension protection short-circuit current and the turn-on extension sensitivity of the self-protected thyristor, thus achieving safe conduction of the self-protected thyristor.

[0044] Example 2 Figure 6 , Figure 4 As shown, unlike embodiment 1, the central gate 61, auxiliary cathode N+62 and auxiliary cathode P-type short circuit point 63 are set as a recessed circular groove. At the same time, a P-buffer layer recessed disk junction 8 or a P-layer recessed concentration distribution layer 9 is created in the positive blocking region below this circular groove. By controlling the width L or depth of the recessed disk junction 8, the size of the current passage can be controlled.

[0045] Example 3 Figure 7 , Figure 4 As shown, Example 4 is as follows Figure 8 , Figure 4 As shown, unlike Embodiments 1 and 2, the central gate 61 and the auxiliary cathode N+62 of the amplification gate are etched to form a first isolation trench 650, with a trench width of 0.5-0.7 mm and a depth of 8.0-12.0 µm from the surface of the auxiliary cathode N+62; the amplification gate ring 64, the amplification gate extension G'2a, the amplification gate extension branch G'2b and the contact area with the cathode N+44 are etched to form a second isolation trench 660, with a trench width of 0.5-0.7 mm and a depth of 8.0-12.0 µm from the surface of the cathode N+44.

[0046] This invention provides a self-protected thyristor with a breakover voltage and a manufacturing method thereof, specifically including the following steps: (1) Select type N <100> or <111> High-resistivity single-crystal silicon wafers, used as N-region substrate materials, have a thickness of 700–970 μm or 1050–1300 μm, a resistivity of 160–200 Ω•cm or 300–450 Ω•cm, and undergo double-sided chemical etching or phosphorus absorption treatment. (2) Etching trench: Selectively trench on one side of the central area of ​​the cathode surface of the silicon wafer, with an inner diameter of 3.6-4 mm and a width of 2-4 mm for the trench, or a diameter of 4-8 mm for the trench disc; trench depth of 10-20 μm; (3) P-diffusion: After cleaning the silicon wafer, double-sided aluminum pre-deposition is performed on the silicon wafer at a temperature of 950–1150℃. Then, the aluminum impurities are diffused and oxidized at a low concentration distribution on both sides at a temperature of 1200–1250℃ for 10–30 hours. The resulting P-structures in the P1 and P2 regions have a junction depth of 80–100 μm or 100–120 μm, and the surface impurity concentration is 0.35–8.5 × 10⁻⁶. 16 / cm 3 ; (4) P-diffusion oxidation: After cleaning the silicon wafer, the silicon wafer is pre-deposited with high-concentration aluminum on both sides at a temperature of 950–1150℃; then, the aluminum impurities on both sides are diffused and oxidized at a low concentration distribution at a temperature of 1200–1250℃ for 4–8 hours. The resulting P-structures in the P1 and P2 regions have a junction depth of 30–60 μm and a surface impurity concentration of 0.65–8.5 × 10⁻⁶ μm. 18 / cm 3 ; (5) N+ photolithography: Coating photoresist on the cathode surface of the silicon wafer, photolithography of the P area, exposure, development, protection of the anodic oxide layer, and removal of the oxide layer in the cathode N+44 window area; (6) N+ diffusion: After cleaning the silicon wafer, the cathode surface of the silicon wafer is subjected to low-temperature phosphorus pre-deposition or phosphorus ion implantation at a temperature of 1000–1125℃; then diffusion and oxidation are carried out at a temperature of 1120–1240℃ for 8–12 hours to form a P1-N1-P2-N+ structure, with an impurity concentration of 0.58–8.0 × 10⁻⁶ on the cathode N+44 surface. 20 / cm 3 The cathode N+ depth is 12–20 μm; (7) P+ photolithography: Coating photoresist on the cathode surface of the silicon wafer, photolithographically tracing the P+ region, exposing, developing, removing the oxide layer in the cathode window area, and removing the oxide layer on the anode surface; (8) P+ diffusion: After cleaning the silicon wafer, boron is sprayed onto the anode surface of the silicon wafer. After boron diffusion, an anode P+ layer 411 and a cathode P+ short-circuit point 433 are formed. The depth of the anode P+ layer 411 is 5-15 μm and the depth of the cathode P+ short-circuit point 433 is 5-10 μm. The impurity concentration on the surface of the anode P+ layer 411 is 0.6-8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration of the cathode P+ layer is 0.4–3.0 × 10⁻⁶. 20 / cm 3 The anode P+ is formed by high-concentration boron diffusion, and the cathode P+ is formed by reverse diffusion from the anode boron source. The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source. The silicon wafer is diffused by boron spraying source and constant surface source on both sides. Propulsion conditions: 1180~1250℃, N2=6L / min, O2=0.5L / min, time 60~200min; (9) A metal conductive layer is deposited on both surfaces of the silicon wafer by evaporation. The thickness of the metal conductive layer is 15-30 μm. The metal layer of the central gate 61 and the amplification gate 46 is removed by photolithography on the cathode K surface. The metal layer of the cathode K and the metal layer of the anode A are formed. A metal conductive layer is deposited on the cathode surface of the silicon wafer. The thickness of the metal conductive layer is 8-20 μm. The metal layer of the isolation region between the central gate 61 and the amplification gate 46, and between the amplification gate 46 and the electrode cathode K is removed by photolithography to form the metal layer 47 of the electrode gate G and the amplification gate surface metal layer G' of the amplification gate 46, while retaining the metal layer of the electrode cathode K. (10) Chip surface design, with a double positive angle or double negative angle design; (11) Chemical etching of the chip mesa, followed by passivation and adhesive coating of the edge surface of the mesa 49; (12) Final test of semiconductor chip 4 product parameters.

[0047] This invention provides a self-protected thyristor with a transition voltage and a manufacturing method thereof. Between steps (9) and (10) above, an isolation channel is formed by etching and trenching. An oxide insulating film is disposed in the area corresponding to the isolation channel. This insulating film is a SiN polycrystalline silicon film, a SiO2 film, or a polyimide film.

Claims

1. A turnaround voltage self-protected thyristor, comprising an anode (A), a cathode (K), a gate (G), and a semiconductor chip (4), wherein the semiconductor chip (4) is a four-layer three-terminal structure, comprising a central gate (61) and a central gate metal layer (47), an amplifying gate (46) and an amplifying gate surface metal layer (G'), and a surrounding annular cathode and a cathode metal layer (45), wherein the amplifying gate (46) is provided with an auxiliary cathode N+ (62), the central gate metal layer (47) is electrically connected to the gate (G), and the cathode metal layer (45) is electrically connected to the cathode (K), characterized in that: The amplifying gate (46) includes an amplifying gate ring (64) outside the auxiliary cathode N+ (62); the auxiliary cathode N+ (62) portion of the amplifying gate (46) is a recessed annular groove structure, or the auxiliary cathode N+ (62) portion and the central gate (61) of the amplifying gate (46) are recessed disk structures; the auxiliary cathode N+ (62) portion of the amplifying gate (46) or the auxiliary cathode N+ (62) portion and the central gate (61) of the amplifying gate (46) are... The corresponding positive blocking region below is provided with a recessed circular abrupt junction (8) or a recessed disk abrupt junction; the recessed circular abrupt junction (8) is aluminum ion doped and has a junction width (L) and depth, and the size of the current passage can be controlled by controlling the junction width (L) and / or the depth; the amplifying gate (46), the electrode cathode (K) and the electrode anode (A) constitute the main thyristor; the central gate (61), the auxiliary cathode N+ (62) and the electrode anode (A) constitute the auxiliary thyristor.

2. The self-protected thyristor with a breakover voltage according to claim 1, characterized in that: The auxiliary cathode N+ (62) is a double-ring structure with an auxiliary cathode P-type short-circuit point (63) between them; the amplification gate surface metal layer (G') includes a scattering amplification gate extension section (G'2a) and an amplification gate extension branch (G'2b) at its outer end, which are electrically connected to the auxiliary cathode N+ (62), the auxiliary cathode P-type short-circuit point (63) and the amplification gate ring (64); the annular cathode includes inner, middle and outer annular cathodes N+ (44) and a cathode P-type short-circuit point (48) between them; a first isolation groove (65) is provided between the central gate (61) and the auxiliary cathode N+ (62); a second isolation groove (66) is provided between the amplification gate ring (64) and the cathode N+ (44), and between the cathode metal layer (45) and the surface metal layer.

3. A self-protected thyristor with a breakover voltage according to claim 2, characterized in that: The first isolation trench (65) is formed by etching a trench to form a first isolation trench (650), the trench width is 0.5 to 0.7 mm, and the depth from the surface of the auxiliary cathode N+ (62) is 8.0 to 12.0 µm; the second isolation trench (66) is formed by etching a trench to form a second isolation trench (660), the trench width is 0.5 to 0.7 mm, and the depth from the surface of the cathode N+ (44) is 8.0 to 12.0 µm.

4. A self-protected thyristor with a breakover voltage according to any one of claims 1-3, characterized in that: The cathode metal layer (45) and the amplification gate surface metal layer (G') are made of aluminum electrode material, and the amplification gate surface metal layer (G') is lower than the cathode metal layer (45); the second isolation trench (66) has a width of 0.5-0.7 mm and a depth of 8.0-40.0 µm; the amplification gate extension (G'2a) is composed of 6 P-type line segments, with a width of 1.8-2.8 mm near the amplification gate (46), and is connected to the P-type ring of the amplification gate (46), with the width gradually decreasing; at the end of the amplification gate extension (G'2a), it is divided into a V-shaped amplification gate extension branch (G'2b), with the P-type doped width gradually decreasing from 1.6-2.4 mm to 0.6-1.2 mm; aluminum electrode material is covered on the amplification gate extension (G'2a) and the amplification gate extension branch (G'2b), and is connected to the aluminum electrode material of the amplification gate ring (64).

5. A self-protected thyristor with a breakover voltage according to any one of claims 1-3, characterized in that: The semiconductor chip (4) has a mesa (49); the central gate (61), the amplification gate (46), the cathode N+ (44) and the mesa (49) constitute the transverse structure of the cathode.

6. A self-protected thyristor with a breakover voltage according to any one of claims 1-3, characterized in that: The semiconductor chip (4) includes an anode P1 conductive layer (41) and a cathode P2 conductive layer (43) made of a first type of conductive material, an N1 substrate conductive layer (42) made of a second type of conductive material, and an emitter region conductive layer cathode N+ (44) on the cathode P2 conductive layer (43); the anode P1 conductive layer (41) has an anode metal layer (40) as an electrode anode (A) on the side away from the N1 substrate conductive layer (42), a cathode metal layer (45) as an electrode cathode (K), and a central gate metal layer (47) as an electrode gate (G).

7. A self-protected thyristor with a breakover voltage according to claim 6, characterized in that: The semiconductor chip (4) has a diameter of Φ38~Φ146; the anode P1 conductive layer (41) is composed of an anode P+ layer (411), an anode P layer (412), and an anode P- buffer layer (413); the cathode P2 conductive layer (43) is composed of a cathode P- buffer layer (431), a cathode P layer (432), a cathode N+ (44) surrounding a cathode P+ short-circuit point (433), an auxiliary cathode N+ (62) surrounding an auxiliary cathode P+ short-circuit point (630), an amplification gate ring P+ (640), and a central gate P+ (610); the cathode P+ short-circuit point (433), the auxiliary cathode P+ short-circuit point (433), the auxiliary cathode N+ (62) surrounding an auxiliary cathode P+ short-circuit point (630), an amplification gate ring P+ (640), and a central gate P+ (610); The path point (630), the amplifying gate ring P+ (640), and the center gate P+ (610) are nested in the cathode P-type short-circuit point (48), the auxiliary cathode P-type short-circuit point (63), the amplifying gate ring (64), and the center gate (61), respectively; the cathode P-buffer layer (431) or the cathode P layer (432) creates a P-buffer layer-depressed circular abrupt junction (8) and a P-layer-depressed concentration distribution layer (9) in the positive blocking region below the auxiliary cathode N+ (62) and the auxiliary cathode P-type short-circuit point (63); the surface concentration of the anode P+ layer (411) is 0.6~8.0×10 20 / cm 3 The junction depth is 5–15 μm; the surface concentration of the anode P layer (412) and cathode P layer (432) is 0.5–6.0 × 10⁻⁶. 18 / cm 3 The depth is 40–75 µm; the surface concentration of the anode P-buffer layer (413) and the cathode P-buffer layer (431) is 0.22–6.3 × 10⁻⁶. 16 / cm 3 The junction depth is 90–110 μm or 110–130 μm; the surface concentration of cathode N+ (44) and auxiliary cathode N+ (62) is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 15–25 μm; the surface concentrations of the cathode P+ short-circuit point (433), auxiliary cathode P+ short-circuit point (630), amplification gate ring P+ (640), and center gate P+ (610) are 0.4–3.0 × 10⁻⁶. 20 / cm 3 The junction depth is 5-10 μm; the cathode P+ short circuit point (433) or the auxiliary cathode P+ short circuit point (630) is cylindrical with a diameter of 100-300 μm; the recessed circular abrupt junction (8) has a width of 2-4 cm and a depth of 10-20 µm; the auxiliary cathode N+ (62) or cathode N+ (44) is an N-type doped region, and the cathode P-type short circuit point (48) or auxiliary cathode P-type short circuit point (63) with a diameter of 0.10-0.30 mm is uniformly distributed in the N+ doped region, which is connected to the cathode P2 conductive layer (43) under the cathode N+ (44) doped region; the cathode P+ short circuit point (433) or auxiliary cathode P+ short circuit point (630) is distributed in the P-type short circuit point, and the amplification gate P-type doped region is embedded with the amplification gate circular ring P+ (640) and the amplification gate extension P+, forming a P-type low-resistance current channel.

8. A self-protected thyristor with a breakover voltage according to any one of claims 1-3 and 7, characterized in that: It includes a lower sealing component (1), a lower molybdenum wafer (2), a glue ring (3), an upper molybdenum wafer (5), a gate assembly (6), and an upper sealing component (7); the semiconductor chip (4) is mounted between the lower molybdenum wafer (2) and the upper molybdenum wafer (5).

9. A method for manufacturing a self-protected thyristor with a breakover voltage, characterized in that: Includes the following steps: (1) Select type N <100> or <111> High-resistivity single-crystal silicon wafers, used as N-region substrate materials, have a thickness of 700–970 μm or 1050–1300 μm, a resistivity of 160–200 Ω•cm or 300–450 Ω•cm, and undergo double-sided chemical etching or phosphorus absorption treatment. (2) Etching trench: Selectively trench on one side of the central area of ​​the cathode surface of the silicon wafer, with an inner diameter of 3.6-4 mm and a width of 2-4 mm for the trench, or a diameter of 4-8 mm for the trench disc; trench depth of 10-20 μm; (3) P-diffusion: After cleaning the silicon wafer, double-sided aluminum pre-deposition is performed on the silicon wafer at a temperature of 950–1150℃. Then, the aluminum impurities are diffused and oxidized at a low concentration distribution on both sides at a temperature of 1200–1250℃ for 10–30 hours. The resulting P-structures in the P1 and P2 regions have a junction depth of 80–100 μm or 100–120 μm, and the surface impurity concentration is 0.35–8.5 × 10⁻⁶. 16 / cm 3 ; (4) P-diffusion oxidation: After cleaning the silicon wafer, the silicon wafer is pre-deposited with high-concentration aluminum on both sides at a temperature of 950–1150℃; then, the aluminum impurities on both sides are diffused and oxidized at a low concentration distribution at a temperature of 1200–1250℃ for 4–8 hours. The resulting P-structures in the P1 and P2 regions have a junction depth of 30–60 μm and a surface impurity concentration of 0.65–8.5 × 10⁻⁶ μm. 18 / cm 3 ; (5) N+ photolithography: Coating photoresist on the cathode surface of the silicon wafer, photolithography of the P region, exposure, development, protection of the anodic oxide layer, and removal of the oxide layer in the cathode N+ (44) window region; (6) N+ diffusion: After cleaning the silicon wafer, the cathode surface of the silicon wafer is subjected to low-temperature phosphorus pre-deposition or phosphorus ion implantation at a temperature of 1000-1125℃; then diffusion and oxidation are carried out at a temperature of 1120-1240℃ for 8-12 hours to form a P1-N1-P2-N+ structure, and the impurity concentration of N+ (44) on the cathode surface is 0.58-8.0×10 20 / cm 3 The cathode N+ depth is 12–20 μm; (7) P+ photolithography: Coating photoresist on the cathode surface of the silicon wafer, photolithographically tracing the P+ region, exposing, developing, removing the oxide layer in the cathode window area, and removing the oxide layer on the anode surface; (8) P+ diffusion: After cleaning the silicon wafer, boron is sprayed onto the anode surface of the silicon wafer. After boron diffusion, an anode P+ layer (411) and a cathode P+ short-circuit point (433) are formed. The depth of the anode P+ layer (411) is 5-15 μm and the depth of the cathode P+ short-circuit point (433) is 5-10 μm. The impurity concentration on the surface of the anode P+ layer (411) is 0.6-8.0×10⁻⁶. 20 / cm 3 The surface impurity concentration of the cathode P+ layer is 0.4–3.0 × 10⁻⁶. 20 / cm 3 The anode P+ is formed by high-concentration boron diffusion, and the cathode P+ is formed by reverse diffusion from the anode boron source. The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source. The silicon wafer is diffused by boron spraying source and constant surface source on both sides. Propulsion conditions: 1180~1250℃, N2=6L / min, O2=0.5L / min, time 60~200min; (9) A metal conductive layer is deposited on both surfaces of the silicon wafer by evaporation. The thickness of the metal conductive layer is 15-30 μm. The metal layers of the central gate (61) and the amplification gate (46) are removed by photolithography on the cathode (K) surface of the electrode. The metal layers of the cathode (K) and the anode (A) are formed. A metal conductive layer is deposited on the cathode surface of the silicon wafer. The thickness of the metal conductive layer is 8-20 μm. The metal layer of the isolation region between the central gate and the amplification gate (46), and between the amplification gate (46) and the electrode cathode (K) is removed by photolithography to form the metal layers of the electrode gate (G) and the amplification gate (G'), while retaining the metal layer of the electrode cathode (K). (10) Chip surface design, with a double positive angle or double negative angle design; (11) Chemical etching of the chip mesa, followed by passivation and adhesive coating of the mesa (49) edge surfaces; (12) Final test of semiconductor chip (4) product parameters.

10. A method for manufacturing a self-protected thyristor with a breakover voltage according to claim 9, characterized in that: Between steps (9) and (10), an isolation trench is formed by corrosion trenching; an oxide layer is set in the area corresponding to the isolation trench.

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