Fine circuit FCBGA packaging substrate and preparation method thereof

Abstract

The invention discloses a preparation method of a fine circuit FCBGA packaging substrate, and the method comprises the steps: S1, providing an inner-layer core plate, attaching photosensitive dry films to the two sides of the inner-layer core plate, and manufacturing a graphic circuit of a Core layer through a subtractive method; s2, preprocessing the circuit, and laminating an ABF film to the surface of the circuit through vacuum lamination to form a lamination BU01 layer; s3, drilling is conducted on the ABF film, first-time surface treatment is conducted, and the surface appearance of the ABF film laminated with the BU01 layer is treated; s4, forming a metal seed layer on the ABF film on which the BU01 layer is laminated, and manufacturing a pattern circuit of the BU01 layer by adopting a semi-additive method; s5, repeatedly executing the steps S2 to S4, and continuously constructing a BU (n + 1) layer on the formed BU (n) layer in sequence; and S6, preprocessing the pattern circuit on the outermost layer, and pressing the solder resist ink to the surface of the pattern circuit to form a solder resist layer. The method can solve the problem that a traditional FCBGA packaging substrate is difficult to meet low roughness and high binding force at the same time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically to a fine-line FCB-GA packaging substrate and its preparation method. Background Technology

[0002] With the continuous advancement of semiconductor technology and the widespread adoption of high-performance electronic products, packaging substrates, as crucial bridges connecting chips to external circuits, are undergoing constant innovation in their processes and materials. FCBGA packaging substrates, due to their compact structure, high-speed signal transmission, and excellent heat dissipation, are widely used in high-end electronic products. In the traditional manufacturing process of FCBGA packaging substrates, a wet adhesive removal process is typically used to create a high surface roughness on the dielectric layer, thereby increasing the bonding strength between dielectric layers, between dielectric layers and circuit layers, and between dielectric layers and solder mask layers, ensuring the overall reliability of the packaging substrate. However, as electronic products trend towards high-density wiring, high-speed transmission, and high-layer-count, low-warpage designs, the requirements for packaging substrate materials and processes are becoming increasingly stringent. Under high-frequency signals, the skin effect causes current to concentrate on the conductor surface. A high-roughness dielectric layer leads to unevenness on the surface of the circuit layers it contacts, increasing the tortuosity of the current path, thus increasing AC resistance and exacerbating conductor losses. Simultaneously, the rough surface may cause transmission line impedance discontinuities, resulting in signal reflection and scattering, especially when the signal wavelength and roughness are comparable.

[0003] On the one hand, while higher surface roughness ensures the overall reliability of the packaging substrate, it may lead to localized plating risks during patterning, especially in fine-line areas. Excessive roughness can easily cause micro-short circuits or short circuits at the bottom of fine lines, thus affecting line shape control and overall product yield. On the other hand, with the development of fine-line technology, the line spacing is gradually decreasing, placing higher demands on the flatness of the substrate surface. Traditional processes can no longer balance low roughness and high adhesion, thus affecting product reliability. Therefore, it is necessary to provide a fine-line FC-BGA packaging substrate and its preparation method to effectively solve the balance between low surface roughness and high adhesion of the dielectric layer, while ensuring the product reliability of the packaging substrate. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a fine-line FCBGA packaging substrate and its preparation method in order to overcome the shortcomings of the prior art. The method can solve the problem that traditional FC-BGA packaging substrates are difficult to simultaneously meet the requirements of low roughness and high bonding strength.

[0005] To achieve the above objectives, according to one aspect of the present invention, a method for fabricating a fine-line FCBGA package substrate is provided, comprising the following steps: S1. Provide an inner core board, attach photosensitive dry film to the copper surfaces on both sides of the inner core board, and fabricate the pattern circuit of the Core layer by subtractive processing. S2. Preprocess the patterned circuit of the Core layer and press the ABF film onto the surface of the Core layer to form a stacked BU01 layer; S3. Drill holes and perform surface treatment on the ABF film of the stacked BU01 layer to process the surface morphology of the ABF film of the stacked BU01 layer. S4. A metal seed layer is formed on the ABF film of the stacked BU01 layer, and the patterned circuit of the BU01 layer is fabricated by a semi-additive method. S5. Repeat steps S2 to S4, sequentially constructing BU(n+1) layers on top of the already formed BU(n) layers, where n≥1, and the formation of each BU(n+1) layer includes: The pattern circuit of the previous BU(n) layer is preprocessed; the ABF film is pressed onto the surface of the BU(n) layer to form a new stacked BU(n+1) layer; the ABF film of the BU(n+1) layer is drilled and surface-processed; a metal seed layer is formed on the ABF film of the BU(n+1) layer; the pattern circuit of the BU(n+1) layer is fabricated by a semi-additive method. S6. Preprocess the outermost graphic circuit and press the solder resist ink onto its surface to form a solder resist layer.

[0006] In the above scheme, the thickness of the photosensitive dry film is 15-25 μm.

[0007] In the above scheme, the process of fabricating the core layer pattern circuit by subtractive method includes pattern preprocessing, film application, exposure, development, etching and film removal.

[0008] In the above scheme, the pretreatment includes ultra-roughening treatment and baking.

[0009] In the above scheme, the metal seed layer is formed by a thin film deposition process.

[0010] In the above scheme, the solder resist ink includes liquid photosensitive solder resist ink or dry film solder resist ink.

[0011] In the above scheme, the drilling is performed using CO2 laser drilling or UV laser drilling.

[0012] In the above scheme, the method for treating the surface morphology of the ABF film of the stacked BU01 layer includes wet chemical degumming and dry plasma treatment.

[0013] In the above scheme, the material of the metal seed layer is Ti, Ni, P, Ag, Au or Cu, and its thickness is 30nm-1000nm.

[0014] In the above scheme, the process of fabricating patterned circuits by the semi-additive method includes seed layer deposition, film application, exposure, development, pattern electroplating, film removal, and etching.

[0015] In the above scheme, the surface treatment is wet chemical desmearing and dry plasma treatment, which selectively acts on the exposed ABF film at the line gap to increase its surface roughness, thereby improving the adhesion between the laminated ABF film and the laminated ABF film and the solder resist ink layer, but has no effect on the line surface.

[0016] The present invention also provides a fine-line FC-BGA package substrate prepared by the above-described method for preparing a fine-line FCBGA package substrate.

[0017] This invention provides a method for fabricating an FCBGA package substrate. The method involves a first ABF film surface treatment to create a surface morphology that satisfies the relationship between the ABF film and the plating layer. Then, a semi-additive method is used to fabricate the BU layer pattern circuitry, forming low-roughness circuitry to protect the package substrate and minimize signal transmission loss. Subsequently, a second surface treatment is performed on the exposed ABF film to create a surface morphology that satisfies the relationship between the ABF film and the solder resist ink layer. Finally, the solder resist layer is fabricated using a solder resist lamination process.

[0018] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: This invention provides a method for fabricating a fine-line FCBGA packaging substrate. This method can solve the problem that traditional FCBGA packaging substrates cannot simultaneously meet the requirements of low roughness and high bonding strength. This method breaks down the interlayer bonding reliability of traditional FCBGA packaging substrates into three parts. Taking the 6-layer packaging substrate of this invention as an example, it includes the Core layer circuit and the BU01 layer dielectric layer, the BU01 layer dielectric layer and the BU02 layer circuit, and the BU02 layer dielectric layer and the solder mask layer. The surface roughness of the dielectric layer of the corresponding layer is controlled step by step, thereby ensuring that the dielectric layer under the circuit layer has low roughness and high transmission efficiency, while the dielectric layer to dielectric layer and the dielectric layer to solder mask layer can maintain high roughness and relatively stable reliability.

[0019] This invention provides a fine-line FCBGA packaging substrate. Compared with the traditional FCBGA packaging substrate, the FC-BGA packaging substrate of this invention can achieve a lower roughness of the dielectric layer under the circuit layer while maintaining product reliability. This is beneficial for reducing AC resistance and conductor loss, and improving the skin effect. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic flowchart illustrating a method for fabricating a fine-line FCBGA packaging substrate according to an embodiment of the present invention.

[0021] Figure 2 A schematic diagram of the core board in an embodiment of the present invention.

[0022] Figure 3 A schematic diagram of the structure after the Core layer graphic circuit is formed in an embodiment of the present invention.

[0023] Figure 4 A schematic diagram of the structure after the formation of the BU01 layer in an embodiment of the present invention.

[0024] Figure 5 This invention provides a schematic diagram of the structure of the BU01 layer ABF film after laser drilling, descaling, and the first surface treatment.

[0025] Figure 6 A schematic diagram of the structure of the BU01 layer pattern circuit and the secondary surface treatment of the ABF film completed by the semi-additive method in this embodiment of the invention.

[0026] Figure 7 A schematic diagram of the structure after the BU02 layer ABF film and patterned circuit are completed in this embodiment of the invention.

[0027] Figure 8 A schematic diagram of the structure of the BU02 layer pattern circuit and the secondary surface treatment of the ABF film completed by the semi-additive method in this embodiment of the invention.

[0028] Figure 9 A schematic diagram of the structure after the solder mask layer is completed in an embodiment of the present invention.

[0029] Figure label: 0. Core board resin layer; 1. Core board copper foil layer; 2. Through-hole; 3. Core layer pattern circuit; 4. ABF film of stacked BU01 layer; 5. Blind via; 6. ABF film with surface morphology treatment; 7. BU01 layer pattern circuit; 8. Exposed ABF film; 9. BU02 layer pattern circuit; 10. ABF film exposed again; 11. ABF film with surface treatment again; 12. BU02 layer pattern circuit; 13. Solder mask layer; 14. Solder mask layer. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0031] It should be understood that the sequence number of each step in the embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0032] This application provides a method for fabricating a fine-line FCBGA packaging substrate. The resulting packaging substrate has a 6-layer board structure. Please refer to [link / reference]. Figure 1 The preparation method of this embodiment includes: S1. Provide an inner core board, attach photosensitive dry film to the copper surfaces on both sides of the inner core board, and fabricate the pattern circuit of the Core layer using a subtractive method. S2. The pattern circuit of the Core layer is roughened and baked pre-processed, and the ABF film is pressed onto the surface of the Core layer by vacuum pressing to form a stacked BU01 layer. S3. Drill holes, remove adhesive residue, and perform a first surface treatment on the ABF film of the stacked BU01 layer to remove adhesive residue in the blind holes and treat the surface morphology of the ABF film of the stacked BU01 layer. S4. A metal seed layer is formed on the ABF film of the stacked BU01 layer by thin film deposition process, and the patterned circuit of the BU01 layer is fabricated by semi-addition method. S5. Perform a second surface treatment on the BU01 layer, then perform ultra-roughening and baking pretreatment on the pattern circuit of the BU01 layer, and press the ABF film onto the surface of the BU01 layer to form a stacked BU02 layer by vacuum pressing, and then fabricate the pattern circuit of the BU02 layer by a semi-additive method. S6. The graphic circuit of the BU02 layer is roughened and pre-treated by baking, and the solder resist ink is pressed onto the surface of the BU02 layer by vacuum pressing to form a solder resist layer.

[0033] The method for fabricating the FC-BGA package substrate according to this application involves: firstly, surface treatment of the ABF film to form a surface morphology that satisfies the relationship between the ABF film and the plating layer; then, fabrication of the BU layer pattern circuit using a semi-additive method to form a low-roughness circuit to protect the package substrate and minimize signal transmission loss; subsequently, a second surface treatment of the exposed ABF film to form a surface morphology that satisfies the relationship between the ABF film and the solder mask; and finally, fabrication of the solder mask layer by solder mask lamination, thereby preparing an FCBGA package substrate with good reliability and low signal loss.

[0034] The following is in conjunction with the appendix Figures 1-9 This paper further describes a method for fabricating a fine-line FC-BGA packaging substrate, specifically including: First, refer to Figure 1 and Figure 2 Step S1 is executed, providing an inner core board, wherein the inner core board includes a core board resin layer 0 and core board copper foil layers 1 located on opposite sides of the core board resin layer 0. Next, refer to... Figure 3 A through-hole 2 is formed to penetrate the inner core board, and the graphic circuit 3 of the Core layer is made by subtraction method.

[0035] Specifically, when making through holes 2 on the inner core board, mechanical drilling or laser drilling can be used. Mechanical drilling can be performed using a mechanical drilling machine. In this embodiment, the diameter of the mechanical through hole formed by mechanical drilling is 150μm, but it is not limited to this. In some preferred embodiments of this application, the diameter can be 100μm to 200μm, such as 100μm, 150μm, 200μm, etc. Laser drilling can be performed by drilling on both sides of the inner core board using a laser drilling machine, and the diameter can be 100μm to 200μm, etc. Subsequently, the through hole 2 is subjected to desmearing, copper plating, and electroplating to form the final through hole 2. The selected method is wet chemical desmearing and chemical copper plating, but it is not limited to this. Some preferred embodiments of this application can select the corresponding desmearing and copper plating methods according to specific needs. Among them, the surface copper thickness of chemical copper plating is 1.2μm to 1.6μm, the hole copper thickness of chemical copper plating is 0.8μm to 1.2μm, and the surface copper thickness of electroplated copper is 25μm to 37μm.

[0036] Next, refer to Figure 3 After the inner core board is electroplated with copper, the graphic circuit 3 of the Core layer is fabricated by the subtractive method.

[0037] Specifically, the fabrication of the Core layer patterned circuit 3 is completed using a subtractive method, mainly including the following processes: dry film attachment, pattern exposure, pattern development, etching, and film removal. In this embodiment, the dry film used is LDF515F, the exposure data is specific data, and the parameters for development, etching, and film removal are all specific parameters. Finally, the Core layer patterned circuit 3 is formed after film removal.

[0038] Then refer to Figure 4 Step S2 is executed to perform ultra-coarsening and baking pretreatment on the patterned circuit 3 of the Core layer, and the ABF film is pressed onto the surface of the Core layer by vacuum pressing to form a stacked BU01 layer.

[0039] Specifically, when performing ultra-roughening treatment on the patterned circuit 3 of the Core layer, the ultra-roughening solution used in this embodiment is CZ8101. Specific operating conditions need to be selected according to specific product requirements. After ultra-roughening is completed, the substrate undergoes a baking pretreatment at a temperature of 90~120℃. Next, the ABF film 4 is pressed onto the surface of the Core layer using vacuum lamination to form a stacked BU01 layer. The ABF film includes the GX series, GL series, or GZ series; in this embodiment, the ABF film used is GX-92.

[0040] Then refer to Figure 5 Step S3 is executed to perform laser drilling, desmearing, and ABF surface treatment on the ABF film 4 of the stacked BU01 layer, in order to remove the desmearing material in the blind holes and treat the surface morphology of the ABF.

[0041] Specifically, blind holes 5 are formed by laser drilling of the ABF film 4 with the BU01 layer. The selected laser drilling machine type is CO2 laser drilling, and the hole diameter is 60μm, but it is not limited to this. In some preferred embodiments of this application, the corresponding laser machine type and blind hole diameter can be selected according to specific needs. Subsequently, the blind holes 5 are subjected to desmearing and first surface treatment. The method used in this embodiment is a combination of dry plasma desmearing and wet chemical desmearing, but it is not limited to this. In some preferred embodiments of this application, the corresponding desmearing method can be selected according to specific needs. In this embodiment, the ABF film 6 after surface morphology treatment only undergoes one surface treatment.

[0042] Then refer to Figure 6 In step S4, a metal seed layer is formed on the surface of the ABF film 6 after surface morphology treatment by thin film deposition process, and the pattern circuit of the BU01 layer is fabricated by semi-addition method.

[0043] Specifically, this embodiment forms a metal seed layer on the surface of the ABF film using a thin film deposition process, but is not limited to this. The metal seed layer may include a copper seed layer formed by chemical plating or a metal seed stack formed by sputtering, which can be selected as needed. Subsequently, the patterned circuit 7 of the BU01 layer is fabricated using a semi-additive method, mainly including the following processes: dry film attachment, pattern exposure, pattern development, pattern electroplating, film removal, and etching. The relevant parameters and information of the patterned segments are selected according to their respective needs, and therefore will not be described in detail. The patterned circuit 7 of the BU01 layer is formed when the substrate undergoes film removal, and the bare ABF film 8 is exposed after etching.

[0044] Then refer to Figure 7 and Figure 8In step S5, the surface of the exposed ABF film 8 on the packaging substrate is treated again. Then, the lines on the BU01 layer pattern are roughened and baked pre-treated. The ABF film is pressed onto the lines to form the stacked BU02 layer by vacuum lamination. The patterned lines of the BU02 layer are fabricated by semi-additive method.

[0045] Specifically, a second surface treatment is performed on the packaging substrate. In this embodiment, the surface treatment used is wet chemical desmearing and dry plasma desmearing. This treatment only affects the surface... Figure 6 The exposed ABF film 8 undergoes a process that further increases the surface roughness of the ABF film, thereby ensuring its bonding with the BU02 layer ABF film. Subsequently, steps S2, S3, and S4 are performed again to complete the patterned circuitry 9 of the BU02 layer and the ABF film 10 is exposed again.

[0046] Then refer to Figure 8 and Figure 9 Step S6 is executed to perform ultra-roughening and baking pretreatment on the graphic circuit 9 of the BU02 layer, and to press the solder resist ink onto the inner circuit to form a solder resist layer by vacuum pressing.

[0047] Specifically, referring to step S2, for the ABF film 11 that has undergone further surface treatment and the patterned circuit 12 of the ultra-roughened BU02 layer, solder resist ink is pressed onto the inner circuit to form solder resist layers 13 and 14 by vacuum pressing. The solder resist ink used in this embodiment is a dry film type ink.

[0048] In summary, the method for fabricating the FC-BGA packaging substrate of the present invention divides the surface treatment step of the ABF film into two parts, namely before and after the formation of the patterned circuit. The first ABF film surface treatment involves treating the entire board surface, followed by the fabrication of the BU layer patterned circuit. The second ABF film surface treatment is performed on the exposed ABF film after the circuit layer processing is completed, which increases its surface roughness and improves its surface morphology. This ensures the adhesion between the ABF film and the next ABF film and the solder mask layer, while also ensuring low roughness between the ABF film and the circuit layer.

[0049] It should be noted that, depending on the implementation needs, the various steps described in this application can be broken down into more steps, or two or more steps or parts of the steps can be combined into new steps to achieve the purpose of this invention.

[0050] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a fine-line FCBGA packaging substrate, characterized in that, Includes the following steps: S1. Provide an inner core board, attach photosensitive dry film to the copper surfaces on both sides of the inner core board, and fabricate the pattern circuit of the Core layer by subtractive processing. S2. Preprocess the patterned circuit of the Core layer and press the ABF film onto the surface of the Core layer to form a stacked BU01 layer; S3. Drill holes and perform surface treatment on the ABF film of the stacked BU01 layer to process the surface morphology of the ABF film of the stacked BU01 layer. S4. A metal seed layer is formed on the ABF film of the stacked BU01 layer, and the patterned circuit of the BU01 layer is fabricated by a semi-additive method. S5. Repeat steps S2 to S4, sequentially constructing BU(n+1) layers on top of the already formed BU(n) layers, where n≥1, and the formation of each BU(n+1) layer includes: The pattern circuit of the previous BU(n) layer is preprocessed; the ABF film is pressed onto the surface of the BU(n) layer to form a new stacked BU(n+1) layer; the ABF film of the BU(n+1) layer is drilled and surface-processed; a metal seed layer is formed on the ABF film of the BU(n+1) layer; the pattern circuit of the BU(n+1) layer is fabricated by a semi-additive method. S6. Preprocess the outermost graphic circuit and press the solder resist ink onto its surface to form a solder resist layer.

2. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The thickness of the photosensitive dry film is 15-25μm; the process of fabricating the patterned circuit of the Core layer by subtractive method includes pattern preprocessing, film application, exposure, development, etching and film removal.

3. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The pretreatment includes roughening and baking.

4. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The metal seed layer is formed by a thin film deposition process.

5. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The solder resist ink includes liquid photosensitive solder resist ink or dry film solder resist ink.

6. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The drilling is performed using CO2 laser drilling or UV laser drilling; Methods for treating the surface morphology of the ABF film of the stacked BU01 layer include wet chemical degumming and dry plasma treatment.

7. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The material of the metal seed layer is Ti, Ni, P, Ag, Au or Cu, and its thickness is 30nm-1000nm.

8. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The semi-additive process for fabricating patterned circuits includes seed layer deposition, film lamination, exposure, development, pattern electroplating, film removal, and etching.

9. The method for fabricating a fine-line FCBGA packaging substrate according to claim 1, characterized in that, The surface treatment includes wet chemical desmearing and dry plasma treatment, which selectively act on the exposed ABF film at the line gaps to increase its surface roughness.

10. A fine-line FC-BGA package substrate prepared by the method of preparing a fine-line FCBGA package substrate as described in any one of claims 1 to 9.

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