Power semiconductor device packaging structure and preparation method thereof

Abstract

According to the power semiconductor device packaging structure and the preparation method thereof provided by the invention, the chips are wrapped by the plastic packaging layers, the metal sheets are connected with the front electrodes of the chips, and multi-chip parallel connection is realized through the metal layers and the metal plates; the effects of enlarging the process window range of pressing and laser drilling in the embedding process, reducing the reject ratio and reducing the risk of chip fracturing are achieved, a single-chip small-area electrode metal disc is converted into a large-area metal disc of a metal layer, the influence of the position of the chip on the laser drilling precision is avoided, and in addition, the production efficiency is improved. The metal sheet sintering process can be compatible with various surface metals of the chip, the flexibility is high, a special chip front copper plating process is not needed to adapt to the laser drilling process, and the plastic package layer provides a filling and wrapping effect superior to that of a traditional prepreg.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a power semiconductor device packaging structure and its fabrication method. Background Technology

[0002] With the rapid development of power electronics technology towards higher efficiency, higher power density, higher reliability, and miniaturization, the performance of power semiconductor devices is constantly improving, posing unprecedented challenges to packaging technology. Traditional power module packaging methods, such as wire bonding, suffer from drawbacks such as large parasitic parameters and limited power density and integration, which have gradually become bottlenecks restricting further optimization of system performance. To overcome these problems, embedded packaging on printed circuit boards has been put on the agenda in recent years. Currently, the most promising embedded packaging method for mass production is copper embedding, with Infineon's S-Cell (Standard Cell) being the most well-known. However, this technology has extremely high requirements for the positional accuracy and height difference between the chip and the copper block, resulting in significant yield losses in subsequent printed circuit board lamination and laser drilling processes. The current mainstream process flow for hole-type embedded copper block components is as follows: ① The copper block is milled to create a cavity; silver is selectively plated on the corresponding area of ​​the chip at the bottom of the cavity; the chip is thermally attached to the silver-plated area by silver film transfer; and after pressure and heating sintering, the chip and the copper block are connected together. ② Stack the prepreg on top of the copper block module; ③ Heat and pressurize, the prepreg melts and flows to fill the gaps, then cools and solidifies; ④ Laser drill holes to the front of the chip; ⑤ Electroless copper plating and copper plating fill the holes to connect the chip. For cavity-type copper block components, the height difference between the highest point of the chip and the highest point of the copper block should usually be controlled within ±30µm. If the chip is too high above the copper block, it may break during subsequent lamination; if the chip is too low below the copper block, insufficient resin filling may occur during subsequent lamination, leading to air entry and high-temperature bursting; the positional accuracy of the chip center relative to the center of the copper block should be controlled within ±100µm, otherwise the subsequent laser drilling may deviate, affecting the subsequent copper plating connection. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power semiconductor device packaging structure and its fabrication method, which solves the problems of narrow process window and large yield loss in lamination and laser drilling processes caused by excessively high requirements for the position and height difference between the chip and the copper block in the prior art.

[0004] To achieve the above and other related objectives, the present invention provides a power semiconductor device packaging structure, the packaging structure comprising:

[0005] A metal plate and several power semiconductor device chips connected in parallel. The power semiconductor device chips have opposing front and back sides. Several front electrodes are formed on the front side of the power semiconductor device chips, and back electrodes are formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the metal plate with their front sides facing upwards, and all the back electrodes are electrically connected to the metal plate.

[0006] A plurality of metal sheets are fixedly connected to a preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet;

[0007] A molding compound that encapsulates all the power semiconductor device chips and exposes the metal sheet at a predetermined height;

[0008] A metal layer is located on the molding layer and on all the metal sheets in the preset area, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer.

[0009] Optionally, the power semiconductor device chip includes one or more of silicon chips, gallium nitride chips, and silicon carbide chips.

[0010] Optionally, the metal sheet may include a copper sheet, and the thickness of the metal sheet may be greater than 0.05 mm.

[0011] Optionally, the metal plate may include a copper plate or a ceramic backing plate with metal cladding on both sides.

[0012] Optionally, the glass transition temperature of the material of the molding layer is greater than 200°C.

[0013] Optionally, the metal layer includes a metal seed layer formed on the molding layer and all the metal sheets in the preset region, and interconnecting metal sheets formed on the metal seed layer.

[0014] The present invention also provides a method for fabricating a power semiconductor device packaging structure, the method comprising:

[0015] S11, a metal plate and a plurality of power semiconductor device chips are provided. The power semiconductor device chips have opposite front and back sides. A plurality of front electrodes are formed on the front side of the power semiconductor device chips and a back electrode is formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the metal plate with their front sides facing up, and all the back electrodes are electrically connected to the metal plate.

[0016] S12, providing a plurality of metal sheets, and fixing all the metal sheets to the preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet;

[0017] S13, a molding compound is formed on the metal plate, the molding compound covering all the power semiconductor device chips and exposing the metal sheet at a predetermined height;

[0018] S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

[0019] Optionally, in step S11, all the power semiconductor device chips are fixed to the metal plate with their front faces facing up using silver sintering, copper sintering, or tin-gold eutectic bonding processes.

[0020] Optionally, the side of the metal sheet that is fixedly connected to the front electrode has a sintered layer, and in step S12, a sintering process is used to fix all the metal sheets to the front electrode.

[0021] Optionally, in step S13, the molding layer is formed on the metal plate, the molding layer covering all the power semiconductor device chips and exposing at most half the height of the metal sheet.

[0022] Optionally, in step S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

[0023] A seed layer is formed on the molding layer and on all the metal sheets in the preset area;

[0024] An electroplating process is used to form a thickened electroplating layer on the seed layer. The seed layer and the thickened electroplating layer constitute the metal layer, so that the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

[0025] Optionally, in step S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

[0026] A metal seed layer is formed on the molding layer and on all the metal sheets in the preset area;

[0027] An interconnect metal sheet is provided, and the interconnect metal sheet is fixedly connected to the metal seed layer by a sintering process. The metal seed layer and the interconnect metal sheet constitute the metal layer, so that the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

[0028] Optionally, the metal plates provided in step S11 are multiple, and all the metal plates are interconnected by an array of reinforcing ribs; after step S14, the method further includes cutting to form a structural unit comprising a single metal plate.

[0029] The present invention also provides a method for fabricating a power semiconductor device packaging structure, the method comprising:

[0030] S21, an intermediate carrier board and a plurality of power semiconductor device chips are provided. The power semiconductor device chips have opposite front and back sides. A plurality of front electrodes are formed on the front side of the power semiconductor device chips and a back electrode is formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the intermediate carrier board with their front sides facing up.

[0031] S22, Provide a plurality of metal sheets, and fix all the metal sheets to the preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet;

[0032] S23, a molding compound is formed on the intermediate carrier board, the molding compound covering all the power semiconductor device chips and exposing the metal sheet at a predetermined height;

[0033] S24, remove the intermediate carrier board; form a front metal layer on a predetermined area on the upper surface of the molding compound and on all the metal sheets; form a back metal plate on the lower surface of the molding compound and on the lower surface of all the back electrodes; the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the front metal layer, and the back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the back metal plate, thereby realizing the parallel connection of all the power semiconductor device chips.

[0034] Optionally, the side of the metal sheet that is fixedly connected to the front electrode has a sintered layer, and in step S22, a sintering process is used to fix all the metal sheets to the front electrode.

[0035] Optionally, in step S23, the molding layer is formed on the intermediate carrier, the molding layer covering all the power semiconductor device chips and exposing at most half the height of the metal sheet.

[0036] Optionally, in step S24, the method of forming a front metal layer on a predetermined area on the upper surface of the molding compound and on all the metal sheets includes:

[0037] A front seed layer is formed on the molding layer and on all the metal sheets in the preset area; a front thickened electroplating layer is formed on the front seed layer using an electroplating process. The front seed layer and the front thickened electroplating layer constitute the front metal layer. The front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the front metal layer.

[0038] Alternatively, a front metal seed layer is formed on the molding layer and on all the metal sheets in the preset region; a front metal sheet is provided, and the front metal sheet is fixedly connected to the front metal seed layer by a sintering process, the front metal seed layer and the front metal sheet constitute the metal layer, so that the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer.

[0039] Optionally, in step S24, the method of forming a back metal plate on the lower surface of the molding layer and on the lower surfaces of all the back electrodes includes:

[0040] A back seed layer is formed on the lower surface of the molding layer and the lower surface of all the back electrodes. An electroplating process is used to form a back thickened electroplating layer on the lower surface of the back seed layer. The back seed layer and the back thickened electroplating layer constitute the back metal plate. The back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the back metal plate.

[0041] Alternatively, a back metal seed layer is formed on the lower surface of the molding layer and the lower surfaces of all the back electrodes; a back metal sheet is provided, and the back metal sheet is fixedly connected to the lower surface of the back metal seed layer by a sintering process. The back metal seed layer and the back metal sheet constitute the back metal plate, so that the back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal plate.

[0042] As described above, the power semiconductor device packaging structure and its fabrication method of the present invention have the following beneficial effects:

[0043] ① By encapsulating the power semiconductor device chip with a plastic encapsulation layer, pressure is not directly applied to the chip when the package structure is pressed and embedded into the printed circuit board, reducing the risk of cracking.

[0044] ② By using metal plates or metal layers to connect multiple power semiconductor device chips in parallel, and transforming the small-area electrode metal disk of a single chip into a large-area metal disk of the metal layer, the influence of chip position on laser drilling accuracy is avoided. This solves the problem of narrow process window and large yield loss in lamination and laser drilling processes caused by excessively high requirements for the position and height difference between the chip and the copper block in the existing technology. It achieves the effect of increasing the process window range of lamination and laser drilling in the embedded process, reducing the defect rate, and reducing the risk of chip cracking. At the same time, the large-area metal disk can accommodate more laser holes for copper plating and lead-out, increasing the volume of the copper lead-out wires and increasing the current carrying capacity and heat dissipation capacity.

[0045] ③ The metal sheet sintering process is compatible with various surface metals of the chip, offering high flexibility and eliminating the need for a dedicated front-side copper plating process to adapt to laser drilling.

[0046] ④ The molding layer is generally composed of epoxy resin, filler and catalyst. It is more effective than the prepreg composed of glass fiber cloth and epoxy resin mixture in filling and wrapping power semiconductor device chips.

[0047] ⑤ Increasing the process window for related steps in the embedding process reduces the defect rate, thereby increasing output and reducing manufacturing costs.

[0048] ⑥ Printed circuit board manufacturers have low-level cleanrooms, and the environment cannot meet the requirements. In the existing technology, because the chip is not completely encapsulated, the lamination process needs to be moved into a cleanroom to support chip embedding. The construction of a new cleanroom requires a lot of capital investment and is costly. In the power semiconductor device packaging structure of this invention, the power semiconductor device chip is completely encapsulated by the plastic encapsulation layer, and the requirements for the cleanroom environment are lower. Attached Figure Description

[0049] Figure 1 The diagram shown is a cross-sectional view of the power semiconductor device packaging structure of the present invention.

[0050] Figure 2 The diagram shows a process flow diagram of the fabrication method of the power semiconductor device packaging structure according to Embodiment 2 of the present invention.

[0051] Figures 3 to 7 , Figure 10 and Figure 11 The diagram shows the structural schematics of each step in the fabrication method of the power semiconductor device packaging structure according to Embodiment 2 of the present invention.

[0052] Figure 8 The diagram shows a cross-sectional structure of a power semiconductor device packaging structure fabrication method according to Embodiment 2 of the present invention, in which a seed layer and a thickened electroplating layer constitute a metal layer, so that the front electrodes of all semiconductor chips are electrically connected to each other through the metal layer.

[0053] Figure 9 The diagram shows a cross-sectional structure of a power semiconductor device packaging structure fabrication method according to Embodiment 2 of the present invention, in which a metal seed layer and an interconnecting metal sheet constitute a metal layer, so that the front electrodes of all semiconductor chips are electrically connected to each other through the metal layer.

[0054] Figure 12 The diagram shows a process flow diagram of the fabrication method of the power semiconductor device packaging structure according to Embodiment 3 of the present invention.

[0055] Figures 13 to 20 and Figure 23 The diagram shows the structural schematics of each step in the fabrication method of the power semiconductor device packaging structure according to Embodiment 3 of the present invention.

[0056] Figure 21 The diagram shows a cross-sectional structure of the power semiconductor device packaging structure fabrication method of Embodiment 3 of the present invention, in which the front seed layer and the front thickened electroplating layer constitute the front metal layer to connect the front electrode in parallel, and the back seed layer and the back thickened electroplating layer constitute the back metal plate to connect the back electrode in parallel.

[0057] Figure 22 The diagram shows a cross-sectional structure of the front metal seed layer and the front metal sheet forming a metal layer to connect the front electrode in parallel, and the back metal seed layer and the back metal sheet forming a back metal plate to connect the back electrode in parallel, as shown in the preparation method of the power semiconductor device packaging structure of Embodiment 3 of the present invention.

[0058] Component labeling: 10, 25 Metal plate, 101 Solder layer, 20 Intermediate carrier, 201 Temporary bonding adhesive, 11, 21 Power semiconductor device chip, 110, 210 Front electrode, 111, 211 Source, 112, 212 Gate, 113, 213 Kelvin electrode, 12, 22 Metal sheet, 121, 221 Source metal sheet, 122, 222 Gate metal sheet, 123, 223 Sintered layer, 13, 23 Molding layer, 14, 24 Metal layer, 141, 241 Source metal layer, 142, 242 Gate metal layer, 143 Seed layer, 144 Thickened electroplated layer, 145 Metal seed layer, 146 Interconnect metal sheet, 243 Front seed layer, 244 Front thickened electroplated layer, 245 Front metal seed layer, 246 front metal sheet, 251 back seed layer, 252 back thickened electroplated layer, 253 back metal seed layer, 254 back metal sheet, 15, 26 surface treatment layers, 151, 261 source surface treatment layers, 152, 262 gate surface treatment layers, steps S11~S14, S21~S24. Detailed Implementation

[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] Example 1

[0061] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] This embodiment provides a power semiconductor device packaging structure, referenced... Figure 1 The packaging structure includes:

[0063] A metal plate 10 and several power semiconductor device chips 11 connected in parallel, each power semiconductor device chip 11 having a front and a back side facing each other, as shown in the reference. Figure 3 The power semiconductor device chip 11 has a plurality of front electrodes 110 formed on the front side and a back electrode formed on the back side. All the power semiconductor device chips 11 are fixed on the metal plate 10 with their front sides facing upwards, and all the back electrodes are electrically connected to the metal plate 10.

[0064] A plurality of metal sheets 12 are fixedly connected to a preset front electrode 110, so that the corresponding front electrodes 110 in the same power semiconductor device chip 11 are electrically connected to each other through the same metal sheet 12.

[0065] A molding layer 13 covers all the power semiconductor device chips 11 and exposes the metal sheet 12 at a predetermined height;

[0066] The metal layer 14 is located on the molding layer 13 in the preset area and on all the metal sheets 12. The front electrodes 110 corresponding to all the power semiconductor device chips 11 are electrically connected to each other through the metal layer 14.

[0067] The power semiconductor device packaging structure of this embodiment encapsulates the semiconductor chip with a molding compound, connects the front electrode of the chip with a metal sheet, and enables multiple chips to be connected in parallel through the metal layer and metal plate. This not only avoids direct pressure on the semiconductor chip when the packaging structure is pressed and embedded into the printed circuit board, reducing the risk of cracking, but also solves the problems in the prior art where the requirements for the position and height difference between the chip and the copper block are too high, resulting in a narrow process window and large yield loss in the pressing and laser drilling processes. It achieves the effects of increasing the process window range of pressing and laser drilling in the embedding process, reducing the defect rate, and reducing the risk of chip cracking. Furthermore, by transforming the small-area electrode metal disk of a single chip into a large-area metal disk of the metal layer, the influence of the chip position on the accuracy of laser drilling is avoided. In addition, the metal sheet sintering process is compatible with various surface metals of the chip, which is highly flexible and does not require a special chip front copper plating process to adapt to the laser drilling process. Moreover, the molding compound provides a filling and encapsulation effect that is superior to that of traditional prepregs.

[0068] As an example, the metal plate 10 may be a flat metal plate, including a copper plate or a ceramic backing plate with metal cladding on both sides.

[0069] As a further example, the material of the copper plate includes, but is not limited to, copper or copper alloys, and preferably oxygen-free copper. The shape of the metal plate 10 can be designed according to actual packaging requirements. Preferably, in this embodiment, the shape of the metal plate 10 is rectangular or square to improve utilization. The thickness of the metal plate 10 is generally selected to be greater than 0.2 mm. The material, shape, and thickness of the metal plate 10 are not limited to this embodiment.

[0070] As a further example, the ceramic liner is made of one or more of alumina, silicon nitride, and aluminum nitride. The thickness of the ceramic liner can be 0.25mm, 0.3mm, 0.32mm, 0.38mm, 0.5mm, 0.635mm, 0.76mm, or 1.0mm, and the thickness of the metal layer covering the surface of the ceramic liner can be 0.127mm, 0.2mm, 0.25mm, 0.3mm, 0.4mm, 0.5mm, or 0.8mm. Specifically, a suitable combination of ceramic liner thickness and metal layer thickness can be selected based on design requirements and the processing capabilities of the ceramic liner supplier. Furthermore, designs such as asymmetrical double-sided metal layer thickness or grooved back metal layer can be used to reduce warping caused by subsequent injection molding.

[0071] As an example, the power semiconductor device chip 11 includes one or more of silicon chips, gallium nitride chips, and silicon carbide chips. See also... Figure 3The following embodiments use the silicon carbide chip as an example for illustration. When the power semiconductor device chip 11 is the silicon carbide chip, the front electrode 110 includes a source 111, a gate 112, and a Kelvin electrode 113, and the back electrode is the drain. When the power semiconductor device chip 11 is the gallium nitride chip, the front electrode 110 also includes a drain. When the power semiconductor device chip is an insulated gate bipolar transistor (IGBT) chip, the back electrode is the collector. Furthermore, illustratively, silver or gold can be plated on the back electrode as needed, and nickel-palladium-gold, copper, silver, nickel-gold, or aluminum can be plated on the front electrode 110. It should be noted that all the back electrodes are electrically connected to the metal plate 10 to achieve mutual electrical connection between all the back electrodes; that is, all the back electrodes are electrically connected to each other through the metal plate 10.

[0072] Specifically, the metal sheet 12 can be sintered and connected to all the front electrodes 110, meaning all the front electrodes 110 are ultimately connected in parallel through the metal sheet 12. Alternatively, the metal sheet 12 can be sintered and connected to only some of the front electrodes 110, with the remaining front electrodes 110 without the metal sheet 12 being connected in parallel using another method. The method of implementation can be chosen according to requirements, and no excessive restrictions are imposed here. (Reference) Figure 4 In this embodiment, the metal sheet 12 is sintered and connected to all the source electrodes 111 and all the gate electrodes 112, but not sintered and connected to the Kelvin electrode 113, as an example for illustration. In other embodiments, the metal sheet 12 may be sintered and connected only to all the source electrodes 111 or all the gate electrodes 112.

[0073] Furthermore, the number of power semiconductor device chips 11 can be selected according to actual packaging requirements, such as 1, 2, 4, 6 or 8, etc. It should be noted that the number of power semiconductor device chips 11 to be packaged here is generally more than 2. The above "parallel connection" is based on more than 2 power semiconductor device chips 11. This invention uses 2 as an example for illustration.

[0074] As an example, all the power semiconductor device chips 11 are fixed to the metal plate 10 by a solder layer 101, wherein the material of the solder layer 101 includes, but is not limited to, silver, copper or gold-tin alloy.

[0075] As an example, the metal sheet 12 includes a copper sheet, and the thickness of the metal sheet 12 is, for example, greater than 0.05 mm. This material and its thickness setting can not only improve the conductivity and heat dissipation performance of the packaging structure, but also enhance its mechanical and thermal stability. The material and thickness of the metal sheet 12 can be adjusted according to actual needs, and no excessive restrictions are imposed here.

[0076] As a preferred example, the glass transition temperature of the material of the molding compound 13 is higher than the subsequent printed circuit board bonding temperature, for example, greater than 200°C. The higher glass transition temperature ensures that the molding compound 13 maintains stable physical and chemical properties during the subsequent high-temperature bonding process, preventing softening or deformation due to temperature increases. This effectively avoids potential flow or shrinkage of the molding compound 13 at high temperatures. This not only helps maintain the integrity of the package structure but also ensures a tight fit between the power semiconductor device chip 11 and the molding compound 13, enhancing the mechanical stability and reliability of the package.

[0077] Specifically, as an example, refer to Figure 8 The metal layer 14 includes a seed layer 143 formed on the molding layer 13 in the preset area and on all the metal sheets 12, and a thickened electroplated layer 144 formed on the seed layer 143. The material of the seed layer 143 includes, but is not limited to, copper, and the material of the thickened electroplated layer 144 includes, but is not limited to, copper; or refer to... Figure 9 The metal layer 14 includes a metal seed layer 145 formed on the molding layer 13 and all the metal sheets 12 in the preset region, and interconnecting metal sheets 146 formed on the metal seed layer 145. The material of the metal seed layer 145 includes, but is not limited to, copper, and the material of the interconnecting metal sheets 146 includes, but is not limited to, copper. No excessive limitations are placed here regarding the structure, number of layers, formation method, and material of the metal layer 14.

[0078] Example 2

[0079] Please see Figures 2 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0080] This embodiment provides a method for fabricating a power semiconductor device packaging structure, used to fabricate the power semiconductor device packaging structure of Embodiment 1 above. However, it is not limited to this method; other suitable fabrication methods are also possible. The foregoing content can be quoted in its entirety here, and for the sake of brevity, it will not be repeated below. Figure 2 As shown, the preparation method includes:

[0081] S11, a metal plate and a plurality of power semiconductor device chips are provided. The power semiconductor device chips have opposite front and back sides. A plurality of front electrodes are formed on the front side of the power semiconductor device chips and a back electrode is formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the metal plate with their front sides facing up, and all the back electrodes are electrically connected to the metal plate.

[0082] S12, providing a plurality of metal sheets, and fixing all the metal sheets to the preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet;

[0083] S13, a molding compound is formed on the metal plate, the molding compound covering all the power semiconductor device chips and exposing the metal sheet at a predetermined height;

[0084] S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

[0085] The method for fabricating the power semiconductor device packaging structure in this embodiment solves the problems of narrow process windows and high yield loss in lamination and laser drilling caused by excessively high requirements for the position and height difference between the chip and the copper block in the prior art. It increases the process window range of lamination and laser drilling in the embedded process, reduces the defect rate, and reduces the risk of chip cracking. Furthermore, by transforming the small-area electrode metal disk of a single chip into a large-area metal disk of the metal layer, the influence of the chip position on the laser drilling accuracy is avoided. In addition, the metal sheet sintering process can be compatible with various surface metals of the chip, which is highly flexible and does not require a special chip front copper plating process to adapt to the laser drilling process. Moreover, the plastic encapsulation layer provides a better filling and wrapping effect than traditional prepreg.

[0086] The following is combined with Figures 3 to 11The fabrication method of the power semiconductor device packaging structure in this embodiment will be described in detail. Figure 3 , Figure 4 , Figure 10 and Figure 11 This is a top-down view of the planar structure. Figures 5 to 9 This is a schematic diagram of the cross-sectional structure.

[0087] like Figure 3 As shown, step S11 is performed first, providing a metal plate 10 and a plurality of power semiconductor device chips 11. The power semiconductor device chips 11 have opposing front and back sides. A plurality of front electrodes 110 are formed on the front side of the power semiconductor device chips 11, and a back electrode is formed on the back side of the power semiconductor device chips 11. All the power semiconductor device chips 11 are fixed on the metal plate 10 with their front sides facing up, and all the back electrodes are electrically connected to the metal plate 10.

[0088] As an example, in step S11, all the power semiconductor device chips 11 can be fixed to the metal plate 10 with their front sides facing up using processes including but not limited to silver sintering, copper sintering, or tin-gold eutectic bonding. (Refer to...) Figure 5 At this time, a solder layer 101 is formed between all the power semiconductor device chips 11 and the metal plate 10.

[0089] As an example, when the power semiconductor device chip 11 is a silicon carbide chip, the front electrode 110 includes a source 111, a gate 112 and a Kelvin electrode 113, and the back electrode is a drain.

[0090] like Figure 4 As shown, step S12 is then performed, in which a plurality of metal sheets 12 are provided, and all the metal sheets 12 are fixedly connected to the preset front electrode 110, so that the corresponding front electrodes 110 in the same power semiconductor device chip 11 are electrically connected to each other through the same metal sheet 12.

[0091] Specifically, such as Figure 4 As shown, in the same power semiconductor device chip 11, all the sources 111 are electrically connected to each other through the same source metal sheet 121, and the gates 112 are electrically connected through the same gate metal sheet 122.

[0092] As an example, such as Figure 5As shown, the side of the metal sheet 12 that is fixedly connected to the front electrode 110 has a sintered layer 123. In step S12, a sintering process is used to fix all the metal sheets 12 onto the front electrode 110. As a further example, the material of the sintered layer 123 includes, but is not limited to, silver or copper. That is, silver sintering or copper sintering processes, including but not limited to, can be used to fix all the metal sheets 12 onto the front electrode 110. Inventively, the thickness of the sintered layer 123 is 40 μm to 50 μm.

[0093] As a specific example, in step S12, the method of fixing all the metal sheets 12 to the preset front electrode 110 so that the corresponding front electrodes 110 in the same power semiconductor device chip 11 are electrically connected to each other through the same metal sheet 12 includes:

[0094] S121, a plurality of the metal sheets 12 are provided, and the side of the metal sheet 12 to be fixedly connected to the front electrode 110 has the sintered layer 123.

[0095] S122, the metal sheet 12 is adsorbed by a vacuum nozzle, and the side of the metal sheet 12 with the sintered layer 123 is thermally attached to the corresponding front electrode 110 in the same power semiconductor device chip 11, so that the corresponding front electrodes 110 in the same power semiconductor device chip 11 are electrically connected through the metal sheet 12; this step is repeated until all the metal sheets 12 are thermally attached to the front electrode 110.

[0096] S123, cover the obtained structure with a Teflon film or add graphite sheets and perform a sintering process to fix all the metal sheets 12 to the front electrode 110.

[0097] S124, Remove the Teflon film and the graphite sheet.

[0098] Specifically, such as Figure 4 As shown, the planar dimension of the metal sheet 12 is smaller than the planar dimension of the outer frame of the integral metal disk composed of all the front electrodes 110 on the same power semiconductor device chip 11 connected to it.

[0099] like Figure 6 As shown, step S13 is then performed, in which a molding compound 13 is formed on the metal plate 10, the molding compound 13 covering all the power semiconductor device chips 11 and exposing the metal sheet 12 at a predetermined height.

[0100] As a preferred example, before performing step S13, a pretreatment step is included for the film surface to which the molding compound 13 is to be formed. The pretreatment includes, but is not limited to, plasma treatment, chemical etching roughening, browning, and one or more combinations of adhesion-promoting adhesives to improve its bonding strength with the molding compound 13.

[0101] As a specific example, in step S13, the method of forming a molding compound 13 on the metal plate 10, wherein the molding compound 13 covers all the power semiconductor device chips 11 and exposes the metal sheet 12 at a predetermined height, includes:

[0102] S131, as Figure 5 As shown, a molding compound 13 is formed on the metal plate 10, and the molding compound 13 covers all the power semiconductor device chips 11 and all the metal sheets 12. The thickness of the molding compound 13 is determined according to the device capability, for example, greater than 0.5 mm. The planar dimensions of the molding compound 13 may be equal to, larger than or smaller than the dimensions of the metal plate 10. Preferably, in this embodiment, the dimension of the molding compound 13 extending or recessed into the edge of the metal plate 10 on one side is less than 1 mm.

[0103] S132, as shown Figure 6 As shown, the upper surface of the molding compound 13 is thinned until the metal sheet 12 of a predetermined height is exposed. In illustrative terms, methods for thinning the upper surface of the molding compound 13 include one or more of mechanical polishing, plasma etching, reactive ion etching, chemical mechanical polishing, and laser ablation. Preferably, a low-stress thinning method can be selected, and a stress-relief annealing process can be added, i.e., baking at a lower temperature to release the stress introduced during the thinning process.

[0104] As another example, the metal sheet 12 provided in step S12 is thick enough that the molding layer 13 formed in step S13 can directly expose the metal sheet 12 of a preset height without going through the thinning step, thereby simplifying the process.

[0105] As an example, in step S13, the molding layer 13 is formed on the metal plate 10. The molding layer 13 covers all the power semiconductor device chips 11 and exposes at most half the height of the metal sheet 12. This not only provides sufficient space for subsequent electrical connection processes, but also reduces the damage that the metal sheet 12 may suffer, ensuring the integrity and conductivity of the metal sheet 12.

[0106] like Figure 7 and Figure 10As shown, then step S14 is carried out. A metal layer 14 is formed on the encapsulation layer 13 in the preset area and on all the metal sheets 12. The front electrodes 110 corresponding to all the power semiconductor device chips 11 are electrically connected to each other through the metal layer 14, so as to realize the parallel connection of all the power semiconductor device chips 11.

[0107] Specifically, as Figure 7 shown, the metal layer 14 includes a source metal layer 141 and a gate metal layer 142. The sources 111 of all the power semiconductor device chips 11 are electrically connected to each other through the source metal layer 141, and the gates 112 of all the power semiconductor device chips 11 are electrically connected to each other through the gate metal layer 142.

[0108] The shape of the metal layer 14 will change according to the number of the power semiconductor device chips 11. As Figure 10 shown, there are 2 power semiconductor device chips 11, and the formed metal layer 14 is in the shape of a Chinese character 'hui'. In other embodiments, for example, when there are 4 power semiconductor device chips 11, the metal layer 14 can be in the shape of 'kou + gong' or 'hui'. On the premise of ensuring insulation between different electrodes (such as between the source 111 and the gate 112), the larger the planar size of the metal layer 14 (the source metal layer 141 and the gate metal layer 142) is, the better.

[0109] As a preferred example, before step S14, there is also a step of surface activation treatment for the encapsulation layer 13 in the preset area and all the metal sheets 12. As a further specific example, the methods of surface activation treatment include cleaning, degreasing treatment and roughening treatment, and the method of the roughening treatment includes one or more of acid or alkaline solution etching, plasma treatment and sand blasting.

[0110] As a specific example, as Figure 8 shown, in step S14, the method of forming a metal layer 14 on the encapsulation layer 13 in the preset area and on all the metal sheets 12, and electrically connecting the front electrodes 110 corresponding to all the power semiconductor device chips 11 to each other through the metal layer 14 to realize the parallel connection of all the power semiconductor device chips 11 includes:

[0111] Forming a seed layer 143 on the encapsulation layer 13 in the preset area and on all the metal sheets 12.

[0112] A thickened electroplating layer 144 is formed on the seed layer 143 using an electroplating process. The seed layer 143 and the thickened electroplating layer 144 constitute the metal layer 14, so that the front electrodes 110 corresponding to all the power semiconductor device chips 11 are electrically connected to each other through the metal layer 14, realizing the parallel connection of all the power semiconductor device chips 11. In addition, the surface of the metal plate 10 away from the power semiconductor device chip 11 can be shielded, or a metal plate 10 of appropriate thickness can be selected in step S11. Depending on the thickness of the thickened electroplating layer 144, when the thickened electroplating layer 144 is formed on the seed layer 143 using an electroplating process, a metal layer is also electroplated on the surface of the metal plate 10 away from the power semiconductor device chip 11. The thickness of this electroplated metal layer is required in reverse according to the target thickness requirements such as current carrying capacity and heat dissipation.

[0113] As another specific example, such as Figure 9 As shown, in step S14, a metal layer 14 is formed on the molding layer 13 in the preset area and on all the metal sheets 12. The front electrodes 110 corresponding to all the power semiconductor device chips 11 are electrically connected to each other through the metal layer 14, thereby realizing the parallel connection of all the power semiconductor device chips 11.

[0114] A metal seed layer 145 is formed on the molding layer 13 in the preset area and on all the metal sheets 12.

[0115] An interconnect metal sheet 146 is provided, and the interconnect metal sheet 146 is fixedly connected to the metal seed layer 145 by a sintering process. The metal seed layer 145 and the interconnect metal sheet 146 constitute the metal layer 14, so that the front electrodes 110 corresponding to all the power semiconductor device chips 11 are electrically connected to each other through the metal layer 14, thereby realizing the parallel connection of all the power semiconductor device chips 11.

[0116] As a further specific example, according to the parallel connection requirements of the power semiconductor device chips 11, the interconnect metal sheet 146 with a specific shape and size can be selected, and then the interconnect metal sheet 146 can be fixedly connected to the metal seed layer 145 using a sintering process. In other embodiments, the entire interconnect metal sheet 146 can also be fixedly connected to the metal seed layer 145 using a sintering process, and then the entire interconnect metal sheet 146 can be patterned using methods including but not limited to laser ablation or etching to achieve parallel connection of all the power semiconductor device chips 11. The specific formation method and structure of the metal layer 14 are not limited to this embodiment, and the material of the metal layer 14 is not excessively limited here.

[0117] As an example, after step S14, a surface treatment step is included for the metal layer 14. The surface treatment method includes one or more of the following: immersion nickel-gold, immersion nickel-palladium-gold, immersion gold, immersion silver, nickel plating, tin plating, tin spraying, and passivation, to expand application scenarios. For example, the thickness of immersion gold can be greater than 0.05µm, the thickness of immersion silver can be less than 1µm, and the thickness of nickel or tin plating can be 2µm to 5µm. The surface of the metal plate 10 away from the power semiconductor device chip 11 can also be surface treated simultaneously with the metal layer 14, or it can be shielded and not surface treated. Specifically, for example... Figure 11 As shown, the surface treatment layer 15 formed by the surface treatment includes a source surface treatment layer 151 formed on the source metal layer 141 and a gate surface treatment layer 152 formed on the gate metal layer 142.

[0118] As a preferred example, the metal plates 10 provided in step S11 are multiple, and all the metal plates 10 are interconnected by an array of reinforcing ribs; after step S14, the method further includes a step of cutting to form a structural unit comprising a single metal plate 10, in order to improve packaging efficiency.

[0119] Example 3

[0120] Please see Figures 12 to 23 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0121] This embodiment provides a method for fabricating a power semiconductor device packaging structure, used to fabricate the power semiconductor device packaging structure of Embodiment 1 above. However, it is not limited to this; other suitable fabrication methods are also possible. The difference from Embodiment 2 is that this embodiment uses an intermediate carrier plate instead of a metal plate, and removes the intermediate carrier plate after forming the molding compound. Furthermore, the resulting parallel connection method of the back electrodes of the power semiconductor device chip is also different, such as... Figure 12 As shown, the preparation method includes:

[0122] S21, an intermediate carrier board and a plurality of power semiconductor device chips are provided. The power semiconductor device chips have opposite front and back sides. A plurality of front electrodes are formed on the front side of the power semiconductor device chips and a back electrode is formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the intermediate carrier board with their front sides facing up.

[0123] S22, Provide a plurality of metal sheets, and fix all the metal sheets to the preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet;

[0124] S23, a molding compound is formed on the metal plate, the molding compound covering all the power semiconductor device chips and exposing the metal sheet at a predetermined height;

[0125] S24, remove the intermediate carrier board; form a front metal layer on a predetermined area on the upper surface of the molding compound and on all the metal sheets; form a back metal plate on the lower surface of the molding compound and on the lower surface of all the back electrodes; the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the front metal layer, and the back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the back metal plate, thereby realizing the parallel connection of all the power semiconductor device chips.

[0126] The method for fabricating the power semiconductor device packaging structure in this embodiment involves fixing the chip face up on an intermediate carrier, connecting the front electrode of the chip with a metal sheet, forming a molding compound to protect the chip and expose the metal sheet at a predetermined height, removing the intermediate carrier, and forming a metal layer or metal plate on the upper and lower surfaces of the molding compound, the metal sheet, and the lower surface of the back electrode in a predetermined area to achieve parallel connection of multiple chips. This solves the problems in the prior art where the requirements for the position and height difference between the chip and the copper block are too high, resulting in a narrow process window and large yield loss in the lamination and laser drilling processes. It achieves the effects of increasing the process window range of lamination and laser drilling in the embedded process, reducing the defect rate, and reducing the risk of chip cracking. Furthermore, by transforming the small-area front electrode metal disk of a single chip into a large-area metal disk of the metal layer, the influence of the chip position on the accuracy of laser drilling is avoided. In addition, the metal sheet sintering process can be compatible with various surface metals of the chip, which is highly flexible and does not require a special chip front copper plating process to adapt to the laser drilling process. Moreover, the molding compound provides a filling and wrapping effect that is superior to that of traditional prepreg.

[0127] The following is combined with Figures 13 to 23 The fabrication method of the power semiconductor device packaging structure in this embodiment will be described in detail. Figure 13 , Figure 15 , Figure 19 and Figure 23 This is a top-down view of the planar structure. Figure 14 , Figures 16 to 18 , Figures 20 to 22 This is a schematic diagram of the cross-sectional structure.

[0128] like Figure 13 and Figure 14As shown, step S21 is performed first, providing an intermediate carrier board 20 and a plurality of power semiconductor device chips 21. The power semiconductor device chips 21 have opposite front and back sides. A plurality of front electrodes 210 are formed on the front side of the power semiconductor device chips 21, and a back electrode is formed on the back side of the power semiconductor device chips 21. All the power semiconductor device chips 21 are fixed on the intermediate carrier board 20 with their front sides facing up.

[0129] As an example, when the power semiconductor device chip 21 is a silicon carbide chip, the front electrode 210 includes a source 211, a gate 212 and a Kelvin electrode 213, and the back electrode is a drain electrode.

[0130] As an example, the material of the intermediate carrier plate 20 includes, but is not limited to, inorganic non-metals, metals, or polymers.

[0131] As an example, such as Figure 14 As shown, all the power semiconductor device chips 21 can be fixed to the intermediate carrier 20, for example, by temporary bonding adhesive 201. The release type of the temporary bonding adhesive 201 includes, but is not limited to, one or more of thermoplastic, UV-release, thermosetting, and laser-release types. The temporary bonding adhesive 201 is removed when the intermediate carrier 20 is removed in the subsequent step S24.

[0132] like Figure 15 As shown, step S22 is then performed, in which a plurality of metal sheets 22 are provided, and all the metal sheets 22 are fixedly connected to the preset front electrode 210, so that the corresponding front electrodes 210 in the same power semiconductor device chip 21 are electrically connected to each other through the same metal sheet 22.

[0133] Specifically, such as Figure 15 As shown, in the same power semiconductor device chip 11, all the sources 211 are electrically connected to each other through the same source metal sheet 221, and the gates 212 are electrically connected through the same gate metal sheet 222.

[0134] As an example, such as Figure 16 As shown, the side of the metal sheet 22 that is fixedly connected to the front electrode 210 has a sintered layer 223. In step S22, a sintering process is used to fix all the metal sheets 22 onto the front electrode 210. As a further example, the material of the sintered layer 223 includes, but is not limited to, silver or copper. That is, processes including, but not limited to, silver sintering or copper sintering can be used to fix all the metal sheets 22 onto the front electrode 210. Inventively, the thickness of the sintered layer 223 is 40 μm to 50 μm.

[0135] As a specific example, in step S22, the method of fixing all the metal sheets 22 to the preset front electrode 210 so that the corresponding front electrodes 210 in the same power semiconductor device chip 21 are electrically connected to each other through the same metal sheet 22 includes:

[0136] S221, a plurality of the metal sheets 22 are provided, the side of the metal sheet 22 to be fixedly connected to the front electrode 210 has the sintered layer 223.

[0137] S222, the metal sheet 22 is adsorbed by a vacuum nozzle, and the side of the metal sheet 22 with the sintered layer 223 is thermally attached to the corresponding front electrode 210 in the same power semiconductor device chip 21, so that the corresponding front electrodes 210 in the same power semiconductor device chip 21 are electrically connected through the metal sheet 22; this step is repeated until all the metal sheets 22 are thermally attached to the front electrode 210.

[0138] S223, cover the obtained structure with a Teflon film or add graphite sheets and perform a sintering process to fix all the metal sheets 22 to the front electrode 210.

[0139] S224, Remove the Teflon film and the graphite sheet.

[0140] Specifically, such as Figure 15 As shown, the planar dimension of the metal sheet 22 is smaller than the planar dimension of the outer frame of the integral metal disk composed of all the front electrodes 210 on the same power semiconductor device chip 21 connected to it.

[0141] like Figure 17 As shown, step S23 is then performed, in which a molding compound 23 is formed on the intermediate carrier 20. The molding compound 23 covers all the power semiconductor device chips 21 and exposes the metal sheet 22 at a predetermined height.

[0142] As a specific example, in step S23, the method of forming a molding compound 23 on the intermediate carrier 20, wherein the molding compound 23 covers all the power semiconductor device chips 21 and exposes the metal sheet 22 at a predetermined height, includes:

[0143] S231, such as Figure 16 As shown, the molding compound 23 is formed on the intermediate carrier 20, and the molding compound 23 covers all the power semiconductor device chips 21 and all the metal sheets 22.

[0144] S232, such as Figure 17As shown, the upper surface of the molding compound 23 is thinned until the metal sheet 22 of a predetermined height is exposed. In illustrative terms, methods for thinning the upper surface of the molding compound 23 include one or more of mechanical polishing, plasma etching, reactive ion etching, chemical mechanical polishing, and laser ablation. Preferably, a low-stress thinning method can be selected, and a stress-relief annealing process can be added, i.e., baking at a lower temperature to release the stress introduced during the thinning process.

[0145] As another example, the metal sheet 22 provided in step S22 is thick enough that the molding layer 23 formed in step S23 can directly expose the metal sheet 22 of a preset height without going through a thinning step.

[0146] As an example, in step S23, the molding layer 23 is formed on the intermediate carrier 20. The molding layer 23 covers all the power semiconductor device chips 21 and exposes at most half the height of the metal sheet 22. This not only provides sufficient space for subsequent electrical connection processes, but also reduces the potential damage to the metal sheet 22, ensuring the integrity and conductivity of the leads.

[0147] Next, proceed to step S24, refer to... Figure 18 Remove the intermediate carrier plate 20; refer to Figure 19 and Figure 20 A front metal layer 24 is formed on a predetermined area on the upper surface of the molding layer 23 and on all the metal sheets 22; a back metal plate 25 is formed on the lower surface of the molding layer 23 and on the lower surface of all the back electrodes; the front electrodes 210 corresponding to all the power semiconductor device chips 21 are electrically connected to each other through the front metal layer 24, and the back electrodes corresponding to all the power semiconductor device chips 21 are electrically connected to each other through the back metal plate 25, thereby realizing the parallel connection of all the power semiconductor device chips 21.

[0148] As a specific example, the process for removing the intermediate carrier plate 20 can be selected according to the type of the temporary bonding adhesive 201. If the temporary bonding adhesive 201 is a thermoplastic adhesive, it is reheated to allow the adhesive to flow and separate before cleaning. If the temporary bonding adhesive 201 is a UV-emitting adhesive, it loses its tackiness and separates after being irradiated with UV light. If the temporary bonding adhesive 201 is a thermoplastic or laser-emitting type, the intermediate carrier plate 20 is mechanically separated from the temporary bonding adhesive 201, and then the temporary bonding adhesive 201 is removed using a laser.

[0149] Specifically, such as Figure 19As shown, the metal layer 24 includes a source metal layer 241 and a gate metal layer 242. All the sources 211 are electrically connected to each other through the source metal layer 241, and all the gates 212 are electrically connected to each other through the gate metal layer 242.

[0150] As a preferred example, before step S24, a step of surface activation treatment is performed on the preset area on the upper surface of the molding layer 23, the upper surfaces of all the metal sheets 22, the lower surface of the molding layer 23, and the lower surfaces of all the back electrodes.

[0151] As a specific example, step S24, the method of forming a front metal layer 24 on a predetermined area on the upper surface of the molding layer 23 and on all the metal sheets 22, includes:

[0152] like Figure 21 As shown, a front seed layer 243 is formed on the molding layer 23 and all the metal sheets 22 in the preset area; a front thickened electroplating layer 244 is formed on the front seed layer 243 by electroplating process. The front seed layer 243 and the front thickened electroplating layer 244 constitute the front metal layer 24. The front electrodes 210 corresponding to all the power semiconductor device chips 21 are electrically connected to each other through the front metal layer 24.

[0153] Or, such as Figure 22 As shown, a front metal seed layer 245 is formed on the molding layer 23 and all the metal sheets 22 in the preset area; a front metal sheet 246 is provided, and the side of the front metal sheet 246 to be fixedly connected to the front metal seed layer 245 is formed with, for example, a silver sintered layer or a copper sintered layer. The front metal sheet 246 is fixedly connected to the front metal seed layer 245 by a sintering process. The front metal seed layer 245 and the front metal sheet 246 constitute the metal layer 24, so that the front electrodes 210 corresponding to all the power semiconductor device chips 21 are electrically connected to each other through the metal layer 24.

[0154] As a further example, the front metal sheet 246 with a specific shape and size can be selected according to the parallel connection requirements of the power semiconductor device chip 21, and then the front metal sheet 246 can be fixedly connected to the front metal seed layer 245 by a sintering process. In other embodiments, the entire front metal sheet 246 can also be fixedly connected to the front metal seed layer 245 by a sintering process, and then the entire front metal sheet 246 can be patterned by methods including but not limited to laser ablation or etching to achieve the parallel connection of all the power semiconductor device chips 21.

[0155] As a specific example, step S24, the method of forming a back metal plate 25 on the lower surface of the molding layer 23 and the lower surfaces of all the back electrodes, includes:

[0156] like Figure 21 As shown, a back seed layer 251 is formed on the lower surface of the molding layer 23 and the lower surface of all the back electrodes. A back thickened electroplating layer 252 is formed on the lower surface of the back seed layer 251 by electroplating. The back seed layer 251 and the back thickened electroplating layer 252 constitute the back metal plate 25. The back electrodes corresponding to all the power semiconductor device chips 21 are electrically connected to each other through the back metal plate 25.

[0157] Or, such as Figure 22 As shown, a back metal seed layer 253 is formed on the lower surface of the molding layer 23 and the lower surfaces of all the back electrodes; a back metal sheet 254 is provided, the side of the back metal sheet 254 to be fixedly connected to the back metal seed layer 253 is formed with, for example, a silver sintered layer or a copper sintered layer, and the back metal sheet 254 is fixedly connected to the lower surface of the back metal seed layer 253 by a sintering process. The back metal seed layer 253 and the back metal sheet 254 constitute the back metal plate 25, so that the back electrodes corresponding to all the power semiconductor device chips 21 are electrically connected to each other through the metal plate 25.

[0158] Specifically, the method for forming the metal layer 24 on the front side and the metal plate 25 on the back side can be selected according to actual needs, for example, such as... Figure 21 As shown, the front seed layer 243 can be formed on the molding compound 23 and all the metal sheets 22 in the preset area; the front thickened electroplating layer 244 is formed on the front seed layer 243 using an electroplating process, and the back seed layer 251 is formed on the lower surface of the molding compound 23 and the lower surface of all the back electrodes, and the back thickened electroplating layer 252 is formed on the back seed layer 251 using an electroplating process. Figure 22 As shown, alternatively, the front metal seed layer 245 can be formed on the molding layer 23 and all the metal sheets 22 in the preset area, and then the front metal sheet 246 can be fixedly connected to the front metal seed layer 245 using a sintering process. A back metal seed layer 253 can be formed on the lower surface of the molding layer 23 and the lower surface of all the back electrodes, and the back metal sheet 254 can be fixedly connected to the back metal seed layer 253 using a sintering process. The methods for forming the metal layer 24 and the metal plate 25 can be freely chosen and combined, and are not limited to this embodiment.

[0159] Furthermore, regarding step S24, the order of steps such as removing the intermediate carrier plate 20, forming the front metal layer 24 on the predetermined area of ​​the upper surface of the molding compound 23 and on all the metal sheets 22, and forming the back metal plate 25 on the lower surface of the molding compound 23 and on the lower surface of all the back electrodes can be adjusted according to actual needs. For example, the front metal layer 24 can be formed first on the predetermined area of ​​the upper surface of the molding compound 23 and on all the metal sheets 22, then the intermediate carrier plate 20 can be removed, and finally the front metal layer 24 can be formed on the lower surface of the molding compound 23 and on the lower surface of all the back electrodes. Alternatively, the intermediate carrier plate 20 can be removed first, and then the back metal plate 25 can be formed on the lower surface of the molding layer 23 and the lower surfaces of all the back electrodes. Finally, the front metal layer 24 can be formed on a predetermined area on the upper surface of the molding layer 23 and on all the metal sheets 22. Alternatively, the intermediate carrier plate 20 can be removed first, and then the front metal layer 24 can be formed on a predetermined area on the upper surface of the molding layer 23 and on all the metal sheets 22, and the back metal plate 25 can be formed on the lower surface of the molding layer 23 and the lower surfaces of all the back electrodes.

[0160] As an example, after step S24, a surface treatment step is further included on the front metal layer 24 and the back metal plate 25. The surface treatment method includes one or more of the following: immersion nickel-gold, immersion nickel-palladium-gold, immersion silver, nickel plating, tin plating, tin spraying, and passivation. Specifically, such as... Figure 23 As shown, the surface treatment layer 26 formed on the front side of the structure includes a source surface treatment layer 261 formed on the source metal layer 241 and a gate surface treatment layer 262 formed on the gate metal layer 242.

[0161] In summary, the power semiconductor device packaging structure and its fabrication method of the present invention, by encapsulating the semiconductor chip with a molding compound and connecting the front electrode of the chip with a metal sheet, and achieving parallel connection of multiple chips through the metal layer and metal plate, not only avoids direct pressure on the semiconductor chip during the lamination and embedding of the packaging structure into the printed circuit board, reducing the risk of cracking, but also solves the problems of narrow process windows and large yield losses in lamination and laser drilling processes caused by excessively high requirements for the position and height difference between the chip and the copper block in the prior art. This achieves the effects of increasing the process window range of lamination and laser drilling in the embedding process, reducing the defect rate, and reducing the risk of chip cracking. Furthermore, by transforming the small-area electrode metal disk of a single chip into a large-area metal disk of the metal layer, the influence of chip position on laser drilling accuracy is avoided. In addition, the metal sheet sintering process is compatible with various surface metals of the chip, offering high flexibility and eliminating the need for a special chip front copper plating process to adapt to laser drilling. Moreover, the molding compound provides a better filling and encapsulation effect than traditional prepregs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0162] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power semiconductor device packaging structure, characterized in that, The packaging structure includes: A metal plate and several power semiconductor device chips connected in parallel. The power semiconductor device chips have opposing front and back sides. Several front electrodes are formed on the front side of the power semiconductor device chips, and back electrodes are formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the metal plate with their front sides facing upwards, and all the back electrodes are electrically connected to the metal plate. A plurality of metal sheets are fixedly connected to a preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet; A molding compound that encapsulates all the power semiconductor device chips and exposes the metal sheet at a predetermined height; A metal layer is located on the molding layer and on all the metal sheets in the preset area, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer.

2. The power semiconductor device packaging structure according to claim 1, characterized in that: The power semiconductor device chip includes one or more of silicon chips, gallium nitride chips, and silicon carbide chips.

3. The power semiconductor device packaging structure according to claim 1, characterized in that: The metal sheet includes a copper sheet, and the thickness of the metal sheet is greater than 0.05 mm.

4. The power semiconductor device packaging structure according to claim 1, characterized in that: The metal plate includes a copper plate or a ceramic backing plate with metal cladding on both sides.

5. The power semiconductor device packaging structure according to claim 1, characterized in that: The glass transition temperature of the material of the molding layer is greater than 200°C.

6. The power semiconductor device packaging structure according to claim 1, characterized in that: The metal layer includes a metal seed layer formed on the molding layer and on all the metal sheets in the preset region, and interconnecting metal sheets formed on the metal seed layer.

7. A method for fabricating a power semiconductor device packaging structure, characterized in that, The preparation method includes: S11, a metal plate and a plurality of power semiconductor device chips are provided. The power semiconductor device chips have opposite front and back sides. A plurality of front electrodes are formed on the front side of the power semiconductor device chips and a back electrode is formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the metal plate with their front sides facing up, and all the back electrodes are electrically connected to the metal plate. S12, providing a plurality of metal sheets, and fixing all the metal sheets to the preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet; S13, a molding compound is formed on the metal plate, the molding compound covering all the power semiconductor device chips and exposing the metal sheet at a predetermined height; S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets, and the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

8. The method for fabricating a power semiconductor device packaging structure according to claim 7, characterized in that: In step S11, all the power semiconductor device chips are fixed to the metal plate with their front faces facing up using silver sintering, copper sintering, or tin-gold eutectic bonding processes.

9. The method for fabricating a power semiconductor device packaging structure according to claim 7, characterized in that: The side of the metal sheet that is fixedly connected to the front electrode has a sintered layer. In step S12, a sintering process is used to fix all the metal sheets to the front electrode.

10. The method for fabricating a power semiconductor device packaging structure according to claim 7, characterized in that: In step S13, the molding layer is formed on the metal plate, the molding layer covering all the power semiconductor device chips and exposing at most half the height of the metal sheet.

11. The method for fabricating a power semiconductor device packaging structure according to claim 7, characterized in that, In step S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets. The front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips. The method includes: A seed layer is formed on the molding layer and on all the metal sheets in the preset area; An electroplating process is used to form a thickened electroplating layer on the seed layer. The seed layer and the thickened electroplating layer constitute the metal layer, so that the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

12. The method for fabricating a power semiconductor device packaging structure according to claim 7, characterized in that, In step S14, a metal layer is formed on the molding layer in the preset area and on all the metal sheets. The front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips. The method includes: A metal seed layer is formed on the molding layer and on all the metal sheets in the preset area; An interconnect metal sheet is provided, and the interconnect metal sheet is fixedly connected to the metal seed layer by a sintering process. The metal seed layer and the interconnect metal sheet constitute the metal layer, so that the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer, thereby realizing the parallel connection of all the power semiconductor device chips.

13. The method for fabricating a power semiconductor device packaging structure according to claim 7, characterized in that: The metal plates provided in step S11 are multiple, and all the metal plates are interconnected by an array of reinforcing ribs; after step S14, the step of cutting to form a structural unit including a single metal plate is further included.

14. A method for fabricating a power semiconductor device packaging structure, characterized in that, The preparation method includes: S21, an intermediate carrier board and a plurality of power semiconductor device chips are provided. The power semiconductor device chips have opposite front and back sides. A plurality of front electrodes are formed on the front side of the power semiconductor device chips and a back electrode is formed on the back side of the power semiconductor device chips. All the power semiconductor device chips are fixed on the intermediate carrier board with their front sides facing up. S22, Provide a plurality of metal sheets, and fix all the metal sheets to the preset front electrode, so that the corresponding front electrodes in the same power semiconductor device chip are electrically connected to each other through the same metal sheet; S23, a molding compound is formed on the intermediate carrier board, the molding compound covering all the power semiconductor device chips and exposing the metal sheet at a predetermined height; S24, remove the intermediate carrier board; form a front metal layer on a predetermined area on the upper surface of the molding compound and on all the metal sheets; form a back metal plate on the lower surface of the molding compound and on the lower surface of all the back electrodes; the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the front metal layer, and the back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the back metal plate, thereby realizing the parallel connection of all the power semiconductor device chips.

15. The method for fabricating a power semiconductor device packaging structure according to claim 14, characterized in that: The side of the metal sheet that is fixedly connected to the front electrode has a sintered layer. In step S22, a sintering process is used to fix all the metal sheets to the front electrode.

16. The method for fabricating a power semiconductor device packaging structure according to claim 14, characterized in that: In step S23, the molding compound is formed on the intermediate carrier, the molding compound covering all the power semiconductor device chips and exposing at most half the height of the metal sheet.

17. The method for fabricating a power semiconductor device packaging structure according to claim 14, characterized in that, In step S24, the method of forming a front metal layer on a predetermined area on the upper surface of the molding compound and on all the metal sheets includes: A front seed layer is formed on the molding layer and on all the metal sheets in the preset area; a front thickened electroplating layer is formed on the front seed layer using an electroplating process. The front seed layer and the front thickened electroplating layer constitute the front metal layer. The front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the front metal layer. Alternatively, a front metal seed layer is formed on the molding layer and on all the metal sheets in the preset region; a front metal sheet is provided, and the front metal sheet is fixedly connected to the front metal seed layer by a sintering process, the front metal seed layer and the front metal sheet constitute the metal layer, so that the front electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal layer.

18. The method for fabricating a power semiconductor device packaging structure according to claim 14, characterized in that, In step S24, the method of forming a back metal plate on the lower surface of the molding layer and on the lower surfaces of all the back electrodes includes: A back seed layer is formed on the lower surface of the molding layer and the lower surface of all the back electrodes. An electroplating process is used to form a back thickened electroplating layer on the lower surface of the back seed layer. The back seed layer and the back thickened electroplating layer constitute the back metal plate. The back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the back metal plate. Alternatively, a back metal seed layer is formed on the lower surface of the molding layer and the lower surfaces of all the back electrodes; a back metal sheet is provided, and the back metal sheet is fixedly connected to the lower surface of the back metal seed layer by a sintering process. The back metal seed layer and the back metal sheet constitute the back metal plate, so that the back electrodes corresponding to all the power semiconductor device chips are electrically connected to each other through the metal plate.

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