Deposition mask, method of manufacturing deposition mask, and electronic device

Abstract

The invention relates to a deposition mask, a method of manufacturing the deposition mask, and an electronic device. The deposition mask includes: a mask frame having cell openings; an intermediate inorganic film disposed on the mask frame; and a diaphragm disposed on the intermediate inorganic film and having a plurality of pixel openings communicating with the cell openings. The intermediate inorganic film is formed of a material including germanium.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0136444 filed on October 8, 2024, and all benefits therefrom, the contents of which are incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The disclosure relates to a deposition mask, a method of manufacturing a deposition mask, and an electronic device manufactured by using the deposition mask. BACKGROUND

[0004] A wearable device that forms a focal point at a distance close to a user's eyes in the form of glasses or a helmet has been developed. For example, the wearable device can be a head-mounted display (HMD) or augmented reality (AR) glasses. The wearable device can provide a user with an augmented reality (herein, referred to as "AR") screen or a virtual reality (referred to as "VR") screen.

[0005] In the case of a wearable device such as the HMD or the AR glasses, a display specification of approximately 3000 PPI (pixels per inch) or more is implemented to allow a user to use the wearable device for a long time without a symptom of dizziness. For this purpose, a silicon on organic light emitting diode (OLEDoS) technology used in a small-sized organic light emitting display device of high resolution is on the rise. The OLEDoS is a technology in which an organic light emitting diode (OLED) is disposed on a semiconductor substrate on which a complementary metal oxide semiconductor (CMOS) element is disposed.

[0006] In some cases, in order to manufacture a display panel having a high resolution of about 3000 PPI or more, a high resolution deposition mask is implemented. For example, the deposition mask can be manufactured by forming a membrane having a plurality of pixel openings on a substrate such as a silicon wafer and partially etching the substrate to form a cell opening that exposes the pixel openings. For example, a silicon nitride film can be used as the membrane, and the cell opening can be formed by a wet etching process using a tetramethylammonium hydroxide (TMAH) solution. However, when the TMAH solution is used, the etching rate will be very low, and the membrane can be damaged by hydrogen (H2) bubbles generated by a reaction between the silicon substrate and the TMAH solution. SUMMARY

[0007] Aspects and features of embodiments of the disclosure provide a deposition mask capable of shortening a manufacturing time and preventing damage to a membrane, a method of manufacturing a deposition mask, and an electronic device manufactured by using the deposition mask.

[0008] However, embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0009] According to an aspect of the present disclosure, a deposition mask can include a mask frame having a cell opening, an intermediate inorganic film disposed on the mask frame, and a separation membrane disposed on the intermediate inorganic film and having a plurality of pixel openings that communicate with the cell opening. The intermediate inorganic film can be formed of a material including germanium.

[0010] According to some embodiments of the present disclosure, the intermediate inorganic film can be formed of at least one selected from the group consisting of amorphous germanium, single-crystal germanium, polycrystal germanium, and silicon germanium.

[0011] According to some embodiments of the present disclosure, the mask frame can be formed of single-crystal silicon, and the intermediate inorganic film can be formed of boron-doped germanium or boron-doped silicon germanium.

[0012] According to some embodiments of the present disclosure, the intermediate inorganic film can have a thickness in the range of 50 nm to 1 µm.

[0013] According to some embodiments of the present disclosure, the separation membrane can be formed of silicon nitride and have a thickness in the range of about 0.5 µm to about 3 µm.

[0014] According to some embodiments of the present disclosure, the deposition mask can further include a buffer inorganic film disposed between the mask frame and the intermediate inorganic film.

[0015] According to some embodiments of the present disclosure, the buffer inorganic film can be formed of silicon oxide and have a thickness in the range of about 0.5 µm to about 2 µm.

[0016] According to another aspect of the present disclosure, a method of manufacturing a deposition mask can include forming an intermediate inorganic film on a mask substrate, forming a separation membrane having a plurality of pixel openings on the intermediate inorganic film, patterning the mask substrate, wherein the patterning the mask substrate forms a cell opening that partially exposes the intermediate inorganic film, and removing a portion of the intermediate inorganic film exposed by the cell opening such that the cell opening communicates with the pixel openings. The intermediate inorganic film can be formed of a material including germanium.

[0017] According to some embodiments of the present disclosure, the intermediate inorganic film can be formed of at least one selected from the group consisting of amorphous germanium, single-crystal germanium, polycrystal germanium, and silicon germanium.

[0018] According to some embodiments of the present disclosure, the mask substrate can be formed of single-crystal silicon, and the intermediate inorganic film can be formed of boron-doped germanium or boron-doped silicon germanium.

[0019] According to some embodiments of the disclosure, the intermediate inorganic film can be formed to have a thickness in a range of about 50 nm to about 1 µm.

[0020] According to some embodiments of the disclosure, the separation film can be formed of silicon nitride and formed to have a thickness in a range of about 0.5 µm to about 3 µm.

[0021] According to some embodiments of the disclosure, the patterned mask base can include forming the unit openings by performing a wet etching process using an etchant including potassium hydroxide (KOH).

[0022] According to some embodiments of the disclosure, the wet etching process can be performed at a temperature in a range of about 40 °C to about 100 °C.

[0023] According to some embodiments of the disclosure, removing the portion of the intermediate inorganic film exposed by the unit openings can include performing a wet etching process using an etchant including hydrogen fluoride (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH), and water (H2O).

[0024] According to some embodiments of the disclosure, removing the portion of the intermediate inorganic film exposed by the unit openings can include performing a wet etching process using an etchant including ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O).

[0025] According to some embodiments of the disclosure, the method can further include forming a buffer inorganic film on the mask base. The intermediate inorganic film can be formed on the buffer inorganic film.

[0026] According to some embodiments of the disclosure, the buffer inorganic film can be formed of silicon oxide and formed to have a thickness in a range of about 0.5 µm to about 2 µm.

[0027] According to some embodiments of the disclosure, the method can further include partially removing the buffer inorganic film such that the intermediate inorganic film is partially exposed by the unit openings.

[0028] According to some embodiments of the disclosure, the method can further include forming a back inorganic film on a back surface of the mask base that exposes a back portion of the mask base. The patterned mask base can include forming the unit openings by performing a wet etching process using the back inorganic film as an etching mask.

[0029] According to yet another aspect of the disclosure, an electronic device can include a display panel. The display panel can include a substrate; and a light emitting layer formed on the substrate using a deposition mask. The deposition mask can include a mask frame having a cell opening; an intermediate inorganic film disposed on the mask frame; and a separator disposed on the intermediate inorganic film and having a plurality of pixel openings that communicate with the cell opening. The intermediate inorganic film can be formed of a material including germanium.

[0030] According to embodiments of the disclosure, the intermediate inorganic film can act as an etch stop film in a wet etching process for forming the cell opening. In particular, the etchant including potassium hydroxide (KOH) can be prevented from being provided to the mask substrate through the pixel openings by the intermediate inorganic film, such that damage to the separator can be prevented during the wet etching process. In some aspects, the amount of time associated with forming the cell opening can be greatly reduced when using an etchant containing potassium hydroxide (KOH).

[0031] Other features and embodiments can be apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] Example embodiments of the disclosure are described in detail below with reference to the attached drawing figures, which are incorporated by reference in their entirety. The foregoing and other aspects and features of the disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a block diagram of an electronic device according to embodiments of the disclosure;

[0034] Figure 2 is a schematic diagram of an electronic device according to various embodiments of the disclosure;

[0035] Figure 3 is an exploded perspective view showing a display device according to embodiments of the disclosure;

[0036] Figure 4 is a block diagram of a display device shown in Figure 3

[0037] Figure 5 is an equivalent circuit diagram showing an example of a first sub-pixel shown in Figure 4

[0038] Figure 6 is a schematic plan view showing an example of a display panel shown in Figure 3

[0039] Figure 7 is a schematic enlarged plan view showing an example of a display area shown in Figure 6

[0040] Figure 8 is a block diagram of a display device shown in Figure 6 ​​​​schematic enlarged plan view of another example of a display area shown in

[0041] Figure 9 is a schematic cross-sectional view taken along the line I1 -I1'shown in Figure 7

[0042] Figure 10 is a schematic cross-sectional view taken along the line I1 -I1'shown in Figure 7

[0043] Figure 11 is a schematic perspective view showing an example of a head-mounted display;

[0044] Figure 12 is a schematic perspective view showing Figure 11

[0045] Figure 13 is a schematic perspective view showing another example of a head-mounted display;

[0046] Figure 14 is a schematic view showing a deposition mask and a deposition apparatus comprising the deposition mask according to an embodiment of the present disclosure;

[0047] Figure 15 is a schematic bottom view showing Figure 14

[0048] Figure 16 is a schematic plan view showing Figure 14

[0049] Figure 17 is a schematic enlarged plan view of a mask cell region shown in Figure 16

[0050] Figure 18 is a schematic cross-sectional view taken along the line I2-I2' shown in Figure 17

[0051] is a cross-sectional view showing a deposition mask according to another embodiment of the present disclosure; Figure 19

[0052] is a schematic cross-sectional view showing a method of manufacturing a deposition mask according to yet another embodiment of the present disclosure; and Figures 20 to 25

[0053] is a schematic cross-sectional view showing a method of manufacturing a deposition mask according to yet another embodiment of the present disclosure. Figures 26 to 33 DETAILED DESCRIPTION ​​​​​​​

[0054] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments of the disclosure are shown. The aspects supported by the present disclosure may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the present disclosure to those skilled in the art.

[0055] It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers can also be present. Throughout the specification, like reference numerals refer to like elements.

[0056] It will be understood that, although the terms "first" and "second" etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present application. Similarly, a second element could be termed a first element.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "a," "an," and "the" are intended to include both singular and plural forms, unless the context clearly indicates otherwise. For example, "an element" or "the element" means one or more elements. "At least one" should be construed as "one or more," unless the context clearly indicates otherwise. "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0058] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's relationship to another element as the device is oriented in the drawing. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower" can then encompass both an orientation of lower and upper, according to the particular orientation being referred to in the figures. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The terms "below" or "beneath" can then encompass both an orientation of above and below, according to the particular orientation being referred to in the figures.

[0059] The features of each of the various embodiments of the present disclosure can be partially or entirely combined with each other, and can be technically interacted with each other, and each of the various embodiments can be implemented independently of each other or can be implemented together in association with each other.

[0060] "About" or "approximately," as used herein, includes the recited value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0061] The term "substantially," as used herein, means roughly or approximately. The term "substantially equal" means roughly equal or approximately equal. The term "substantially the same" means roughly the same or approximately the same. The term "substantially perpendicular" means roughly perpendicular or approximately perpendicular. The term "substantially parallel" means roughly parallel or approximately parallel.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0063] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments as examples. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can often have rough and / or nonlinear features. Moreover, sharp angles as illustrated can be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0064] Embodiments will be described in detail below with reference to the attached drawings.

[0065] The display device according to embodiments of the present disclosure can be applied to various electronic devices. The electronic device according to embodiments of the present disclosure includes the display device described herein and can include a module or a device having an additional function in addition to the display device.

[0066] Figure 1 is a block diagram of an electronic device according to embodiments of the present disclosure.

[0067] Referring to Figure 1 The electronic device 10 according to embodiments of the present disclosure can include a display module 11, a processor 12, a memory 13, and a power module 14.

[0068] The processor 12 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0069] The memory 13 can store data information supporting the operation of the processor 12 or the display module 11. In an example in which the processor 12 executes an application program stored in the memory 13, an image data signal and / or an input control signal are transmitted to the display module 11, and the display module 11 can process the received signal and output image information through a display screen.

[0070] The power module 14 can include a power supply module such as a power adapter or a battery, and a power conversion module that converts power supplied by the power supply module to generate power for the operation of the electronic device 10.

[0071] At least one of the components of the electronic device 10 according to embodiments of the present disclosure can be included in the display device 20 (see Figure 3) in FIG. 1. In some aspects, some of the various modules functionally included in one module can be included in the display device 20, and other modules can be provided separately from the display device 10. For example, the display device 20 can include the display module 11, and the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices within the electronic device 10 other than the display device 20.

[0072] Figure 2 is a schematic view of an electronic device according to various embodiments of the disclosure.

[0073] Referring to Figure 2 , the display device 20 (see Figure 3 ) to which the display device 20 according to the embodiments of the disclosure is applied can not only include image display electronic devices such as the smart phone 10_1a, the tablet PC (personal computer) 10_1b, the laptop computer 10_1c, the television (TV) 10_1d, and the desktop monitor 10_1e, but also include wearable electronic devices including a display module such as the smart glasses 10_2a, the head-mounted display 10_2b, and the smart watch 10_2c, and vehicle electronic devices including a display module such as a CID (central information display) and an in-vehicle rear mirror display arranged on an instrument panel, a center console, and an instrument cluster of a car 10_3.

[0074] Figure 3 is an exploded perspective view illustrating a display device according to an embodiment of the disclosure. Figure 4 is a block diagram illustrating a display device shown in Figure 3 .

[0075] Referring to Figure 3 and Figure 4 , the display device 20 according to an embodiment can be a device that displays a moving image or a still image. The display device 20 according to an embodiment can be used as the electronic device 10 or the display module 11 of the electronic device 10. For example, the display device 20 according to an embodiment can be applied to a portable electronic device 10 such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, and an ultra-mobile PC (UMPC). The display device 20 according to an embodiment can be applied as a display module 11 of an electronic device 10 such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) terminal. The display device 20 according to an embodiment can be applied to an electronic device 10 such as a smart watch, a watch phone, and a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0076] The display device 20 according to an embodiment can include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0077] The display panel 100 can have a planar shape similar to a quadrangular shape. For example, the display panel 100 can have a planar shape similar to a quadrangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, an angle at which the short side in the first direction DR1 and the long side in the second direction DR2 meet can be a right angle or be rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to the quadrangular shape, and can be a planar shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The planar shape of the display device 20 can coincide with the planar shape of the display panel 100, but embodiments of the disclosure are not limited thereto.

[0078] The display panel 100 can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, a plurality of data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. As shown in FIG. 1A, the display panel 100 can include a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed. Figure 4

[0079] The plurality of pixels PX can be disposed in the display area DAA. The plurality of pixels PX can be arranged in a matrix form along the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 while being arranged in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 while being arranged in the first direction DR1.

[0080] The plurality of scan lines SL can include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL includes a plurality of first emission control lines ECL1 and a plurality of second emission control lines ECL2.

[0081] The plurality of pixels PX can include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in FIG. 1B, and the plurality of pixel transistors can be formed by a semiconductor process and disposed in a semiconductor substrate SSUB (see FIG. 1C). Figure 5 Figure 9 For example, the plurality of pixel transistors of the sub-pixels SP1, SP2, and SP3 can be formed of a complementary metal-oxide semiconductor (CMOS), but embodiments of the disclosure are not limited thereto.

[0082] ​​Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to one write scan line GWL, one control scan line GCL, one bias scan line GBL, one first emission control line ECL1, one second emission control line ECL2, and one data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0083] The scan driver 610, the emission driver 620, and the data driver 700 can be disposed in the non-display area NDA.

[0084] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed in a semiconductor substrate SSUB (see FIG. 1) by a semiconductor process. Figure 9 ) For example, the plurality of scan transistors and the plurality of light emitting transistors can be formed by CMOS, but embodiments of the disclosure are not limited thereto.

[0085] The scan driver 610 can include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 can generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 can generate a control scan signal in response to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 can generate a bias scan signal according to the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line GBL.

[0086] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate a first emission control signal according to the emission timing control signal ECS and sequentially output the first emission control signal to the first emission control line ECL1. The second emission control driver 622 can generate a second emission control signal according to the emission timing control signal ECS and sequentially output the second emission control signal to the second emission control line ECL2.

[0087] The data driver 700 can include a plurality of data transistors, and the plurality of data transistors can be formed in a semiconductor substrate S SUB (see Figure 9 ) by a semiconductor process. For example, the plurality of data transistors can be formed of CMOS, but embodiments of the present disclosure are not limited thereto.

[0088] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the analog data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0089] The heat dissipation layer 200 can overlap the display panel 100 in a third direction DR3 that is a thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 serves to dissipate heat generated from the display panel 100. The heat dissipation layer 200 can include graphite having a high thermal conductivity or a metal such as silver (Ag), copper (Cu), or aluminum (Al), for example.

[0090] The circuit board 300 can be electrically connected to the plurality of first pads PD1 (see Figure 6 ) of the first pad portion PDA1 (see Figure 6 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film, for example. The circuit board 300 can be a flexible printed circuit board or a flexible film having a flexible material. Although the circuit board 300 is shown as being unfolded in Figure 3 , the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the plurality of first pads PD1 (see Figure 6 ) of the first pad portion PDA1 (see Figure 6 ) of the display panel 100 by using a conductive adhesive member. The one end of the circuit board 300 can be an opposite end of the other end of the circuit board 300.

[0091] The timing control circuit 400 can receive digital video data DATA and a timing signal input from the outside. The timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0092] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later in connection with FIG. 4. Figure 5 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0093] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Also, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0094] Alternatively, each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100 similarly to the scan driver 610, the emission driver 620, and the data driver 700. In this case, the timing control circuit 400 can include a plurality of timing transistors, and each of the power supply circuits 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed in a semiconductor substrate SSUB (see FIG. 4) through a semiconductor process. For example, the plurality of timing transistors and the plurality of power transistors can be formed of CMOS, but embodiments of the disclosure are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed between the data driver 700 and the first pad portion PDA1 (see FIG. 4). Figure 9 ) between the data driver 700 and the first pad portion PDA1 (see Figure 6

[0095] ​Figure 5 is a circuit diagram showing an example of the first sub-pixel shown in Figure 4

[0096] Referring to Figure 5 , the first sub-pixel SP1 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. In addition, the first sub-pixel SP1 can be connected to a first drive voltage line VSL to which a first drive voltage VSS (see Figure 4 ) corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD (see Figure 4 ) corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT (see Figure 4 ) corresponding to an initialization voltage is applied.

[0097] The first sub-pixel SP1 can include a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0098] The light emitting element LE emits light in response to a drive current flowing through a channel of the first transistor T1. An emission amount of the light emitting element LE can be proportional to the drive current. A first electrode of the light emitting element LE can be an anode electrode, and a second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including the first electrode, the second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but embodiments of the present disclosure are not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including the first electrode, the second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0099] The first transistor T1 can be a drive transistor that controls a source-drain current (also referred to as a "drive current") flowing between a source electrode and a drain electrode of the first transistor T1 according to a voltage applied to a gate electrode of the first transistor T1.

[0100] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1.

[0101] ​The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal that controls the scan line GCL to connect the first node N1 to the second node N2. To this end, the first transistor T1 can operate like a diode when the gate electrode and the source electrode of the first transistor T1 are connected.

[0102] The fourth transistor T4 can be connected between the second node N2 and a third node N3. The fourth transistor T4 is turned on by a first emission control signal of the first emission control line ECL1 to connect the second node N2 to the third node N3. Accordingly, the driving current of the first transistor T1 can be supplied to the light emitting element LE. The fifth transistor T5 can be disposed between the third node N3 and a third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal that biases the scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, a third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE.

[0103] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and a second driving voltage line VDL. The sixth transistor T6 is turned on by a second emission control signal of the second emission control line ECL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, a second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1.

[0104] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL.

[0105] Each of the first to sixth transistors T1 to T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 can be a P-type MOSFET, but embodiments of the present disclosure are not limited thereto. Each of the first to sixth transistors T1 to T6 can be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0106] Although the first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors CP1 and CP2 in Figure 5 , it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the equivalent circuit diagram shown in Figure 5 . For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to those shown in the equivalent circuit diagram.Figure 5 the number of transistors and the number of capacitors.

[0107] Further, an equivalent circuit diagram of the second sub-pixel SP2 (see Figure 4 ) and an equivalent circuit diagram of the third sub-pixel SP3 (see Figure 4 ) can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in connection with Figure 5 . Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 is not repeated in the present disclosure.

[0108] Figure 6 is a schematic plan view showing an example of the display panel shown in Figure 3

[0109] Referring to Figure 6 , the display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to the embodiment includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0110] The scan driver 610 can be disposed at a first side of the display area DAA, and the emission driver 620 can be disposed at a second side of the display area DAA. For example, the scan driver 610 can be disposed at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be disposed at the other side of the display area DAA in the first direction DR1. However, embodiments of the present disclosure are not limited thereto, and both the scan driver 610 and the emission driver 620 can be disposed at the first side or the second side of the display area DAA.

[0111] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 (see Figure 3 ) by a conductive adhesive member. The first pad portion PDA1 can be disposed at a third side of the display area DAA. For example, the first pad portion PDA1 can be disposed at one side of the display area DAA in the second direction DR2. The first pad portion PDA1 can be disposed outside the data driver 700 in the second direction DR2.

[0112] ​The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board formed of a rigid material or a flexible printed circuit board formed of a flexible material.

[0113] The second pad portion PDA2 can be located on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be located on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be located outside the second distribution circuit 720 on the second direction DR2.

[0114] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL (see...). Figure 4 For example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2.

[0115] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2.

[0116] The cathode connection portion CCA can be the display element layer EML (see...). Figure 9 The second electrode CAT (see) Figure 9 The area connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection portion CCA can be located outside at least one side of the display area DAA. For example, the cathode connection portion CCA can be located outside at least one of the left, right, upper, and lower sides of the display area DAA. Alternatively, the cathode connection portion CCA can be configured as follows: Figure 6The ground shown surrounds the display area DAA in order to minimize the deviation of the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA.

[0117] Figure 7 It is shown Figure 6 A schematic enlarged plan view of an example of the display area shown in the diagram. Figure 8 It is shown Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0118] refer to Figure 7 and Figure 8 Multiple pixel PX (see Figure 6 Each of the sub-pixels includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0119] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can be arranged as follows in the plan view: Figure 7 and Figure 8 The quadrilateral or hexagonal shape shown is not the only embodiment of this disclosure. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have other polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than quadrilaterals or hexagons in the plan view.

[0120] like Figure 7 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In some aspects, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0121] Alternatively, such as Figure 8As shown in FIG. 1, the emission areas EA1, EA2, EA3, and EA4 can have a hexagonal shape in a plan view. In this case, the first emission area EA1 and the third emission area EA3 can be adjacent in a first direction DR1, and the second emission area EA2 and the fourth emission area EA4 can be adjacent in a second direction DR2. In some aspects, the first emission area EA1 and the second emission area EA2 can be adjacent in a first diagonal direction DD1, and the second emission area EA2 and the third emission area EA3 can be adjacent in a second diagonal direction DD2. In some aspects, the first emission area EA1 and the fourth emission area EA4 can be adjacent in the second diagonal direction DD2, and the third emission area EA3 and the fourth emission area EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be a direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined by 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0122] The first sub-pixel SP1 can emit first light, the second sub-pixel SP2 can emit second light, and the third sub-pixel SP3 can emit third light. Here, the first light can be light of a blue wavelength band, the second light can be light of a green wavelength band, and the third light can be light of a red wavelength band. For example, the blue wavelength band can be a wavelength band of light whose main peak wavelength is in a range of approximately 370 nm to approximately 460 nm, the green wavelength band can be a wavelength band of light whose main peak wavelength is in a range of approximately 480 nm to 560 nm, and the red wavelength band can be a wavelength band of light whose main peak wavelength is in a range of approximately 600 nm to 750 nm.

[0123] Each of the plurality of pixels PX can include three emission areas EA1, EA2, and EA3 as shown in FIG. 1, or can include four emission areas EA1, EA2, EA3, and EA4 as shown in FIG. 2. In this case, the fourth emission area EA4 can emit the same second light as the second emission area EA2, but embodiments of the disclosure are not limited thereto. Figure 8 Figure 9 In this case, the fourth emission area EA4 can emit the same second light as the second emission area EA2, but embodiments of the disclosure are not limited thereto.

[0124] The emission areas of the plurality of pixels PX can be arranged in a bar structure in which the emission areas are arranged in the first direction DR1, a diamond structure in which the emission areas EA1, EA2, EA3, and EA4 are arranged as shown in FIG. 1, or a hexagonal structure in which the emission areas are arranged in a hexagonal shape. Figure 7 In this case, the fourth emission area EA4 can emit the same second light as the second emission area EA2, but embodiments of the disclosure are not limited thereto.

[0125] Figure 9 is a plan view showing the emission areas EA1, EA2, EA3, and EA4 arranged in a bar structure in which the emission areas are arranged in the first direction DR1. Figure 5 ​​A schematic cross-sectional view of an example of a display panel taken along the line 11-11' indicated in FIG. 1.

[0126] Reference Figure 5 The display panel 100 includes a semiconductor backplane SBP, an emission element backplane EBP, a display element layer EML, a sealing layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0127] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films SINS1, SINS2, and SINS3 covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the pixel transistors PTR described with reference to FIGS. 1 to 3. Figure 5 The first transistor T1 to the sixth transistor T6 described.

[0128] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first-type impurity. A plurality of well regions WA can be provided on / in a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second-type impurity. The second-type impurity can be different from the first-type impurity. In an example in which the first-type impurity is a P-type impurity, the second-type impurity can be an N-type impurity. Alternatively, when the first-type impurity is an N-type impurity, the second-type impurity can be a P-type impurity.

[0129] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH provided between the source region SA and the drain region DA.

[0130] A bottom insulating film BINS can be provided between the gate electrode GE and the well region WA. A side insulating film SINS can be provided on a side surface of the gate electrode GE. The side insulating film SINS can be provided on the bottom insulating film BINS.

[0131] Each of the source region SA and the drain region DA can be a region doped with the first-type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3 that is a thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be provided on one side of the gate electrode GE, and the drain region DA can be provided on the other side of the gate electrode GE.

[0132] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 provided between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 provided between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. Due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased, thereby increasing the length of the channel region CH of each of the plurality of pixel transistors PTR.

[0133] A first semiconductor insulating film SINS1 can be provided on the semiconductor substrate SSUB. A second semiconductor insulating film SINS2 can be provided on the first semiconductor insulating film SINS1.

[0134] A plurality of contact terminals CTE can be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the plurality of pixel transistors PTR through a hole that penetrates the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0135] A third semiconductor insulating film SINS3 can be provided on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE can be exposed and not covered by the third semiconductor insulating film SINS3.

[0136] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be formed of a silicon carbon nitride (SiCN) or a silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto.

[0137] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as a polyimide substrate, for example. In this case, a thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that is not bendable, and the polymer resin substrate can be a flexible substrate that is bendable or curvable.

[0138] The light emitting element base plate EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of interlayer insulating films INS1 to INS9.

[0139] The first to ninth interlayer insulating films INS1 to INS9 serve to insulate the first to eighth conductive layers ML1 to ML8. The first to eighth conductive layers ML1 to ML8 serve to connect a plurality of contact terminals CTE exposed from the semiconductor base plate SBP, thereby realizing Figure 5 the circuit of the first sub-pixel SP1 illustrated in FIG. 1.

[0140] For example, Figure 9 The first to sixth transistors T1 to T6 are formed in the semiconductor base plate SBP, and the connection of the first to sixth transistors T1 to T6 with Figure 9 the first and second capacitors CP1 and CP2 in FIG. 1 is realized by the first to eighth conductive layers ML1 to ML8. In some aspects, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light emitting element LE is also realized by the first to eighth conductive layers ML1 to ML8.

[0141] The first to eighth conductive layers ML1 to ML8 and the first to eighth interlayer insulating films INS1 to INS8 can be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first to eighth vias VA1 to VA8 can be formed of substantially the same material. The first to eighth interlayer insulating films INS1 to INS8 can be formed of a silicon oxide (SiO x ) type inorganic layer, but embodiments of the present disclosure are not limited thereto.

[0142] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 can be formed of a silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto.

[0143] Each of the plurality of ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0144] The display element layer EML can be provided on the light emitting element base plate EBP. The display element layer EML can include a tenth interlayer insulating film INS10 and an eleventh interlayer insulating film INS11, a reflective electrode RL, a first electrode AND, a light emitting stack IL, a second electrode CAT, a pixel definition film PDL, and a plurality of trenches TRC.

[0145] The reflective electrode RL can be provided on the ninth interlayer insulating film INS9. Each of the plurality of reflective electrodes RL can include at least one of a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4. For example, as shown in FIG. 1A, each of the plurality of reflective electrodes RL can include the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4. Figure 9

[0146] The first reflective electrode RL1 can be provided on the ninth interlayer insulating film INS9 and can be connected to the ninth via VA9. Each of the plurality of second reflective electrodes RL2 can be provided on the first reflective electrode RL1 corresponding thereto. Each of the plurality of third reflective electrodes RL3 can be provided on the second reflective electrode RL2 corresponding thereto. Each of the plurality of fourth reflective electrodes RL4 can be provided on the third reflective electrode RL3 corresponding thereto.

[0147] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0148] The first reflective electrode RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a nitride or an alloy including any one of them. For example, the first reflective electrode RL1 can include titanium nitride (TiN), the second reflective electrode RL2 can include aluminum (Al), the third reflective electrode RL3 can include titanium nitride (TiN), and the fourth reflective electrode RL4 can include titanium (Ti).

[0149] ​The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to flatten the stepped portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0150] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0151] The eleventh interlayer insulating film INS11 can be an optical auxiliary layer for adjusting the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0152] For example, such as Figure 9 As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. In some aspects, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0153] Each of the plurality of tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and be connected to the exposed fourth reflective electrode RL4. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0154] The first electrode AND of each of the plurality of light emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a nitride or an alloy including any one of them. For example, the first electrode AND of each of the plurality of light emitting elements LE can be titanium nitride (TiN).

[0155] The pixel definition film PDL can be disposed on a portion of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL can cover edges of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL can separate the first, second, and third emission areas EA1, EA2, and EA3. Each of the first, second, and third emission areas EA1, EA2, and EA3 can be an area in which the light emitting element LE including the first electrode AND, the light emitting stack IL, and the second electrode CAT is disposed.

[0156] The first emission area EA1 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0157] The pixel definition film PDL can include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 can be disposed on an edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel definition film PDL2 can be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 can be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can be formed of a silicon oxide (SiO x ) type inorganic film. Alternatively, the first pixel definition film PDL1 and the third pixel definition film PDL3 can be formed of a silicon nitride (SiN x ) type inorganic film, and the second pixel definition film PDL2 can be formed of a silicon oxide (SiO x ) type inorganic film. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can each have a thickness of about .

[0158] In order to reduce or prevent the possibility that the first encapsulation inorganic film TFE1 is cut off due to step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure having a step portion. Step coverage (step coverage) refers to the ratio of the degree (thickness) of a thin film coated on an inclined portion to the degree (thickness) of a thin film coated on a flat portion. The lower the step coverage, the more likely the thin film will be cut off at the inclined portion.

[0159] Each of the plurality of trenches TRC can penetrate the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3. The eleventh interlayer insulating film INS11 can be partially recessed at each of the plurality of trenches TRC.

[0160] At least one trench TRC can be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 10 two trenches TRC are shown as being disposed between adjacent sub-pixels SP1, SP2, and SP3, embodiments of the disclosure are not limited thereto.

[0161] The light emitting stack IL can include a plurality of stack layers IL1, IL2, and IL3. Figure 9 A three-series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 is shown as the light emitting stack IL, but embodiments of the disclosure are not limited thereto. For example, as shown in Figure 2 , the light emitting stack IL can have a two-series structure including two stack layers.

[0162] In the triple series structure, the light emitting stack IL can have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different light. For example, the light emitting stack IL can include a first stack layer IL1 that emits first light, a second stack layer IL2 that emits second light, and a third stack layer IL3 that emits third light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be sequentially stacked.

[0163] The first stack layer IL1 can have a structure in which a first hole transport layer, a first light emitting layer that emits first light, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second light emitting layer that emits second light, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third light emitting layer that emits third light, and a third electron transport layer are sequentially stacked.

[0164] A first charge generation layer for supplying holes to the second stack layer IL2 and supplying electrons to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer that supplies electrons to the first stack layer IL1 and a P-type charge generation layer that supplies holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metal material.

[0165] A second charge generation layer for supplying holes to the third stack layer IL3 and supplying electrons to the second stack layer IL2 can be disposed between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer that supplies electrons to the second stack layer IL2 and a P-type charge generation layer that supplies holes to the third stack layer IL3.

[0166] The first stack layer IL1 can be disposed on the first electrode AND and the pixel definition film PDL, and a residual film RIL disposed on a bottom surface of each trench TRC can include the same material as the first stack layer IL1. The first stack layer IL1 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trench TRC. The second stack layer IL2 can be disposed on the first stack layer IL1. The second stack layer IL2 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trench TRC. A cavity ESS or an empty space can be disposed between the residual film RIL and the second stack layer IL2 in the trench TRC. The third stack layer IL3 can be disposed on the second stack layer IL2. The third stack layer IL3 is not cut by the trench TRC and can be disposed such that the third stack layer IL3 covers the second stack layer IL2 in each of the plurality of trenches TRC.

[0167] In the triple series structure, each of the plurality of trench TRC can be a structure for cutting off the first to third hole transport layers, the first and second charge generation layers of the first to third stacked layers IL1, IL2 and IL3 of the display element layer EML between the adjacent sub-pixels SP1, SP2 and SP3. In some aspects, in the double series structure, each of the plurality of trench TRC can be a structure for cutting off the charge generation layer and the lower stacked layer disposed between the lower stacked layer and the upper stacked layer.

[0168] In order to stably cut off the first and second stacked layers IL1 and IL2 of the display element layer EML between the adjacent sub-pixels SP1, SP2 and SP3, the height of each of the plurality of trench TRC can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRC refers to the length of each of the plurality of trench TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In order to cut off the charge generation layer and the hole transport layer of the light emitting stack IL of the display element layer EML between the adjacent sub-pixels SP1, SP2 and SP3, there can be different structures instead of the trench TRC. For example, instead of the trench TRC, a reverse tapered partition wall can be provided on the pixel defining film PDL.

[0169] In some aspects, Figure 10 The light emitting stack IL emitting light is shown to be disposed in the first, second and third emission areas EA1, EA2 and EA3, but embodiments of the present disclosure are not limited thereto. For example, instead of the light emitting stack IL, a first light emitting layer can be disposed in the first emission area EA1, and the first light emitting layer can be omitted from the second and third emission areas EA2 and EA3. Further, a second light emitting layer can be disposed in the second emission area EA2, and the second light emitting layer can be omitted from the first and third emission areas EA1 and EA3. Further, a third light emitting layer can be disposed in the third emission area EA3, and the third light emitting layer can be omitted from the first and second emission areas EA1 and EA2. In this case, the first, second and third color filters CF1, CF2 and CF3 of the optical layer OPL can be omitted.

[0170] The second electrode CAT can be disposed on the light emitting stack IL. That is, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be formed of a transparent conductive oxide (TCO) capable of transmitting light, such as ITO or IZO, for example, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag, for example. In an example in which the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency in each of the first, second, and third sub-pixels SP1, SP2, and SP3 can be improved due to a microcavity effect.

[0171] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one encapsulation inorganic film TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be formed of a plurality of layers in which one or more inorganic films of a silicon nitride (SiN x ) layer, a silicon oxynitride (SiON) layer, a silicon oxide (SiO x ) layer, a titanium oxide (TiO x ) layer, and an aluminum oxide (AlO x ) layer are alternately stacked.

[0172] In some aspects, the encapsulation layer TFE can include at least one encapsulation organic film TFE2 to protect the display element layer EML from foreign substances such as dust, for example. The encapsulation organic film TFE2 can be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 can be a monomer. Alternatively, the encapsulation organic film TFE2 can be an organic film such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin, for example.

[0173] The adhesive layer ADL can be a layer for joining the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive member. In some aspects, the adhesive layer ADL can be a transparent adhesive member including a transparent adhesive such as a transparent adhesive or a transparent adhesive resin, for example.

[0174] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a fill layer FIL. The plurality of color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed on the adhesive layer ADL.

[0175] The first color filter CF1 can overlap the first emission area EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, i.e., light of a blue band. The blue band can be about 370 nm to about 460 nm. Accordingly, the first color filter CF1 can transmit light of the first color among light emitted from the first emission area EA1.

[0176] The second color filter CF2 can overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, i.e., light of a green band. The green band can be about 480 nm to about 560 nm. Accordingly, the second color filter CF2 can transmit light of the second color among light emitted from the second emission area EA2.

[0177] The third color filter CF3 can overlap the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color, i.e., light of a red band. The red band can be about 600 nm to about 750 nm. Accordingly, the third color filter CF3 can transmit light of the third color among light emitted from the third emission area EA3.

[0178] The plurality of lenses LNS can be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS can be a structure for increasing a proportion of light directed to the front of the display device 20 (see FIG. 1). Figure 7 ) of the display device 20. Each of the plurality of lenses LNS can have a cross-sectional shape that is convex in the upward direction.

[0179] The filling layer FIL can be disposed on the plurality of lenses LNS. The filling layer FIL can have a predetermined refractive index so that light travels in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. In addition, the filling layer FIL can be a planarization layer. The filling layer FIL can be an organic film including, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0180] The cover layer CVL can be disposed on the filling layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. In an example in which the cover layer CVL is a glass substrate, the cover layer CVL can be attached to the filling layer FIL. In this case, the filling layer FIL can serve to bond the cover layer CVL. In an example in which the cover layer CVL is a glass substrate, the cover layer CVL can serve as an encapsulation substrate. In an example in which the cover layer CVL is a polymer resin, the cover layer CVL can be directly applied to the filling layer FIL.

[0181] The polarizer POL can be disposed on one surface of the CVL cover layer. The polarizer can be a structure used to reduce or prevent visibility reduction caused by reflection of external light. The polarizer can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. However, the polarizer can be omitted when the visibility reduction caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0182] Figure 10 It shows along Figure 9 The diagram shows a schematic cross-sectional view of another example of a display panel, taken by line I1-I1'.

[0183] Figure 10 Implementation examples and Figure 9 The difference in the embodiment is that the first electrode AND of each of the plurality of light-emitting elements LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation examples and Figure 9 The embodiment also differs in that the trench TRC is omitted, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have an eaves-shaped or mushroom-shaped cross-sectional structure. Figure 10 In the embodiments, the references to Figure 7 Redundant descriptions of components already described in the embodiments.

[0184] refer to Figure 7 Multiple connecting electrodes ANC can be respectively disposed on multiple first portions AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be disposed on its corresponding first portion AA1 of the ninth interlayer insulating film INS9. The multiple connecting electrodes ANC can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys, nitrides, or transparent conductive oxides thereof. For example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0185] The plurality of reflective electrodes RL can be respectively disposed on the plurality of connection electrodes ANC. Each of the plurality of reflective electrodes RL can be disposed on the connection electrode ANC corresponding thereto. The plurality of reflective electrodes RL can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, each of the plurality of reflective electrodes RL can include aluminum (Al) having high reflectivity.

[0186] The plurality of optical auxiliary films OAL can be respectively disposed on the plurality of reflective electrodes RL. Each of the plurality of optical auxiliary films OAL can be disposed on the reflective electrode RL corresponding thereto. The plurality of optical auxiliary films OAL can be formed of a silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto.

[0187] In each of the first emission area EA1 and the third emission area EA3, a step layer STPL can be disposed on the reflective electrode RL, and the optical auxiliary film OAL can be disposed on the step layer STPL. In the second emission area EA2, the optical auxiliary film OAL can be disposed on the reflective electrode RL (and without the step layer STPL). In the first emission area EA1, the second emission area EA2, and the third emission area EA3, the thickness of the optical auxiliary film OAL can be substantially the same.

[0188] Due to the step layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first emission area EA1 and the third emission area EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission area EA2. The thickness of the step layer STPL and the thickness of the optical auxiliary film OAL can be set in consideration of the wavelength and resonance distance of light emitted from the first stack layer IL1 of the light emitting stack IL and the wavelength and resonance distance of light emitted from the second stack layer IL2 of the light emitting stack IL.

[0189] Each of the plurality of light emitting elements LE can include the first electrode AND, the light emitting stack IL, and the second electrode CAT.

[0190] The first electrode AND of each of the plurality of light emitting elements LE can be disposed on the optical auxiliary film OAL corresponding thereto. Since the connection electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are sequentially stacked, the first electrode AND of each of the plurality of light emitting elements LE can be disposed on the top surface and the side surface of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connection electrode ANC. Accordingly, the first electrode AND of each of the plurality of light emitting elements LE can be in contact with and electrically connected to the side surface of the reflective electrode RL and the side surface of the connection electrode ANC. Accordingly, compared to when the first electrode AND of each of the plurality of light emitting elements LE is connected to the exposed reflective electrode RL through a via hole that penetrates the optical auxiliary film OAL, the number of mask processes can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0191] The first electrode AND of each of the plurality of light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the connection electrode ANC, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE.

[0192] The ninth interlayer insulating film INS9 can include a first portion AA1 overlapping the connection electrode ANC in the third direction DR3 and a second portion AA2 not overlapping the connection electrode ANC in the third direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 can be substantially the same.

[0193] Alternatively, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 can be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this case, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 can be exposed, and the first electrode AND of each of the plurality of light emitting elements LE can be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0194] The first electrode AND of each of the plurality of light emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy, a nitride, or a transparent conductive oxide including any one of them. For example, the first electrode AND of each of the plurality of light emitting elements LE can include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the present disclosure is not limited thereto.

[0195] The pixel definition film PDL can be provided on a part of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL can cover edges of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL can separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0196] The pixel definition film PDL can include a first pixel definition film PDL1, a second pixel definition film PDL2, a third pixel definition film PDL3, and a fourth pixel definition film PDL4.

[0197] The first pixel definition film PDL1 can be provided on the first electrode AND of each of the plurality of light emitting elements LE. Specifically, the first pixel definition film PDL1 can cover a part of a top surface of the first electrode AND provided on the optical auxiliary film OAL. Further, the first pixel definition film PDL1 can cover the first electrode AND provided on side surfaces of the connection electrode ANC, side surfaces of the reflective electrode RL, and side surfaces of the optical auxiliary film OAL. The first pixel definition film PDL1 can be provided on a top surface of the second part AA2 of the ninth interlayer insulating film INS9.

[0198] The planarization film PNS is a film for planarizing a stepped portion caused by the connection electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0199] The planarization film PNS can be provided on the first pixel definition film PDL1 covering the first electrode AND provided on side surfaces of the connection electrode ANC, side surfaces of the reflective electrode RL, and side surfaces of the optical auxiliary film OAL. The planarization film PNS can be provided on the first pixel definition film PDL1 provided on the second part AA2 of the ninth interlayer insulating film INS9.

[0200] The planarization film PNS can be provided between the connection electrodes ANC adjacent in the first direction DR1 (see Figure 10 ) or the second direction DR2 (see Figure 10 ). The planarization film PNS can be provided between the reflective electrodes RL adjacent in the first direction DR1 or the second direction DR2. The planarization film PNS can be provided between the optical auxiliary films OAL adjacent in the first direction DR1 or the second direction DR2.

[0201] The step layer STPL is not present in the second emission area EA2, whereas the step layer STPL is present in each of the first emission area EA1 and the third emission area EA3. Therefore, the height of the connection electrode ANC, the reflection electrode RL, and the optical auxiliary film OAL in the second emission area EA2 can be smaller than the height of the connection electrode ANC, the reflection electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission area EA1 and the third emission area EA3. Therefore, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 provided on the top surface of the first electrode AND provided in the second emission area EA2.

[0202] In contrast, the top surface of the planarization film PNS can be connected flat to the top surface of the first pixel defining film PDL1 provided on the top surface of the first electrode AND provided in the first emission area EA1 and the third emission area EA3. That is, the planarization film PNS can not cover the top surface of the first pixel defining film PDL1 provided on the top surface of the first electrode AND provided in each of the first emission area EA1 and the third emission area EA3.

[0203] The second pixel defining film PDL2 can be provided on the first pixel defining film PDL1 and the planarization film PNS, the third pixel defining film PDL3 can be provided on the second pixel defining film PDL2, and the fourth pixel defining film PDL4 can be provided on the third pixel defining film PDL3. The first pixel defining film PDL1 and the third pixel defining film PDL3 can be formed of a silicon nitride (SiN x ) type inorganic film, and the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS can be formed of a silicon oxide (SiO x ) type inorganic film. The first pixel defining film PDL1 is formed of a material different from that of the planarization film PNS, and thus can serve as a stopper in a chemical mechanical polishing process for the planarization film PNS.

[0204] When the planarization film PNS and the second pixel defining film PDL2 are both formed as a silicon oxide (SiO x ) type inorganic film, the planarization film PNS and the second pixel defining film PDL2 can be formed as a single film.

[0205] Since the length of the third pixel defining film PDL3 in one direction is smaller than the length of the fourth pixel defining film PDL4 in the one direction, the bottom surface of the fourth pixel defining film PDL4 can be exposed and not covered by the third pixel defining film PDL3. That is, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have a eave-shaped or mushroom-shaped cross-sectional structure.

[0206] The light emitting stack IL can be disposed on the first electrode AND and the pixel definition film PDL. The light emitting stack IL can include a first stack layer IL1 and a second stack layer IL2 that emit different light. In an example in which the light emitting stack IL has a two-series structure, one of the first stack layer IL1 and the second stack layer IL2 can emit light of a wavelength range including any one of the first light, the second light, and the third light, and the other can emit light of a wavelength range including the other two lights. For example, the first stack layer IL1 can emit light of a wavelength range including the first light and a wavelength range including the third light, and the second stack layer IL2 can emit light of a wavelength range including the second light. Here, the first light can be light of a blue band, the second light can be light of a green band, and the third light can be light of a red band.

[0207] A charge generation layer for supplying holes to the second stack layer IL2 and for supplying electrons to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The charge generation layer can include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metal material.

[0208] The first stack layer IL1 is not formed on a bottom surface of the fourth pixel definition film PDL4 that is exposed without being covered by the third pixel definition film PDL3, and thus can be cut off by the eave-shaped or mushroom-shaped cross-sectional structure of the third pixel definition film PDL3 and the fourth pixel definition film PDL4. In this case, the first hole transport layer of the first stack layer IL1 and the charge generation layer disposed between the first stack layer IL1 and the second stack layer IL2 can also be cut off. In addition, although Figure 9 Although the second stack layer IL2 is shown as being connected without being cut off, the second hole transport layer of the second stack layer IL2 can be cut off, and the second electron transport layer of the second stack layer IL2 can be connected without being cut off. Thus, a leakage current can be prevented from flowing through the first hole transport layer of the first stack layer IL1, the second hole transport layer of the second stack layer IL2, and the charge generation layer between the adjacent emission areas EA1, EA2, and EA3. Thus, the light emitting stack IL in the adjacent emission areas EA1, EA2, and EA3 can be prevented from emitting light other than the originally intended light due to the influence of the described current.

[0209] Although Figure 9 Although the light emitting stack IL is shown as including a two-series structure of two stack layers IL1 and IL2, embodiments of the present disclosure are not limited thereto. For example, as Figure 11As shown in FIG. 1, the light emitting stack IL can have a three-series structure including three stack layers. In this case, the light emitting stack IL can be designed such that the charge generation layers between the first stack layer IL1 and the second stack layer IL2 and between the second stack layer IL2 and the third stack layer IL3 are cut off by adjusting the height of the third pixel definition film PDL3. Alternatively, as shown in FIG. 2, a trench TRC can be additionally formed to penetrate the first pixel definition film PDL1, the planarization film PNS, the second pixel definition film PDL2, and the third pixel definition film PDL3. In this case, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but embodiments of the disclosure are not limited thereto. Figure 12

[0210] Figure 11 is a schematic perspective view showing an example of a head-mounted display. Figure 11 is a schematic perspective view showing an example of a head-mounted display. Figure 12 is a schematic exploded perspective view of the head-mounted display shown in FIG. 1.

[0211] Reference will now be made to Figures 3 to 10 and Figure 4 The head-mounted display 1000 according to an embodiment includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0212] The first display device 20_1 provides an image to the left eye of a user, and the second display device 20_2 provides an image to the right eye of the user. Since each of the first display device 20_1 and the second display device 20_2 is substantially the same as the display device 20 described in conjunction with Figure 11 the description of the first display device 20_1 and the second display device 20_2 will be omitted.

[0213] The first optical member 1510 can be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0214] The intermediate frame 1400 can be disposed between the first display device 20_1 and the control circuit board 1600 and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 serves to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0215] ​The control circuit board 1600 can be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 through the connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA (see Figure 12 ) to the first display device 20_1 and the second display device 20_2 through the connectors.

[0216] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 20_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 20_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 20_1 and the second display device 20_2.

[0217] The display device housing 1100 serves to accommodate the first display device 20_1, the second display device 20_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is disposed such that the housing cover 1200 covers one open surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 in which the left eye of the user is positioned and a second eyepiece 1220 in which the right eye of the user is positioned. Figure 13 and Figure 13 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately disposed, but embodiments of the present disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0218] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 20_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0219] The head-mounted band 1300 serves to fix the display device housing 1100 to the head of the user such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are maintained to be positioned on the left eye and the right eye of the user, respectively. In an example in which the display device housing 1100 is implemented to be light in weight and compact, the head-mounted display 1000 can be provided with a headband as Figure 13The eyeglass frame shown in FIG. 1 can be replaced with a head-mounted band 1300.

[0220] Figure 13 is a schematic perspective view showing another example of a head-mounted display.

[0221] Referring to Figure 14 , the head-mounted display 1000_1 according to an embodiment can be a glasses-type display device in which the display device housing 1200_1 is implemented in a light-weight and compact manner. The head-mounted display 1000_1 according to an embodiment can include a display device 20_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple pieces 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0222] The display device housing 1200_1 can accommodate the display device 20_3, the optical member 1060, and the optical path changing member 1070. An image displayed in the display device 20_3 can be magnified by the optical member 1060 and can be provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can view, through the right eye, an augmented reality image in which a virtual image displayed in the display device 20_3 and a real image seen through the right-eye lens 1020 are combined.

[0223] Figure 14 It is shown that the display device housing 1200_1 is disposed at the right end of the support frame 1030, but embodiments of the disclosure are not limited thereto. For example, the display device housing 1200_1 can be disposed at the left end of the support frame 1030, and in this case, an image of the display device 20_3 can be provided to the left eye of the user. Alternatively, the display device housing 1200_1 can be disposed at both the left and right ends of the support frame 1030, and in this case, the user can view an image displayed in the display device 20_3 through both the left and right eyes.

[0224] Figure 3 is a schematic view showing a deposition mask and a deposition apparatus including the deposition mask according to an embodiment of the disclosure.

[0225] Referring to Figure 9 , the deposition apparatus 3000 can be used to form a light-emitting material layer on a backplane substrate 3002 in a manufacturing process of a display panel 100 (see Figure 15 ). For example, as Figure 14As shown in the middle, the semiconductor backplane SBP and the light emitting element backplane EBP can be provided on the backplane base 3002, and the reflective electrode RL and the insulating films INS10 and INS11 can be provided on the light emitting element backplane EBP. An electrode pattern (e.g., a first electrode AND (hereinafter, also referred to as an anode electrode AND)) can be provided on the insulating film INS11, and the anode electrode AND can be electrically connected to the reflective electrode RL through a via VA10. As an example, the deposition apparatus 3000 can form a first light emitting layer on the anode electrode AND of the first emission area EA1. As another example, the deposition apparatus 3000 can form a second light emitting layer on the anode electrode AND of the second emission area EA2. As still another example, the deposition apparatus 3000 can form a third light emitting layer on the anode electrode AND of the third emission area EA3.

[0226] The deposition apparatus 3000 can include a deposition source 3200 for providing a deposition material in a vapor phase on the backplane base 3002, a deposition mask 2000 provided above the deposition source 3200, and a substrate chuck 3300 provided above the deposition mask 2000 to support the backplane base 3002 so that the backplane base 3002 faces the deposition mask 2000. That is, the substrate chuck 3300 can support the backplane base 3002 so that a front surface of the backplane base 3002 faces downward, and can position the backplane base 3002 above the deposition mask 2000 to perform a deposition process.

[0227] The deposition source 3200, the deposition mask 2000, and the substrate chuck 3300 can be provided in a process chamber 3100. The process chamber 3100 can have an inner space, and a deposition process for forming a deposition material layer on the backplane base 3002 can be performed in the inner space of the process chamber 3100. Although not shown, the process chamber 3100 can be connected to a vacuum pump (not shown), and the inner space of the process chamber 3100 can be set to a vacuum atmosphere by the vacuum pump. An opening (not shown) for loading and unloading the backplane base 3002 and the deposition mask 2000 can be provided in a wall of the process chamber 3100, and the opening can be opened and closed by a gate valve (not shown).

[0228] A deposition material can be contained in the deposition source 3200. The deposition source 3200 can evaporate the deposition material (such as, for example, an organic material, an inorganic material, or a conductive material) toward the backplane base 3002, and the evaporated deposition material can be deposited on the backplane base 3002 through the deposition mask 2000. For example, the deposition source 3200 can evaporate an organic material for forming a light emitting material layer on the backplane base 3002, and the evaporated organic material can be deposited on an electrode pattern on the backplane base 3002 through the deposition mask 2000.

[0229] Figure 15 is a schematic bottom view showing Figure 15 the back surface of the substrate base shown in

[0230] Referring to Figure 3 , the substrate base 3002 can include a plurality of display cell regions 3010 and scribe lane regions 3020 disposed between the display cell regions 3010. The display cell regions 3010 can be arranged in a matrix form along a first direction DR1 and a second direction DR2 as shown in Figure 9 , and can be individualized into display panels 100 (see Figure 9 ) after a display device manufacturing process is completed through a scribing process. For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. In some aspects, as shown in the drawings, each of the plurality of display cell regions 3010 can have, for example, a quadrilateral shape.

[0231] For example, each of the plurality of display cell regions 3010 can include a semiconductor substrate SBP, a light emitting element substrate EBP disposed on the semiconductor substrate SBP, a reflective electrode RL disposed on the light emitting element substrate EBP, and insulating films INS10 and INS11 disposed on the reflective electrode RL as shown in Figure 14 . In some aspects, in conjunction with Figure 16 and Figure 14 , each of the plurality of display cell regions 3010 can include a plurality of electrode patterns (e.g., a plurality of anode electrodes AND) disposed on the insulating film INS11, and the plurality of anode electrodes AND can be connected to the reflective electrode RL through a plurality of vias VA10. In this case, the electrode patterns of the display cell regions 3010 can be disposed on the front surface of the substrate base 3002, and the substrate chuck 3300 can support the back surface of the substrate base 3002 so that the electrode patterns of the display cell regions 3010 face downward, i.e., toward the deposition source 3200.

[0232] Figure 17 is a schematic plan view showing Figure 16 the deposition mask shown in Figure 18 is a schematic enlarged plan view showing Figure 17 the mask cell region shown in Figures 16 to 18 is a schematic cross-sectional view taken along Figure 15 line I2-I2' shown in

[0233] Referring to Figure 15 , the deposition mask 2000 can include a plurality of mask cell regions 2010 (see Figure 9 ) corresponding to the plurality of display cell regions 3010 (seeFigure 14 Multiple mask cell regions 2310. Each of the multiple mask cell regions 2310 may have an anode electrode exposed during the deposition process AND (see [link to deposition process]). Figure 16 Multiple pixel openings 2312. For example, the deposition mask 2000 may include a mask frame 2100, an intermediate inorganic film 2200 disposed on the mask frame 2100, and a septum 2300 disposed on the intermediate inorganic film 2200. In this case, the septum 2300 may include a plurality of mask unit regions 2310, and each of the plurality of mask unit regions 2310 may have a plurality of pixel openings 2312.

[0234] For example, the mask frame 2100 may have cell openings 2110 and include rib regions 2120 defining the cell openings 2110. The diaphragm 2300 may include a plurality of mask cell regions 2310 respectively disposed on the plurality of cell openings 2110 and a grid region 2320 surrounding the plurality of mask cell regions 2310. That is, the grid region 2320 of the diaphragm 2300 may be disposed on the rib region 2120 of the mask frame 2100. The mask cell regions 2310 may face the deposition source 3200 (participating in) through the cell openings 2110. Figure 16 The pixel opening 2312 can be formed to penetrate the mask unit region 2310. That is, the pixel opening 2312 can communicate with the unit opening 2110. In this case, while performing the deposition process, the vapor deposition material provided from the deposition source 3200 can be deposited on the anode AND of the substrate 3002 through the unit opening 2110 and the pixel opening 2312.

[0235] like Figure 9 As shown, the mask unit region 2310 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. In this case, the third direction DR3 can be a vertical direction. That is, the third direction DR3 can be a direction perpendicular to the first direction DR1 and the second direction DR2. For example, the third direction DR3 can be the thickness direction of the mask frame 2100. The mask unit region 2310 can have, for example, as shown in the diagram. Figure 19 The quadrilateral shape shown, and the pixel opening 2312 can be arranged to correspond to Figures 16 to 18 The anode AND of any one of the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0236] According to one or more embodiments of the disclosure, an intermediate inorganic film 2200 can be disposed between the mask frame 2100 and the separation membrane 2300. That is, the intermediate inorganic film 2200 can be disposed between the rib region 2120 of the mask frame 2100 and the grid region 2320 of the separation membrane 2300. For example, the intermediate inorganic film 2200 and the separation membrane 2300 can be disposed on a front surface of the mask frame 2100, and the rear inorganic film 2400 can be disposed on a rear surface of the mask frame 2100.

[0237] The mask frame 2100 can be formed of a single crystal silicon. For example, a single crystal silicon substrate having a thickness in a range of about 700 µm to about 800 µm (e.g., a thickness of about 775 µm) can be used as the mask frame 2100. The separation membrane 2300 can be formed of silicon nitride (SiN x ) and can be formed to have a thickness in a range of about 0.5 µm to about 3 µm (e.g., a thickness of about 1 µm) by a thermal chemical vapor deposition (TCVD) process. The rear inorganic film 2400 can be formed of silicon nitride (SiN x ) and can be formed by a TCVD process. For example, the separation membrane 2300 and the rear inorganic film 2400 can be simultaneously formed by a TCVD process. The description herein of an element (e.g., the separation membrane 2300 or the intermediate inorganic film 2200, etc.) formed to have a certain thickness can refer to forming the element such that the element has the certain thickness.

[0238] The intermediate inorganic film 2200 can be formed of a material having etching selectivity with respect to the separation membrane 2300 and the rear inorganic film 2400. According to one or more embodiments of the disclosure, the intermediate inorganic film 2200 can be formed of a material including germanium (Ge) and can be formed to have a thickness in a range of about 50 nm to about 1 µm (e.g., a thickness of about 0.5 µm) by an epitaxial growth process, an electron beam evaporation process, a low pressure chemical vapor deposition (LPCVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process, etc. For example, the intermediate inorganic film 2200 can be formed of amorphous germanium (Ge), single crystal germanium (Ge), polycrystalline germanium (Ge), or silicon germanium (SiGe).

[0239] As another example, the intermediate inorganic film 2200 can be formed of boron-doped germanium (Ge:B) or boron-doped silicon germanium (SiGe:B). In this case, the intermediate inorganic film 2200 can be formed by an epitaxial growth process, and a lattice constant of the intermediate inorganic film 2200 can be reduced by boron doping. Specifically, a lattice constant of silicon (Si) is and a lattice constant of germanium (Ge) is Accordingly, when the intermediate inorganic film 2200 is formed of germanium (Ge) or silicon germanium (SiGe), residual compressive stress can be generated in the intermediate inorganic film 2200 due to a difference in lattice constant between the mask frame 2100 and the intermediate inorganic film 2200. However, when the intermediate inorganic film 2200 is formed of boron-doped germanium (Ge:B) or boron-doped silicon germanium (SiGe:B), the difference in lattice constant can be reduced, so that the residual compressive stress of the intermediate inorganic film 2200 can be reduced.

[0240] The pixel openings 2312 of the separation film 2300 can be formed through an anisotropic etching process. For example, after forming a first photoresist pattern (not shown) that exposes portions of the separation film 2300 where the pixel openings 2312 are to be formed, an anisotropic etching process (e.g., a reactive ion etching (RIE) process) using the first photoresist pattern as an etching mask can be performed to form the pixel openings 2312 that penetrate the separation film 2300. In this case, the intermediate inorganic film 2200 can serve as an etching stop film in the anisotropic etching process, and after forming the pixel openings 2312, the first photoresist pattern can be removed through a stripping and / or ashing process.

[0241] The back inorganic film 2400 can have back openings 2410 corresponding to the cell openings 2110 of the mask frame 2100, and can serve as an etching mask in an etching process for forming the cell openings 2110 of the mask frame 2100. For example, after forming a second photoresist pattern (not shown) that exposes portions of the back inorganic film 2400 where the back openings 2410 are to be formed, an anisotropic etching process (e.g., a RIE process) using the second photoresist pattern as an etching mask can be performed to form the back openings 2410 that penetrate the back inorganic film 2400. After forming the back openings 2410, the second photoresist pattern can be removed through a stripping and / or ashing process.

[0242] The cell openings 2110 of the mask frame 2100 can be formed through an anisotropic etching process using the back inorganic film 2400 as an etching mask. According to one or more embodiments of the present disclosure, the cell openings 2110 of the mask frame 2100 can be formed through a first wet etching process using an etchant containing potassium hydroxide (KOH). For example, an etchant containing about 10 wt% to about 40 wt% of KOH and water (H2O) (hereinafter, referred to as a “KOH solution”) can be used, and isopropyl alcohol (IPA) can be added as a surfactant.

[0243] The first wet-etching process can be performed until the intermediate inorganic film 2200 is exposed. In this case, the intermediate inorganic film 2200 can serve as an etch stop film in the first wet-etching process, and thus, the cell opening 2110 can be formed from the rear surface of the mask frame 2100 toward the front surface of the mask frame 2100. That is, the intermediate inorganic film 2200 can prevent the KOH solution from being provided onto the front surface of the mask frame 2100 through the pixel opening 2312 of the septum 2300.

[0244] The septum 2300 formed of silicon nitride (SiN x ) and the intermediate inorganic film 2200 including germanium (Ge) can be hardly removed by the KOH solution. That is, the etching rate of the KOH solution on the septum 2300 and the intermediate inorganic film 2200 is negligible (e.g., less than a threshold etching rate), and thus, damage to the septum 2300 can be prevented during the first wet-etching process.

[0245] During the first wet-etching process, hydrogen (H2) bubbles can be generated due to a reaction between silicon of the mask frame 2100 and the KOH solution. For example, if the intermediate inorganic film 2200 does not exist between the mask frame 2100 and the septum 2300, the KOH solution can be provided onto the front surface of the mask frame 2100 through the pixel opening 2312. In this case, hydrogen (H2) bubbles can be generated in the pixel opening 2312, and the septum 2300 can be damaged by the hydrogen (H2) bubbles. However, according to an embodiment of the disclosure, the intermediate inorganic film 2200 can prevent the KOH solution from being provided onto the front surface of the mask frame 2100 through the pixel opening 2312. Thus, when the first wet-etching process described herein is performed, damage to the septum 2300 can be prevented.

[0246] In the first wet-etching process using the KOH solution, the etching rate can be controlled by the temperature of the KOH solution. According to one or more embodiments of the disclosure, the first wet-etching process described herein can be performed at a temperature in the range of about 40℃ to about 100℃. When the cell opening 2110 is formed by a wet-etching process using a TMAH solution, a long processing time of about 24 hours to about 25 hours can be required. However, according to one or more embodiments of the disclosure, when the cell opening 2110 is formed using the KOH solution, the processing time can be shortened to about 6 hours or less (e.g., about 3 hours to about 4 hours) by appropriately controlling the concentration of the KOH solution and the temperature of the KOH solution.

[0247] In some embodiments, the <100> crystal direction of the single-crystalline silicon substrate used as the mask frame 2100 can be the third direction DR3, such that the cell openings 2110 can be formed to have a width that gradually decreases toward the separation membrane 2300 (i.e., in the third direction DR3) by the first wet etching process. For example, the inner surface of the cell openings 2110 can be formed to have a tilt angle of about 54.74°.

[0248] After the cell openings 2110 of the mask frame 2100 are formed, the portions of the intermediate inorganic film 2200 exposed by the cell openings 2110 can be removed by a second wet etching process, such that the cell openings 2110 of the mask frame 2100 are in communication with the pixel openings 2312 of the separation membrane 2300. Specifically, the cell openings 2110 of the mask frame 2100 can be in communication with the pixel openings 2312 of the separation membrane 2300 due to the second wet etching process, and the intermediate openings 2210 that penetrate the intermediate inorganic film 2200 can be formed by the second wet etching process. That is, the intermediate openings 2210 that connect the cell openings 2110 to the pixel openings 2312 can be formed by the second wet etching process.

[0249] For example, an etchant including hydrofluoric acid (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH), and water (H2O) can be used to remove the portions of the intermediate inorganic film 2200 exposed by the cell openings 2110. As another example, an etchant including ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) can be used to remove the portions of the intermediate inorganic film 2200 exposed by the cell openings 2110. In this case, a standard cleaning solution (SC-1) having a mixing ratio of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) of 1:5:1 or an etchant having a mixing ratio of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) of 1:5:20 can be used, and the etchant can further include peroxyacetic acid (CH3COOOH), acetic acid (CH3COOH), hydrofluoric acid (HF), and / or a surfactant. In some aspects, the second wet etching process can be performed at a temperature in a range of about 40 °C to about 80 °C.

[0250] Figure 14 FIG. 22 is a cross-sectional view illustrating a deposition mask according to another embodiment of the present disclosure.

[0251] Referring to Figure 9According to another embodiment of the disclosure, a deposition mask 2000 can include a mask frame 2100 having a plurality of cell openings 2110, an intermediate inorganic film 2700 disposed on the mask frame 2100, and a separation film 2800 disposed on the intermediate inorganic film 2700. The separation film 2800 can include a plurality of mask cell regions 2810 disposed on the plurality of cell openings 2110, respectively, and each of the plurality of mask cell regions 2810 can have a plurality of pixel openings 2812. The mask frame 2100 can include a rib region 2120 defining the cell openings 2110, and the separation film 2800 can include a grid region 2820 disposed on the rib region 2120.

[0252] According to the present embodiment, the deposition mask 2000 can include a buffer inorganic film 2500 disposed between the mask frame 2100 and the intermediate inorganic film 2700. For example, the buffer inorganic film 2500 can be formed of silicon oxide (SiO x ) and can be formed to have a thickness in a range of about 0.5 µm to about 2 µm by a thermal oxidation process. That is, the buffer inorganic film 2500 can be disposed on the mask frame 2100, and the intermediate inorganic film 2700 can be disposed on the buffer inorganic film 2500.

[0253] The intermediate inorganic film 2700 can be formed of a material including germanium (Ge). For example, the intermediate inorganic film 2700 can be formed to have a thickness in a range of about 50 nm to about 1 µm (e.g., a thickness of about 0.5 µm) by an e-beam evaporation process, an LPCVD process, or a PECVD process, etc., and can be formed of amorphous germanium (Ge), polycrystalline germanium (Ge), or silicon germanium (SiGe). The separation film 2800 can be formed of silicon nitride (SiN x ) and can be formed to have a thickness in a range of about 0.5 µm to about 3 µm (e.g., a thickness of about 1 µm) by a TCVD process.

[0254] The buffer inorganic film 2500, the intermediate inorganic film 2700, and the separation film 2800 can be disposed on a front surface of the mask frame 2100, and the first rear inorganic film 2600 and the second rear inorganic film 2900 can be disposed on a rear surface of the mask frame 2100. For example, the first rear inorganic film 2600 can be formed simultaneously with the buffer inorganic film 2500 by a thermal oxidation process, and the second rear inorganic film 2900 can be formed simultaneously with the separation film 2800 by a TCVD process. The first rear inorganic film 2600 and the second rear inorganic film 2900 can have a first rear opening 2610 and a second rear opening 2910, respectively, and can be used as etching masks in an etching process for forming the cell openings 2110.

[0255] The buffer inorganic film 2500 and the first rear inorganic film 2600 can be used to reduce stress applied to the mask frame 2100 by the intermediate inorganic film 2700, the separator 2800, and the second rear inorganic film 2900. For example, the separator 2800 and the second rear inorganic film 2900 can have residual tensile stress, and the intermediate inorganic film 2700 can have residual compressive stress. The buffer inorganic film 2500 and the first rear inorganic film 2600 can be formed to have residual compressive stress that is smaller than the residual compressive stress of the intermediate inorganic film 2700, so as to alleviate stress applied to the mask frame 2100 by the intermediate inorganic film 2700, the separator 2800, and the second rear inorganic film 2900.

[0256] An etching process for forming the unit opening 2110 of the mask frame 2100 can be performed until the buffer inorganic film 2500 is exposed, and in this case, the intermediate inorganic film 2700 and the buffer inorganic film 2500 can prevent an etchant (i.e., a KOH solution) from being provided onto the front surface of the mask frame 2100 through the pixel opening 2812. The portion of the buffer inorganic film 2500 exposed by the unit opening 2110 after the unit opening 2110 is formed can be removed by a third wet etching process using an etchant such as a diluted hydrofluoric acid (HF) or a buffered oxide etchant (BOE), and the front opening 2510 penetrating the buffer inorganic film 2500 can be formed by the third etching process.

[0257] The front opening 2510 of the buffer inorganic film 2500 can partially expose the intermediate inorganic film 2700, and the portion of the intermediate inorganic film 2700 exposed by the front opening 2510 can be removed by a second wet etching process. The intermediate opening 2710 penetrating the intermediate inorganic film 2700 can be formed by the second wet etching process, and the mask unit region 2810 can be exposed by the intermediate opening 2710. As a result, the pixel opening 2812 can be connected to the unit opening 2110 through the intermediate opening 2710 and the front opening 2510.

[0258] In the present embodiment, other elements except for the buffer inorganic film 2500 and the first rear inorganic film 2600 are substantially the same as those described herein with reference to Figures 20 to 25 the first embodiment. Therefore, further description thereof will be omitted.

[0259] Referring back to Figure 20 , a substrate chuck 3300 can be disposed above the deposition source 3200 and can support the backplane substrate 3002 such that the backplane substrate 3002 faces the deposition source 3200. For example, the substrate chuck 3300 can be an electrostatic chuck configured to support a back surface of the backplane substrate 3002 using electrostatic force. In detail, an electrode pattern (i.e., a plurality of electrodes) can be formed on the substrate chuck 3300, and a voltage can be applied to the electrode pattern to generate electrostatic force. Figure 18An anode electrode (AND) in the anode electrode (AND) can be disposed on a front surface of the floor base 3002, and the base chuck 3300 can support a rear surface of the floor base 3002 such that the front surface of the floor base 3002 faces the deposition source 3200 (i.e., faces downward toward the deposition source 3200).

[0260] Although not shown, the floor base 3002 can be loaded into the process chamber 3100 by a transfer robot (not shown), and a lift finger (not shown) for transferring the floor base 3002 from the transfer robot to the base chuck 3300 can be disposed in the process chamber 3100. For example, the floor base 3002 can be placed on the lift finger after being brought into the process chamber 3100 by the transfer robot, and the lift finger can be raised to load the floor base 3002 on the base chuck 3300. Subsequently, the base chuck 3300 can support the rear surface of the floor base 3002 by using electrostatic force.

[0261] An upper drive unit 3310 for moving and rotating the base chuck 3300 can be disposed above the base chuck 3300 to adjust the position and angle of the floor base 3002. For example, the upper drive unit 3310 can move the base chuck 3300 in a first direction DR1 and a second direction DR2 to adjust the horizontal position of the floor base 3002, and can move the base chuck 3300 in a third direction DR3 to adjust the vertical position of the floor base 3002. In this case, the first direction DR1, the second direction DR2, and the third direction DR3 can be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0262] In some aspects, the upper drive unit 3310 can rotate the base chuck 3300 about the Z-axis to adjust the azimuth angle of the floor base 3002. In addition, to adjust the tilt angle of the floor base 3002, the upper drive unit 3310 can rotate the base chuck 3300 about the X-axis, and can rotate the base chuck 3300 about the Y-axis. For example, the upper drive unit 3310 can include a hexapod actuator that provides motion of 6 degrees of freedom (X, Y, Z, θx, θy, and θz).

[0263] A mask stage 3400 on which the deposition mask 2000 is placed can be disposed above the deposition source 3200. That is, the mask stage 3400 can be disposed below the base chuck 3300, and can support an edge portion of the deposition mask 2000. The deposition mask 2000 can be carried into the process chamber 3100 by a transfer robot. For example, the deposition mask 2000 brought into the process chamber 3100 by the transfer robot can be placed on the lift finger, and the lift finger can be lowered to load the deposition mask 2000 on the mask stage 3400.

[0264] The mask stage 3400 can include a mask chuck 3410 for supporting the deposition mask 2000. Although not shown in detail, the mask chuck 3410 can have a circular ring planar shape and support an edge portion of the deposition mask 2000. For example, the mask chuck 3410 can be an electrostatic chuck configured to support the edge portion of the deposition mask 2000 using electrostatic force.

[0265] The mask stage 3400 can include a support plate 3420 for supporting the mask chuck 3410. The support plate 3420 can have an opening that can expose the mask cell region 2310 of the deposition mask 2000 toward the deposition source 3200, and a lower driving unit 3430 for adjusting a position and an angle of the deposition mask 2000 can be disposed between the support plate 3420 and the mask chuck 3410. For example, the lower driving unit 3430 can move the mask chuck 3410 in the first direction DR1 and the second direction DR2 to adjust a horizontal position of the deposition mask 2000, and can rotate the mask chuck 3410 about the Z-axis to adjust an azimuth angle of the deposition mask 2000. As an example, the lower driving unit 3430 can include a piezoelectric actuator that provides motion of 3 degrees of freedom (X, Y, and θz), and the piezoelectric actuator can have a quadrilateral ring planar shape.

[0266] Figure 21 is a schematic cross-sectional view illustrating a method of manufacturing a deposition mask according to yet another embodiment of the disclosure.

[0267] In the description of methods and processes herein, the various operations can be performed in different sequences from the illustrated and / or described, or operations can be added, modified or deleted. Certain operations can also be omitted from the flow charts. One or more operations can be repeated, or other operations can be added. The description of "may be provided," "may be formed," "may be patterned," and the like elements includes methods, processes, and techniques for providing, forming, and patterning, and the like, in accordance with the example aspects described herein.

[0268] Referring to Figure 22 , the method can include forming an intermediate inorganic film 2200 on a mask base 2010. For example, a single-crystal silicon substrate can be used as the mask base 2010, and the mask base 2010 can be used as a mask frame 2100 of a deposition mask 2000 (see Figure 23 ).

[0269] The intermediate inorganic film 2200 can be formed from a material containing germanium (Ge). For example, the intermediate inorganic film 2200 can be formed to have a thickness in the range of about 50 nm to about 1 μm (e.g., about 0.5 μm) by epitaxial growth, electron beam evaporation, LPCVD, or PECVD processes. For example, the intermediate inorganic film 2200 can be formed from amorphous germanium (Ge), monocrystalline germanium (Ge), polycrystalline germanium (Ge), or silicon germanium (SiGe). For example, the intermediate inorganic film 2200 can be formed by an LPCVD process using a germanium source gas such as GeH4, GeF4, or Ge2H6. As another example, when the intermediate inorganic film 2200 contains silicon germanium (SiGe), a germanium source gas such as GeH4, GeF4, or Ge2H6 and a silicon source gas such as SiH4, Si2H6, or SiH2Cl2 can be used.

[0270] As another example, the intermediate inorganic film 2200 can be formed from boron-doped germanium (Ge:B) or boron-doped silicon-germanium (SiGe:B). In this case, the intermediate inorganic film 2200 can be formed by an epitaxial growth process, and the lattice constant of the intermediate inorganic film 2200 can be reduced by boron doping. By way of example, the intermediate inorganic film 2200 can be formed by an epitaxial growth process using silicon source gases such as SiH4, Si2H6, or SiH2Cl2, germanium source gases such as GeH4, GeF4, or Ge2H6, and boron-doped gases such as B2H6. Specifically, the lattice constant of silicon (Si) is... Furthermore, the lattice constant of germanium (Ge) is Therefore, when the intermediate inorganic film 2200 is formed of germanium (Ge) or silicon germanium (SiGe), residual compressive stress may be generated in the intermediate inorganic film 2200 due to the difference in lattice constant between the mask substrate 2010 and the intermediate inorganic film 2200. However, when the intermediate inorganic film 2200 is formed of boron-doped germanium (Ge:B) or boron-doped silicon germanium (SiGe:B) according to one or more embodiments of the present disclosure, the difference in lattice constant can be reduced, thereby reducing the residual compressive stress of the intermediate inorganic film 2200.

[0271] refer to Figure 24 The method may include forming a separator 2300 on the intermediate inorganic membrane 2200. The separator 2300 may be made of silicon nitride (SiN). x The membrane can be formed and can be formed to have a thickness in the range of about 0.5 μm to about 3 μm by a TCVD process. For example, the membrane 2300 can be formed by the reaction between a silicon source gas such as SiH4, Si2H6 or SiH2Cl2 and a nitrogen source gas such as ammonia (NH3).

[0272] The method may include forming an intermediate inorganic membrane 2200 and a diaphragm 2300 on the front surface of the mask substrate 2010, and the method may include forming a rear inorganic membrane 2400 on the rear surface of the mask substrate 2010. For example, the rear inorganic membrane 2400 may be formed simultaneously with the diaphragm 2300 by a TCVD process, and may be formed from the same material as the diaphragm 2300.

[0273] refer to Figure 25 The method may include patterning the diaphragm 2300 to form a plurality of pixel openings 2312 that partially expose the intermediate inorganic film 2200. For example, after forming a first photoresist pattern (not shown) on the diaphragm 2300 to expose the portions where the pixel openings 2312 will be formed, the method may include performing an anisotropic etching process using the first photoresist pattern as an etching mask to form the pixel openings 2312 exposing the intermediate inorganic film 2200. For example, the pixel openings 2312 may be formed using a refining etching (RIE) process using a reactive gas such as CHF3, CH3F, CH2F2, CF4, C2F6, or C3F6 and a sputtering gas such as Ar or O2 and Ar. In this case, the intermediate inorganic film 2200 may be used as an etch stop film in the RIE process. After forming the pixel openings 2312, the first photoresist pattern may be removed by a stripping and / or ashing process.

[0274] refer to Figures 26 to 33 The method may include patterning the inorganic film 2400 to form a rear opening 2410. For example, after forming a second photoresist pattern (not shown) on the inorganic film 2400 that exposes the portion where the rear opening 2410 will be formed, the method may include performing an anisotropic etching process (such as a RIE process) using the second photoresist pattern as an etching mask. The anisotropic etching process may be performed until the rear portion of the mask substrate 2010 is exposed. In this case, the rear opening 2410 may overlap with a plurality of pixel openings 2312 on a third-dimensional DR3. That is, the rear opening 2410 may expose the rear portion of the mask substrate 2010 where the unit opening 2110 will be formed. After the rear opening 2410 is formed, the second photoresist pattern may be removed by a stripping and / or ashing process.

[0275] refer to Figure 26The method may include patterning a mask substrate 2010 to form cell openings 2110 that partially expose the intermediate inorganic film 2200. For example, the method may include performing a first wet etching process using the inorganic film 2400 as an etching mask. The mask substrate 2010 may be partially removed by the first wet etching process, and as a result, cell openings 2110 that partially expose the intermediate inorganic film 2200 may be formed. That is, rib regions 2120 defining the cell openings 2110 may be formed by the first wet etching process.

[0276] According to this embodiment, in the first wet etching process, a KOH solution can be used as an etchant, and isopropanol (IPA) can be added as a surfactant to the etchant. The method may include performing the first wet etching process until the intermediate inorganic film 2200 is exposed. In this case, the intermediate inorganic film 2200 can be used as an etching stop film in the first wet etching process, and therefore, the cell opening 2110 can be formed from the rear surface of the mask substrate 2010 toward the front surface of the mask substrate 2010. That is, the intermediate inorganic film 2200 can prevent the KOH solution from being supplied to the front surface of the mask substrate 2010 through the pixel opening 2312 of the diaphragm 2300.

[0277] Silicon nitride (SiN) x The diaphragm 2300 and the intermediate inorganic film 2200 containing germanium (Ge) formed can be hardly removed by the KOH solution. That is, the etching rate of the KOH solution on the diaphragm 2300 and the intermediate inorganic film 2200 is negligible (i.e., less than the threshold etching rate), and therefore, damage to the diaphragm 2300 can be prevented during the first wet etching process.

[0278] During the first wet etching process, hydrogen (H2) bubbles may be generated due to the reaction between the silicon of the mask substrate 2010 and the KOH solution. For example, if there is no intermediate inorganic film 2200 between the mask substrate 2010 and the separator 2300, the KOH solution may be supplied to the front surface of the mask substrate 2010 through the pixel opening 2312. In this case, hydrogen (H2) bubbles may be generated in the pixel opening 2312, and the separator 2300 may be damaged by these hydrogen (H2) bubbles. However, according to embodiments of the present disclosure, the intermediate inorganic film 2200 can prevent the KOH solution from being supplied to the front surface of the mask substrate 2010 through the pixel opening 2312. Therefore, damage to the separator 2300 can be prevented when the wet etching process described herein is performed.

[0279] In some cases, during the first wet etching process, differences in etching rates may occur between different portions of the mask substrate 2010 (e.g., between the central and edge portions of the mask substrate 2010). In this case, while the cell openings 2110 are formed in the portions with relatively low etching rates, the intermediate inorganic film 2200 may be exposed to the KOH solution through the cell openings 2110 that are first formed in the portions with relatively high etching rates. However, according to this embodiment, the intermediate inorganic film 2200 is hardly etched by the KOH solution. Therefore, even if differences in etching rates occur between different portions of the mask substrate 2010, damage to the diaphragm 2300 by hydrogen (H2) bubbles can be prevented.

[0280] In the first wet etching process, the etching rate can be controlled by the temperature of the KOH solution. For example, the first wet etching process can be performed at a temperature in the range of about 40°C to about 100°C. According to this embodiment, the amount of time used to perform the first wet etching process (i.e., the duration of the first wet etching process) can be reduced to about 6 hours or less (e.g., about 3 hours to about 4 hours) by appropriately controlling the concentration and temperature of the KOH solution.

[0281] refer to Figure 27 After forming the cell opening 2110, the method may include removing the portion of the intermediate inorganic film 2200 exposed by the cell opening 2110, such that the pixel opening 2312 is connected to the cell opening 2110. For example, the method may include performing a second wet etching process associated with removing the portion of the intermediate inorganic film 2200 exposed by the cell opening 2110, such that an intermediate opening 2210 penetrating the intermediate inorganic film 2200 can be formed. That is, the pixel opening 2312 can communicate with the cell opening 2110 through the intermediate opening 2210.

[0282] For example, the method may include performing a second wet etching process using an etchant comprising hydrofluoric acid (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH), and water (H2O). As another example, the method may include performing a second wet etching process using an etchant comprising ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). In this case, a standard cleaning solution (SC-1) having a mixing ratio of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) of 1:5:1 or an etchant having a mixing ratio of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) of 1:5:20 can be used, and the etchant may also contain peracetic acid (CH3COOOH), acetic acid (CH3COOH), hydrofluoric acid (HF), and / or a surfactant. In some aspects, the second wet etching process may be performed at a temperature ranging from about 40°C to about 80°C.

[0283] Figure 28 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to yet another embodiment of the present disclosure.

[0284] refer to Figure 29 The method may include forming a buffer inorganic film 2500 on a mask substrate 2010. For example, a single-crystal silicon substrate may be used as the mask substrate 2010, and the buffer inorganic film 2500 may be formed by a thermal oxidation process to have a thickness in the range of about 0.5 μm to about 2 μm. That is, the buffer inorganic film 2500 may be formed of silicon oxide. In this case, the buffer inorganic film 2500 may be formed on the front surface of the mask substrate 2010, and a first rear inorganic film 2600 may be formed on the rear surface of the mask substrate 2010. By way of example, the first rear inorganic film 2600 may comprise silicon oxide and may be formed simultaneously with the buffer inorganic film 2500 by a thermal oxidation process.

[0285] refer to Figure 30The method may include forming an intermediate inorganic film 2700 on a buffer inorganic film 2500. The intermediate inorganic film 2700 may be formed from a material containing germanium (Ge) and may be formed to have a thickness in the range of about 50 nm to about 1 μm (e.g., about 0.5 μm) by electron beam evaporation, LPCVD, or PECVD processes. For example, the intermediate inorganic film 2700 may be formed from amorphous germanium (Ge), polycrystalline germanium (Ge), or silicon germanium (SiGe). For example, the intermediate inorganic film 2700 may be formed by an LPCVD process using a germanium source gas such as GeH4, GeF4, or Ge2H6. As another example, when the intermediate inorganic film 2700 contains silicon germanium (SiGe), a germanium source gas such as GeH4, GeF4, or Ge2H6 and a silicon source gas such as SiH4, Si2H6, or SiH2Cl2 may be used.

[0286] refer to Figure 31 The method may include forming a separator 2800 on the intermediate inorganic membrane 2700. The separator 2800 may be made of silicon nitride (SiN). x The membrane 2800 can be formed by a TCVD process to have a thickness in the range of about 0.5 μm to about 3 μm. For example, the membrane 2800 can be formed by a reaction between a silicon source gas, such as SiH4, Si2H6, or SiH2Cl2, and a nitrogen source gas, such as ammonia (NH3). In some embodiments, a second post-inorganic membrane 2900 can be formed on the first post-inorganic membrane 2600. For example, the second post-inorganic membrane 2900 can be formed simultaneously with the membrane 2800 by a TCVD process and can be formed from the same material as the membrane 2800.

[0287] refer to Figure 32 The method may include patterning the diaphragm 2800 to form a plurality of pixel openings 2812 that partially expose the intermediate inorganic film 2700. For example, after forming a first photoresist pattern (not shown) on the diaphragm 2800 to expose the portion where the pixel openings 2812 will be formed, the method may include performing an anisotropic etching process using the first photoresist pattern as an etching mask to form the pixel openings 2812 exposing the intermediate inorganic film 2700. For example, the pixel openings 2812 may be formed by a RIE process using a reactive gas such as CHF3, CH3F, CH2F2, CF4, C2F6, or C3F6 and a sputtering gas such as Ar or O2 and Ar. In this case, the intermediate inorganic film 2700 may be used as an etch stop film in the RIE process. After forming the pixel openings 2812, the first photoresist pattern may be removed by a stripping and / or ashing process.

[0288] refer toFigure 33 The method may include patterning a first rear inorganic film 2600 and a second rear inorganic film 2900, respectively, to form a first rear opening 2610 and a second rear opening 2910. For example, after forming a second photoresist pattern (not shown) on the second rear inorganic film 2900 that exposes the portion where the second rear opening 2910 will be formed, the method may include performing an anisotropic etching process (such as a RIE process) using the second photoresist pattern as an etching mask. The method may include performing the anisotropic etching process until a portion of the mask substrate 2010 is exposed. In this case, the first rear opening 2610 and the second rear opening 2910 may overlap with a plurality of pixel openings 2812 on a third-party DR3. That is, the first rear opening 2610 and the second rear opening 2910 may expose the rear portion of the mask substrate 2010 where the unit opening 2110 will be formed. After forming the first rear opening 2610 and the second rear opening 2910, the second photoresist pattern may be removed by a stripping and / or ashing process.

[0289] refer to ​ The method may include patterning a mask substrate 2010 to form cell openings 2110 that partially expose the buffer inorganic film 2500. For example, the method may include performing a first wet etching process using a first post-inorganic film 2600 and a second post-inorganic film 2900 as an etching mask. The mask substrate 2010 may be partially removed by the first wet etching process, and as a result, cell openings 2110 that partially expose the buffer inorganic film 2500 may be formed. That is, rib regions 2120 defining the cell openings 2110 may be formed by the first wet etching process.

[0290] In the first wet etching process, a KOH solution can be used as the etchant, and isopropanol (IPA) can be added as a surfactant to the etchant. The method may include performing the first wet etching process until the buffer inorganic film 2500 is exposed. In this case, the buffer inorganic film 2500 and the intermediate inorganic film 2700 can be used as etching stop films in the first wet etching process, and therefore, the cell opening 2110 can be formed from the rear surface of the mask substrate 2010 toward the front surface of the mask substrate 2010. In this case, the intermediate inorganic film 2700 can prevent the KOH solution from being supplied to the front surface of the mask substrate 2010 through the pixel opening 2812 of the diaphragm 2800, thereby preventing damage to the diaphragm 2800 during the first wet etching process.

[0291] In the first wet etching process, the etching rate can be controlled by the temperature of the KOH solution. For example, the method may include controlling the etching rate in the first wet etching process by controlling the temperature of the KOH solution. In the example, the first wet etching process may be performed at a temperature in the range of about 40°C to about 100°C. According to this embodiment, the amount of time used to perform the first wet etching process (i.e., the duration of the first wet etching process) can be reduced to about 6 hours or less (e.g., about 3 hours to about 4 hours) by appropriately controlling the concentration and temperature of the KOH solution.

[0292] refer to ​ After forming the unit opening 2110, the portion of the buffer inorganic film 2500 exposed by the unit opening 2110 can be removed. By way of example, said portion of the buffer inorganic film 2500 can be removed by a third wet etching process using an etchant such as BOE or diluted hydrofluoric acid (HF). The third wet etching process can be performed until the intermediate inorganic film 2700 is exposed, and the front opening 2510 penetrating the buffer inorganic film 2500 can be formed by the third etching process.

[0293] refer to ​ The portion of the intermediate inorganic film 2700 exposed by the front opening 2510 can be removed, allowing the pixel opening 2812 to connect to the unit opening 2110. For example, the portion of the intermediate inorganic film 2700 exposed by the front opening 2510 can be removed by a second wet etching process, allowing the intermediate opening 2710 to penetrate the intermediate inorganic film 2700 to be formed. That is, the pixel opening 2812 can communicate with the unit opening 2110 through the intermediate opening 2710 and the front opening 2510. For example, the second wet etching process can be performed using an etchant containing hydrofluoric acid (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH), and water (H2O). As another example, the second wet etching process can be performed using an etchant containing ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O).

[0294] This invention should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0295] While the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A deposition mask, wherein, The deposition mask includes: Mask frame with unit openings; An intermediate inorganic membrane is disposed on the mask frame; and A diaphragm, disposed on the intermediate inorganic membrane, has multiple pixel openings that communicate with the unit openings. The intermediate inorganic film is formed from a material including germanium.

2. The deposition mask according to claim 1, wherein, The intermediate inorganic film is formed from at least one selected from the group consisting of amorphous germanium, monocrystalline germanium, polycrystalline germanium, and silicon germanium.

3. The deposition mask according to claim 1, wherein: The mask frame is formed of single-crystal silicon, and The intermediate inorganic film is formed by boron-doped germanium or boron-doped silicon-germanium.

4. The deposition mask according to claim 1, wherein, The intermediate inorganic film has a thickness in the range of 50 nm to 1 μm.

5. The deposition mask according to claim 1, wherein, The diaphragm is formed of silicon nitride and has a thickness in the range of 0.5 μm to 3 μm.

6. The deposition mask according to claim 1, wherein, The deposition mask also includes a buffer inorganic membrane disposed between the mask frame and the intermediate inorganic membrane.

7. The deposition mask according to claim 6, wherein, The buffer inorganic film is formed of silicon oxide and has a thickness in the range of 0.5 μm to 2 μm.

8. A method for manufacturing a deposition mask, wherein, The method includes: An intermediate inorganic film is formed on the mask substrate; A septum with multiple pixel openings is formed on the intermediate inorganic film; Patterning the mask substrate, wherein the patterning of the mask substrate forms unit openings that partially expose the intermediate inorganic film; and Remove the portion of the intermediate inorganic film exposed by the cell opening, so that the cell opening is in communication with the plurality of pixel openings. The intermediate inorganic film is formed from a material including germanium.

9. The method according to claim 8, wherein, The intermediate inorganic film is formed from at least one selected from the group consisting of amorphous germanium, monocrystalline germanium, polycrystalline germanium, and silicon germanium.

10. The method according to claim 8, wherein: The mask substrate is formed of single-crystal silicon, and The intermediate inorganic film is formed by boron-doped germanium or boron-doped silicon-germanium.

11. The method according to claim 8, wherein, The intermediate inorganic film is formed such that it has a thickness in the range of 50 nm to 1 μm.

12. The method according to claim 8, wherein, The diaphragm is formed of silicon nitride and is formed such that the diaphragm has a thickness in the range of 0.5 μm to 3 μm.

13. The method according to claim 8, wherein, Patterning the mask substrate involves forming the cell openings by performing a wet etching process using an etchant comprising potassium hydroxide.

14. The method according to claim 13, wherein, The wet etching process is performed at a temperature ranging from 40°C to 100°C.

15. The method according to claim 8, wherein, Removing the portion of the intermediate inorganic film exposed by the cell opening involves performing a wet etching process using an etchant comprising hydrofluoric acid, hydrogen peroxide, acetic acid, and water.

16. The method according to claim 8, wherein, Removing the portion of the intermediate inorganic film exposed by the cell opening involves performing a wet etching process using an etchant comprising ammonium hydroxide, hydrogen peroxide, and water.

17. The method according to claim 8, wherein, The method further includes forming a buffer inorganic film on the mask substrate. The buffer inorganic film is formed of silicon oxide and is formed such that the buffer inorganic film has a thickness in the range of 0.5 μm to 2 μm. The intermediate inorganic membrane is formed on the buffer inorganic membrane.

18. The method according to claim 17, wherein, The method further includes partially removing the buffer inorganic membrane, such that the intermediate inorganic membrane is partially exposed by the cell opening.

19. The method according to claim 8, wherein, The method further includes forming a rear inorganic film on the rear surface of the mask substrate that exposes the rear portion of the mask substrate. The patterning of the mask substrate includes forming the cell openings by performing a wet etching process using the post-inorganic film as an etching mask.

20. An electronic device, wherein, The electronic device includes a display panel. The display panel includes: Base; and A light-emitting layer is formed on the substrate using a deposition mask, and the deposition mask comprises: Mask frame with unit openings; An intermediate inorganic membrane is disposed on the mask frame; and A diaphragm, disposed on the intermediate inorganic membrane, has multiple pixel openings that communicate with the unit openings. The intermediate inorganic film is formed from a material including germanium.

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