Batch data processing method, device and equipment suitable for database and medium

Abstract

The application discloses a batch data processing method and device suitable for a database, equipment and a medium, relates to the technical field of data processing, and is applied to a processor and comprises the following steps: after starting batch data processing corresponding to a preset database, it is monitored whether a target instruction meeting preset step conditions exists in a data processing instruction stream corresponding to the preset database in a target pipeline; if the target instruction exists, an instruction pre-execution mode is entered, the target instruction and subsequent instructions having a dependency relationship with the register of the target instruction are vectorized, instruction pre-execution is carried out based on the vectorized instruction and a first execution unit, and the instruction pre-execution result is saved to a first physical register stack and a result cache area; when the data processing instruction stream in the target pipeline reaches the input end of a second execution unit, the instruction pre-execution result in the result cache area is matched, and batch data processing operation is completed based on the information matching result. The application improves the efficiency and accuracy of batch data processing.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to batch data processing methods, apparatus, devices and media suitable for databases. Background Technology

[0002] Traditional batch data processing schemes typically execute instructions sequentially, which fails to fully utilize the parallel computing capabilities of modern processors.

[0003] Although vectorization technology has been applied to the processing of batch data, in the existing related solutions: (1) Hardware-accelerated vectorization solution: the data is vectorized by the hardware parallel computing capability, but this solution has the problem of insufficient instruction scheduling flexibility when dealing with computational tasks with complex data dependencies; (2) Software-optimized vectorization solution: the scalar code is automatically converted into vector code through compiler optimization, but it cannot fully explore all parallel opportunities in the code, and if there is a circular dependency, the compiler may not be able to correctly vectorize the code, or it may need to perform complex dependency analysis, which increases the complexity of the compiler and the possibility of errors.

[0004] It is evident that how to solve the problems existing in the current related solutions, thereby improving the efficiency and accuracy of batch data processing, is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a batch data processing method, apparatus, device, and medium suitable for databases, which can solve the problems existing in existing related solutions, thereby improving the efficiency and accuracy of batch data processing. The specific solution is as follows:

[0006] In a first aspect, the present invention provides a batch data processing method suitable for databases, applied to a processor, comprising:

[0007] After starting the batch data processing corresponding to the preset database, based on the preset detector, monitor whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset step size conditions, so as to obtain the step size detection results; wherein, the preset step size conditions are that they belong to the same program counter, appear repeatedly, and the memory access step size changes regularly.

[0008] If the stride detection result indicates that the instruction pre-execution mode is entered, and based on the vectorized execution engine, the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction are vectorized to determine the vectorized instruction.

[0009] Based on the vectorized instructions, the first issue queue, and the first execution unit, instruction pre-execution is performed, and the corresponding instruction pre-execution results are saved to the first physical register file and the result cache using a preset result storage strategy.

[0010] When the data processing instruction stream in the target pipeline reaches the input of the second execution unit, the pre-execution results of the instructions in the result buffer are matched based on the instruction information corresponding to the data processing instruction stream to determine the information matching result; the instruction information includes program counter information, source operands, and destination operands;

[0011] Based on the information matching results, data processing instruction stream, and the second execution unit, the batch data processing operation corresponding to the preset database is completed.

[0012] Optionally, based on a preset detector, the system monitors whether there are target instructions that meet preset stride conditions in the data processing instruction stream corresponding to the preset database in the target pipeline, in order to obtain stride detection results, including:

[0013] Based on the stride information corresponding to each data processing instruction in the preset detector and data processing instruction stream, stride changes are monitored to determine the monitoring results; stride information includes the instruction address in the program counter, stride value, and stride confidence level.

[0014] Based on the preset detector and monitoring results, it is determined whether there is a target instruction in the data processing instruction stream that meets the preset stride conditions, so as to obtain the stride detection result.

[0015] Optionally, based on the vectorized execution engine, the target instruction and subsequent instructions in the data processing instruction stream that have register dependencies on the target instruction are vectorized to determine the vectorized instructions, including:

[0016] In instruction pre-execution mode, the target instruction is vectorized based on the vectorized execution engine and the corresponding stride value to determine the first vectorized instruction;

[0017] Based on the vectorized execution engine and the corresponding step value, data processing instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction and whose execution order is after the target instruction are vectorized to determine the second vectorized instruction.

[0018] Optionally, instruction pre-execution is performed based on the vectorized instructions, the first issue queue, and the first execution unit, including:

[0019] The vectorized instructions are renamed to determine the renamed instructions;

[0020] Based on the first renaming table and the first physical register file, registers are reallocated for the renamed instructions to determine the register reallocation result;

[0021] Store the renamed command in the first launch queue;

[0022] Based on the first launch queue, check whether the renamed instruction meets the preset instruction execution conditions to determine the check result;

[0023] If the check results are satisfactory, the renamed instruction will be sent to the first execution unit based on the first transmission queue.

[0024] Based on the first execution unit, the renamed instruction, and the register reallocation result, instruction pre-execution is performed to determine the instruction pre-execution result corresponding to the renamed instruction.

[0025] Optionally, using a preset result storage strategy, the corresponding instruction pre-execution results are saved to the first physical register file and the result cache, including:

[0026] For any renamed instruction, save the pre-execution result of the instruction corresponding to the current renamed instruction to the first physical register file;

[0027] Determine whether the operation type of the currently renamed instruction belongs to the preset operation type to determine the type determination result; the preset operation types include floating-point operation, multiplication operation, and division operation;

[0028] If the type determination result indicates that it belongs to the category, then the pre-execution result of the instruction corresponding to the currently renamed instruction will be saved to the result cache.

[0029] Optionally, based on the instruction information corresponding to the data processing instruction stream, the pre-execution results of the instructions in the result buffer are matched to determine the information matching result, including:

[0030] For any data processing instruction in the target pipeline that corresponds to the preset database, obtain the instruction information corresponding to the current data processing instruction;

[0031] Based on the program counter information, source operands, destination operands, and operation type corresponding to the current data processing instruction, instruction matching is performed on the instruction pre-execution results in the result buffer to determine the information matching result.

[0032] Optionally, based on the information matching results, the data processing instruction stream, and the second execution unit, batch data processing operations corresponding to the preset database are completed, including:

[0033] If the information matching result indicates that there is a vectorized instruction in the result buffer that is identical to the current data processing instruction information, then the corresponding instruction pre-execution result will be bypassed to the output of the second execution unit.

[0034] If the information matching result indicates that there is no vectorized instruction in the result cache that is identical to the current data processing instruction, then the current data processing instruction is executed based on the second execution unit.

[0035] In a second aspect, the present invention provides a batch data processing apparatus suitable for databases, applied to a processor, comprising:

[0036] The stride detection module is used to monitor, based on a preset detector, whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset stride conditions after the batch data processing corresponding to the preset database is started, so as to obtain the stride detection result; wherein, the preset stride conditions are that they belong to the same program counter, appear repeatedly, and the memory access stride changes regularly.

[0037] The instruction vectorization module is used to enter the instruction pre-execution mode if the stride detection result shows that it exists, and based on the vectorization execution engine, to perform vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction, so as to determine the vectorized instruction.

[0038] The instruction pre-execution module is used to perform instruction pre-execution based on the vectorized instructions, the first issue queue and the first execution unit, and to save the corresponding instruction pre-execution results to the first physical register file and the result cache using a preset result storage strategy.

[0039] The result cache matching module is used to match the pre-execution results of instructions in the result cache area based on the instruction information corresponding to the data processing instruction stream in the target pipeline when the data processing instruction stream arrives at the input of the second execution unit, so as to determine the information matching result; the instruction information includes program counter information, source operands and destination operands;

[0040] The processing operation completion module is used to complete batch data processing operations corresponding to the preset database based on information matching results, data processing instruction stream, and the second execution unit.

[0041] Thirdly, the present invention provides an electronic device, comprising:

[0042] Memory, used to store computer programs;

[0043] A processor for executing computer programs to implement the steps of the aforementioned batch data processing method applicable to databases.

[0044] Fourthly, the present invention provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the aforementioned batch data processing method applicable to a database.

[0045] As can be seen, in this invention, applied to a processor, after starting batch data processing corresponding to a preset database, a preset detector monitors whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet preset step size conditions, so as to obtain step size detection results. The preset step size conditions are: belonging to the same program counter, appearing repeatedly, and memory access step sizes changing regularly. If the step size detection result indicates existence, the system enters instruction pre-execution mode, and based on a vectorized execution engine, it performs vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the target instruction's register, in order to determine the vectorized instructions. Based on the vectorized instructions, the first issue queue, and the first execution unit, instruction pre-execution is performed, and the corresponding instruction pre-execution results are saved to the first physical register file and the result buffer using a preset result storage strategy. When the data processing instruction stream in the target pipeline reaches the input of the second execution unit, the instruction pre-execution results in the result buffer are matched based on the instruction information corresponding to the data processing instruction stream to determine the information matching result. The instruction information includes program counter information, source operands, and destination operands. Based on the information matching result, the data processing instruction stream, and the second execution unit, the batch data processing operation corresponding to the preset database is completed.

[0046] As can be seen from the above technical solution, in this invention, applied to a processor, firstly, after starting batch data processing corresponding to the preset database, based on a preset detector, it monitors whether there are target instructions in the data processing instruction stream corresponding to the preset database that belong to the same program counter, appear repeatedly, and have memory access steps that change regularly, so as to obtain step detection results; then, if the step detection results show that they exist, it enters the instruction pre-execution mode, and based on the vectorized execution engine, it performs vectorized processing on the target instruction and subsequent instructions in the instruction stream that have a dependency relationship with the register of the target instruction; then, based on the corresponding vectorized instructions, the first issue queue, and the first execution unit, it determines the instruction pre-execution result and saves the instruction pre-execution result to the first physical register file and the result buffer; then, when the data processing instruction stream in the target pipeline reaches the input end of the second execution unit, it matches the instruction pre-execution result in the result buffer based on the instruction information corresponding to the data processing instruction stream, and uses the corresponding information matching result and the second execution unit to complete the batch data processing operation corresponding to the preset database. This approach addresses the problems present in existing solutions, thereby improving the efficiency and accuracy of batch data processing, increasing the parallelism of instruction execution, improving cache hit rate during target pipeline execution, and reducing redundant computations. Attached Figure Description

[0047] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A framework diagram of a batch data processing system suitable for databases is provided for this invention;

[0049] Figure 2 A schematic diagram of a specific workflow framework for batch data processing in a database, provided by the present invention;

[0050] Figure 3 This invention provides a schematic diagram of the design of a preset detector;

[0051] Figure 4 A schematic diagram illustrating the implementation of instruction vectorization provided by the present invention;

[0052] Figure 5 A schematic diagram illustrating the storage of instruction pre-execution results provided by the present invention;

[0053] Figure 6 A schematic diagram of a batch data processing device suitable for databases provided by the present invention;

[0054] Figure 7 This invention provides a structural diagram of an electronic device. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0056] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0057] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] In traditional batch data processing schemes, instructions are usually executed sequentially, which cannot fully utilize the parallel computing capabilities of modern processors. Although vectorization technology has been applied to batch data processing, in existing related schemes: (1) Hardware-accelerated vectorization schemes: Data is vectorized through hardware parallel computing capabilities, but this scheme has the problem of insufficient instruction scheduling flexibility when dealing with computational tasks with complex data dependencies; (2) Software-optimized vectorization schemes: Scalar code is automatically converted into vector code through compiler optimization, but it cannot fully exploit all parallel opportunities in the code, and if there are circular dependencies, the compiler may not be able to correctly vectorize the code, or complex dependency analysis may be required, which increases the complexity of the compiler and the possibility of errors.

[0059] Therefore, this invention provides a batch data processing scheme suitable for databases, which can solve the problems existing in the existing related schemes, thereby improving the efficiency and accuracy of batch data processing, increasing the parallelism of instruction execution, improving the cache hit rate during target pipeline execution, and reducing redundant calculations.

[0060] See Figure 1 As shown, this embodiment of the invention discloses a batch data processing method suitable for databases, applied to a processor, including:

[0061] Step S11: After starting the batch data processing corresponding to the preset database, based on the preset detector, monitor whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset step size conditions, so as to obtain the step size detection result; wherein, the preset step size conditions are that they belong to the same program counter, appear repeatedly, and the memory access step size changes regularly.

[0062] In this embodiment, when using, as Figure 2 After the batch data processing corresponding to the preset database is initiated in the illustrated process framework, the step size in the decoded data processing instruction stream is monitored in real time during the data processing process to determine whether it is necessary to enter the instruction pre-execution mode. Specifically, based on the preset detector and the step size information corresponding to each data processing instruction in the data processing instruction stream, step size changes are monitored to determine the monitoring results. The step size information includes the instruction address, step size value, and step size confidence in the program counter. Based on the preset detector and the monitoring results, it is determined whether there is a target instruction in the data processing instruction stream that meets the preset step size condition, so as to obtain the step size detection result. It can be understood that this embodiment uses a preset detector (i.e., Figure 2 The stride detector monitors in real time whether the stride meets specific conditions (i.e., preset stride conditions). These conditions can be set or adjusted according to specific data processing needs and processor performance, such as the stride reaching a certain value or the stride variation conforming to a certain pattern.

[0063] It is important to understand that the design of the stride detector, in conjunction with... Figure 3 As shown, in this embodiment, after the processor front-end completes the instruction decoding operation, a stride detector is added to detect in real time whether there are strides with access patterns under the same instruction PC in the instruction stream. If so, the instruction is converted into a vector instruction and the corresponding vector logic register is allocated. The specific implementation of this detector is as follows:

[0064] The stride detector contains 32 entries (meaning it can store a maximum of 32 strides accessed by different instructions), and each entry contains an instruction PC (Program Counter). There are four items: stride, confidence, and PC. The PC of the instruction represents the PC address of this instruction. The instruction storing the PC address accessed the memory address last time it was executed; stride is the difference between the instruction being executed this time and the memory address accessed last time; conf represents the confidence level of the stride, i.e., if the currently calculated stride is the same as the stored stride, the value of conf is incremented by 1. When conf reaches a set threshold, it is considered that the vectorization condition has been met, and the instruction needs to be vectorized.

[0065] Taking the following for loop code segment as an example, this code segment stores the value of i into array a, and adds the value in array a to the value in array P, storing the result into array b, where array P is a known array. The code segment is shown below:

[0066] .

[0067] The pseudo-instruction stream converted from the above program segment is shown below. The loop begins at that point, and The loop ends there.

[0068] MOV R1, 0; Initialize i to 0;

[0069] MOV R2, 0; Initialize the address of a;

[0070] MOV R3, P; Initialize the address of P;

[0071] MOV R4, N; This transfers the value of N to R4;

[0072] :

[0073] CMP R1, R4; Compare i and N;

[0074] JGE If i>=N, then jump to ;

[0075] MOV [R2], R1; Store the value of i into a[i];

[0076] MOV R5, [R2]; Load the value of a[i] into R5;

[0077] MOV R6, [R3]; Load the value of P[i] into R6;

[0078] ADD R7, R5, R6; Calculate the sum of a[i] + P[i] and store it in R7;

[0079] MOV [R2+ R7; Store the result in b[i] (assuming...) (where P is the size of each element in the array).

[0080] INC R1; i increments;

[0081] ADD R2, 1; Increment the current address of a by 1, assuming each element is 1 byte;

[0082] ADD R3, ;P's current address plus ;

[0083] ADD R2, b's current address plus (Because a and b are separate);

[0084] JMP loop_start; jump back ;

[0085] ;

[0086] During instruction execution, stride changes are detected in real time using a stride detector, for example... The third instruction in the code, `MOV [R2], R1`, stores the value of `i` in variable `R1` and `R2` is the starting address of array `a`. The value of `i` is stored in array `a`. After stride detection, it is found that the value of `R1` changes by incrementing by one, thus being identified as a regularly changing stride. This instruction is then vectorized to obtain `MOV [V2], V1`, where `V1` and `V2` are vector registers. Similarly, for... The fifth instruction in the code, MOV R6, [R3], shows that the address of variable R3 also exhibits a step-like change pattern, so this instruction also needs to be vectorized.

[0087] In this way, for common operations such as for loops and while loops in the program, the stride detector can detect the repeated occurrence of instructions on the same PC and the stride pattern of the access address, and then enter the instruction pre-execution mode to perform subsequent processing.

[0088] Step S12: If the stride detection result indicates that the target instruction exists, then enter the instruction pre-execution mode and, based on the vectorized execution engine, perform vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction, so as to determine the vectorized instruction.

[0089] In this embodiment, when the stride length is detected to meet specific conditions, the system enters the instruction pre-execution mode and utilizes the vectorized execution engine, that is... Figure 2The vectorizer in the processor performs instruction vectorization, converting scalar instructions that are originally executed sequentially into vector instructions that can process multiple data elements simultaneously. This fully utilizes the processor's vector processing unit and improves the parallelism of data processing. Specifically: in instruction pre-execution mode, the target instruction is vectorized based on the vectorization execution engine and the corresponding stride value to determine the first vectorized instruction; based on the vectorization execution engine and the corresponding stride value, data processing instructions in the data processing instruction stream that have a register dependency on the target instruction and whose execution order is after the target instruction are vectorized to determine the second vectorized instruction.

[0090] It's important to understand that, regarding the implementation of the vectorizer, in this embodiment, the vectorizer's role is to vectorize instructions with regularly changing strides detected by the stride detector, and also vectorize subsequent instructions that have a dependency on the register of that instruction. This allows for the vectorized execution of a large number of subsequent instructions within loops such as for loops. Combined with... Figure 4 As shown, the specific implementation of the instruction vectorization process is as follows:

[0091] Taking the for loop code segment listed in the previous steps as an example, firstly, instructions with regularly changing step sizes are vectorized. For example, in the above code segment, the third instruction MOV [R2], R1 can be vectorized. The value of R1 changes by incrementing by one. Therefore, this instruction is converted into the corresponding vectorized instruction VMOV [V2], V1, and the corresponding vector registers V1 and V2 are allocated. V1 is used as the source register corresponding to the value of R1. V1 can be represented as V1={R1+1, R1+2, R1+3, R1+4}. Similarly, the MOV R6, [R3] instruction in the above code segment can also be vectorized, resulting in the vectorized instruction VMOV [V6], V3, where V3={R3+ R3+2 R3+3 R3+4 }, It is the step size of the address change of array P.

[0092] Secondly, subsequent instructions that depend on the registers of the instruction are also vectorized to ensure that subsequent instructions in the loop can continue to be vectorized and executed. For example, in the above program segment, the third instruction `MOV R5, [R2]`, since `MOV [R2], R1` has already been vectorized to `VMOV [V2], V1`, and the related instruction `MOV R5, [R2]` can also be vectorized, resulting in `VMOV V5, [V2]`. The value of the vector register V2 can be obtained after executing `VMOV [V2], V1`. Therefore, the quantized instruction `VMOV V5, [V2]` can be executed. Similarly, the addition instruction `ADD R7, R5, R6` in the loop segment can still be vectorized, resulting in `VADD V7, V5, V6`. Since the values ​​of registers V5 and V6 have already been obtained through the aforementioned vectorized instructions, `VADD V7, V5, V6` can be executed.

[0093] In this way, not only the target instruction is vectorized, but also the instructions output by the register using the target instruction are vectorized, thereby expanding the scope of vectorization and ensuring that register-related instructions can be executed in a vectorized manner, thus improving the overall execution efficiency.

[0094] Step S13: Based on the vectorized instructions, the first issue queue and the first execution unit, perform instruction pre-execution, and use a preset result storage strategy to save the corresponding instruction pre-execution results to the first physical register file and the result cache.

[0095] In this embodiment, after instruction vectorization is completed and the vectorized instruction is obtained, the vectorized instruction will be executed. However, before execution, renaming and vector register reallocation are required. Specifically: the vectorized instruction is renamed to determine the renamed instruction; based on the first renaming table and the first physical register file, the registers of the renamed instruction are reallocated to determine the register reallocation result; the renamed instruction is stored in the first issue queue; based on the first issue queue, it is checked whether the renamed instruction meets the preset instruction execution conditions to determine the check result; if the check result shows that it meets the conditions, the renamed instruction is sent to the first execution unit based on the first issue queue; based on the first execution unit, the renamed instruction, and the register reallocation result, instruction pre-execution is performed to determine the instruction pre-execution result corresponding to the renamed instruction. That is to say, in this embodiment, firstly, the vectorized instruction is renamed, and then the vector register is reallocated to avoid register conflicts, optimize the order of instruction execution and resource allocation, and improve the processor's execution efficiency. Finally, vector calculation is performed: after completing the above preparations, the vector calculation operation is performed. The vector processing unit of the processor is used to perform calculations on the vectorized data, enabling rapid processing of large amounts of data.

[0096] As we can understand, the issue queue is a buffer in the CPU (Central Processing Unit) used to temporarily store instructions awaiting execution. When an instruction is fetched from the instruction cache and undergoes certain preprocessing, it is placed in the issue queue. The issue queue checks the instruction to determine if it meets the execution conditions, such as whether the required operands are ready. When the execution conditions are met, the instruction is issued from the issue queue to the corresponding execution unit for processing. The rename table (also known as the register rename table, RAT) is used to handle dependencies between instructions. When the processor executes instructions, to avoid conflicts such as register conflicts, it uses the rename table to map the logical registers used in the instructions to physical registers. In this way, the processor can adjust the execution order of instructions without changing the instruction semantics, improving the parallelism of instruction execution. The execution unit (EXU) is the functional module in the processor responsible for executing specific instruction operations.

[0097] It is important to understand that after vectorization, the normal pipeline, i.e. the target pipeline, continues to issue and execute instructions normally. After vectorization, the instructions are issued to the vector execution unit (represented by VEXU, i.e. the first execution unit) through a separate renaming table (represented by VRAT, also known as the first renaming table) and a separate issue queue (represented by Vector IQ, also known as the first issue queue) to complete the operation.

[0098] Furthermore, after obtaining the computation result (i.e., the instruction pre-execution result), since the vectorized instruction is pre-executed, the complete correctness of the result cannot be guaranteed. Therefore, the computation result is saved to a separate physical register file (i.e., the pre-execution physical register file, or Pre-execution PRF (Physical Register File)), instead of being written back to the general physical register file, and certainly not to the cache. Specifically: for any renamed instruction, the instruction pre-execution result corresponding to the current renamed instruction is saved to the first physical register file; it is determined whether the operation type of the current renamed instruction belongs to a preset operation type to determine the type judgment result; the preset operation types include floating-point operations, multiplication operations, and division operations; if the type judgment result indicates that it belongs to the preset operation type, the instruction pre-execution result corresponding to the current renamed instruction is saved to the result cache. In this way, it is prevented that the pre-executed instruction may have speculative errors that affect the normal result.

[0099] Regarding the processing of instruction pre-execution results, this part includes a pre-execution physical register file and a result cache. Since these instructions are executed in advance, the complete correctness of the results cannot be guaranteed. Therefore, the calculation results are saved to a separate pre-execution register file instead of being written back to the normal register file, let alone the cache. However, pre-execution allows the data required for the calculation to be read from memory into the cache, improving the cache hit rate. In addition, this implementation also saves the results of some complex pre-executed calculations to a separate result cache. When the pre-executed instructions are found to be completely correct, the results can be read directly, avoiding duplicate calculations.

[0100] Combination Figure 5 As shown, firstly, after the vectorized instruction to be executed completes its operation, the result is saved to a separate pre-execution physical register file. Simultaneously, the operation type of the instruction is determined. If the instruction type is a complex calculation instruction such as floating-point operation, multiplication, or division, the result is saved to the result buffer. The result buffer contains 8 entries, each storing the result of a complex vector instruction. Assuming the vector instruction is a vectorization of 4 ordinary execution instructions, each entry stores the common PC value of these 4 instructions, the source operands and the result of each instruction, and a V bit. When the result is used, the V bit is set to 0, and a new pre-execution result can be written to this entry.

[0101] In this way, the results stored in the pre-execution register file can be used by subsequent pre-execution instructions. During execution, some operation results are also stored in the result cache. When a normally executed instruction arrives at the execution unit input, this cache is checked. If the source operand, destination operand, and operation instruction are all the same, the calculation result is bypassed directly to the execution unit output, avoiding duplicate operations. The result cache only stores the results of complex instructions such as multiplication, division, and floating-point operations, which often require many cycles to complete. The results of other simple operations (such as addition and subtraction) are not stored, thereby reducing the space occupied by data storage.

[0102] Step S14: When the data processing instruction stream in the target pipeline arrives at the input of the second execution unit, the pre-execution result of the instruction in the result buffer is matched based on the instruction information corresponding to the data processing instruction stream to determine the information matching result; the instruction information includes program counter information, source operands and destination operands.

[0103] In this embodiment, combined with Figure 2As shown, when an instruction in the normal pipeline obtains the values ​​of the source operand and the destination operand, it checks the result buffer according to the PC to match the corresponding operation result. Specifically: for any data processing instruction in the target pipeline that corresponds to the preset database, the instruction information corresponding to the current data processing instruction is obtained; based on the program counter information, source operand, destination operand, and operation type corresponding to the current data processing instruction, the instruction pre-execution result in the result buffer is matched to determine the information matching result.

[0104] Step S15: Based on the information matching results, data processing instruction stream, and the second execution unit, complete the batch data processing operation corresponding to the preset database.

[0105] In this embodiment, it can be understood that when the operation type, source operand, and destination operand of the instruction are completely identical, the operation result in the result buffer is directly bypassed to the output of the second execution unit (represented by EXU). That is, if the information matching result indicates that there is a vectorized instruction in the result buffer that is identical to the current data processing instruction information, the corresponding instruction pre-execution result is bypassed to the output of the second execution unit; if the information matching result indicates that there is no vectorized instruction in the result buffer that is identical to the current data processing instruction information, the current data processing instruction is executed based on the second execution unit.

[0106] This avoids time-consuming and complex calculations, and improves execution efficiency.

[0107] In summary, the solution proposed in this embodiment has the following beneficial effects:

[0108] (1) Dynamic stride detection mechanism: The stride detector monitors in real time whether there are regular changes in stride after decoding the instructions, so as to identify the instructions of the loop program and provide a basis for vectorization processing.

[0109] (2) Vectorization: Using the stride detected by the stride detector, ordinary instructions are vectorized, a vector register is allocated to them, and instructions that have a dependency on the original instruction are also vectorized, thus improving the degree of vectorization. In this way, by vectorizing the instructions of the loop program and executing them in advance, the parallelism of instruction execution is improved.

[0110] (3) By executing the vectorized instructions in advance, the required data is read into the cache in advance, which improves the cache hit rate during normal pipeline execution.

[0111] (4) Saving the results of pre-execution operations: The execution results are saved in a separate pre-execution physical register file, providing data for the execution of subsequent vectorized instructions.

[0112] (5) A result buffer is used to save the results of some complex instructions to be executed before execution, so that the results can be read directly when the normal pipeline instructions are executed, thus avoiding repeated calculations.

[0113] Therefore, in this embodiment of the invention, firstly, after starting the batch data processing corresponding to the preset database, based on the preset detector, it monitors whether there is a target instruction in the data processing instruction stream corresponding to the preset database that belongs to the same program counter, appears repeatedly, and has a regular change in memory access step size, so as to obtain the step size detection result; then, if the step size detection result shows that it exists, it enters the instruction pre-execution mode, and based on the vectorized execution engine, it performs vectorized processing on the target instruction and subsequent instructions in the instruction stream that have a dependency relationship with the register of the target instruction; then, based on the corresponding vectorized instructions, the first issue queue, and the first execution unit, it determines the instruction pre-execution result and saves the instruction pre-execution result to the first physical register file and the result buffer; then, when the data processing instruction stream in the target pipeline reaches the input end of the second execution unit, it matches the instruction pre-execution result in the result buffer based on the instruction information corresponding to the data processing instruction stream, and uses the corresponding information matching result and the second execution unit to complete the batch data processing operation corresponding to the preset database. This approach addresses the problems present in existing solutions, thereby improving the efficiency and accuracy of batch data processing, increasing the parallelism of instruction execution, improving cache hit rate during target pipeline execution, and reducing redundant computations.

[0114] As a preferred embodiment, since the overhead of frequently entering / exiting instruction pre-execution mode may offset the vectorization benefits, an adaptive pre-execution control mechanism can be added to this embodiment. Through this mechanism, when the stride detector detects that there is a target instruction that needs to enter the instruction pre-execution mode, a predictor is used to estimate the performance benefits and overhead of this pre-execution. Then, based on the estimated benefits and overhead, it is compared with the corresponding thresholds. Based on the threshold comparison results and the current processor state, the main decision is made on whether to enter pre-execution and at what intensity to perform instruction pre-execution. After deciding to enter the pre-execution mode, the pre-execution status is monitored so as to actively exit when the benefits are insufficient, thereby maximizing the overall performance.

[0115] See Figure 6 As shown, this embodiment of the invention also discloses a batch data processing device suitable for databases, applied to a processor, comprising:

[0116] The stride detection module 11 is used to monitor, based on a preset detector, whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset stride conditions after starting the batch data processing corresponding to the preset database, so as to obtain the stride detection result; wherein, the preset stride conditions are that they belong to the same program counter, appear repeatedly, and the memory access stride changes regularly.

[0117] The instruction vectorization module 12 is used to enter the instruction pre-execution mode if the stride detection result shows that it exists, and based on the vectorization execution engine, to perform vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction, so as to determine the vectorized instruction.

[0118] The instruction pre-execution module 13 is used to perform instruction pre-execution based on the vectorized instruction, the first issue queue and the first execution unit, and to save the corresponding instruction pre-execution results to the first physical register file and the result cache area using a preset result storage strategy.

[0119] The result cache matching module 14 is used to match the pre-execution results of instructions in the result cache area based on the instruction information corresponding to the data processing instruction stream in the target pipeline when the data processing instruction stream arrives at the input of the second execution unit, so as to determine the information matching result; the instruction information includes program counter information, source operands and destination operands;

[0120] The processing operation completion module 15 is used to complete the batch data processing operation corresponding to the preset database based on the information matching result, the data processing instruction stream and the second execution unit.

[0121] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0122] Furthermore, embodiments of the present invention also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of the invention. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the batch data processing method for databases disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0123] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this invention, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0124] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0125] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the batch data processing method for a database disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0126] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned batch data processing method suitable for databases. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0127] Furthermore, the present invention also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned batch data processing method applicable to databases. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0128] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0129] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0130] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0131] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0132] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A batch data processing method suitable for databases, characterized in that, Applied to processors, including: After starting the batch data processing corresponding to the preset database, based on the preset detector, monitor whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset step size conditions, so as to obtain the step size detection result; wherein, the preset step size conditions are that they belong to the same program counter, appear repeatedly, and the memory access step size changes regularly. If the stride detection result indicates that the target instruction exists, the system enters the instruction pre-execution mode and, based on the vectorized execution engine, performs vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction, in order to determine the vectorized instruction. Based on the vectorized instructions, the first launch queue, and the first execution unit, instruction pre-execution is performed, and the corresponding instruction pre-execution results are saved to the first physical register file and the result cache using a preset result storage strategy. When the data processing instruction stream in the target pipeline reaches the input of the second execution unit, the pre-execution result of the instruction in the result buffer is matched based on the instruction information corresponding to the data processing instruction stream to determine the information matching result; the instruction information includes program counter information, source operands, and destination operands; Based on the information matching results, the data processing instruction stream, and the second execution unit, the batch data processing operation corresponding to the preset database is completed.

2. The batch data processing method for databases according to claim 1, characterized in that, The step of monitoring whether there are target instructions that meet preset stride conditions in the data processing instruction stream corresponding to the preset database in the target pipeline based on a preset detector, in order to obtain stride detection results, includes: Based on the stride information corresponding to each data processing instruction in the preset detector and the data processing instruction stream, stride changes are monitored to determine the monitoring results; the stride information includes the instruction address, stride value, and stride confidence level in the program counter. Based on the preset detector and the monitoring results, it is determined whether there is a target instruction in the data processing instruction stream that meets the preset stride conditions, so as to obtain the stride detection result.

3. The batch data processing method for databases according to claim 2, characterized in that, The vectorized execution engine performs vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have register dependencies on the target instruction, in order to determine the vectorized instruction, including: In instruction pre-execution mode, the target instruction is vectorized based on the vectorized execution engine and the corresponding step value to determine the first vectorized instruction; Based on the vectorized execution engine and the corresponding step value, the data processing instructions in the data processing instruction stream that have a register dependency relationship with the target instruction and whose execution order is after the target instruction are vectorized to determine the second vectorized instruction.

4. The batch data processing method for databases according to claim 1, characterized in that, The instruction pre-execution based on the vectorized instructions, the first launch queue, and the first execution unit includes: The vectorized instructions are renamed to determine the renamed instructions; Based on the first renaming table and the first physical register file, the renamed instructions are reassigned to determine the register reassignment result. The renamed instruction is stored in the first launch queue; Based on the first transmission queue, check whether the renamed instruction meets the preset instruction execution conditions to determine the check result; If the check result is satisfactory, then the renamed instruction is sent to the first execution unit based on the first transmission queue; Based on the first execution unit, the renamed instruction, and the register reallocation result, instruction pre-execution is performed to determine the instruction pre-execution result corresponding to the renamed instruction.

5. The batch data processing method for databases according to claim 4, characterized in that, The step of using a preset result storage strategy to save the corresponding instruction pre-execution results to the first physical register file and the result cache includes: For any of the renamed instructions, the instruction pre-execution result corresponding to the current renamed instruction is saved to the first physical register file; Determine whether the operation type of the currently renamed instruction belongs to a preset operation type to determine the type determination result; the preset operation types include floating-point operations, multiplication operations, and division operations; If the type determination result indicates that it belongs to the category, then the pre-execution result of the instruction corresponding to the currently renamed instruction is saved to the result cache area.

6. The batch data processing method for databases according to any one of claims 1 to 5, characterized in that, The step of matching the instruction pre-execution results in the result cache with the instruction information corresponding to the data processing instruction stream to determine the information matching result includes: For any data processing instruction in the target pipeline that corresponds to the preset database, obtain the instruction information corresponding to the current data processing instruction; Based on the program counter information, source operands, destination operands, and operation type corresponding to the current data processing instruction, the instruction pre-execution result in the result buffer is matched to determine the information matching result.

7. The batch data processing method for databases according to claim 6, characterized in that, The step of completing the batch data processing operation corresponding to the preset database based on the information matching result, the data processing instruction stream, and the second execution unit includes: If the information matching result indicates that there is a vectorized instruction in the result cache that is identical to the current data processing instruction information, then the corresponding instruction pre-execution result is bypassed to the output of the second execution unit; If the information matching result indicates that there is no vectorized instruction in the result cache that is identical to the current data processing instruction information, then the current data processing instruction is executed based on the second execution unit.

8. A batch data processing device suitable for databases, characterized in that, Applied to processors, including: The stride detection module is used to monitor, based on a preset detector, whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset stride conditions after the batch data processing corresponding to the preset database is started, so as to obtain the stride detection result; wherein, the preset stride conditions are that they belong to the same program counter, appear repeatedly, and the memory access stride changes regularly. The instruction vectorization module is used to enter the instruction pre-execution mode if the stride detection result indicates that the target instruction exists, and to perform vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction based on the vectorization execution engine, so as to determine the vectorized instruction. The instruction pre-execution module is used to perform instruction pre-execution based on the vectorized instruction, the first issue queue and the first execution unit, and to save the corresponding instruction pre-execution results to the first physical register file and the result cache area using a preset result storage strategy. The result cache matching module is used to match the pre-execution results of the instructions in the result cache area based on the instruction information corresponding to the data processing instruction stream in the target pipeline when the data processing instruction stream arrives at the input of the second execution unit, so as to determine the information matching result; the instruction information includes program counter information, source operands and destination operands; The processing operation completion module is used to complete the batch data processing operation corresponding to the preset database based on the information matching result, the data processing instruction stream, and the second execution unit.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the batch data processing method for a database as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the batch data processing method for a database as described in any one of claims 1 to 7.

Images