Embedded controller, control method thereof, chip and electronic equipment
By designing the first and second processing units to work together in the embedded controller, localized AI inference is achieved, solving the problem that traditional embedded controllers cannot efficiently execute core AI calculations, improving response speed and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI CHIPSEA ELECTRONICS TECH CO LTD
- Filing Date
- 2025-12-22
- Publication Date
- 2026-04-10
AI Technical Summary
Traditional embedded controllers cannot efficiently execute core AI calculations, leading to increased host load and higher response latency, thus failing to meet real-time requirements.
The architecture adopts an embedded controller, including a first processing unit and a second processing unit. They are connected by a bus and start up the second processing unit by triggering data transfer through an interrupt, thereby realizing localized AI inference and reducing dependence on host computing power.
It improves AI inference efficiency, reduces latency and power consumption, and enhances response speed and overall system performance.
Smart Images
Figure CN121833561A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, specifically to an embedded controller and its control method, chip, and electronic device. Background Technology
[0002] With the rapid development of artificial intelligence (AI) technology and edge computing, the demand for local intelligent control in electronic devices (such as laptops and PCs) is increasing. Traditional embedded controllers (ECs) are mainly used to manage low-speed devices on the computer motherboard (such as keyboards, mice, and fans), power management (such as power-on and power-off), low power consumption, and battery management. However, they typically use a single CPU core architecture, which can only handle simple logic and low-speed peripheral control, and cannot efficiently perform core AI operations such as convolution and matrix multiplication and addition. As AI functions are pushed to the edge (such as local facial recognition unlocking and user presence detection), traditional ECs need to rely on the computing power of the host (such as Intel / AMD processors), leading to increased host load and higher response latency. Due to the lack of dedicated AI acceleration units and optimized data flow control, inference efficiency is low and cannot meet real-time requirements. Summary of the Invention
[0003] In view of the above problems, embodiments of this application provide an embedded controller and its control method, chip and electronic device to solve the above technical problems.
[0004] In a first aspect, embodiments of this application provide a control method for an embedded controller, the embedded controller including a first processing unit and a second processing unit connected via a bus, and a first communication interface connected to the bus; the control method includes: When the first processing unit receives the first interrupt request sent by the first communication interface, the first processing unit responds to the first interrupt request, reads input data from the first communication interface, loads the input data into the pre-configured first storage area, and sends a start command to the second processing unit; When the second processing unit receives the start command, it reads the input data from the first storage area and calls the preloaded AI model parameters to perform inference on the input data, writes the inference result into the pre-configured second storage area, and sends a second interrupt request to the first processing unit.
[0005] This embodiment enables localized AI inference in an embedded controller without relying on host computing power, thus improving inference efficiency. By triggering data transfer and the startup of the second processing unit through interrupts, it avoids the delay of polling detection and improves response speed.
[0006] Secondly, embodiments of this application also provide an embedded controller for executing a control method including the embedded controller.
[0007] Thirdly, embodiments of this application also provide a chip including the aforementioned embedded controller.
[0008] Fourthly, embodiments of this application also provide an electronic device, including a device body and the chip disposed on the device body.
[0009] The embedded controller control method provided in this application includes: when the first processing unit receives a first interrupt request sent by the first communication interface, the first processing unit responds to the first interrupt request, reads input data from the first communication interface, loads the input data into a pre-configured first storage area, and sends a start command to the second processing unit; when the second processing unit receives the start command, it reads the input data from the first storage area and calls pre-loaded AI model parameters to perform inference on the input data, writes the inference result into a pre-configured second storage area, and sends a second interrupt request to the first processing unit. This method enables localized AI inference in the embedded controller without relying on host computing power, improving inference efficiency. By triggering data transfer and the start of the second processing unit through interrupt, the delay of polling detection is avoided, improving response speed.
[0010] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 A schematic diagram of the architecture of an embedded controller provided in an embodiment of this application is shown.
[0013] Figure 2 A schematic diagram of the architecture of an embedded controller provided in another embodiment of this application is shown.
[0014] Figure 3 A schematic diagram of the architecture of an embedded controller provided in another embodiment of this application is shown.
[0015] Figure 4 A schematic diagram of the architecture of an embedded controller provided in another embodiment of this application is shown.
[0016] Figure 5 A schematic diagram of the architecture of an embedded controller provided in another embodiment of this application is shown.
[0017] Figure 6 A schematic diagram of the architecture of an encryption unit provided in an embodiment of this application is shown.
[0018] Figure 7 A schematic diagram of the architecture of an embedded controller provided in another embodiment of this application is shown.
[0019] Figure 8 A flowchart illustrating a control method for an embedded controller according to an embodiment of this application is shown.
[0020] Figure 9 A flowchart illustrating a control method for an embedded controller according to another embodiment of this application is shown.
[0021] Figure 10 A flowchart illustrating a control method for an embedded controller according to another embodiment of this application is shown.
[0022] Figure 11 A flowchart illustrating a control method for an embedded controller according to another embodiment of this application is shown. Detailed Implementation
[0023] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0024] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0025] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0026] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0027] In the description of the embodiments in this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0028] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0029] Modern smart electronic devices (such as laptops and computers) and smart home devices (such as smart door locks and smart cameras) widely adopt biometric technologies such as facial recognition and fingerprint recognition to replace traditional passwords, thereby improving convenience and security. However, in traditional solutions, AI inference relies on the host (such as Intel / AMD processors) or a separate AI chip, which has problems such as high power consumption (such as shortened battery life due to the host running at full load), high latency (such as data needing to be processed back and forth to the host), and security risks (such as the vulnerability of biometric data to theft when transmitted in plaintext).
[0030] The embedded controllers, control methods, chips, and electronic devices provided in this application are geared towards embedded intelligent device scenarios that require "real-time AI inference + high security assurance + ultra-low power consumption operation," and are particularly suitable for scenarios in consumer electronics, IoT terminals, industrial control, and other fields that require localized intelligent processing and data security, such as smart meters, monitoring and measurement, battery power management, and smart homes.
[0031] like Figure 1 As shown, Figure 1An embedded controller 100 provided in an embodiment of this application is schematically illustrated. The embedded controller 100 includes a first processing unit 20 and a second processing unit 30 connected via a bus 10, and a first communication interface 40 connected to the bus 10. The first processing unit 20 is used to execute startup code, manage system power-on / power-off, low-power mode switching, battery management, and peripheral interface management, such as a CPU (Central Processing Unit). The second processing unit 30 integrates AI acceleration functions, supporting at least one of convolution, fast Fourier transform, matrix multiplication-accumulation, and SoftMax activation functions, such as an NPU (Neural Processing Unit). The first communication interface 40 is used to receive input data from sensors (such as cameras, fingerprint sensors, ambient light sensors, proximity sensors, etc.), and can be an interface such as USB or I2C. The bus 10 can be an AHB bus (Advanced High-performance Bus), and the units are directly connected via the bus 10, reducing data transmission latency and improving the overall system response speed.
[0032] In this embodiment, the first processing unit 20 and the second processing unit 30 can work together to implement local AI inference in the embedded controller 100, such as face recognition, liveness detection, user behavior analysis, industrial inspection, etc., without relying on the computing power of the host, reducing the computing burden of the host and the first processing unit 20, and reducing latency and power consumption.
[0033] In the architecture of the embedded controller 100, the connection of the sensor module 200 can be implemented in two ways. For one feasible implementation, please refer to... Figure 2 The sensor module 200 (including the sensor body and image signal processor) is directly integrated into the embedded controller 100, forming an on-chip sensor subsystem. In this solution, the analog front-end, digital signal acquisition, and preprocessing (such as noise reduction, white balance, and color correction) of the sensor module 200 are all completed within the embedded controller 100, which improves the integration of the embedded controller 100 and reduces data transmission latency. For another feasible implementation, please refer to... Figure 3 The sensor module 200 is placed externally to the embedded controller 100 and connected to the embedded controller 100 via the first communication interface 40. In this solution, placing the sensor module 200 externally reduces the area of the embedded controller 100, and different applications can use different external sensors according to scenario requirements, increasing flexibility. The embodiments of this application are not limited to these two integration methods; it can be either external or embedded.
[0034] For example, in an environmental monitoring application scenario, a camera is connected to the first communication interface 40. The first processing unit 20 reads the image captured by the camera through the first communication interface 40, loads the image into a pre-configured first storage area, and sends a start command to the second processing unit 30. When the second processing unit 30 receives the start command, it reads the image from the first storage area, calls the pre-loaded AI model parameters to perform inference on the image, writes the inference result into the pre-configured second storage area, and sends an interrupt request to the first processing unit 20. When the first processing unit 20 receives the interrupt request, it responds to the interrupt request, reads the inference result from the second storage area, and performs corresponding operations based on the inference result. Taking face recognition as an example, if face recognition is successful, the first processing unit 20 notifies the external main processor, grants permissions to the program running on the external main processor, and continues to the next step.
[0035] As one example, please refer to Figure 4 The embedded controller 100 also includes a storage unit 50 connected to the bus 10. The storage unit 50 includes a non-volatile memory module 51 (such as NVM) and a volatile memory module 52 (such as SRAM). The non-volatile memory module 51 is used to store firmware (such as boot code and control programs), AI models (such as face recognition models and liveness detection models), post-quantum encryption algorithm libraries, and key configuration parameters (such as low-power mode thresholds); it supports data retention after power failure, ensuring that the system can be restored to the latest state after a restart. The volatile memory module 52 is used to store the operating data and intermediate results of the first processing unit 20 and the second processing unit 30, such as raw sensor data, intermediate feature maps inferred by the second processing unit 30, and post-quantum encryption temporary variables; it supports low-latency access and meets real-time requirements.
[0036] In a scenario where the first processing unit 20 and the second processing unit 30 interact, after the embedded controller 100 is powered on for the first time, the first processing unit 20 loads startup code from the storage unit 50 and configures the second processing unit 30, the first communication interface 40, and the storage unit 50. Configuring the second processing unit 30 includes configuring the computing unit and loading the AI model into the volatile storage module 52. Configuring the first communication interface 40 includes binding the interface address and configuring the sampling rate. Configuring the storage unit 50 includes dividing the storage unit into a first storage area and a second storage area. The first storage area stores the raw data from the sensors, and the second storage area stores the inference results from the second processing unit 30.
[0037] As one example, please refer to Figure 5The embedded controller 100 also includes an encryption unit 60 and a second communication interface 70, both connected to the bus 10. The second communication interface 70 is used to connect to an external main processor and may include an eSPI interface, a local bus, and peripheral interfaces (mouse, keyboard, UART module, etc.). The first processing unit 20 communicates with the external main processor through the second communication interface 70. The encryption unit 60 provides hardware acceleration through post-quantum cryptography operations (such as polynomial multiplication in lattice-based encryption and compression operations of hash functions), which can be used to perform post-quantum encryption / decryption on sensitive data (such as AI model parameters and raw sensor data), resist quantum computing attacks, ensure data transmission and storage security, and solve the security risks of traditional embedded controllers 100 relying on RSA / ECC.
[0038] Please see Figure 6 The encryption unit 60 includes a computing module 61 for encryption / decryption using post-quantum cryptography, a first sub-interface 62 for reading input data (such as data to be encrypted and data to be decrypted) and writing computation results (such as encryption results and decryption results), a second sub-interface 63 for automatically transferring data from the bus, and an interrupt control module 64 for triggering an interrupt after computation. For example, the first sub-interface 62 is a RAM interface, and the second sub-interface 63 is a DMA interface. In the interaction scenario between the encryption unit 60 and the external main controller, the external main processor constructs a command structure according to the post-quantum encryption algorithm to be executed. The command structure includes the algorithm type, configuration parameters, input data address, output data address, and checksum; the external main processor writes the command structure to a specified address on the bus 10. When the first processing unit 20 receives an encryption request from the second communication interface 70, the computing module 61 reads and parses the pre-stored command structure through the DMA interface to obtain the encryption algorithm type, configuration parameters, input data address, and output data address. Based on the input data address, it reads the data to be encrypted from the storage unit 50 through the RAM interface and performs calculations on the data to be encrypted according to the encryption algorithm type to obtain ciphertext. Based on the output data address, it writes the ciphertext into the storage unit 50 through the RAM interface. An interrupt is triggered by the interrupt control module 64. After responding to the interrupt, the first processing unit 20 reads the ciphertext and feeds it back to the external main processor. In this embodiment, the interaction protocol between the external main processor and the encryption unit 60 is standardized through the command structure, allowing support for new post-quantum encryption algorithms without hardware modifications, thus improving architectural scalability. The automatic transfer of task data through the DMA interface reduces the intervention of the first processing unit 20, freeing up memory resources for other tasks and improving data processing efficiency.
[0039] As one example, please refer to Figure 7The embedded controller 100 also includes a wake-up unit 80 connected to the bus 10. The wake-up unit 80 is powered on and used to monitor wake-up signals from buttons and sensors. The wake-up unit 80 includes a power-on / wake-up monitor. This wake-up unit 80 has few functions, simple logic, and low power consumption. Whether the embedded controller 100 is in a power-off state, standby state, or running state, the wake-up unit 80 continues to operate normally, ensuring that it can quickly wake up the embedded controller 100 when detecting external input (buttons or sensors) in low-power mode, thus solving the problem that the embedded controller 100 cannot be intelligently woken up when completely powered off.
[0040] For example, in a low-power scenario where the laptop or computer is powered off, the external main processor is completely powered off, and only the wake-up unit 80 is powered on. The wake-up unit 80 continuously monitors the power button. When it detects that the power button has been pressed for more than 3 seconds, it triggers the embedded controller 100 to power on and starts the power-on sequence, such as turning on the power of the first processing unit 20, the storage unit 50, the first communication interface 40, and the second communication interface 70.
[0041] For example, in a low-power scenario where a laptop or computer is in standby mode, the external main processor is completely powered off, and the embedded controller 100 enters a low-power mode (only the wake-up unit 80 runs, the first processing unit 20 is in sleep mode, the second processing unit 30 is powered off, and the storage unit 50 retains some key data). When the wake-up unit 80 detects key or sensor input, it wakes up the first processing unit 20. The first processing unit 20 identifies the sensor input data (such as fingerprint images, facial features, etc.) and triggers the second processing unit 30 to perform AI inference. After correct identification, it sends a wake-up command through the second communication interface 70 to wake up the external main processor.
[0042] For example, in a low-power scenario where the laptop or computer is running, both the external main processor and the embedded controller 100 are running, but the second processing unit 30 is in a low-power mode. The embedded controller 100 periodically collects input data from the sensors through the first communication interface 40. For example, when it detects that the operator has left or the line of sight has shifted, it assumes that the computer is not working and the system enters a low-power state (e.g., the screen is turned off). Or, when it detects that someone is behind the operator, it turns off the screen to prevent leakage. Or, when the input data requires AI inference, the first processing unit 20 wakes up the second processing unit 30, and the second processing unit 30 returns to a low-power state after completing the inference.
[0043] Please see Figure 8 This application also provides a control method for an embedded controller, applied to the aforementioned embedded controller architecture. In the interaction scenario between the first processing unit 20 and the second processing unit 30, the control method includes: Step S10: When the first processing unit receives the first interrupt request sent by the first communication interface, the first processing unit responds to the first interrupt request, reads the input data from the first communication interface, loads the input data into the pre-configured first storage area, and sends a start command to the second processing unit.
[0044] In this step, the first communication interface is used to receive input data from the sensor. This interface can be a USB, I2C, or similar interface. The sensor includes, but is not limited to, a camera, fingerprint sensor, ambient light sensor, and proximity sensor. Input data includes fingerprint images, facial features, and ambient brightness values. The first processing unit can be a CPU, and the second processing unit can be an NPU.
[0045] After the embedded controller is powered on for the first time, the first processing unit loads the startup code from the storage unit and configures the storage unit, dividing the storage unit into a first storage area and a second storage area. The first storage area is used to store the raw data of the sensor, and the second storage area is used to store the inference results of the second processing unit.
[0046] In this step, after the sensor collects valid data, it sends a first interrupt request to the first processing unit through the first communication interface, causing the first processing unit to pause its current task and prioritize processing the event corresponding to the interrupt request. This avoids the delay of polling detection and improves the response speed.
[0047] Step S20: When the second processing unit receives the start command, it reads the input data from the first storage area and calls the preloaded AI model parameters to perform inference on the input data, writes the inference result into the pre-configured second storage area and sends a second interrupt request to the first processing unit.
[0048] In this step, the second processing unit supports at least one of convolution, fast Fourier transform, matrix multiplication and addition, and SoftMax activation function.
[0049] This embodiment enables localized AI inference in the embedded controller through the collaborative interaction of the first processing unit and the second processing unit. It does not rely on the computing power of the host, reducing the computational burden on the host and the first processing unit, and lowering latency and power consumption.
[0050] As one example, please refer to Figure 9 The control method also includes: Step S30: When the first processing unit receives the second interrupt request, the first processing unit responds to the second interrupt request, reads the inference result from the second storage area, and performs corresponding operations based on the inference result.
[0051] In this step, after the second processing unit completes the AI inference calculation, it sends a second interrupt request to the first processing unit through the interrupt controller. The first processing unit responds to the second interrupt request, reads the inference result, and performs subsequent operations, such as comparing with a face database: calling the face feature database stored in NVM and calculating similarity through Euclidean distance, etc.
[0052] As one example, please refer to Figure 10 In applications involving encrypted data, this control method also includes: Step S40: When the first processing unit receives an encryption request sent by the first communication interface and / or the second communication interface, it parses the encryption request and obtains the data to be encrypted, the encryption algorithm type, and the encryption configuration parameters based on the parsing result.
[0053] In this step, the first communication interface is connected to the sensor. When the input data of the first communication interface needs to be encrypted, an encryption request can be sent to the first processing unit. The second communication interface is connected to an external main processor and can forward encryption requests sent by the external main processor. The second communication interface includes, but is not limited to, an eSPI interface, a local bus, and peripheral interfaces. The encryption request carries the address information of the data to be encrypted, the encryption algorithm type, and encryption configuration parameters.
[0054] Step S50: Call the encryption unit to encrypt the data to be encrypted using the encryption algorithm type and encryption configuration parameters.
[0055] Step S60: Store the encryption result in a pre-configured storage unit and / or off-chip memory.
[0056] In this step, the storage unit can be embedded in the memory inside the controller, and the off-chip memory can be embedded in the memory outside the controller.
[0057] As one embodiment, after encrypting the data to be encrypted, the encryption unit sends a third interrupt request to the first processing unit. When the first processing unit receives the third interrupt request, it returns the encryption result to the first communication interface and / or the second communication interface.
[0058] This embodiment uses a cryptographic unit to perform post-quantum encryption on sensitive data (such as AI model parameters and raw sensor data), which can resist quantum computing attacks and ensure the security of data transmission and storage.
[0059] As one example, please refer to Figure 11 In applications involving data decryption, this control method also includes: Step S70: When the first processing unit receives a decryption request sent by the first communication interface and / or the second communication interface, it parses the decryption request and obtains the data to be decrypted, the decryption algorithm type, and the decryption configuration parameters based on the parsing result.
[0060] In this step, the first communication interface is connected to the sensor. When the input data of the first communication interface needs to be decrypted, a decryption request can be sent to the first processing unit. The second communication interface is connected to the external main processor and can forward the decryption requests sent by the external main processor. The decryption request carries the address information of the data to be decrypted, the decryption algorithm type, and decryption configuration parameters.
[0061] Step S80: Call the encryption unit to decrypt the data to be decrypted using the decryption algorithm type and decryption configuration parameters.
[0062] Step S90: Store the decryption result in a pre-configured storage unit and / or off-chip memory.
[0063] In this step, the storage unit can be embedded within the controller's internal memory, while the off-chip memory can be embedded outside the controller's memory. As one embodiment, after decrypting the data to be decrypted, the encryption unit sends a third interrupt request to the first processing unit. When the first processing unit receives the third interrupt request, it returns the decryption result to the first communication interface and / or the second communication interface.
[0064] As one embodiment, in a low-power mode switching scenario, the control method further includes: when the first processing unit receives a control command for controlling the device state, acquiring the device state and adjusting the power supply state of the second processing unit, storage unit, encryption unit, wake-up unit, first communication interface, and second communication interface according to the device state.
[0065] In this step, the device states include power-off, standby, and running states. In the power-off state, the wake-up unit remains powered, while the second processing unit, encryption unit, storage unit, and second communication interface are powered off. In the standby state, the wake-up unit remains powered, the first processing unit is in hibernation mode, the second processing unit is powered off, the encryption unit is powered off, the storage unit retains some critical data, and the second communication interface is powered off. In the running state, the wake-up unit, second processing unit, encryption unit, storage unit, and second communication interface are all powered, but the second processing unit is in a low-power mode. The embedded controller periodically collects sensor input data through the first communication interface. For example, when it detects that the operator has left or their gaze has shifted, it assumes the computer is not working, and the system enters low-power mode (e.g., the screen is turned off); or, when it detects someone behind the operator, it turns off the screen to prevent data leakage; or, when the input data requires AI inference, the first processing unit wakes up the second processing unit, and the second processing unit returns to the low-power state after completing the inference.
[0066] This embodiment enables low-power management across all scenarios—power off, standby, and running—in an embedded controller, improving the overall battery life of the device. It integrates AI computing, security encryption, and low-power management modules into a single embedded controller, enhancing the intelligence of the embedded controller and the user experience.
[0067] This application also provides a chip that includes the aforementioned embedded controller. The chip (Integrated Circuit, IC) can be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. This chip, through the collaborative interaction of a first processing unit and a second processing unit, enables localized AI inference within the embedded controller, eliminating reliance on host computing power, reducing the computational burden on the host and the first processing unit, and lowering latency and power consumption. Furthermore, by triggering data transfer and the startup of the second processing unit via interrupts, the latency of polling detection is avoided, improving response speed.
[0068] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, car central control screen, car, smart wearable device, mobile terminal, or smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart door locks and smart cameras. This electronic device, through collaborative interaction between a first processing unit and a second processing unit, can achieve localized AI inference in an embedded controller, without relying on HOST computing power, reducing the computational burden on the HOST and the first processing unit, and lowering latency and power consumption; by triggering data transfer and the start of the second processing unit through interrupts, it avoids the latency of polling detection and improves response speed.
[0069] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A control method of an embedded controller, characterized by, The embedded controller comprises a first processing unit and a second processing unit connected through a bus, a first communication interface connected with the bus; The control method comprises: When the first processing unit receives a first interrupt request sent by the first communication interface, the first processing unit reads input data from the first communication interface in response to the first interrupt request, loads the input data into a pre-configured first storage area, and sends a start instruction to the second processing unit; When the second processing unit receives the start instruction, the input data is read from the first storage area, and a pre-loaded AI model parameter is called to perform inference on the input data, the inference result is written into a pre-configured second storage area, and a second interrupt request is sent to the first processing unit.
2. The control method of the embedded controller according to claim 1, wherein, The control method of the embedded controller further comprises: When the first processing unit receives the second interrupt request, the first processing unit reads the inference result from the second storage area and performs corresponding operations according to the inference result in response to the second interrupt request.
3. The control method of the embedded controller according to claim 1, wherein, The embedded controller further comprises a storage unit connected with the bus, and the control method of the embedded controller further comprises: After the embedded controller is powered on for the first time, the first processing unit loads a start code from the storage unit and configures the second processing unit, the first communication interface, and the storage unit.
4. The control method of the embedded controller according to claim 3, characterized by, Comprise: The embedded controller further comprises an encryption unit and a second communication interface connected with the bus respectively, and the control method of the embedded controller further comprises: When the first processing unit receives an encryption request sent by the first communication interface and / or the second communication interface, the encryption request is parsed, and the to-be-encrypted data, the encryption algorithm type, and the encryption configuration parameter are obtained according to the parsing result; The encryption unit is called to encrypt the to-be-encrypted data by using the encryption algorithm type and the encryption configuration parameter; The encryption result is stored in a pre-configured storage unit and / or an off-chip memory.
5. The control method of the embedded controller according to claim 4, wherein The control method of the embedded controller further comprises: When the first processing unit receives a decryption request sent by the first communication interface and / or the second communication interface, the decryption request is parsed, and the to-be-decrypted data, the decryption algorithm type, and the decryption configuration parameter are obtained according to the parsing result; The encryption unit is called to encrypt the to-be-encrypted data by using the encryption algorithm type and the encryption configuration parameter; The decryption result is stored in a pre-configured storage unit and / or an off-chip memory.
6. The control method of the embedded controller according to claim 5, wherein The encryption unit comprises a first sub-interface for reading the to-be-encrypted data or the to-be-decrypted data and feeding back the encryption result or the decryption result, a second sub-interface for automatically transferring data from the bus, a calculation module for encryption / decryption by using post-quantum cryptography, and an interrupt control module for triggering an interrupt after calculation.
7. The control method of the embedded controller according to claim 6, wherein The embedded controller comprises a wake-up unit connected with the bus, and the control method of the embedded controller further comprises: When the first processing unit receives a control instruction for controlling a device state, the device state is acquired and the power supply state of the second processing unit, the storage unit, the encryption unit, the wake-up unit, the first communication interface, and the second communication interface is adjusted according to the device state.
8. An embedded controller, characterized by A control method for executing the embedded controller according to any one of claims 1 to 7.
9. A chip, characterized by An embedded controller according to claim 8.
10. An electronic device, comprising: A chip according to claim 9, which is provided in a device main body. A chip according to claim 9, which is provided in a device main body.