Flow control method and device based on AXI bus, medium and product

Abstract

The invention discloses a flow control method and device based on an AXI bus, a medium and a product, and the method comprises the steps: obtaining a first credit value needed by the calculation of a matched first data volume before a write address and write data are continuously sent to a first opposite-end chip in a multi-chip system; and querying a locally maintained target write operation counter matched with the first opposite-end chip, judging whether the current credit value is greater than or equal to the first credit value, if so, updating and storing a calculation result obtained by subtracting the first credit value from the current credit value in the target write operation counter, and continuously sending the write address and the write data to the first opposite-end chip. Whenever target write response information fed back by the first opposite-end chip is received, a first release credit value is obtained, and a result obtained by adding the current credit value and the first release credit value is updated and stored in the target write operation counter. According to the technical scheme, a special signaling packet can be avoided, the protocol overhead is reduced, and the link utilization rate and the system throughput are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and in particular to a flow control method, device, medium and product based on the AXI bus. Background Technology

[0002] With the increasing complexity of chip functions and the development of heterogeneous integration technology, multi-chip systems have become a core path to improve computing power and integration. In such systems, chips need to complete large-scale data exchange through high-speed interconnects. As the de facto standard high-performance bus protocol within on-chip systems, the need for inter-chip expansion of the AXI (Advanced Scalable Interface) bus is becoming increasingly urgent.

[0003] Existing technologies mainly include the following solutions: First, a flow control mechanism based on the standard IEEE 802.3X flow control (Pause) frame, which sends a Pause frame to the sender to request a pause in data transmission when the receiver's buffer is about to be full; second, priority flow control as an enhanced version of the Pause frame, which can perform pause and resume operations for eight different priority queues; third, a simple packet acknowledgment and retransmission mechanism, which requires the sender to receive an acknowledgment (ACK) from the receiver for a single data packet or a data packet within a window before continuing to send, and triggers a retransmission process if no ACK is received within a timeout; fourth, a flow control scheme based on a custom credit request and credit reply packet format, where the sender initiates a credit request, the remote device responds, and the local end compares the changes in the credit value to determine whether to resend the credit request or update the local credit value.

[0004] The existing technologies mentioned above still have some shortcomings. First, the flow control granularity does not match the protocol requirements. Ethernet flow control mechanisms can only achieve coarse-grained flow control for links or queues, and cannot accurately map the channel-level independent fine-grained backpressure semantics required by the AXI protocol. Second, there is a serious performance loss. Global pause and waiting for confirmation introduce huge performance overhead, making it difficult to fully utilize the physical bandwidth of Ethernet links, resulting in an effective throughput of interconnection that is far lower than the theoretical value. Third, true lossless transmission cannot be achieved. Coarse-grained flow control is prone to instantaneous buffer overflow, and the retransmission mechanism is a "post-hoc remedy" rather than a "pre-emptive prevention." Both will cause packet loss or a decrease in transmission reliability, which does not meet the basic requirements of the AXI protocol for reliable transmission. Fourth, resource utilization is low. To avoid packet loss, a large-capacity receive buffer needs to be configured to absorb transmission delay, which significantly increases the chip area and cost. Summary of the Invention

[0005] This invention provides a flow control method, device, medium, and product based on the AXI bus to solve the problem of data packet loss caused by buffer overflow at the receiving end when the AXI protocol is encapsulated on Ethernet for transmission during inter-chip interconnection of integrated circuits.

[0006] According to one aspect of the present invention, a flow control method based on an AXI bus is provided, executed by a target chip in a multi-chip system networked via an AXI bus, the method comprising:

[0007] Before continuously sending write address and write data to the first peer chip in the multi-chip system, a first data volume matching the write address and write data is obtained, and a first credit value required for the first data volume is calculated.

[0008] Query the target write operation counter that matches the first peer chip maintained locally, and determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0009] The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip. The first memory is used by the first peer chip to temporarily store the write data obtained from the target chip.

[0010] If so, after updating the calculation result of storing the current credit value minus the first credit value in the target write operation counter, the write address and write data are continuously sent to the first peer chip.

[0011] Whenever the target write response information describing the first memory release status is received from the first peer chip, the first release credit value corresponding to the target write response information is obtained, and the calculation result of the current credit value plus the first release credit value is updated in the target write operation counter.

[0012] According to another aspect of the present invention, a flow control device based on an AXI bus is provided, which can be installed in a target chip in a multi-chip system networked via an AXI bus. The device includes:

[0013] The write operation credit value acquisition module is used to acquire a first data volume that matches the write address and write data before continuously sending the write address and write data to the first peer chip in the multi-chip system, and to calculate the first credit value required for the first data volume.

[0014] The write operation credit value calculation module is used to query the target write operation counter that matches the first peer chip maintained locally, and determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0015] The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip. The first memory is used by the first peer chip to temporarily store the write data obtained from the target chip.

[0016] If so, after updating the calculation result of storing the current credit value minus the first credit value in the target write operation counter, the write address and write data are continuously sent to the first peer chip.

[0017] The write operation credit value update module is used to obtain the first release credit value corresponding to the target write response information whenever it receives the target write response information from the first peer chip, which describes the first memory release status, and update the target write operation counter with the calculation result of the current credit value plus the first release credit value.

[0018] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0019] At least one processor; and

[0020] A memory communicatively connected to the at least one processor; wherein,

[0021] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the flow control method based on the AXI bus as described in any embodiment of the present invention.

[0022] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the flow control method based on the AXI bus as described in any embodiment of the present invention.

[0023] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the method as described in any embodiment of the present invention.

[0024] The technical solution of this invention enables execution by a target chip in a multi-chip system networked via an AXI bus. Before continuously sending write addresses and write data to the first peer chip in the multi-chip system, a first data volume matching the write address and write data is obtained, and a first credit value required for the first data volume is calculated. A locally maintained target write operation counter matching the first peer chip is queried to determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value. The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip, which is used by the first peer chip to temporarily store the first data volume obtained from the target chip. If so, the calculation result of subtracting the first credit value from the current credit value is updated in the target write operation counter, and then write addresses and write data are continuously sent to the first peer chip. Whenever a target write response information describing the release status of the first memory is received from the first peer chip, a first release credit value corresponding to the target write response information is obtained, and the calculation result of adding the first release credit value to the current credit value is updated in the target write operation counter. The above technical solution, by designing differentiated and independent flow control for the five channels of the AXI protocol, establishes a credit value mechanism for data transmission in dedicated channels, accurately simulates the native handshake behavior of the AXI protocol, avoids the use of dedicated signaling packets, reduces protocol overhead, and greatly improves link utilization and system throughput.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart of a flow control method based on an AXI bus according to Embodiment 1 of the present invention;

[0028] Figure 2 This is a flowchart of a flow control method based on an AXI bus according to Embodiment 2 of the present invention;

[0029] Figure 3 This is a scenario diagram illustrating the implementation of flow control based on the AXI bus in this embodiment of the invention.

[0030] Figure 4This is a schematic diagram of a flow control device based on an AXI bus according to Embodiment 3 of the present invention;

[0031] Figure 5 This is a schematic diagram of the structure of an electronic device that implements the flow control method based on the AXI bus according to an embodiment of the present invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] Example 1

[0035] Figure 1 This is a flowchart of a flow control method based on the AXI bus provided in Embodiment 1 of the present invention. This embodiment is applicable to inter-chip interconnection communication based on the Ethernet physical layer and the AXI protocol. The method can be executed by an AXI bus-based flow control device, which can be implemented in hardware and / or software, and is generally configured in the target chip of a multi-chip system that is networked via Ethernet and interacts with information via the AXI bus. Figure 1 As shown, the method includes:

[0036] S110. Before continuously sending write address and write data to the first peer chip in the multi-chip system, obtain a first data volume that matches the write address and write data, and calculate a first credit value required for the first data volume.

[0037] In this context, "write address" refers to the target address of the write data sent via a dedicated channel when data is transmitted between chips via the AXI protocol. "Write data" refers to the target data sent to the write address via a dedicated channel when data is transmitted between chips via the AXI protocol. "First peer chip" refers to the chip located at the receiving end of the write address and write data during data transmission between chips via the AXI protocol. "First data volume" refers to the size of the memory occupied by the specific address data corresponding to the write address and write data when the sending chip performs a write operation to the first peer chip via the AXI protocol. "First credit value" refers to a pre-set credit value representing the available memory size for storing data, indicating the required memory size for the first data volume. For example, if 1 credit value represents 10KB of content, and the first data volume is 30KB, then 3 credit values ​​are needed to satisfy the requirement of sending the first data volume.

[0038] Understandably, in a multi-chip system networked via Ethernet and exchanging information via the AXI bus, when chips send data, a pre-defined credit value is used to determine whether the available memory size meets the data transmission and reception requirements. The AXI bus contains five channels related to read and write data operations: AW (Write Address Channel), W (Write Data Channel), B (Write Response Channel), AR (Read Address Channel), and R (Read Data Channel). Before the sending end sends a write address to the first peer chip via the AW channel and writes data via the W channel, it can obtain the specific address data corresponding to the write address and the total memory size required for the write data, thus obtaining the value of the first data volume. Based on the pre-defined correspondence between the credit value and the memory space size, the first credit value corresponding to the memory size required for the first peer chip to receive the first data volume can be calculated.

[0039] S120. Query the target write operation counter that matches the first peer chip maintained locally, and determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0040] The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip. The first memory is used by the first peer chip to temporarily store the write data obtained from the target chip.

[0041] The target write operation counter can refer to a counter on the transmitting chip used to maintain the write address and write data credit value sent to the current first peer chip. The target chip can be the transmitting chip that sends the write address and write data to the first peer chip.

[0042] Understandably, before sending the write address and write data to the first peer chip, the sending target chip calculates the first credit value required for the first data volume. It then queries the first peer chip's current credit value and compares it with the first credit value to determine if the available memory space of the first peer chip can satisfy the memory space size corresponding to the first credit value required for the current write operation. The first peer chip's credit value is maintained by a target write operation counter on the sending target chip. Its initial value is determined by the size of the first memory in the first peer chip before inter-chip communication occurs. The size of the available first memory space determines the size of the first data volume temporarily stored by the first peer chip from the target chip.

[0043] S130. If so, after updating the calculation result of storing the current credit value minus the first credit value in the target write operation counter, continuously send the write address and write data to the first peer chip.

[0044] Understandably, the target write operation counter matching the first peer chip is queried to obtain the current credit value. If it is greater than or equal to the first credit value, the current credit value can be subtracted from the first credit value, and the calculation result is updated and stored in the target write operation counter. This counter represents the reduction of the first peer chip's available memory space and the current available space size, allowing the execution of write address and write data transmission to the first peer chip. Upon receiving the write address and write data, the first peer chip, acting as the receiving end, temporarily stores them in its first memory. When the upper-level application in the first peer chip reads the data from the first memory, it releases the memory space and records the corresponding information value. Upon triggering the feedback information value condition, it sends the released information value to the target chip, acting as the sending end, via channel B.

[0045] Optionally, after determining whether the current credit value in the target write operation counter is greater than or equal to the first credit value, the method further includes:

[0046] If not, wait for the preset rate limiting duration, then return to perform the operation of judging whether the current credit value in the target write operation counter is greater than or equal to the first credit value, until the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0047] The rate limiting duration can refer to the waiting time when the current credit value does not meet the conditions for sending data, and the current credit value is re-acquired for judgment.

[0048] Understandably, when the current credit value stored in the target write operation counter matched with the first peer chip is less than the first credit value, it can wait for a preset rate limiting duration and then re-acquire the current credit value in the target write operation counter to determine its relationship with the first credit value. When the first peer chip, acting as the receiving end, releases the first memory space size and feeds back the release information value to the sending target chip to update the target write operation counter, if the current credit value is greater than or equal to the first credit value, the conditions for sending the write address and writing data are met. Otherwise, it continues to wait for the preset rate limiting duration and then re-determines the relationship between the current credit value and the first credit value. The above process is repeated until the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0049] S140. Whenever the target write response information describing the first memory release status is received from the first peer chip, the first release credit value corresponding to the target write response information is obtained, and the calculation result of the current credit value plus the first release credit value is updated in the target write operation counter.

[0050] The target write response information can refer to channel information fed back by the first peer chip to the target chip (which acts as the sender) via channel B, containing a credit value corresponding to the size of the first memory space released. The first released credit value can refer to the credit value in the target write response information corresponding to the size of the first memory space released by the first peer chip.

[0051] Understandably, the target write operation counter determines the size of the first available memory space in the first peer chip by maintaining a credit value. When the target chip, acting as the sender, receives the target write response information from the first peer chip, it can obtain the first release credit value regarding the size of the first available memory space in the target write response information. It can also add the first release credit value to the current credit value in the target write operation counter, update and store the calculation result in the target write operation counter, and indicate the latest status of the size of the first available memory space in the first peer chip.

[0052] Optionally, whenever the target write response information describing the first memory release status is received from the first peer chip, the first release credit value corresponding to the target write response information is obtained, including:

[0053] Whenever a write response message is received from the first peer chip through the write response channel, the write response message is parsed and processed.

[0054] If the parsing result is determined to contain a credit value release field that describes the release status of the first memory, then the write response information is determined as the target write response information;

[0055] Extract the first released credit value from the credit value release field of the target write response information.

[0056] In this context, the write response channel refers to a dedicated channel in a multi-chip system networked via an AXI bus, through which the first peer chip returns write operation feedback information to the target chip (acting as the sender); this is essentially the B channel in the AXI protocol bus. The write response information refers to the feedback information sent by the first peer chip to the target chip (acting as the sender) via the write response channel. The credit value release field refers to the field in the write response information that represents the credit value corresponding to the size of the space released in the first memory of the first peer chip.

[0057] Understandably, when the sending target chip performs a write operation to the first peer chip, the first peer chip sends a write response message through the write response channel for each write address and write data transmission. When the first peer chip detects that the condition for sending a release information value has been triggered, it also actively sends a write response message containing a release credit value through the write response channel. Therefore, whenever the sending target chip receives a write response message sent by the first peer chip through the write response channel, it parses the message. If the parsing result contains a credit value release field describing the size of the released space in the first memory, the received write response message can be identified as the target write response message. The first release credit value is extracted from the credit value release field of the target write response message, and this extracted credit value is added to the current credit value in the target write operation counter. Finally, the calculation result is updated and stored in the target write operation counter. Additionally, it's important to note that the sending end needs to reserve sufficient dedicated memory space to receive write response information from the first paired chip via the write response channel. Since the memory space required to temporarily store each write response is fixed, the sending chip must determine whether the memory space used to receive write response information is sufficient to temporarily store at least one write response. This ensures the proper reception of the write response information for each write operation. The write response information that releases the credit value does not occupy memory space; the sending end parses and releases it immediately upon receiving it, without consuming additional memory. Therefore, the write operation is executed only when the above memory requirement is met; otherwise, the chip waits for a preset rate-limiting duration and then repeats the above judgment logic until the requirements are met before executing the write operation.

[0058] The technical solution of this invention enables execution by a target chip in a multi-chip system networked via an AXI bus. Before continuously sending write addresses and write data to the first peer chip in the multi-chip system, a first data volume matching the write address and write data is obtained, and a first credit value required for the first data volume is calculated. A locally maintained target write operation counter matching the first peer chip is queried to determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value. The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip, which is used by the first peer chip to temporarily store the first data volume obtained from the target chip. If so, the calculation result of subtracting the first credit value from the current credit value is updated in the target write operation counter, and then write addresses and write data are continuously sent to the first peer chip. Whenever a target write response information describing the release status of the first memory is received from the first peer chip, a first release credit value corresponding to the target write response information is obtained, and the calculation result of adding the first release credit value to the current credit value is updated in the target write operation counter. The above technical solution, by designing differentiated and independent flow control for the five channels of the AXI protocol, establishes a credit value mechanism for data transmission in dedicated channels, accurately simulates the native handshake behavior of the AXI protocol, avoids the use of dedicated signaling packets, reduces protocol overhead, and greatly improves link utilization and system throughput.

[0059] Optionally, based on the above embodiments, when receiving the write address and write data continuously sent by the second peer chip in the multi-chip system, the write address and write data are temporarily stored in the second memory, wherein the second memory is used by the target chip to cache the write data obtained from the second peer chip.

[0060] In response to the first read operation of the upper layer application on the temporary data in the second memory, a first memory release amount matching the first read operation is obtained, and a second release credit value is calculated based on the first memory release amount;

[0061] Retrieve the target release credit counter that matches the second memory location, and update the current release credit value in the target release credit counter to the calculated result of the current release credit value plus the second release credit value;

[0062] Whenever the release credit value reporting condition matching the second peer chip is met, a write response information with an additional credit value release field is constructed based on the current release credit value in the target release credit counter. After the constructed write response information is fed back to the second peer chip, the target release credit counter is reset.

[0063] In this context, the second peer chip can refer to the chip that sends write addresses and write data to the target chip when the target chip acts as the receiver in a write operation. The second memory can refer to the memory space on the target chip, acting as the receiver, used to temporarily store the write addresses and write data received from the second peer chip. The first read operation can refer to the operation of the upper-layer application on the target chip, acting as the receiver, reading the write addresses and write data from the second memory. The first memory release amount can refer to the size of the memory space corresponding to the read write addresses and write data released on the target chip after completing the first read operation. The second release credit value can refer to the credit value corresponding to the first memory release amount, determined according to a preset correspondence between credit values ​​and memory space sizes. The target release credit counter can refer to the counter on the target chip, acting as the receiver, used to record data not sent to the second peer chip after the first read operation.

[0064] Understandably, in a multi-chip system, when the target chip acts as the receiver, the write addresses and write data continuously sent by the second peer chip are temporarily stored in the second memory, occupying a portion of the second memory space and consuming corresponding credit values. The upper-layer application in the target chip performs a first read operation on the temporarily stored data in the second memory. After the first read operation is completed, it can obtain a first memory release amount matching the size of the read data and calculate the corresponding second release credit value. The target chip has a local target release credit counter that matches the second memory. It can add the current release credit value to the target release credit counter, update the result, and store it in the target release credit counter, thus achieving the cumulative recording of released credit values ​​in each round of credit value write response information cycle. When the target chip detects that the condition for feeding back the released credit value to the second peer chip is met, it can construct a write response information containing a credit value release field representing the released credit value based on the current release credit value in the target release credit counter, feed it back to the second peer chip through the write response channel, reset the value of the target release credit counter to zero, and continue to accumulate and record the second release credit value in the next feedback cycle.

[0065] Optionally, based on the above embodiments, whenever the write address and write data of the target number of consecutive transactions are received from the second peer chip, it is determined that the release credit value reporting condition matching the second peer chip is met; or

[0066] Whenever the timing starts from the preset clock cycle and the target number of clock cycles have elapsed, it is determined that the release credit value reporting condition matching the second peer chip is met.

[0067] The target number of writes can refer to the number of write addresses and write data entries required to complete the write operation when the second peer chip sends the data to the target chip (which acts as the receiving end). The target quantity can refer to the number of clock cycles in which the preset condition for the feedback release information value is reached when the second peer chip performs a write operation to the target chip (which acts as the receiving end).

[0068] Understandably, for the target chip, acting as the receiving end, to send release credit value feedback information to the second peer chip, preset reporting conditions must be met. The second peer chip can divide the data to be written into multiple data entries and perform multiple write operations, sending the write address and write data to the target chip. Multiple clock cycles can pass during a single write operation or multiple write operations. Therefore, the reporting condition can be set according to the target number of data entries continuously sent by the second peer chip during the write operations received by the target chip, or it can be set as the target number of clock cycles elapsed during the write operation, counting from zero at the start of each feedback cycle. When the target chip detects that either of these reporting conditions is met, it actively triggers a B-channel write response message, feeding back the current release credit value in the target release credit counter to the second peer chip.

[0069] Example 2

[0070] Figure 2 This is a flowchart of a flow control method based on the AXI bus provided in Embodiment 2 of the present invention. The read operation flow control based on the AXI bus in this embodiment, together with the write operation flow control based on the AXI bus in the above embodiments, constitutes a flow control method based on the AXI bus. Figure 2 As shown, the method includes:

[0071] S210. Before sending the read address to the third peer chip in the multi-chip system, obtain the second data volume that matches the read address and calculate the second credit value required for the second data volume.

[0072] Here, "read address" can refer to the storage address of the target data in the chip's memory space, serving as an identifier for retrieving the target data during a read operation. "Third peer chip" can refer to the chip in a multi-chip system that receives the read address sent by the target chip and feeds back the read data. "Second data volume" can refer to the size of the storage space occupied by the data to be read, matching the read address. "Second credit value" can refer to the credit value corresponding to the second data volume, determined according to a preset correspondence between credit values ​​and storage space sizes.

[0073] Understandably, before the target chip, acting as the sender, performs a read operation to the third peer chip, it needs to determine whether its local storage space meets the requirements for the temporary storage space for the read data. Therefore, it can first obtain the second data volume matching the read address of the current read operation and calculate the second credit value required for the second data volume, thereby determining the size of the temporary storage space required to read the data. Additionally, it's important to note that the third peer chip needs sufficient memory space to receive the read addresses sent by the target chip. It's known that the memory space required to temporarily store each read address is fixed, and each time read data is fed back through the read data channel, it indicates that the memory occupied by the corresponding read address information has been released. Therefore, based on the minimum value of the read data size fed back to the target chip by the third peer chip through the read channel, and the size of the memory space on the target chip used to temporarily store read data, the maximum number of read data information that can be temporarily stored can be calculated. Then, the size of the memory space used by the third peer chip to temporarily store the read address sent by the target chip can be determined by multiplying this number by the memory space required for each read address information. This ensures that when the second credit value meets the requirements for performing the read operation, the third peer chip can definitely meet the memory space requirements for temporarily storing the read address information.

[0074] S220. Query the locally maintained read operation counter and determine whether the current credit value in the read operation counter is greater than or equal to the second credit value.

[0075] The initial value of the credit value in the read operation counter is determined by the size of the third memory in the target chip. The third memory is used by the target chip to temporarily store read data obtained from other chips in the multi-chip system.

[0076] The third memory can refer to the memory on the target chip (actually the sending end) used to temporarily store read data fed back by the third peer chip. The read operation counter can refer to a counter on the target chip (actually the sending end) used to maintain the credit value corresponding to the available storage space of the third memory.

[0077] Understandably, after calculating the second credit value to determine the required temporary storage space for reading data, the read operation counter corresponding to the credit value in the locally maintained third memory can be queried to determine whether the current credit value in the read operation counter is greater than or equal to the second credit value, thus determining whether the available space in the third memory meets the temporary storage requirements for the second data volume. The initial value of the credit value in the read operation counter is based on the credit value corresponding to the total available space in the third memory before any read operations are performed by the target chip, and will be dynamically updated accordingly as the third memory space is used during subsequent read operations.

[0078] S230. If so, after updating the calculation result of storing the current credit value minus the second credit value in the read operation counter, send the read address to the third peer chip.

[0079] Understandably, if the current credit value in the current read operation counter is greater than or equal to the second credit value, that is, the available space of the third memory meets the temporary storage requirements of the second data volume, then the current credit value can be subtracted from the second credit value, and the calculation result can be updated and stored in the read operation counter. After that, the read address can be sent to the third peer chip through the AR channel to obtain the read data.

[0080] Optionally, if not, wait for the preset rate limiting duration, then return to perform the operation of judging whether the current credit value in the read operation counter is greater than or equal to the second credit value, until the current credit value in the read operation counter is greater than or equal to the second credit value.

[0081] Understandably, the current credit value in the current read operation counter is dynamically updated according to the size of the third available memory space. If the current credit value in the current read operation counter is less than the second credit value, the operation of judging the relationship between the current credit value in the read operation counter and the second credit value can be performed again after waiting for the preset rate limiting time. If it is still less, the operation of judging the relationship between the current credit value in the read operation counter and the second credit value can be repeated for the preset rate limiting time. This process continues until the current credit value in the read operation counter is greater than or equal to the second credit value, which satisfies the read data temporary storage space size requirement, and the read address sending operation is then performed.

[0082] S240, In response to the second read operation of the upper layer application on the temporary data in the third memory, obtain the second memory release amount that matches the second read operation.

[0083] The second read operation can refer to the read operation of temporary data stored in the third memory by the upper-level application in the target chip. The second memory release amount can refer to the amount of memory space released after the upper-level application in the target chip reads the data from the third memory.

[0084] It is understandable that after the target chip receives the read data fed back by the third peer chip through the R channel, it temporarily stores it in the third memory. When the upper-level application of the target chip performs a second read operation on the temporarily stored data in the third memory, it can release the memory space of the read data size, thereby obtaining the second memory release amount corresponding to the size of the released memory space.

[0085] S250. Calculate the third release credit value based on the second memory release amount, and update the calculation result of storing the current credit value plus the third release credit value in the read operation counter.

[0086] The third released credit value can refer to the credit value corresponding to the second memory release amount, which is determined according to the preset correspondence between credit value and available memory space.

[0087] Understandably, when the upper-layer application in the target chip reads the temporary data in the third memory, it can release memory space equal to the amount of the second memory release. It needs to update the credit value in the read operation counter synchronously. Therefore, the third release credit value can be calculated based on the amount of the second memory release, and added to the current credit value in the read operation counter. The calculation result is then updated and stored in the read operation counter.

[0088] The technical solution of this invention enables the target chip to obtain a second data volume matching the read address and calculate the second credit value required for the second data volume before sending the read address to the third peer chip in a multi-chip system. It then queries the locally maintained read operation counter to determine if the current credit value in the read operation counter is greater than or equal to the second credit value. If so, it updates the read operation counter with the calculated result of subtracting the second credit value from the current credit value before sending the read address to the third peer chip. The target chip responds to the upper-layer application's second read operation on temporarily stored data in the third memory, obtains a second memory release amount matching the second read operation, calculates a third release credit value based on the second memory release amount, and updates the read operation counter with the calculated result of adding the third release credit value to the current credit value. This technical solution, by introducing a credit value maintenance mechanism to complete read operations based on the AXI protocol read address channel and read data channel, allows credit value flow control decisions to be made locally at the sending end, effectively preventing data buffer overflow, ensuring zero data packet loss, and improving the speed of read data response.

[0089] Figure 3 This is a scenario diagram illustrating the flow control based on the AXI bus implemented in this embodiment of the invention. Applicable to scenarios involving flow control based on the AXI bus, it achieves fine-grained lossless flow control for each AXI channel through a credit value management mechanism, resolving the mismatch between traditional Ethernet flow control mechanisms and the backpressure requirements of the AXI protocol. Its system architecture and specific implementation process are as follows.

[0090] System architecture and implementation prerequisites: Both the transmitting and receiving ends of this system integrate an AXI interface module, a protocol encapsulation / decapsulation module, a credit management unit, and an Ethernet MAC / PHY (data link layer / physical layer) module. These modules work together to achieve the conversion between AXI signals and Ethernet frames and flow control management. The core implementation prerequisite is that the AW, W, B, AR, and R channels of the AXI protocol do not support direct backpressure to the front-end Ethernet receiving module on the Ethernet receiving side. End-to-end flow control is completed entirely through the active interaction and implicit inference mechanism of the credit management unit.

[0091] The active credit value interaction process between the AW and W channels: This channel adopts an active credit value interaction mechanism. During the initialization phase, since both the sending and receiving ends are self-developed modules, the initial values ​​of the write and read operation credit values ​​at the receiving end can be identified and configured locally. During the sending phase, before initiating a write operation, the sending end needs to verify that it holds sufficient corresponding credit values, and the receiving end's credit values ​​must meet the write address and write data requirements. The credit value must be greater than the memory space required for this data transmission. Each time an AW+W (write address and write data) transmission is completed, the local credit counter is synchronously decremented. During the credit value feedback phase, the receiving end will... After the +W related data is read by the upper-layer application, the AW and W credit release counters are incremented for each credit value released to the lower-level module. The counters are reset to zero and recounted after the credit value is fed back. When the B credit value feedback condition is triggered, the receiver carries the currently available AW and W credit value information in the B channel response. After receiving the B credit value, the sender performs a summation operation with the locally maintained credit value and updates the local counter. At the same time, the receiver supports a configurable B credit value feedback triggering strategy, which triggers feedback based on the preset Burst number (i.e., the number of burst transactions accumulated in a single flow control triggering cycle) threshold and the Timeout cycle (clock cycle) threshold. After the trigger, the counters are reset to zero and recounted to balance the credit value overhead and the timeliness of flow control.

[0092] The AR channel's credit interaction process employs an implicit credit interaction mechanism. During the initialization phase, based on the characteristics of self-developed modules at both the sending and receiving ends, the initial R credit value at the sending end can be identified and configured. During the sending phase, before initiating an AR transaction, the sending end needs to confirm that it holds sufficient AR credit, and decrements the local AR credit value counter for each completed AR transmission. During the credit recovery phase, recovery is achieved through reading from the upper-layer application. The sending end's credit value management unit infers the size of the AR buffer memory space to be released based on the size of the R data read by the upper-layer application, thereby determining the corresponding released AR credit value and synchronously accumulating and updating the local AR credit counter.

[0093] The latency compensation and high-performance guarantee mechanism ensures that the receiver buffer always has sufficient free space by accurately calculating and updating the credit amount of each channel through the credit management unit, thus completely avoiding the risk of buffer overflow and achieving lossless transmission with no packet loss in AXI-Ethernet interconnection. This credit mechanism is a proactive flow control mechanism, which is different from the passive waiting mode of traditional stop-and-wait protocols. As long as the sender has sufficient credit, it can continue to send data during the link transmission delay, maximizing the physical bandwidth potential of the Ethernet link. At the same time, based on the preset maximum expected delay and actual path delay parameters, the algorithm accurately calculates the minimum buffer depth to meet performance requirements, effectively reducing chip hardware resource consumption and cost while ensuring high performance of end-to-end transmission.

[0094] Example 3

[0095] Figure 4 This is a schematic diagram of a flow control device based on an AXI bus, provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a write operation credit value acquisition module 410, a write operation credit value calculation module 420, and a write operation credit value update module 430.

[0096] The write operation credit value acquisition module 410 is used to acquire a first data volume matching the write address and write data before continuously sending the write address and write data to the first peer chip in the multi-chip system, and to calculate the first credit value required for the first data volume.

[0097] The write operation credit value calculation module 420 is used to query the target write operation counter that matches the first peer chip maintained locally, and determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0098] The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip. The first memory is used by the first peer chip to temporarily store the write data obtained from the target chip.

[0099] If so, after updating the calculation result of storing the current credit value minus the first credit value in the target write operation counter, the write address and write data are continuously sent to the first peer chip.

[0100] The write operation credit value update module 430 is used to obtain the first release credit value corresponding to the target write response information whenever it receives the target write response information that describes the first memory release status from the first peer chip, and update the target write operation counter with the calculation result of the current credit value plus the first release credit value.

[0101] The technical solution of this invention enables execution by a target chip in a multi-chip system networked via an AXI bus. Before continuously sending write addresses and write data to the first peer chip in the multi-chip system, a first data volume matching the write address and write data is obtained, and a first credit value required for the first data volume is calculated. A locally maintained target write operation counter matching the first peer chip is queried to determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value. The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip, which is used by the first peer chip to temporarily store the first data volume obtained from the target chip. If so, the calculation result of subtracting the first credit value from the current credit value is updated in the target write operation counter, and then write addresses and write data are continuously sent to the first peer chip. Whenever a target write response information describing the release status of the first memory is received from the first peer chip, a first release credit value corresponding to the target write response information is obtained, and the calculation result of adding the first release credit value to the current credit value is updated in the target write operation counter. The above technical solution, by designing differentiated and independent flow control for the five channels of the AXI protocol, establishes a credit value mechanism for data transmission in dedicated channels, accurately simulates the native handshake behavior of the AXI protocol, avoids the use of dedicated signaling packets, reduces protocol overhead, and greatly improves link utilization and system throughput.

[0102] Optionally, the write operation credit value calculation module 420 can also be specifically used to: determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value; if not, wait for a preset rate limiting time and then return to perform the operation of determining whether the current credit value in the target write operation counter is greater than or equal to the first credit value, until the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0103] Optionally, the write operation credit value update module 430 can also be specifically used to: parse the write response information whenever it receives a write response message sent by the first peer chip through the write response channel. If it is determined that the parsing result contains a credit value release field describing the release status of the first memory, then the write response information is identified as the target write response information. The first release credit value is extracted from the credit value release field of the target write response information.

[0104] Optionally, it may also include a write operation credit value release module, used to: in response to a first read operation of the upper layer application on the temporary data stored in the second memory, obtain a first memory release amount matching the first read operation, and calculate a second release credit value based on the first memory release amount.

[0105] Optionally, it may also include a write operation release credit value maintenance module, used to: obtain a target release credit counter that matches the second memory maintained locally, and update the current release credit value in the target release credit counter to the calculation result of the current release credit value plus the second release credit value.

[0106] Optionally, a write operation release credit value feedback module may also be included, used to: whenever the release credit value reporting condition matching the second peer chip is met, construct write response information with an additional credit value release field based on the current release credit value in the target release credit counter, and after feeding back the constructed write response information to the second peer chip, reset the target release credit counter. The conditions for meeting the release credit value reporting condition matching the second peer chip include: whenever the target number of write addresses and write data continuously sent by the second peer chip are received, it is determined that the release credit value reporting condition matching the second peer chip is met; or whenever the timer has elapsed for the target number of clock cycles from a preset clock cycle starting point, it is determined that the release credit value reporting condition matching the second peer chip is met.

[0107] Optionally, it may also include a read operation credit value acquisition module, used to: acquire a second data volume matching the read address and calculate a second credit value required for the second data volume before sending the read address to the third peer chip in the multi-chip system.

[0108] Optionally, a read operation credit value calculation module may also be included, used to: query the locally maintained read operation counter and determine whether the current credit value in the read operation counter is greater than or equal to the second credit value. The initial value of the credit value in the read operation counter is determined by the size of the third memory in the target chip, which is used by the target chip to temporarily store read data obtained from other chips in the multi-chip system. If yes, the read operation counter is updated with the calculated result of subtracting the second credit value from the current credit value, and then a read address is sent to the third peer chip. If no, the read operation counter waits for a preset rate-limiting duration and then returns to perform the operation of determining whether the current credit value in the read operation counter is greater than or equal to the second credit value, until the current credit value in the read operation counter is greater than or equal to the second credit value.

[0109] Optionally, a read operation credit value update module may also be included, used to: in response to a second read operation by an upper-layer application on temporary data stored in third memory, obtain a second memory release amount matching the second read operation; calculate a third release credit value based on the second memory release amount; and update the read operation counter with the calculated result of the current credit value plus the third release credit value.

[0110] The flow control device based on the AXI bus provided in the embodiments of the present invention can execute the flow control method based on the AXI bus provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0111] Example 4

[0112] Figure 5 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0113] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0114] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0115] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as flow control methods based on the AXI bus.

[0116] That is, before continuously sending write address and write data to the first peer chip in the multi-chip system, a first data volume matching the write address and write data is obtained, and a first credit value required for the first data volume is calculated.

[0117] Query the target write operation counter that matches the first peer chip maintained locally, and determine whether the current credit value in the target write operation counter is greater than or equal to the first credit value.

[0118] The initial value of the credit value in the target write operation counter is determined by the size of the first memory in the first peer chip. The first memory is used by the first peer chip to temporarily store the first amount of data obtained from the target chip.

[0119] If so, after updating the calculation result of storing the current credit value minus the first credit value in the target write operation counter, the write address and write data are continuously sent to the first peer chip.

[0120] Whenever the target write response information describing the first memory release status is received from the first peer chip, the first release credit value corresponding to the target write response information is obtained, and the calculation result of the current credit value plus the first release credit value is updated in the target write operation counter.

[0121] In some embodiments, the AXI bus-based flow control method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the AXI bus-based flow control method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the AXI bus-based flow control method by any other suitable means (e.g., by means of firmware).

[0122] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0123] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0124] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0125] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0126] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0127] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0128] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0129] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An AXI bus-based flow control method, characterized in that, The method is performed by a target chip in a multi-chip system networked through an AXI bus, and comprises the following steps: Before continuously sending a write address and write data to a first peer chip in the multi-chip system, a first data amount matching the write address and write data is obtained, and a first credit value required by the first data amount is calculated; A target write operation counter locally maintained and matching the first peer chip is queried to determine whether a current credit value in the target write operation counter is greater than or equal to the first credit value; The initial value of the credit value in the target write operation counter is determined by the size of a first memory in the first peer chip, and the first memory is used to temporarily store data of the first data amount obtained from the target chip; If yes, the write address and write data are continuously sent to the first peer chip after the target write operation counter is updated to store a calculation result of the current credit value minus the first credit value; Whenever target write response information describing the release of the first memory is received from the first peer chip, a first release credit value corresponding to the target write response information is obtained, and a calculation result of the current credit value plus the first release credit value is updated and stored in the target write operation counter.

2. The method of claim 1, wherein, After determining whether the current credit value in the target write operation counter is greater than or equal to the first credit value, the method further comprises the following steps: If no, the operation of determining whether the current credit value in the target write operation counter is greater than or equal to the first credit value is performed after waiting for a preset flow limiting duration until the current credit value in the target write operation counter is greater than or equal to the first credit value.

3. The method of claim 1, wherein, Whenever target write response information describing the release of the first memory is received from the first peer chip, a first release credit value corresponding to the target write response information is obtained, comprising the following steps: Whenever write response information sent by the first peer chip through a write response channel is received, the write response information is parsed and processed; If it is determined that the parsed result contains a credit value release field describing the release of the first memory, the write response information is determined as the target write response information; The first release credit value is extracted from the credit value release field of the target write response information.

4. The method of claim 1, wherein, The method further comprises the following steps: When write address and write data continuously sent by a second peer chip in the multi-chip system are received, the write address and write data are temporarily stored in a second memory, wherein the second memory is used to buffer the write address and write data obtained from the second peer chip by the target chip; In response to a first read operation of the temporarily stored data in the second memory by an upper-layer application, a first memory release amount matching the first read operation is obtained, and a second release credit value is calculated according to the first memory release amount; A target release credit counter locally maintained and matching the second memory is obtained, and a current release credit value in the target release credit counter is updated to a calculation result of the current release credit value plus the second release credit value; Whenever a release credit value reporting condition matching the second peer chip is met, write response information with an additional credit value release field is constructed according to the current release credit value in the target release credit counter, and after the constructed write response information is fed back to the second peer chip, the target release credit counter is reset.

5. The method of claim 4, wherein, The release credit value reporting condition matched with the second opposite end chip includes: The release credit value reporting condition matched with the second opposite end chip is determined when the write address and the write data of the target number of pens continuously sent by the second opposite end chip are received; or The release credit value reporting condition matched with the second opposite end chip is determined when the target number of clock cycles elapses from the preset clock cycle timing starting point.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Before sending a read address to a third opposite end chip in a multi-chip system, obtaining a second data amount matched with the read address, and calculating a second credit value required by the second data amount; Querying a locally maintained read operation counter to determine whether a current credit value in the read operation counter is greater than or equal to the second credit value; The initial value of the credit value in the read operation counter is determined by the size of a third memory in the target chip, and the third memory is used to temporarily store read data obtained from other chips in the multi-chip system; If yes, the read address is sent to the third opposite end chip after the read operation counter is updated to store the calculation result of the current credit value minus the second credit value; In response to a second read operation of the temporarily stored data in the third memory by an upper application, a second memory release amount matched with the second read operation is obtained; A third release credit value is calculated according to the second memory release amount, and the read operation counter is updated to store the calculation result of the current credit value plus the third release credit value.

7. The method of claim 6, wherein, After determining whether the current credit value in the read operation counter is greater than or equal to the second credit value, the method further includes: If no, the operation of determining whether the current credit value in the read operation counter is greater than or equal to the second credit value is returned to be executed after waiting for a preset flow limiting time length, until the current credit value in the read operation counter is greater than or equal to the second credit value.

8. An electronic device, comprising: The electronic device includes: At least one processor; and A memory in communication connection with the at least one processor; wherein The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the AXI bus based flow control method in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to execute the AXI bus based flow control method in any one of claims 1-7 when executed.

10. A computer program product, characterised in that, The computer program product includes a computer program, and the computer program implements the AXI bus based flow control method according to any one of claims 1-7 when executed by the processor.

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