Trigger processing method, hardware simulation tool, electronic device and storage medium

Abstract

The present application provides a method of handling a trigger during simulation of a logical design, comprising: causing a hardware simulation tool to simulate the logical system design, the trigger associated with one or more target signals of the logical system design, the logical system design comprising a plurality of key signals, the plurality of key signals are divided into a plurality of signal groups; determining a target key signal associated with the one or more target signals in the key signals according to the description of the logic system design; determining one or more target signal groups corresponding to the target key signal in the plurality of signal groups; and reading signal values of the one or more target signal sets from the hardware simulation tool for processing the trigger.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip verification, and in particular, to a method for processing a trigger during simulation of a logic design, a hardware simulation tool, an electronic device, and a storage medium. BACKGROUND

[0002] A hardware simulation tool (e.g., a prototype verification system or an emulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. Thus, the logic system design being tested in the simulation tool can also be referred to as a Design Under Test (DUT). The simulation tool can simulate the DUT through one or more configurable components (e.g., a Field Programmable Gate Array (FPGA)), including performing various operations of the DUT, to test and verify the functionality of various modules of the DUT before manufacturing. The DUT can also be tested with various peripheral cards attached to the simulation tool to test the DUT with the peripherals as a complete system.

[0003] There are also many software associated with the hardware simulation tool, such as a compiler, a synthesizer, a debugger, etc.

[0004] The compiler is used to compile the source code of the logic system design, the synthesizer is used to synthesize the logic system design into a netlist form and burn into the FPGA, and the debugger is used to implement some simple debugging functions. It can be understood that the above software runs on a host computer connected to the hardware simulation tool. SUMMARY

[0005] A first aspect of the present application provides a method for processing a trigger during simulation of a logic design, comprising: causing a hardware simulation tool to simulate the logic system design, the trigger being associated with one or more target signals of the logic system design, the logic system design including a plurality of key signals, the plurality of key signals being divided into a plurality of signal groups; determining a target key signal associated with the one or more target signals among the key signals according to a description of the logic system design; determining one or more target signal groups corresponding to the target key signal among the plurality of signal groups; and reading signal values of the one or more target signal groups from the hardware simulation tool for processing the trigger.

[0006] The second aspect of the present application provides a hardware simulation tool, comprising: an interface connected with a host and configured to receive a signal value reading request from the host; a programmable logic device configured to implement a logic system design, the logic system design comprising a plurality of key signals, the plurality of key signals being divided into a plurality of signal groups, a trigger being associated with one or more target signals of the logic system design; a selector connected with the programmable logic device, configured to select one or more target signal groups associated with the trigger from the plurality of signal groups according to the signal value reading request and transmit signal values of the one or more target signal groups to the host, a selection number of the selector corresponding to a number of the plurality of signal groups.

[0007] The third aspect of the present application provides an electronic device, comprising: a memory configured to store a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of the first aspect.

[0008] The fourth aspect of the present application provides a non-transitory computer-readable storage medium storing a set of instructions of a computer, the set of instructions configured to cause the computer to perform the method of the first aspect when executed. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the present application or related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0010] Figure 1 A structural schematic diagram of an exemplary host according to an embodiment of the present application is shown.

[0011] Figure 2 A schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0012] Figure 3 A schematic diagram of division of key signals of a logic system design according to an embodiment of the present application is shown.

[0013] Figure 4 A schematic diagram of data transmission of a host and a hardware simulation tool according to an embodiment of the present application is shown.

[0014] Figure 5 A structural schematic diagram of a selector according to an embodiment of the present application is shown.

[0015] Figure 6A flow chart of a method for handling a trigger during simulation logic design is shown. DETAILED DESCRIPTION

[0016] For the purposes of the present application, the technical solutions and advantages thereof, further detailed explanations are provided below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0017] It should be noted that, unless otherwise defined, technical or scientific terms used in the present application should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms "first", "second", and similar terms used in the present application do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "comprising", "including", and similar terms mean that the elements or objects before the term encompass the elements or objects listed after the term and their equivalents, and do not exclude other elements or objects. The terms "connected" and similar terms do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0018] When simulating a logic system design using a hardware simulation tool, a trigger is usually used to monitor the fulfillment of a given condition. The trigger is often an expression containing multiple signals. The trigger is determined by judging whether the expression is true or not. Often, the trigger is implemented when the condition is met. When the trigger is fulfilled, the hardware simulation can be paused to further observe the values of various signals of the logic system design at the time when the trigger is fulfilled.

[0019] The usual practice is to provide the values of the signals included in the trigger to a processing unit for calculation. The processing unit is usually formed using an FPGA on the hardware simulation tool.

[0020] However, this approach has two obvious problems. First, the signals need to be connected to the processing unit through dedicated pins. When the size of the logic system design becomes larger and multiple FPGAs are needed for simulation, the IO ports of the FPGAs will be occupied. However, the number of IO ports of the FPGAs is limited. Second, the hardware processing unit needs to be compiled through the FPGA, which lacks flexibility.

[0021] The above problems are more pronounced on a prototype verification system with debugging functions. This is because the prototype verification system (or prototype verification board) has more limited IO ports for signal detection and transmission.

[0022] To solve the above problems, the embodiments of the present application provide a method for handling a trigger during simulation of a logic design, an electronic device, and a storage medium.

[0023] Figure 1A structural diagram of a host 100 according to an embodiment of the present application is shown. The host 100 can be an electronic device running a simulation system. As Figure 1 shown, the host 100 can include a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are connected to each other through the bus 110 for communication within the electronic device.

[0024] The processor 102 can be a central processing unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 can be used to perform functions related to the techniques described in the present application. In some embodiments, the processor 102 can also include multiple processors integrated as a single logical component. As Figure 1 shown, the processor 102 can include multiple processors 102a, 102b, and 102c.

[0025] The memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulating a test design can be a computer program stored in the memory 104. As Figure 1 shown, the memory-stored data can include program instructions (e.g., program instructions for implementing the method of locating errors of the present application) and data to be processed (e.g., the memory can store temporary code generated in the compilation process). The processor 102 can also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 can include volatile storage devices or non-volatile storage devices. In some embodiments, the memory 104 can include random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard disks, solid-state disks (SSD), flash memory, memory sticks, etc.

[0026] Network interface 106 can be configured to provide communication with other external devices to host 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0027] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0028] Bus 110 can be configured to transfer information between various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0029] It should be noted that although the above electronic device architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, this electronic device architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above electronic device architecture may only include the components necessary for implementing the embodiments of this application, and does not necessarily include all the components shown in the figures.

[0030] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of this application is shown.

[0031] like Figure 2 As shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202.

[0032] Simulation tool 202 is a hardware system used to simulate a design under test (DUT). Simulation tool 202 can be a prototype verification board or a hardware emulator. A design under test may include multiple modules. The design under test can be combinational logic circuits, sequential logic circuits, or a combination of both. Simulation tool 202 may include one or more configurable circuits (e.g., an FPGA) for simulating the design under test.

[0033] The simulation tool 202 can include an interface unit 2022 for communicatively coupling with the host 100 for communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 can include one or more interfaces with electrical connection capability. For example, the interface unit 2022 can include an RS232 interface, a USB interface, a LAN port, a fiber interface, an IEEE 1394 (Firewire interface), etc. In some embodiments, the interface unit 2022 can be a wireless network interface. For example, the interface unit 2022 can be a WIFI interface, a Bluetooth interface, etc.

[0034] The host 100 can transmit the compiled DUT, debug instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 can also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0035] The simulation tool 202 can also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during simulation. In some embodiments, the signal values generated by the design under test during simulation can be directly read by the host 100. It can be appreciated that the memory 2024 can also be independent of the simulation tool 202, e.g., using an external memory.

[0036] The simulation tool 202 can also include an FPGA 2026 for hardware implementation of the logic system design onto the FPGA. It can be appreciated that the simulation tool 202 can include multiple FPGAs, as shown in the example.

[0037] In addition to being connected to the host 100, the simulation tool 202 can also be connected to one or more daughter cards 204 via the interface unit 2022.

[0038] The daughter cards are used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that, before the chip is taped out, tries to restore the real use scenario of the chip as much as possible to verify whether the functions of the chip are accurate and complete. The daughter card 204 can include a memory daughter card (e.g., providing a DDR memory interface), a communication daughter card (e.g., providing various network interfaces or wireless network card interfaces), etc.

[0039] Host 100 can be used to configure simulation tool 202 to simulate a design under test (DUT). The DUT can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, host 100 can be a virtual machine in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed using a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). Configuring simulation tool 202 on host 100 can include configuring the simulation environment (e.g., the connection relationships between multiple simulation tools 202 or the connection relationships between simulation tools and daughter cards).

[0040] Host 100 can compile the logical system design in source code form into an executable file. From a design perspective, the logical system design may include the design under test and the corresponding testbench.

[0041] From a comprehensive perspective, a logic system design can include synthesizable and non-synthesizable parts. Synthesizable parts typically correspond to the actual physical design (e.g., a chip), while non-synthesizable parts usually include initialization modules, test benches, etc. The executable file formed after compiling the non-synthesizable parts can usually be run by the host computer. The synthesizable parts, after compilation, still need to be synthesized to form a bit file. The bit file can be used to configure the FPGA 2026 to run according to the design requirements of the synthesizable parts.

[0042] The host 100 can receive requests from the user to debug the design under test (DUT). As described above, the DUT may include one or more modules. The description of the DUT can be completed using a hardware description language. The host 100 can perform synthesis based on the description of the DUT to generate, for example, a gate-level circuit netlist (not shown). This gate-level circuit netlist of the DUT can be loaded into a simulation tool 202 and run, thereby forming a circuit structure corresponding to the DUT within the simulation tool 202. Therefore, the circuit structure of the DUT can be obtained based on the description, and correspondingly, the circuit structure of each block in the DUT can be obtained similarly.

[0043] The host 100 can also read the values ​​of DUT signals from the simulation tool 202 via the interface unit 2022 and process them accordingly. The DUT signals that can be read need to be specified during the DUT compilation process. Typically, the DUT signals that can be read can be referred to as the DUT's critical signals. Critical signals can include the primary inputs of the logic system design and the register outputs of the logic system design. The primary inputs are typically signals that stimulate the DUT to operate; other signals of the DUT can be determined based on the values ​​of the primary inputs and the DUT's description. For example, the outputs and intermediate signal values ​​of a combinational logic circuit can be calculated based on the input signals of the combinational logic circuit and its structure. In some embodiments, the register outputs of the logic system design can also affect the behavior of the logic system design and are therefore also included among the critical signals.

[0044] The values ​​of key signals in a given clock cycle can be used to recover the state of the logic system design in that given clock cycle. In other words, the values ​​of key signals in a given clock cycle can restore the simulation of the logic system design to that given clock cycle.

[0045] For example, host 100 can read the values ​​of key signals, including main inputs and register outputs, and determine the values ​​of one or more target signals over a period of time (e.g., N clock cycles) based on the values ​​of the key signals and the description of the logic system design.

[0046] Understandably, in order to read critical signals, the logic system design, when implemented in the hardware emulation tool 202, needs to be specifically configured to select the values ​​of the critical signals to probe. For example, the hardware emulation tool can select to probe the values ​​of up to 1 million signals and support reading the values ​​of these 1 million signals to the host. These 1 million signals may include 500,000 main inputs and 500,000 register outputs. Understandably, the number of critical signals (as well as the number of main inputs and register outputs) can vary depending on the specifications of the hardware emulation tool and the specific circumstances of the logic system design.

[0047] Once the values ​​of one or more target signals have been calculated in each clock cycle, the host 100 can determine whether the trigger condition is met based on the specific trigger condition. The trigger condition could be, for example, (a&b==1), meaning that a trigger occurs when the logical AND of the values ​​of signal a and signal b equals 1.

[0048] Therefore, the host 100 not only needs to read the value of the key signal from the hardware simulation tool 202, but also needs to further calculate the value of the key signal and determine whether the triggering condition is met.

[0049] This makes the host 100 process critical signals slower than the hardware emulation tool 202 returns critical signals.

[0050] In some embodiments, in response to the value of the one or more target signals satisfying the triggering condition in a target clock cycle (e.g., the nth clock cycle in N clock cycles), the host 100 may record the target clock cycle (e.g., the nth clock cycle) and cause the hardware simulation tool 202 to restore the simulation of the logic system design to the target clock cycle.

[0051] Understandably, since the hardware emulation tool 202 is faster than the host 100 in processing critical signals, it typically emulates a much later clock cycle by the time the target clock cycle is determined. Therefore, the host 100 needs to restore, or reset, the hardware emulation tool 202 to that target clock cycle. Because the host 100 has the values ​​of the critical signals for that target clock cycle, the hardware emulation tool 202 can easily restore to that clock cycle. After restoring to the target clock cycle, the hardware emulation tool 202 can execute triggered subsequent actions. Since these subsequent actions are beyond the scope of this application, they will not be further described.

[0052] In this way, it appears to the user as if the hardware emulation tool 202 has been triggered and the clock has been paused, and the next action has been performed as required.

[0053] However, because the host 100 processes critical signals much slower than the hardware emulation tool 202, the hardware emulation tool 202 has already been running for a long time while the host 100 is processing the critical signals. Therefore, the speed at which the host 100 processes critical signals is the performance bottleneck of the entire system. Significantly improving the speed at which the host 100 processes critical signals could greatly improve the overall system performance.

[0054] The processing speed of critical signals by host 100 is primarily limited by two factors. First, the computing speed of host 100; second, the speed at which host 100 reads critical signals. In typical hardware emulation tools, the number of critical signals can reach one million. Assuming each signal generates 1 bit of data per clock cycle, one million critical signals would generate 0.12 MB of data in just one cycle. Considering that typical frequencies of hardware emulation tools range from 1 MHz to 10 MHz, even using 1 MHz as an example, 12 GB of data would be generated per second. Such massive data transmission to host 100 would result in significant transmission latency, thus slowing down the processing speed of critical signals.

[0055] The common approach is to increase the communication bandwidth between the host and the hardware emulation tool in order to improve the transmission rate between them. However, as hardware emulation tools and logic system designs grow larger, the number of critical signals also increases. But the maximum communication rate of the host's interface is limited.

[0056] Therefore, improving the speed at which critical signals are transmitted from the hardware simulation tool to the host 100 is key to improving the overall efficiency of the simulation system 200. Accordingly, how to improve the speed of critical signal transmission from the hardware simulation tool to the host 100 is a technical problem that urgently needs to be solved.

[0057] To address this technical problem, the inventors of this application have further proposed the following embodiments.

[0058] The inventors noted that compared to the millions of critical signals, the number of signals associated with a trigger is very limited. For example, for a trigger with the trigger condition (a & b == 1), whether the trigger is successful depends only on the value of signal a and has nothing to do with other signals. The values ​​of signals a and b may only be related to, for example, two critical signals c and d. Thus, for the host 100, it is sufficient to determine whether the trigger is successful by obtaining the values ​​of the two critical signals c and d related to signals a and b. After the trigger is successful, the simulation of the logic system design can perform various specified actions (e.g., pause the clock, save the critical signals of the logic system design for the current clock, etc.).

[0059] Therefore, unlike the usual approach of simply increasing the bandwidth between the host and the hardware emulation tool to accelerate communication, the embodiments of this application intend to reduce the amount of data communicated between the host and the hardware emulation tool in order to transmit the values ​​of critical signals more quickly.

[0060] In embodiments of this application, the trigger is associated with one or more target signals (e.g., signal a above) in the logic system design. Since the target signals typically differ with different triggers, their values ​​are usually determined based on key signals.

[0061] A logic system design may include multiple key signals, which are divided into multiple signal groups. Typically, the division of key signals is based on the description of the logic system design. For example, this division can be completed during the compilation of the logic system design, and the division is simultaneously provided to the host 100 and the hardware simulation tool 202.

[0062] Figure 3 A schematic diagram of the division of key signals in a logic system design 300 according to an embodiment of this application is shown.

[0063] like Figure 3As shown, when compiling the logic system design 300, the compiler (not shown) can determine the structure of the logic system design 300 based on its description. For example, the logic system design 300 may include a top-level module (TOP), modules 301 and 303 under the top-level module, and sub-modules 3011 and 3013 of module 301. The logic system design 300 also includes sub-modules 3011 and 3013, and instances 30111, 30112, 30131, 3031, and 3032 of module 303. An instance is a module corresponding to the actual circuit generated after module instantiation.

[0064] As mentioned above, critical signals include the main inputs and register outputs of the logic system design 300. Therefore, the compiler (not shown) can also determine the critical signals included in each instance. Figure 3 As shown, the compiler (not shown) can determine the critical signals 311-324 based on the description of the logic system design 300. Among them, critical signal 311 is signal c, and critical signal 319 is signal d.

[0065] Critical signals 311-324 can be divided into multiple signal groups. Each signal group can hold a given number of critical signals. Figure 3 In the example, each signal group can hold four signals. In some embodiments, signal groups can hold signals sequentially. Signal group 330 may include key signals 311-314, signal group 340 may include key signals 315-318, signal group 350 may include key signals 319-322, and signal group 360 may include key signals 323 and 324. It can be seen that key signals from different instances may be grouped into the same group. This ensures that each signal group holds as many key signals as possible without waste. In other embodiments, each signal group may include all key signals from one or more instances. This ensures the best correlation among key signals within each signal group, but may result in some idle signals. For example, under this rule, signal group 330 may lack sufficient space to accommodate the key signals of the next instance after including key signals 311-313, therefore key signals 314-316 will be placed in the next signal group.

[0066] It is understood that the method for dividing critical signals is not limited to the above example, and the above process occurs during the compile time phase. The information on the division of critical signals can be stored simultaneously in the host 100 and the hardware simulation tool 202.

[0067] During the simulation phase (or run time) of the logic system design 300, the host 100 can determine one or more target signals (e.g., signals a and b mentioned above) associated with the trigger based on the trigger.

[0068] The host 100 can further determine, based on the description of the logic system design, target key signals associated with one or more target signals (e.g., signals a and b mentioned above) among key signals 311-324. For example, the target key signals associated with signals a and b are signals 311 and 319 (i.e., signals c and d).

[0069] Since the host 100 has information on the division of key signals, the host 100 can determine one or more target signal groups corresponding to the target key signals 311 and 319 from multiple signal groups 330-360, namely, signal groups 330 and 350.

[0070] Figure 4 A schematic diagram of data transmission between a host 100 and a hardware emulation tool 202 according to an embodiment of this application is shown.

[0071] like Figure 4 As shown, based on the determined signal groups 330 and 350, the host 100 can send a signal value read request 401 to the hardware emulation tool 202. The signal value read request 401 may include information about the signal groups 330 and 350.

[0072] In this way, the hardware simulation tool 202 can select signal groups 330 and 350 from signal groups 330, 340, 350 and 360 composed of signals generated by the logic system design 300 according to the signal value reading request 401, and transmit the signal values ​​of signal groups 330 and 350 to the host 100.

[0073] Signal groups 330 and 350 can be selected by selector 403 based on signal value read request 401 (e.g., a selection signal generated via hardware emulation tool 202). In some embodiments, selector 403 may be part of FPGA 2026 on hardware emulation tool 202.

[0074] To avoid the selector 403 consuming excessive resources (e.g., FPGA 2026), the selector 403 may include a first-level selector and multiple second-level selectors.

[0075] Figure 5 A schematic diagram of the structure of selector 403 according to an embodiment of this application is shown.

[0076] like Figure 5As shown, selector 403 may include a first-level selector 501 and multiple (e.g., two) second-level selectors 503 and 505. Assuming each selector can perform a 2-to-1 selection operation, then... Figure 5 The two-level three-selector can complete the operation of selecting the target signal group from four signal groups.

[0077] Meanwhile, because the signals generated by the logic system design 300 in this embodiment are grouped, the resources consumed by the selector 403 are greatly reduced. It is understood that in some embodiments, the number of selectors 403 can choose (e.g., choosing 1 from 2 signal groups, 1 from 200 signal groups, or 1 from 2000 signal groups) can be determined based on the remaining resources of the FPGA 2026. The larger the number of selectors 403 can choose, the more resources they consume; simultaneously, a larger number of selectors 403 can support more signal groups, allowing for more detailed signal group division, thereby improving the accuracy of selecting the target signal and further reducing the amount of data transmission between the host 100 and the hardware emulation tool 202. Therefore, for a given number of critical signals, the number of selectors 403 is a compromise design based on the hardware resources of the hardware emulation tool 202. For example, the number of selectors 403 can be determined based on the remaining resources after the logic system design 300 is implemented on the FPGA 2026 (i.e., the aforementioned remaining resources).

[0078] Back Figure 4 The signal values ​​of the selected target signal groups 330 and 350 are transmitted to the host 100 via the selector 403. The host 100 can read the signal values ​​of one or more target signal groups from the hardware emulation tool 202 to process the trigger.

[0079] Compared to the traditional method of transmitting all signal values ​​to the host 100, the embodiments of this application can greatly reduce the amount of data transmission between the host 100 and the hardware simulation tool 202, improve the speed of trigger processing by the host 100, and thus improve the overall efficiency of the simulation system 200. At the same time, since the key signals are divided into multiple groups, the selection requirement of the selector 403 is reduced, and the resource requirements of the hardware simulation tool 202 are also reduced.

[0080] This application also provides a method for handling triggers during simulation logic design.

[0081] Figure 6 A flowchart of a method 600 for handling triggers during simulation logic design according to an embodiment of this application is shown. Method 600 can be, for example... Figure 2 The host 100 executes the following steps.

[0082] In step 602, host 100 enables hardware emulation tools (e.g., Figure 2 The hardware simulation tool 202) simulates the logic system design. The trigger (e.g., (a&b==1)) is related to the logic system design (e.g., Figure 3 The logic system design 300 associates one or more target signals (e.g., signals a and b). The logic system design includes multiple key signals (e.g., ...). Figure 3 The key signals 311-324), the multiple key signals are divided into multiple signal groups (e.g., Figure 3 Signal groups 330-360). The multiple key signals are divided into multiple signal groups according to the description of the logic system design. For example, the key signals of each instance are determined sequentially according to the tree structure (also known as a deep structure) of the logic system design, and are sequentially divided into multiple signal groups, such as... Figure 3 The description.

[0083] The key signals are used to reconstruct the logic system design. For example, the signal value of a key signal at a given clock cycle can be used to reconstruct the logic system design to that given clock cycle.

[0084] In step 604, target key signals associated with the one or more target signals are determined from the key signals according to the description of the logic system design (e.g., Figure 3 Signals 311 and 319).

[0085] In step 606, one or more target signal groups corresponding to the target key signal are determined from the plurality of signal groups (e.g., Figure 4 Target signal groups 330 and 350).

[0086] In step 608, the signal values ​​of the one or more target signal groups are read from the hardware emulation tool for processing the trigger. In some embodiments, reading the signal values ​​of the one or more target signal groups from the hardware emulation tool further includes: sending a signal value read request to the hardware emulation tool according to the one or more target signal groups (e.g., Figure 4 Signal value read request 401). A signal value read request can be used to indicate a target signal group and generate a selector (e.g., Figure 4 The selector 403 selects a signal. The selector 403 is used to select one or more target signal groups associated with the trigger from the plurality of signal groups according to the signal value read request and transmits the signal values ​​of the one or more target signal groups to the host.

[0087] This application also provides a hardware simulation tool (e.g., Figure 2The hardware simulation tool 202 may include: an interface connected to a host and used to receive signal value read requests from the host; a programmable logic device for implementing a logic system design, the logic system design including multiple key signals, the multiple key signals being divided into multiple signal groups, triggering association with one or more target signals of the logic system design; and a selector connected to the programmable logic device, used to select one or more target signal groups associated with the trigger from the multiple signal groups according to the signal value read request and transmit the signal values ​​of the one or more target signal groups to the host, the number of selections by the selector corresponding to the number of multiple signal groups.

[0088] The selector includes a primary selector and a plurality of secondary selectors connected to the primary selector.

[0089] The number of selectors selected is determined based on the remaining resources of the programmable logic device.

[0090] This application also provides an electronic device. The electronic device may be... Figure 1 The host 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 600.

[0091] This application also provides a non-transitory computer-readable storage medium. This non-transitory computer-readable storage medium stores a set of instructions for a computer, which, when executed, causes the computer to perform method 600.

[0092] The foregoing has described some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0093] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of this application as described above, which are not provided in the details for the sake of brevity.

[0094] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0095] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for handling triggers during simulation logic design, comprising: The hardware simulation tool simulates the logic system design, and the trigger is associated with one or more target signals of the logic system design, which includes multiple key signals and is divided into multiple signal groups. Based on the description of the logic system design, a target key signal associated with the one or more target signals is determined from the key signals; Among the plurality of signal groups, determine one or more target signal groups that correspond to the target key signal; as well as The signal values ​​of the one or more target signal groups are read from the hardware simulation tool for processing the trigger.

2. The method as described in claim 1, wherein, The multiple key signals are divided into multiple signal groups according to the description of the logic system design.

3. The method as described in claim 1, wherein, Reading the signal values ​​of the one or more target signal groups from the hardware simulation tool further includes: A signal value read request is sent to the hardware simulation tool based on one or more target signal groups.

4. The method of claim 1, wherein, The key signals are used to reconstruct the logic system design.

5. A hardware emulation tool, comprising: An interface for connecting to a host and for receiving signal value read requests from the host; A programmable logic device for implementing a logic system design, the logic system design including multiple key signals, the multiple key signals being divided into multiple signal groups, triggering association with one or more target signals of the logic system design; A selector connected to the programmable logic device is used to select one or more target signal groups associated with the trigger from the plurality of signal groups according to the signal value read request and transmit the signal values ​​of the one or more target signal groups to the host, wherein the number of selections by the selector corresponds to the number of the plurality of signal groups.

6. The hardware simulation tool as described in claim 5, wherein, The selector includes a primary selector and a plurality of secondary selectors connected to the primary selector.

7. The method of claim 5, wherein, The number of selectors selected is determined based on the remaining resources of the programmable logic device.

8. An electronic device comprising: Memory, used to store a set of instructions; And at least one processor configured to execute the set of instructions to cause the electronic device to perform the method as described in any one of claims 1-4.

9. A non-transitory computer-readable storage medium storing a set of instructions for a computer, which, when executed, causes the computer to perform the method as described in any one of claims 1-4.

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