Self-adaptive Lut Pack method and device based on comprehensive target

Abstract

The invention relates to the technical field of digital logic design, and discloses an adaptive Lut Pack method and device based on a comprehensive target, and the method comprises the steps: dynamically determining a currently designed LUT packaging scale and a number upper limit of dual-output LUT units; identifying a key module and a non-key module based on a hierarchical netlist reserved after integration and time sequence key evaluation; executing the first LUT packaging at the first packaging strength in the key module and at the second packaging strength in the non-key module; second LUT packaging is executed in the layout stage; storing function information of the merged original LUT and port mapping information between the merged original LUT and the DLUT; and performing reversible splitting operation on the packaged dual-output LUT unit in a layout wiring stage. According to the method and the device, a self-adaptive packaging strategy can be realized, so that a time sequence optimization space is reserved when resources are sufficient, the area efficiency is improved when the resources are insufficient, and self-adaptive balance between resource utilization and performance is realized.

Description

Technical Field

[0001] This disclosure relates to the field of digital logic design technology, and specifically to an adaptive LutPack method and apparatus based on a synthesis objective. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs), as high-performance reconfigurable computing platforms, have been widely used in various communication and computing scenarios. Their core logic resources mainly consist of Look-Up Tables (LUTs), which can implement arbitrary Boolean logic functions. To improve the resource utilization and operating efficiency of FPGAs, the industry generally adopts LUT Pack technology, which combines multiple logic-related or input-shared LUTs into the same physical unit (such as a dual-output LUT), thereby reducing logic resource consumption, reducing path latency, and optimizing routing structure.

[0003] However, relevant LUT packing methods typically rely on fixed or static heuristics during the synthesis phase to perform packing, such as merging as many LUTs as possible with the goal of optimizing area. This approach ignores the dynamic trade-off between resource utilization and circuit performance: over-packing may save area, but it can easily lead to increased routing congestion and critical path timing deterioration; under-packing, on the other hand, wastes resources and affects overall efficiency. Furthermore, packed LUT pairs are usually treated as indivisible rigid units during the placement and routing phase. Once located on the critical path, their fixed coupling structure further increases signal propagation delay, hindering timing convergence. Therefore, there is currently a lack of a mechanism that can dynamically adjust the packing strategy based on design utilization, timing conditions, and physical layout, making it difficult to achieve an adaptive balance among multiple objectives such as area, timing, and routing. Summary of the Invention

[0004] In view of this, this disclosure provides an adaptive Lut Pack method and apparatus based on comprehensive objectives to solve the problem of how to dynamically adjust the packing strategy according to design utilization, timing conditions and physical layout, and achieve adaptive balance among multiple objectives such as area, timing and routing.

[0005] This disclosure provides an adaptive Lut Pack method based on a comprehensive objective, the method comprising: The LUT resource utilization rate of the current design is obtained, and the LUT packing scale and the upper limit of the number of dual-output LUT units are dynamically determined based on the preset range to which the LUT resource utilization rate belongs. The packing scale is characterized by the minimum number of shared input pins required between the LUT pairs that are allowed to be packed, and the packing scale is negatively correlated with the LUT resource utilization rate. Based on the hierarchical netlist retained after synthesis and the time-criticality assessment, the critical and non-critical modules in the current design are identified. During the synthesis phase, based on the shared input signal relationship between logic units and distinguishing the criticality of modules, the first LUT packaging is performed in critical modules with a first packaging strength and in non-critical modules with a second packaging strength; wherein, the first packaging strength is lower than the second packaging strength. After the initial layout of the logic units is completed, a second LUT packing is performed during the layout phase based on the physical location information of the logic units and the relationship of shared input signals. When performing the first LUT packing and / or the second LUT packing, save the functional information of the original LUT being merged and the port mapping information between the original LUT being merged and the dual-output LUT unit; During the placement and routing phase, based on at least one of timing path information, routing congestion information, or signal fan-out distribution information, a reversible splitting operation is performed on the already packaged dual-output LUT unit to restore it to the original LUT.

[0006] This disclosure also provides an adaptive Lut Pack device based on a comprehensive objective, the device comprising: The scale determination module is used to obtain the LUT resource utilization rate of the current design and dynamically determine the LUT packing scale and the upper limit of the number of dual-output LUT units based on the preset range to which the LUT resource utilization rate belongs. The packing scale is characterized by the minimum number of shared input pins required between the LUT pairs that are allowed to be packed, and the packing scale is negatively correlated with the LUT resource utilization rate. The identification module is used to identify critical and non-critical modules in the current design based on the hierarchical netlist retained after synthesis and the timing criticality assessment. The first packaging module is used in the synthesis stage to perform the first LUT packaging with a first packaging strength in critical modules and a second packaging strength in non-critical modules, based on the shared input signal relationship between logic units and the criticality of modules; wherein the first packaging strength is lower than the second packaging strength. The second packaging module is used to perform a second LUT packaging based on the physical location information of the logic units and the relationship of shared input signals during the layout stage after the initial layout of the logic units is completed. The information management module is used to save the functional information of the original LUTs being merged and the port mapping information between the original LUTs being merged and the dual-output LUT units during the first LUT merging and / or the second LUT merging. The splitting module is used to perform a reversible splitting operation on the already packaged dual-output LUT unit during the placement and routing stage, based on at least one of timing path information, routing congestion information, or signal fan-out distribution information, to restore it to the original LUT.

[0007] This disclosure also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described adaptive Lut Pack methods based on a synthesis objective when executing the computer program.

[0008] This disclosure also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described adaptive Lut Pack methods based on a synthesis objective.

[0009] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described adaptive Lut Pack methods based on a synthesis objective.

[0010] In the adaptive LUT Pack method and apparatus based on comprehensive objectives disclosed in the above embodiments, an adaptive packing strategy can be achieved through dynamic evaluation based on the overall LUT resource utilization of the design. This preserves timing optimization space when resources are sufficient and improves area efficiency when resources are scarce, achieving an adaptive balance between resource utilization and performance. By combining hierarchical netlists and timing criticality assessment to identify critical modules and adopting a lower-intensity packing strategy in critical modules, targeted protection of timing critical paths is achieved. This effectively avoids the amplification effect of over-packing on critical path delay, significantly reduces signal delay, and improves timing margin.

[0011] Furthermore, by employing a secondary packaging mechanism based on stage information, the logical optimization of the synthesis stage is combined with the physical optimization of the placement stage, achieving a dual improvement in area efficiency and timing performance. Reversible splitting operations can restore independent LUTs in areas with timing violations or severe congestion, thereby improving critical path delay and routing resource utilization. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart illustrating an adaptive Lut Pack method based on a comprehensive objective, provided for embodiments of this disclosure; Figure 2 A schematic diagram illustrating the number of module shuttles for an adaptive Lut Pack method based on a comprehensive objective, provided in an embodiment of this disclosure; Figure 3 A schematic diagram illustrating the generation of a dual-output LUT cell using an adaptive Lut Pack method based on a synthesis objective, provided in an embodiment of this disclosure; Figure 4 A schematic diagram of dual-output LUT unit splitting for an adaptive Lut Pack method based on a synthesis objective provided in this disclosure embodiment; Figure 5 A schematic diagram illustrating the routing congestion situation before and after splitting an adaptive Lut Pack method based on a synthesis objective, provided in an embodiment of this disclosure; Figure 6 A schematic diagram of the structure of an adaptive Lut Pack device based on a comprehensive objective, provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0014] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0015] As a highly flexible and reconfigurable computing platform, FPGA has become the core carrier for realizing customized hardware acceleration in fields such as high-performance computing, communication acceleration, and artificial intelligence. Its basic logic unit (LUT) can implement arbitrary combinational logic functions, and the lookup table packing (LUT Pack) technology, as a key link in logic mapping and physical implementation, aims to merge multiple logic-related LUTs into the same physical unit (such as a dual-output LUT). The quality of its strategy directly determines the final area utilization, timing performance, and routing smoothness of the FPGA design.

[0016] In related technologies, the following are the mainstream LUT Pack processing solutions: 1. Static packaging strategy based on area priority: This approach prioritizes minimizing the number of LUTs used during the logic synthesis phase, employing fixed heuristic rules (e.g., merging as many LUT pairs with shared inputs as possible). This method is logically straightforward and is the default or commonly used strategy in most current synthesis tools, achieving a high compression ratio at the resource level.

[0017] 2. Conservative packaging strategy based on time-driven approach: This approach focuses on ensuring timing closure during the design process by setting strict constraints (e.g., merging only LUT pairs with very shallow logic depth or those entirely located on non-critical paths) to avoid introducing additional latency due to packaging. This method effectively reduces the negative impact on the critical path and is a common choice in timing-critical designs.

[0018] However, the aforementioned technologies exhibit the following inherent limitations when faced with modern FPGA designs that are large-scale, structurally complex, and have stringent performance requirements: 1. Under a static area-first strategy, the packing process is completely disconnected from the overall resource utilization and local timing criticality of the design. In designs with ample LUT resources, over-packing may save a small amount of area, but it unnecessarily increases logical coupling, leading to increased critical path delays and local routing congestion, thus creating potential timing convergence problems. Conversely, in highly resource-constrained designs, while this strategy can improve area utilization, its "one-size-fits-all" merging mode may generate a large number of DLUTs with large connection spans due to a lack of physical location considerations, which may exacerbate the difficulty of global routing and even lead to placement and routing failures.

[0019] 2. Under a conservative timing-driven strategy, although the critical path is protected, the overly stringent packaging conditions result in a large number of LUT pairs that could have been merged remaining unused, leading to low logic resource utilization. In resource-constrained designs, this may directly cause the design to be unimplementable on the target device, or result in suboptimal timing and power consumption due to intense resource contention after implementation.

[0020] More fundamentally, existing packaging technologies generally exhibit a "one-way solidification" characteristic. Once a LUT pair is packaged into a DLUT during the synthesis phase, it is treated as an indivisible rigid atomic unit in the subsequent place-and-route process. When this DLUT happens to be located on the critical path identified after the final place-and-route, or when unexpected routing congestion occurs in its area, existing processes lack any effective mechanism for internal decoupling or structural adjustment. They can only attempt to alleviate the problem through costly global optimization or manual intervention, severely limiting the ceiling of automatic design optimization.

[0021] Therefore, existing LUT Pack solutions are caught in a dilemma where it's difficult to balance area efficiency, timing performance, and routing quality. Static strategies cannot adapt to the differentiated needs of different design stages, while conservative strategies sacrifice resource efficiency. Both lack the intelligence to dynamically adjust based on design status and are limited by the irreversibility of the packing result. The industry urgently needs an adaptive LUT Pack method that can sense the overall design utilization, distinguish the timing criticality of modules, integrate logic and physical information, and support reversible adjustments later, in order to achieve a dynamic balance between area, timing, and routing, and fully unleash the performance and resource potential of FPGAs.

[0022] To address the aforementioned issues, various embodiments of this disclosure provide an adaptive LutPack method based on a synthesis objective. The method includes: obtaining the LUT resource utilization rate of the current design, and dynamically determining the LUT packing scale and the upper limit of the number of dual-output LUT units in the current design based on a preset interval to which the LUT resource utilization rate belongs; wherein the packing scale is characterized by the minimum number of shared input pins required between allowed packed LUT pairs, and the packing scale is negatively correlated with the LUT resource utilization rate; identifying critical and non-critical modules in the current design based on the hierarchical netlist retained after synthesis and timing criticality assessment; and during the synthesis stage, distinguishing module criticality based on the shared input signal relationship between logic units, and focusing on critical modules... The first LUT packaging is performed with a first packaging strength in the module and a second packaging strength in non-critical modules; wherein the first packaging strength is lower than the second packaging strength; after the initial layout of the logic units is completed, a second LUT packaging is performed during the layout stage based on the physical location information of the logic units and the relationship of shared input signals; during the first LUT packaging and / or the second LUT packaging, the functional information of the merged original LUT and the port mapping information between the merged original LUT and the dual-output LUT unit are saved; during the layout and routing stage, based on at least one of timing path information, routing congestion information or signal fan-out distribution information, a reversible splitting operation is performed on the packaged dual-output LUT unit to restore it to the original LUT.

[0023] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0024] To enable those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Please refer to Figure 1 , Figure 1 A flowchart illustrating an adaptive Lut Pack method based on a synthesis objective, provided for embodiments of this disclosure, is shown below. The method may include the following steps: Step S101: Obtain the LUT resource utilization rate of the current design, and dynamically determine the LUT packaging scale and the upper limit of the number of dual-output LUT units based on the preset range to which the LUT resource utilization rate belongs.

[0026] In this embodiment, LUT resource utilization can reflect the degree to which the current design occupies logic resources in the target FPGA device. Preferably, LUT resource utilization can be determined based on the ratio of the number of mapped LUTs to the total number of LUT resources available from the target device.

[0027] Packing criterion can refer to the criteria used in the adaptive LUT packing process to determine whether two LUTs are allowed to be merged. Preferably, this criterion can be embodied in engineering as a dynamically adjustable threshold parameter, and quantified by the minimum number of shared input pins required between LUT pairs that are allowed to be packed.

[0028] Furthermore, the packaging scale and LUT resource utilization can be negatively correlated. Specifically, when resource utilization is high, a more lenient packaging scale can be used to prioritize the feasibility of the design on the target device; when resource utilization is low, a more stringent packaging scale can be used to reserve more room for subsequent timing optimization.

[0029] A dual-output LUT unit (DLUT) can be a physically implemented lookup table logic unit with two independent output ports, capable of implementing the logic functions of two original LUTs in a single physical resource.

[0030] The upper limit on the number of DLUTs can serve as another constraint to prevent loss of placement and routing flexibility due to over-packaging. This upper limit can be set as a certain percentage of the total number of LUTs in the current design.

[0031] By combining the scale decision based on resource utilization with the dual constraints of quantity limits, the packaging strategy can be adaptively adjusted under different design scenarios.

[0032] Step S102: Based on the hierarchical netlist retained after synthesis and the timing criticality assessment, identify the critical and non-critical modules in the current design.

[0033] In this embodiment, a hierarchical netlist can refer to a circuit netlist that retains the modular hierarchical structure of the original design source code after logic synthesis.

[0034] The timing criticality assessment of hierarchical netlists can be used to analyze the impact of each module on the overall timing performance of the design.

[0035] Based on the above assessment, modules located on more critical paths or more sensitive to temporal convergence can be identified and classified as critical modules; the remaining modules are classified as non-critical modules.

[0036] Here, the identification results provide a basis for the subsequent implementation of differentiated LUT packaging strategies, which aim to adopt a more conservative packaging strategy for critical modules to prioritize timeliness, while adopting a more aggressive packaging strategy for non-critical modules to improve resource utilization efficiency.

[0037] Step S103: In the synthesis stage, based on the shared input signal relationship between logic units and distinguishing the criticality of modules, the first LUT packaging is performed in critical modules with a first packaging strength and in non-critical modules with a second packaging strength.

[0038] In this embodiment, the shared input signal relationship between logic units can refer to the connection topology characteristic that two or more LUTs receive signals from the same source as their inputs. This relationship can be an important basis for determining the logical correlation and merging value between LUTs.

[0039] Packing strength is defined as the strictness of LUT merging conditions; a lower value indicates stricter merging conditions and fewer allowed merging operations. In this step, the first packing strength set for critical modules is lower than the second packing strength set for non-critical modules, thus allowing fewer merging operations in critical modules.

[0040] Specifically, the first LUT packing can occur during the logic synthesis stage. Based on the identification results of step S102, the system first applies a first packing strength (i.e., a stricter merging condition) to critical modules and a second packing strength (i.e., a relatively lenient merging condition) to non-critical modules.

[0041] Based on this, the packing operation, according to the shared input signal relationship between logic units, filters and merges LUT pairs that meet the strength conditions applicable to the current module, thereby generating a dual-output LUT unit and updating the netlist. This process realizes differentiated processing of timing-critical regions and resource-optimized regions at the logic level.

[0042] Step S104: After the initial layout of the logic units is completed, a second LUT packaging is performed during the layout stage based on the physical location information of the logic units and the relationship of shared input signals.

[0043] In this embodiment, the physical location information of the logic unit can refer to the specific coordinates and relative distance of each logic unit on the FPGA chip plane after the initial layout is completed.

[0044] The second LUT packaging can occur during the layout stage of the physical design process. Its core objective is to further optimize the packaging result based on the obtained physical location information in order to achieve synergy between the logical structure and the physical implementation.

[0045] Specifically, the system re-evaluates the packability of LUTs during the layout phase. This evaluation is based not only on the logical correlation reflected by their shared input signals, but also on their physical proximity. As a result, LUT pairs that have logically shared input relationships and are physically close to each other are prioritized for merging.

[0046] Here, the above-mentioned packing strategy based on physical proximity can effectively reduce the internal wiring length of the dual-output LUT unit generated by packing and its connection distance with the external logic, thereby significantly reducing the signal propagation delay in the subsequent wiring stage and alleviating the risk of wiring congestion in local areas.

[0047] Step S105: When performing the first LUT packaging and / or the second LUT packaging, save the functional information of the original LUT being merged and the port mapping information between the original LUT being merged and the dual-output LUT unit.

[0048] In this embodiment, functional information can refer to abstract data used to fully define the logical behavior implemented by the original LUT. For example, functional information may specifically include, but is not limited to: the logical mapping relationship between the input signals of the original LUT and the input signals of the DLUT, or the truth table configuration of the internal lookup table of the original LUT.

[0049] During the packaging process, when one or more pairs of original LUTs are merged to generate a dual-output LUT unit, the functional information of these original LUTs and their port mapping information with the dual-output LUT unit are recorded synchronously and completely to ensure that the complete logical semantics of the original logic units are accurately archived.

[0050] The core purpose of preserving this information is to provide the necessary data foundation for potential splitting operations during the subsequent physical implementation phase. By retaining this original information, the system can, when necessary, accurately restore the specified dual-output LUT unit to its original LUT state before merging based on the archived functional and port mapping information, and reconstruct its connection with surrounding circuits, thereby creating the preconditions for dynamic optimization based on the actual physical layout and timing conditions.

[0051] Step S106: In the placement and routing stage, based on at least one of timing path information, routing congestion information, or signal fan-out distribution information, a reversible splitting operation is performed on the already packaged dual-output LUT unit to restore it to the original LUT.

[0052] In this embodiment, the timing path information may refer to the critical path list and its timing margin data extracted from the global timing analysis report of the design.

[0053] Routing congestion information can refer to statistical data on the ratio of routing resource utilization to demand within a chip area, which is fed back from the placement and routing tools.

[0054] Signal fan-out distribution information can refer to the physical location distribution of multiple receiving logic units loaded by a specific drive signal on the chip plane.

[0055] Based on at least one of the above information, the system dynamically evaluates the packaged dual-output LUT unit during the placement and routing stage to determine whether it becomes a bottleneck in the design implementation.

[0056] Specifically, when the unit is located on the critical path and causes a timing violation, when the cabling resource utilization rate in its area exceeds a preset congestion threshold, or when the physical locations of the logic units driven by its two output ports are too far apart, resulting in long connections, the system will trigger a reversible split operation for the unit.

[0057] Here, the reversible splitting operation can refer to the process of accurately decomposing and restoring the original LUT function information and port mapping information corresponding to the dual-output LUT unit, which is saved in step S105, into two independent LUTs before packaging. This process may include: The logic function of the original LUT is reconstructed based on the saved functional information; all input and output connections between the original LUT and surrounding circuits are restored based on the saved port mapping information; finally, the dual-output LUT unit is removed from the current netlist and replaced with two reconstructed original LUTs.

[0058] In the adaptive LUT Pack method and apparatus based on synthesis objectives disclosed in the above embodiments, an adaptive packing strategy can be implemented through dynamic evaluation based on the overall LUT resource utilization of the design. This preserves timing optimization space when resources are sufficient and improves area efficiency when resources are scarce, achieving an adaptive balance between resource utilization and performance. By combining hierarchical netlists and timing criticality assessment to identify critical modules and adopting a lower-intensity packing strategy in critical modules, targeted protection of timing critical paths is achieved, effectively avoiding the amplification effect of over-packing on critical path delay, significantly reducing signal delay, and improving timing margin. Through a secondary packing mechanism based on stage information, the logical optimization of the synthesis stage and the physical optimization of the placement stage are combined to achieve a dual improvement in area efficiency and timing performance. The reversible splitting operation can restore independent LUTs in areas with timing violations or severe congestion, thereby improving critical path delay and cabling resource utilization.

[0059] In one possible implementation of step S101 above, the LUT packaging scale of the current design is dynamically determined based on the preset range to which the LUT resource utilization belongs, including: Preset first utilization threshold With the second utilization threshold ,in, ; When LUT resource utilization is less than When the LUT is identified as a low-utilization range, the LUT packaging operation is skipped. When LUT resource utilization is not less than and less than When the utilization rate is determined to be in the medium range, the corresponding packaging scale requires that the number of shared input pins between LUT pairs is not less than the first value. ; When LUT resource utilization is not less than When a high utilization range is identified, the corresponding packaging scale requires that the number of shared input pins between LUT pairs be no less than the second value. ;in, .

[0060] In this embodiment, the first utilization threshold With the second utilization threshold These can be preset system parameters used to determine the continuous LUT resource utilization (using...). The numerical range of (represented) is divided into three decision intervals: low utilization interval, medium utilization interval, and high utilization interval.

[0061] Specifically, in the low utilization rate range ( At this point, logic resources are relatively abundant. Performing a packing operation at this time has a low marginal benefit in terms of area saving, but may unnecessarily increase the logic coupling, thereby bringing potential risks to timing and routing.

[0062] Therefore, the LUT packing operation can be skipped in this interval to fully preserve the original netlist structure, providing maximum flexibility for timing optimization in the subsequent placement and routing phase.

[0063] In the medium utilization range ( At this point, resource usage is under control, and LUT packing can be enabled within this range. However, a relatively conservative strategy is adopted, namely, setting a high requirement for the number of shared input pins (i.e., the number of shared input pins ≥ a first value). That is, if and only if the number of shared input pins between the two LUTs is not less than a first value. Only when this condition is met is it considered a pair that can be packaged.

[0064] Here, the strategy ensures that only LUT pairs with highly overlapping inputs and close logical connections are merged. This effectively improves resource utilization while strictly limiting the additional logic depth and routing complexity introduced by packing, thus achieving a balance between area optimization and performance maintenance.

[0065] In the high utilization rate range ( At this point, the design faces resource constraints and shifts to a more aggressive packaging strategy, namely relaxing the shared input requirements (the number of shared input pins ≥ the second value). ,and That is, when the number of shared input pins between two LUTs is not less than the second value. At that time, it was determined that it met the conditions for packaging.

[0066] This strategy aims to maximize the potential of LUT merging, generating as many dual-output LUT units as possible to significantly reduce the total logic resource consumption.

[0067] In the adaptive Lut Pack method and apparatus based on comprehensive objectives in the above embodiments of this disclosure, a preset utilization threshold is used. and The design state is quantified into three distinct ranges: low, medium, and high. Each range is then associated with a specific packaging operation, ensuring that the packaging intensity precisely matches the actual resource constraints of the design. This is achieved by setting higher shared pin requirements for the medium utilization range. This ensures that during this resource-controllable phase, only logically highly overlapping LUT pairs are merged, effectively improving area efficiency while minimizing potential negative impacts on timing. This is achieved by setting more lenient conditions for high-utilization intervals (…). This allows for maximum logic compression when resources are scarce, prioritizing the feasibility of the design.

[0068] In one possible implementation of step S102 above, based on the hierarchical netlist retained after synthesis and the timing criticality assessment, critical and non-critical modules in the current design are identified, including: Count the number of times the critical path traverses each module of the hierarchical netlist in the current design; The criticality of each module is sorted according to the number of shuttles. Modules with more than a preset threshold number of shuttles are identified as critical modules, and the rest are identified as non-critical modules.

[0069] In this embodiment, the critical path can refer to the complete signal path identified in the design timing analysis report that has the largest propagation delay (i.e., the timing margin is negative or minimal) between the start register and the end register.

[0070] The number of shuttle trips can refer to the number of times a critical path crosses (i.e., enters and then leaves) the boundary of a specific module during its journey from the origin to the destination.

[0071] By traversing and counting all critical paths in the design, and accumulating the total number of times each module is traversed, the module criticality can be obtained, which reflects the temporal criticality of the module.

[0072] Please refer to Figure 2 , Figure 2 A schematic diagram illustrating the module shuttle count of an adaptive Lut Pack method based on a comprehensive objective, provided in an embodiment of this disclosure, is shown below. Figure 2 As shown: Module A has 5 shuttle trips, Module B has 4 shuttle trips, and Modules C and D have 2 shuttle trips.

[0073] Furthermore, it is determined whether the number of shuttle trips for each module exceeds a preset threshold.

[0074] Here, the preset number of times threshold can be a configurable system parameter that can be used to define the decision boundaries of key modules.

[0075] Specifically, all modules are sorted in descending order based on the cumulative number of shuttle trips, and modules with a cumulative number of shuttle trips greater than the threshold are identified as key modules.

[0076] For example, continue with Figure 2 For example, assuming the preset threshold for the number of times is 3, then modules A and B are critical modules, while modules C and D are non-critical modules.

[0077] Furthermore, for critical modules, the LUT packing operation can be appropriately reduced to avoid increased logic coupling and amplified timing delays due to excessive packing; for non-critical modules, the conventional packing strategy can be maintained, prioritizing the merging of LUT pairs with more shared inputs to improve area utilization efficiency.

[0078] Here, through this differentiated control, the global packaging strategy can dynamically achieve a balance between area saving and timing optimization.

[0079] In the adaptive LUT Pack method and apparatus based on comprehensive objectives disclosed in the above embodiments, the abstract timing criticality is transformed into a specific, calculable numerical indicator (i.e., the number of shuttles) by statistically analyzing the traversal frequency of modules along the critical path. This eliminates the uncertainty and inconsistency of subjective judgments based on experience or heuristic rules in traditional methods, thereby providing an objective and quantifiable criticality evaluation standard. Applying lower packing intensity to the identified critical modules allows the limited timing optimization margins resulting from not packing or packing less to be concentrated on the modules with the greatest impact on global timing. This resource allocation based on criticality ranking maximizes the positive impact of the packing strategy on overall timing performance under given resource constraints.

[0080] In one possible implementation of step S103 above, during the synthesis stage, based on the shared input signal relationship between logic units and distinguishing the criticality of modules, the first LUT packaging is performed with a first packaging strength in critical modules and a second packaging strength in non-critical modules, including: Based on the shared input signal relationships between logical units within each module of the hierarchical netlist, a set of candidate LUT pairs is generated. Based on the LUT packing scale and according to the criticality of the module, LUT pairs that meet the conditions are selected from the candidate LUT pair set and merged to generate dual-output LUT cells, and the circuit netlist is updated. Specifically, LUT pairs in critical modules are screened using a first packaging strength, while LUT pairs in non-critical modules are screened using a second packaging strength.

[0081] In this embodiment, the hierarchical netlist is divided into multiple logical modules.

[0082] The candidate LUT pair set can be generated by traversing the logical connections within each module and identifying the initial set of all LUT pairs that share at least one input signal source.

[0083] Shared input signal relationships can characterize the logical correlation between LUTs and can serve as a basis for evaluating the merging value between LUTs.

[0084] Furthermore, in large-scale designs, the number of candidate LUT pairs can be enormous, and each LUT can only be merged once in this packaging process. Therefore, selecting the LUT pairs to be merged from the candidate set can be a problem that requires finding the optimal or near-optimal combination under given constraints.

[0085] In this embodiment, graph matching algorithms, heuristic search algorithms, or combinations thereof can be used to solve the problem. The goal is to maximize the number of valid merges that meet the screening criteria, thereby improving the overall utilization of logical resources.

[0086] Specifically, the screening process follows a two-stage decision-making process, which may include: Phase 1 involves initial screening based on the global resource status.

[0087] Here, based on the LUT packing scale (i.e., minimum number of shared input pins) determined in step S101 that is applicable to the current design, such as... This stage involves initial screening of all candidate LUT pairs. Only candidate pairs with a shared input pin count of at least this scale will proceed to further evaluation. This phase ensures that the packing operation matches the overall resource utilization of the design.

[0088] Phase Two involves differentiated optimization based on module criticality.

[0089] Here, based on the module criticality identified in step S102, a differentiated second screening is applied to the candidate pairs that have passed the first screening, including: For candidate LUT pairs located within critical modules, the first packing strength can be used for screening.

[0090] According to the definition in step S103, the lower the packing strength value, the more stringent the merging conditions. Since the first packing strength is lower than the second packing strength, setting the first packing strength for the critical module means applying more stringent additional merging conditions.

[0091] For example, when the minimum number of shared pins has been met ( Based on this, it may be necessary to further require a shorter logic depth or a stricter input port overlap ratio, thereby reducing the number of LUT pairs that are actually allowed to be merged in critical modules.

[0092] For candidate LUT pairs located in non-critical modules, a second packing strength can be used for screening.

[0093] As defined in step S103, the second packing strength is higher than the first packing strength, corresponding to a relatively lenient merging condition. This allows for a more lenient or no-additional-strict conditions to be applied while still meeting the same minimum shared pin count, thus enabling a greater number of LUT pairs to be merged in non-critical modules.

[0094] Furthermore, after the screening is completed, the system performs a merging operation on the finally determined LUT pairs, creates dual-output LUT cells, and updates the circuit netlist accordingly to reflect the new logic cells and their connection relationships.

[0095] In the adaptive Lut Pack method and apparatus based on synthesis objectives in the above embodiments of this disclosure, through the aforementioned two-stage screening mechanism, the system applies strict merging conditions primarily to critical modules, effectively suppressing the packing density in this region and preserving decoupled circuit structures for critical paths to optimize timing. Simultaneously, lenient merging conditions are primarily applied to non-critical modules, improving the logic compression rate in this region to achieve area optimization. This enables the differentiated allocation of packing resources based on the timing criticality of modules within the same design.

[0096] In one possible implementation of step S104 above, after the initial layout of the logic units is completed, a second LUT packing is performed during the layout stage based on the physical location information of the logic units and the relationship of shared input signals, including: From the candidate LUT pair set, select LUT pairs that simultaneously meet the following two conditions: The physical distance between the two LUTs is less than a preset distance threshold; and the number of shared input signals between the two LUTs is not less than a preset number threshold. LUT pairs that meet both conditions are merged to generate a dual-output LUT unit.

[0097] In this embodiment, the physical location information of the logic unit can refer to the coordinate data of each LUT on the FPGA chip plane after the initial layout is completed. The physical distance between two LUTs can refer to the Manhattan distance or Euclidean distance calculated based on the coordinate data.

[0098] The preset distance threshold can be a parameter pre-set based on chip size and layout uniformity. It is used to determine whether two LUTs are close enough in physical location to ensure that merging them into a dual-output LUT unit will not result in excessively long internal interconnects or unreasonable layout shapes.

[0099] The number of shared input signals can refer to the number of input signal lines commonly connected to both LUTs in a candidate LUT pair. The preset threshold can be an independently set parameter used during the placement phase to determine whether the logical associativity of the LUT pair is high enough for merging. It is worth noting that this preset threshold can be related to the packing scale determined in step S101 (i.e., determined based on resource utilization). or The same applies, but it can also be set independently according to the specific optimization goals of the layout stage.

[0100] Specifically, the second LUT packaging may include the following steps: Step a1: Obtain the candidate set.

[0101] Here, the candidate set can reuse the candidate LUT pair set generated in step S103, or the candidate pairs can be regenerated based on the netlist after layout.

[0102] Step a2, physical proximity screening.

[0103] Here, the physical distance between each pair of candidate LUTs can be calculated, and candidate pairs with a distance less than a preset distance threshold can be selected.

[0104] Step a3: Filter logical relationships.

[0105] Here, among the candidate pairs filtered by physical proximity, candidate pairs with a shared input signal number not less than a preset threshold can be further filtered out.

[0106] Step a4, merge operation.

[0107] Here, a merge operation is performed on LUT pairs that simultaneously meet the above two conditions to generate dual-output LUT cells and update the netlist.

[0108] Furthermore, the second packaging occurs during the layout phase, and its optimization objectives differ from the first packaging during the synthesis phase. While the first packaging primarily focuses on resource utilization at the logical level, the second packaging, based on existing layout information, further pursues the quality of the physical implementation.

[0109] By introducing physical distance constraints, the merged dual-output LUT units can be more compact in layout, thereby reducing the length and complexity of subsequent wiring, which helps improve timing and alleviate congestion. By constraining the number of shared input signals, the logical rationality of the merging operation is guaranteed, avoiding resource waste or functional errors caused by forcibly merging physically close but logically unrelated LUTs.

[0110] In the adaptive LUT Pack method and apparatus based on synthesis objectives disclosed in the above embodiments, by setting a physical distance threshold, the forced merging of LUTs that are physically far apart can be actively avoided, fundamentally eliminating the possibility of generating "cross-region" DLUTs. This avoids long-distance, high-fanout global interconnects caused by a single DLUT driving loads distributed across different areas of the chip, significantly reducing the resulting timing degradation and routing congestion risks. Through independently configurable physical distance and sharing quantity thresholds, this method can flexibly adapt to different layout strategies and design constraints. For designs pursuing high performance and low latency, a smaller distance threshold can be used to ensure extreme localization of merging; for designs with extremely limited area, the distance threshold can be appropriately relaxed to explore more merging opportunities, thereby enhancing the adaptability of the packing strategy.

[0111] In one possible implementation of step S104 above, LUT pairs that satisfy the two conditions are merged to generate a dual-output LUT unit, including: Create a dual-output LUT unit; The shared input pins of the LUT pair are combined into one input port of the dual-output LUT unit; The non-shared input pins of the LUT pair are used as independent input ports of the dual-output LUT unit; Based on the logical function of the LUT pair, generate the truth table corresponding to the dual-output LUT unit. Update the circuit netlist, point the input connections of the original LUT pair to the corresponding input ports of the dual-output LUT unit, and redirect the output load connections of the original LUT pair to the two output ports of the dual-output LUT unit; During the merging process, the original types of the LUT pairs, the port mapping relationships between the LUT pairs and the dual-output LUT units, and the truth tables of the LUT pairs are saved to an intermediate file.

[0112] In this embodiment, the merging operation can be a process of integrating two independent LUTs into a single physical unit at the netlist level, and its specific implementation may include the following steps: Step b1, cell creation.

[0113] Here, a new dual-output LUT (DLUT) with sufficient input capacity is instantiated in the hierarchical netlist.

[0114] Step b2, Input port integration.

[0115] In step b21, shared pins are merged.

[0116] Here, all input signals commonly connected to the two original LUTs are identified. In the DLUT, these signals are connected to the same physical input pin. This operation reduces the total number of input pins in the DLUT, reflecting the logical interdependencies between the original LUTs.

[0117] Step b22, independent pin assignment.

[0118] Here, the unique input signals of the two original LUTs are mapped to the remaining different input pins of the DLUT, ensuring that all original input signals have their corresponding connection points in the DLUT.

[0119] Step b3, implementation of logical functions (generation of truth table).

[0120] Based on the logical behavior defined by the original truth tables of the two original LUTs, a new, unified truth table is calculated and constructed, which is configured within the DLUT. This new truth table defines the mapping relationship between the two outputs of the DLUT and all the inputs after integration, and its function must be strictly equivalent to the sum of the logical behaviors of the original two independent LUTs.

[0121] Step b4, Netlist Update and Connection Redirection: In step b41, the input side is updated.

[0122] Reconnect all the signal lines that originally drove the two original LUT input pins in the circuit to the corresponding input ports of the DLUT.

[0123] Step b42, update the output side.

[0124] The inputs of all subsequent logic units that were originally driven by the outputs of these two original LUTs are redirected to the two corresponding output ports of the DLUT.

[0125] Step b5: Save metadata.

[0126] While performing the aforementioned physical and logical merging, the system synchronously saves a set of key metadata to an intermediate file (or database). This metadata includes at least: the original LUT type, port mapping relationships, and the original truth table.

[0127] In one embodiment, please refer to Figure 3 , Figure 3 A schematic diagram illustrating the generation of a dual-output LUT unit using an adaptive LUT Pack method based on a synthesis objective, as provided in this disclosure embodiment, is shown below. Figure 3 As shown: Figure 3The left side shows a pair of candidate original LUTs that logically share inputs, including a 6-input LUT (LUT6) and a 5-input LUT (LUT5), each with independent input pins (such as inputs 10-15 of LUT6 and inputs 11-15 of LUT5) and independent outputs.

[0128] The right side of the figure shows a dual-output lookup table (DLUT) unit generated by merging the two original LUT pairs described above. Its generation logic may include: input signals shared between the two original LUTs (inputs 11-15 in the figure) are merged into a single physical input port in the DLUT, thereby reducing the total number of input pins; The two original LUTs' non-shared (exclusive) input signals (such as input 10 of LUT6) are retained as independent input ports in the DLUT, ensuring the integrity of the original logic function; The original single outputs of the two LUTs are integrated into two independent output ports of the DLUT (i.e., O_1 and O_2). Inside the DLUT, a new, unified internal logic configuration is generated based on the truth tables of the two original LUTs, so that the two outputs (O_1 and O_2) are functionally strictly equivalent to the outputs of the original two independent LUTs.

[0129] In the adaptive LUT Pack method and apparatus based on synthesis objectives as described in the above embodiments of this disclosure, by saving the functional information and port mapping information of the original LUT during packing, selective splitting can be determined based on physical location, routing congestion level, or critical path during the placement and routing stage, ensuring the reversibility of the packing operation. By systematically redirecting the input connections and output loads of the original circuit to the newly generated dual-output LUT unit, correct and seamless integration of the new unit with the entire circuit netlist is achieved, ensuring that the packing operation does not compromise the logical correctness and connection integrity of the design.

[0130] In one embodiment, please refer to Figure 4 , Figure 4 A schematic diagram of dual-output LUT unit splitting for an adaptive LUT Pack method based on a synthesis objective, provided in an embodiment of this disclosure, is shown below. Figure 4 As shown: Figure 4 The left side shows a merged dual-output lookup table unit, which has a set of merged input pins (e.g., inputs 10-15) and two independent output ports (O_1 and O_2). This DLUT is formed by merging two original LUTs during the aforementioned packaging process, and its internal logic configuration ensures that the two outputs functionally correspond to the logical behavior of the original two LUTs respectively.

[0131] Figure 4 The right side shows the process of unpacking the DLUT and restoring it to its original two independent LUTs, specifically including: Based on the metadata information (including the original LUT type, port mapping relationship and truth table) saved during the packaging stage, the merged input of the DLUT is re-separated into the input pin sets of the original two LUTs; Restore the original LUT's independent output port and re-establish its correct connection with downstream logic; Based on the saved truth table information, the original logic functions of the two split LUTs are restored respectively, ensuring the consistency of circuit functions before and after splitting. Update the connection information in the netlist so that subsequent placement and routing processes can be optimized based on the split individual LUTs.

[0132] Furthermore, the triggering of DLUT splitting can be based on the following physical and timing judgment criteria: critical path timing constraints, wiring congestion, signal fan-out and distribution.

[0133] For critical path timing constraints, the top n critical paths in the design can be calculated, and the DLUTs on these paths can be split to reduce combinational logic depth and signal delay. For routing congestion, in the layout and routing analysis, if the routing utilization rate of a certain DLUT's area exceeds a preset threshold (e.g., exceeding 80% of local routing resources), the DLUT is split to distribute fan-out connections and alleviate routing pressure.

[0134] Please refer to this. Figure 5 , Figure 5 A schematic diagram illustrating the routing congestion situation before and after splitting of an adaptive LutPack method based on a synthesis objective, provided in an embodiment of this disclosure, is shown below. Figure 5 As shown, before the DLUT is split (i.e., before unpack), the wiring utilization in the area where the DLUT is located is too high. Figure 5 (The black area in the middle on the left); and after the DLUT is split (i.e., after unpacking), the cabling utilization rate of the area where the DLUT is located is greatly reduced.

[0135] For signal fan-out and distribution, if the two outputs of the DLUT drive logic units that are located in different physical locations, retaining the DLUT will result in long-distance cross-regional connections. In this case, splitting it into two LUTs and placing them in different locations can reduce the complexity of global routing.

[0136] In one embodiment, an adaptive LUT Pack device 600 based on a comprehensive objective is provided, which corresponds one-to-one with the adaptive LUT Pack method based on a comprehensive objective in the above embodiments. For example... Figure 6 As shown, the system includes: The scale determination module 601 is used to obtain the LUT resource utilization rate of the current design, and dynamically determine the LUT packing scale and the upper limit of the number of dual-output LUT units of the current design based on the preset range to which the LUT resource utilization rate belongs; wherein, the packing scale is characterized by the minimum number of shared input pins required between the LUT pairs that are allowed to be packed, and the packing scale is negatively correlated with the LUT resource utilization rate. The identification module 602 is used to identify critical and non-critical modules in the current design based on the hierarchical netlist retained after synthesis and the timing criticality assessment. The first packaging module 603 is used in the synthesis stage to perform the first LUT packaging with a first packaging strength in critical modules and a second packaging strength in non-critical modules, based on the shared input signal relationship between logic units and the criticality of modules; wherein the first packaging strength is lower than the second packaging strength. The second packaging module 604 is used to perform a second LUT packaging based on the physical location information of the logic units and the relationship of shared input signals during the layout stage after the initial layout of the logic units is completed. The information management module 605 is used to save the functional information of the original LUT being merged and the port mapping information between the original LUT being merged and the dual-output LUT unit when performing the first LUT packaging and / or the second LUT packaging. The splitting module 606 is used to perform a reversible splitting operation on the already packaged dual-output LUT unit during the placement and routing stage, based on at least one of timing path information, routing congestion information, or signal fan-out distribution information, to restore it to the original LUT.

[0137] In one embodiment, the scale determination module 601 is specifically used to preset a first utilization threshold. With the second utilization threshold ,in, ; When LUT resource utilization is less than When the LUT is identified as a low-utilization range, the LUT packaging operation is skipped. When LUT resource utilization is not less than and less than When the utilization rate is determined to be in the medium range, the corresponding packaging scale requires that the number of shared input pins between LUT pairs is not less than the first value. ; When LUT resource utilization is not less than When a high utilization range is identified, the corresponding packaging scale requires that the number of shared input pins between LUT pairs be no less than the second value. ;in, .

[0138] In one embodiment, the identification module 602 is specifically used to count the number of times the critical path in the current design traverses each module of the hierarchical netlist; The criticality of each module is sorted according to the number of shuttles. Modules with more than a preset threshold number of shuttles are identified as critical modules, and the rest are identified as non-critical modules.

[0139] In one embodiment, the first packaging module 603 is specifically used to generate a set of candidate LUT pairs based on the shared input signal relationship between logical units within each module of the hierarchical netlist; Based on the LUT packing scale and according to the criticality of the module, LUT pairs that meet the conditions are selected from the candidate LUT pair set and merged to generate dual-output LUT cells, and the circuit netlist is updated. Specifically, LUT pairs in critical modules are screened using a first packaging strength, while LUT pairs in non-critical modules are screened using a second packaging strength.

[0140] In one embodiment, the second packaging module 604 is specifically used to filter out LUT pairs from the candidate LUT pair set that simultaneously meet the following two conditions: The physical distance between the two LUTs is less than a preset distance threshold; and the number of shared input signals between the two LUTs is not less than a preset number threshold. LUT pairs that meet both conditions are merged to generate a dual-output LUT unit.

[0141] In one embodiment, the second packaging module 604 is specifically used to create a dual-output LUT unit; The shared input pins of the LUT pair are combined into one input port of the dual-output LUT unit; The non-shared input pins of the LUT pair are used as independent input ports of the dual-output LUT unit; Based on the logical function of the LUT pair, generate the truth table corresponding to the dual-output LUT unit. Update the circuit netlist, point the input connections of the original LUT pair to the corresponding input ports of the dual-output LUT unit, and redirect the output load connections of the original LUT pair to the two output ports of the dual-output LUT unit; During the merging process, the original types of the LUT pairs, the port mapping relationships between the LUT pairs and the dual-output LUT units, and the truth tables of the LUT pairs are saved to an intermediate file.

[0142] It should be noted that the adaptive LUT Pack device based on the synthesis objective provided in the above embodiments is only illustrated by the division of the above program modules when implementing the corresponding adaptive LUT Pack method based on the synthesis objective. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above device can be divided into different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the corresponding Figure 1 The embodiments of the methods shown belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0143] This disclosure also provides an electronic device having the above-described features. Figure 6 The adaptive Lut Pack device based on the integrated objective is shown.

[0144] Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure.

[0145] The following is a detailed reference. Figure 7 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present disclosure. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 701, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 702 or a program loaded from memory 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the electronic device. The processor 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0146] Typically, the following devices can be connected to I / O interface 705: input devices 706 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 707 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 708 including, for example, magnetic tapes, hard disks, etc.; and communication devices 709. Communication device 709 allows electronic devices to exchange data via wireless or wired communication with other devices. Although Figure 7 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0147] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 709, or installed from memory 708, or installed from ROM 702. When the computer program is executed by processor 701, it performs the functions defined in the network data stream hardware offloading method for heterogeneous descriptor unified processing of embodiments of this disclosure.

[0148] Figure 7 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0149] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the network data stream hardware offloading method for unified processing of heterogeneous descriptors shown in the above embodiments is implemented.

[0150] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0151] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A synthesis target-based adaptive Lut Pack method, characterized by, The method comprises: acquiring LUT resource utilization of a current design, and dynamically determining LUT packing scale and upper limit of the number of double-output LUT units of the current design based on a preset interval to which the LUT resource utilization belongs; wherein the packing scale is represented by the minimum number of shared input pins required between LUT pairs allowed to be packed, and the packing scale is negatively correlated with the LUT resource utilization; identifying critical modules and non-critical modules in the current design based on a retained hierarchical netlist after synthesis and timing criticality evaluation; performing first LUT packing in the critical modules with a first packing strength and in the non-critical modules with a second packing strength based on shared input signal relationships between logic units and distinguishing module criticality in a synthesis stage; wherein the first packing strength is lower than the second packing strength; performing second LUT packing based on physical location information of the logic units and shared input signal relationships in a layout stage after completing preliminary layout of the logic units; saving function information of original LUTs that are merged and port mapping information between the original LUTs and double-output LUT units during the first LUT packing and / or the second LUT packing; performing reversible splitting operation on the double-output LUT units formed after packing based on at least one of timing path information, routing congestion information or signal fan-out distribution information in a layout and routing stage to restore the original LUTs.

2. The method of claim 1, wherein, The dynamically determining LUT packing scale of the current design based on the preset interval to which the LUT resource utilization belongs comprises: a first utilization threshold a second utilization threshold wherein ; when the LUT resource utilization is less than a low utilization interval is determined, and a LUT packing operation is skipped. When the LUT resource utilization is not less than and less than , it is determined as a medium utilization interval, and the corresponding packing scale requires that the number of shared input pins between LUT pairs is not less than a first value . When the LUT resource utilization is not less than , it is determined as a high utilization interval, and the corresponding packing scale requires that the number of shared input pins between LUT pairs is not less than a second value ; wherein .

3. The method of claim 1, wherein, The identifying critical modules and non-critical modules in the current design based on the retained hierarchical netlist after synthesis and the timing criticality evaluation comprises: counting the number of times of shuttling of a critical path in each module in the hierarchical netlist; sorting the criticality of each module according to the number of times of shuttling, identifying a module with a number of times of shuttling greater than a preset number of times threshold as a critical module, and identifying the remaining modules as non-critical modules.

4. The method of claim 1, wherein, The performing first LUT packing in the critical modules with a first packing strength and in the non-critical modules with a second packing strength based on shared input signal relationships between logic units and distinguishing module criticality in a synthesis stage comprises: generating a candidate LUT pair set according to shared input signal relationships between logic units in each module of the hierarchical netlist; merging LUT pairs that meet conditions from the candidate LUT pair set based on LUT packing scale and according to module criticality to generate double-output LUT units and update a circuit netlist; wherein the first packing strength is used for screening LUT pairs in critical modules, and the second packing strength is used for screening LUT pairs in non-critical modules.

5. The method of claim 4, wherein, The performing second LUT packing based on physical location information of the logic units and shared input signal relationships in a layout stage after completing preliminary layout of the logic units comprises: screening LUT pairs that meet the following two conditions from the candidate LUT pair set: a physical distance between two LUTs is less than a preset distance threshold; and a number of shared input signals between two LUTs is not less than a preset number threshold; the LUT pair satisfying the two conditions is merged to generate a dual-output LUT unit.

6. The method of claim 5, wherein, The LUT pair satisfying the two conditions is merged to generate a dual-output LUT unit, including: a dual-output LUT unit is created; shared input pins of the LUT pair are merged into one input port of the dual-output LUT unit; non-shared input pins of the LUT pair are taken as independent input ports of the dual-output LUT unit respectively; a corresponding truth table inside the dual-output LUT unit is generated according to a logic function of the LUT pair; a circuit netlist is updated, input connection of the original LUT pair is directed to a corresponding input port of the dual-output LUT unit, and output load of the original LUT pair is redirected to two output ports of the dual-output LUT unit; wherein, when the merging is performed, original types of the LUT pair, port mapping relationship between the LUT pair and the dual-output LUT unit, and the truth table of the LUT pair are saved to an intermediate file.

7. An adaptive Lut Pack device based on an integrated target, characterized in that, The apparatus includes: a scale determination module configured to obtain LUT resource utilization of a current design, and dynamically determine a LUT packing scale of the current design and an upper limit of a number of dual-output LUT units based on a preset interval to which the LUT resource utilization belongs; wherein the packing scale is represented by a minimum number of shared input pins required between LUT pairs allowed to be packed, and the packing scale is negatively correlated with the LUT resource utilization; an identification module configured to identify critical modules and non-critical modules in the current design based on a hierarchical netlist reserved after synthesis and timing criticality evaluation; a first packing module configured to perform a first LUT packing in the critical modules at a first packing strength and in the non-critical modules at a second packing strength based on shared input signal relationships between logic units and module criticality in a synthesis stage; wherein the first packing strength is lower than the second packing strength; a second packing module configured to perform a second LUT packing based on physical location information of the logic units and the shared input signal relationships in a layout stage after completing preliminary layout of the logic units; an information management module configured to save function information of original LUTs that are merged and port mapping information between the original LUTs that are merged and dual-output LUT units when the first LUT packing and / or the second LUT packing is performed; a splitting module configured to perform reversible splitting operation on the dual-output LUT units formed after packing based on at least one of timing path information, routing congestion information or signal fan-out distribution information in a layout and routing stage, to restore to original LUTs.

8. An electronic device, comprising: include: a memory configured to store a computer program; a processor configured to implement steps of the adaptive Lut Pack method based on a synthesis target according to any one of claims 1 to 6 when the computer program is executed.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps of the adaptive Lut Pack method based on the comprehensive target according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the adaptive Lut Pack method based on the comprehensive target according to any one of claims 1 to 6.

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