Asynchronous dual-port memory and real-time digital phase shifter system
By combining an asynchronous dual-port memory and a real-time digital phase shifter system with a Gray code counter and a clock domain crossover module, the asynchronous operation and data consistency issues of synchronous dual-port memory in multi-channel real-time digital phase shifter systems are solved, achieving efficient and stable data access and low latency, thus meeting the real-time and high-precision requirements of modern multi-channel systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING JIEXI TECH CO LTD
- Filing Date
- 2025-11-11
- Publication Date
- 2026-04-10
AI Technical Summary
Existing dual-port memory and asynchronous access technologies in multi-channel real-time digital phase shifter systems suffer from several problems: synchronous dual-port memory cannot support asynchronous operation, multi-channel dynamic access time slot allocation and data consistency are insufficient, and complex clock management and signal synchronization mechanisms increase design complexity.
An asynchronous dual-port memory is adopted, including a dual-port block RAM, a Gray code counter, and a clock domain crossover module. The controller dynamically allocates memory access time slots. Combined with the Gray code counter and the clock domain crossover module, synchronous access signals and address translation of two independent asynchronous access ports are realized, ensuring data consistency and stability.
It significantly improves data access efficiency and real-time performance, meets the real-time and high-precision requirements of multi-channel systems, and reduces the access latency and design complexity of multi-channel systems.
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Figure CN121835544A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of digital signal processing, in particular, to an asynchronous dual-port memory and a real-time digital phase shifter system. BACKGROUND
[0002] In modern digital signal processing, real-time performance and high precision are key requirements, especially in multi-channel applications such as radar, communication and medical imaging. As a core component, the performance of the digital phase shifter system directly affects the overall performance of digital signal processing. Traditional digital phase shifter systems usually use single-port memory architecture, which requires sequential execution when reading and writing, resulting in increased access delay and difficulty in meeting real-time requirements. In addition, with the increasing complexity of digital signal processing, the demand for parallel processing of multi-channel data is also increasing, further exacerbating the memory access bottleneck.
[0003] To solve these problems, dual-port memory technology is introduced into digital signal processing systems. Dual-port memory allows simultaneous read and write operations, significantly improving data throughput. However, synchronous dual-port memory still relies on a unified clock signal, which limits its applicability in asynchronous digital signal processing.
[0004] Asynchronous memory access technology further breaks through this limitation by allowing operations in different clock domains, enabling asynchronous memory to start new operations without waiting for the completion of the previous operation, thereby reducing latency and improving the response speed of digital signal processing. However, existing asynchronous memory technology still faces challenges in multi-channel digital signal processing, especially in dynamically allocating memory access slots and ensuring data consistency.
[0005] In addition, existing FPGA designs often require complex clock management and signal synchronization mechanisms when implementing high-precision digital phase shifters, making it difficult to directly apply to digital phase shifter systems.
[0006] In summary, although existing dual-port memory and asynchronous access technology have made some progress in improving data throughput and reducing latency, there are still the following limitations in multi-channel real-time digital phase shifter systems: (1) synchronous dual-port memory cannot effectively support asynchronous operations, limiting its applicability in multi-clock domain real-time digital phase shifter systems; (2) existing asynchronous memory technology is insufficient in multi-channel dynamic access time slot allocation and data consistency; (3) complex clock management and signal synchronization mechanisms increase the complexity of real-time digital phase shifter system design, making it difficult to meet high-precision real-time requirements. SUMMARY
[0007] In view of the problems in the prior art, the application provides an asynchronous dual-port memory and a real-time digital phase shifter system, which combines the asynchronous access technology of the dual-port memory to meet the requirements of real-time performance and high precision of the multi-channel digital phase shifter system.
[0008] To achieve the above technical purposes, the application adopts the following technical solutions: The asynchronous dual-port memory comprises a dual-port block RAM, a Gray code counter, a clock domain crossing module and a controller. The controller is configured to dynamically allocate memory access time slots of the dual-port block RAM according to data read-write task requests, and issue stepping instructions of the Gray code counter and cross-domain control instructions of the clock domain crossing module. The Gray code counter receives the stepping instructions of the controller and outputs Gray code addresses to the dual-port block RAM. The clock domain crossing module receives the cross-domain control instructions and provides synchronous access signals to the dual-port block RAM. The dual-port block RAM performs asynchronous read-write operations according to the Gray code addresses, the synchronous access signals and the allocated memory access time slots, and stores phase and power data pairs of the asynchronous read-write operations.
[0009] Further, the dual-port block RAM is composed of two completely independent access ports, each of which has independent clock signals, read-write address lines and control signals, wherein the clock signals are provided by the synchronous access signals of the clock domain crossing module, the read-write address lines are provided by the Gray code addresses output by the Gray code counter, and the control signals are provided by the memory access time slots allocated by the controller.
[0010] Further, the controller comprises a time slot allocation unit, a priority adjustment unit, a request arbitrator, a scheduling state machine and a feedback monitor. The time slot allocation unit is configured to allocate memory access time slots for the asynchronous access ports of the dual-port block RAM. The priority adjustment unit adjusts the access order of the asynchronous access ports according to the dynamically allocated memory access time slots. The request arbitrator selects corresponding data read-write task requests according to the access order of the asynchronous access ports. The scheduling state machine is configured to trigger read-write operations and monitor the execution states of the read-write operations. The feedback monitor is configured to collect performance data of the asynchronous access ports, which is used to dynamically adjust the memory access time slots allocated by the time slot allocation unit.
[0011] Further, the time slot allocation unit divides time into microframes, each of which contains memory access periods, and the asynchronous access ports in the dual-port block RAM and share one access slot, for access port reservation one guaranteed slot, the rest of the access slots are assigned to access port , at the end of each microframe period, the memory access slots of the access port are dynamically adjusted according to the queue depth, average latency and violation times of the access port .
[0012] Further, the dynamic adjustment process of the memory access slots of the access port is:
[0013] wherein, represents the memory access slots of the access port after adjustment, represents the queue depth of the access port , represents the reference queue depth, represents the average latency of the access port , represents the target latency of the access port , represents the violation times of the access port in the deadline, , and respectively represent the first adjustment gain coefficient, the second adjustment gain coefficient and the third adjustment gain coefficient, represents the minimum guaranteed slot number of the access port , represents the minimum access slot number reserved by the access port B, represents a function for limiting between a minimum value and a maximum value.
[0014] Further, the scheduling state machine needs to check whether there is an absolute urgent request in the asynchronous access port before triggering the read-write operation, if there is, the current memory access slot is preempted, and the corresponding number of memory access slots is compensated in the next microframe period.
[0015] Further, when the scheduling state machine monitors the execution state of the read-write operation, if it is monitored that the write address of an access port is read by another access port in the microframe period, the priority of the write operation is raised or the data is pre-empted.
[0016] Further, the application also provides a real-time digital phase shifter system of the asynchronous dual-port memory, comprising: the asynchronous dual-port memory, an adapter, a digital signal processing module, a synchronous clock module, a digital-analog conversion module and an I / O interface. The asynchronous dual-port memory is used for storing the phase and power data pairs of the asynchronous read-write operation; The adapter is used for converting the phase and power data pairs of the asynchronous read-write operation of the asynchronous dual-port memory into the synchronous clock domain; The synchronous clock module is used for providing the synchronous clock signal and the reference clock signal for the adapter, the digital signal processing module, the digital-analog conversion module and the I / O interface, and ensuring the timing consistency; The digital signal processing module is used for converting the phase and power data pairs of the asynchronous read-write operation with the timing consistency into the digital signal; The digital-analog conversion module is used for converting the digital signal into the analog signal and sending the analog signal to the I / O interface; The I / O interface is used for outputting the analog signal and communicating with the external system.
[0017] Compared with the prior art, the application has the following beneficial effects: the dual-port block RAM in the asynchronous dual-port memory adopts two independent asynchronous access ports, supports the simultaneous read-write operation, and thus significantly improves the data access efficiency and real-time performance; the synchronous access signal is provided through the clock domain crossing module, and the data consistency and stability in the multi-clock domain environment are ensured; the Gray code address conversion is performed through the Gray code counter, the address conflict and delay in the asynchronous access are reduced; the memory access time slot is dynamically allocated through the controller, and the access delay of the multi-channel system is significantly reduced, and when the asynchronous dual-port memory is applied to the real-time phase shifter system, the strict requirements of the modern multi-channel system on the real-time performance and high precision are met. BRIEF DESCRIPTION OF DRAWINGS
[0018] Figure 1 Fig. 1 is a schematic diagram of the asynchronous dual-port memory of the application; Figure 2 Fig. 3 is a schematic diagram of the controller in the application; Figure 3 Fig. 4 is a schematic diagram of the real-time digital phase shifter system of the application. DETAILED DESCRIPTION
[0019] The technical solutions of the application will be further explained in combination with the drawings.
[0020] As shown in Fig. 1, the asynchronous dual-port memory of the application comprises a dual-port block RAM, a clock domain crossing module, a controller, a Gray code counter and an adapter. Figure 1As an illustrative diagram of the asynchronous dual-port memory of the present application, the asynchronous dual-port memory comprises: a dual-port block RAM, a Gray code counter, a clock domain crossing module and a controller; the controller is used for dynamically allocating memory access time slots of the dual-port block RAM according to data read-write task requests, thereby optimizing access efficiency of a multi-channel system, and issuing stepping instructions of the Gray code counter and cross-domain control instructions of the clock domain crossing module; the Gray code counter receives the stepping instructions of the controller, outputs a Gray code address to the dual-port block RAM, ensures that only one bit changes in the address conversion process, avoids asynchronous sampling glitches, thereby reducing address conflicts and delays in asynchronous access, and the output of the Gray code counter directly drives an address bus of the memory, thereby ensuring stability and accuracy of the address conversion; the clock domain crossing module receives the cross-domain control instructions, provides synchronous access signals to the dual-port block RAM, ensures stability and data consistency of the asynchronous access, and the clock domain crossing module realizes signal transmission between different clock domains through a synchronizer and a handshake protocol, thereby avoiding data errors caused by different clock domains; the dual-port block RAM performs asynchronous read-write operations according to the Gray code address, the synchronous access signals and the allocated memory access time slots, and stores phase and power data pairs of the asynchronous read-write operations, thereby realizing real-time read-write operations and significantly improving data access efficiency and real-time performance.
[0021] The dual-port block RAM in the present application is composed of two completely independent access ports, each of which can independently perform read-write operations, thereby realizing parallel data processing of multiple channels and avoiding the sequential access bottleneck of a traditional single-port memory. Each access port has an independent clock signal, read-write address lines and control signals, wherein the clock signal is provided by the synchronous access signal of the clock domain crossing module, the read-write address lines are provided by the Gray code address output by the Gray code counter, and the control signals are provided by the memory access time slots allocated by the controller.
[0022] As Figure 2As a schematic diagram of the controller in the application, the controller comprises: a time slot allocation unit, a priority adjustment unit, a request arbitrator, a scheduling state machine and a feedback monitor; the time slot allocation unit is used for allocating memory access time slots for asynchronous access ports of a dual-port block RAM; the priority adjustment unit adjusts the access order of the asynchronous access ports according to the dynamically allocated memory access time slots, and ensures that the phase and power values of each channel can be read and updated in time, specifically, if the memory access time slot of an access port is increased, the priority of the access port is increased, otherwise, the priority of the access port is reduced, and the throughput capacity of another access port is restored; the request arbitrator selects corresponding data read-write task requests according to the access order of the asynchronous access ports; the scheduling state machine is used for triggering read-write operations and monitoring the execution state of the read-write operations; and the feedback monitor is used for collecting performance data of the asynchronous access ports, and is used for dynamically adjusting the memory access time slots allocated by the time slot allocation unit. Through time slot allocation, dynamic scheduling, cross-domain synchronization and feedback adjustment, the controller realizes efficient, stable and low-delay data access control in an asynchronous dual-port memory, and ensures that data access in a multi-task concurrent environment has predictability, data consistency and real-time performance.
[0023] In the application, the time slot allocation unit divides time into microframes, each microframe contains a memory access period, the asynchronous access ports in the dual-port block RAM and share access time slots, the access ports are reserved guaranteed time slots, and the remaining access time slots are allocated to the access ports , at the end of each microframe period, the memory access time slots of the access ports are dynamically adjusted according to the queue depth, average delay and violation number of the access ports , and the specific process is as follows:
[0024] wherein, represents the memory access time slot of the access port after adjustment, represents the queue depth of the access port , represents a reference queue depth, generally taking a value of 0-2; represents the average delay of the access port , represents the target delay of the access port , represents the violation number of the access port in the deadline, , and respectively represent the first, second and third adjustment gain coefficients, represent the minimum guaranteed time slot number of the access port , that is, the lower limit protection value set by the controller for the real-time task, preventing the priority of the access port from being excessively reduced in the dynamic adjustment process, and ensuring the minimum service rate of the real-time task; represent the minimum access time slot number reserved by the access port B, represent the function for limiting between the minimum value and the maximum value.
[0025] The dynamic adjustment of the memory access time slot of the access port in the application takes the average delay and the number of violations of the access port as closed-loop signals, so that the controller can automatically improve the access priority of the access port at the task adjacent deadline, compress the worst-case delay upper bound, and reduce the timeout probability; when the queue depth of the access port is large, the access time slot is automatically supplemented to digest the backlog, and when the queue depth of the access port is small, the time slot is transferred to other ports to improve the overall utilization and throughput, avoid wasting low load and blocking high load caused by fixed quota, and realize dynamic balance; by setting and , it is ensured that both parties have the lowest access opportunity; further, by adjusting the gain coefficient setting, the real-time performance, throughput and stability can be realized in the dual-port memory of the asynchronous multi-clock domain.
[0026] In one technical solution of the application, the scheduling state machine needs to check whether there is an absolute urgent request for the asynchronous access port before triggering the read-write operation, and if there is, the current memory access time slot is preempted, and the corresponding number of memory access time slots is compensated in the next microframe period, which can guarantee the real-time performance of the urgent task and maintain the overall throughput.
[0027] In one technical solution of the application, when the scheduling state machine monitors the execution state of the read-write operation, if it is monitored that the write address of an access port is read by another access port within a microframe period, the priority of the write operation is improved to avoid data inconsistency caused by the blocking of the write operation by the read operation, or when the written data has been stored in the buffer, the data is directly forwarded, eliminating the dependence of the read operation on the old data and directly outputting the latest written value.
[0028] For example, Figure 3This invention also provides a real-time digital phase shifter system based on the Xilinx UltraScale+ series FPGA, which fully utilizes its high-density block RAM resources and advanced clock management capabilities to further reduce system complexity and design costs. The real-time digital phase shifter system includes: an asynchronous dual-port memory, an adapter, a digital signal processing module, a synchronous clock module, a digital-to-analog converter module, and an I / O interface; Asynchronous dual-port memory is used to store phase and power data pairs for asynchronous read and write operations; The adapter is used to convert the phase and power data pairs of asynchronous read and write operations of asynchronous dual-port memory into the synchronous clock domain of the FPGA, ensuring precise synchronization of data with the processing channel; The synchronization clock module is used to provide synchronization clock signals and reference clock signals for the adapter, digital signal processing module, digital-to-analog converter module and I / O interface to ensure timing consistency; The digital signal processing module is used to convert the phase and power data pairs of time-consistent asynchronous read and write operations into digital signals; The digital-to-analog converter module is used to convert digital signals into analog signals and send them to the I / O interface; the I / O interface is used to output analog signals and communicate with external systems.
[0029] This invention's real-time digital phase shifter system significantly improves the data access efficiency and performance of multi-channel real-time systems by introducing an asynchronous dual-port memory. The system achieves simultaneous read and write operations through two independent asynchronous access ports, avoiding the sequential access bottleneck of traditional single-port memories. The combination of a clock domain interleaving mechanism and a Gray code counter ensures data transmission stability and address translation accuracy in multi-clock domain environments. The controller's dynamic memory allocation mechanism further optimizes the access efficiency of the multi-channel system, meeting the stringent requirements of modern applications for high precision and low latency.
[0030] This invention presents a flexible real-time digital phase shifter system suitable for various applications with high real-time requirements, such as radar, communication, medical imaging, audio processing, industrial automation, and video processing. Through the independent access ports of the asynchronous dual-port memory and the dynamic memory allocation mechanism, the system can significantly reduce access latency and increase data throughput, thereby improving the overall system's real-time performance.
[0031] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.
Claims
1. An asynchronous dual-port memory, characterized in that, include: Dual-port block RAM, Gray code counter, clock domain cross module, and controller; The controller is used to dynamically allocate memory access time slots of the dual-port block RAM according to data read and write task requests, and to issue step instructions for the Gray code counter and cross-domain control instructions for the clock domain cross module. The Gray code counter receives the stepping instructions from the controller and outputs the Gray code address to the dual-port block RAM; The clock domain cross module receives cross-domain control commands and provides synchronous access signals to the dual-port block RAM. The dual-port block RAM performs asynchronous read and write operations based on the Gray code address, synchronization access signal, and allocated memory access time slot, and stores the phase and power data pairs of the asynchronous read and write operations.
2. The asynchronous dual-port memory according to claim 1, characterized in that, The dual-port block RAM consists of two completely independent access ports. Each access port has an independent clock signal, read / write address lines, and control signals. The clock signal is provided by the synchronous access signal of the clock domain cross module, the read / write address lines are provided by the Gray code address output by the Gray code counter, and the control signals are provided by the memory access time slots allocated by the controller.
3. An asynchronous dual-port memory according to claim 1, characterized in that, The controller includes: a time slot allocation unit, a priority adjustment unit, a request arbitrator, a scheduling state machine, and a feedback monitor; The time slot allocation unit is used to allocate memory access time slots for the asynchronous access ports of the dual-port block RAM; The priority adjustment unit adjusts the access order of the asynchronous access port according to the dynamically allocated memory access time slots; The request arbitrator selects the corresponding data read / write task request according to the access order of the asynchronous access port; The scheduling state machine is used to trigger read and write operations and monitor the execution status of read and write operations; The feedback monitor is used to collect performance data of the asynchronous access port and to dynamically adjust the memory access time slots allocated by the time slot allocation unit.
4. An asynchronous dual-port memory according to claim 3, characterized in that, The time slot allocation unit divides time into microframes, each microframe containing Each memory access cycle, the asynchronous access port in the dual-port block RAM and Shared One access time slot, for the access port Reserved One guaranteed time slot is allocated, and the remaining access time slots are allocated to the access ports. At the end of each microframe cycle, based on the access port The access port is dynamically adjusted based on queue depth, average latency, and number of defaults. Memory access slots.
5. An asynchronous dual-port memory according to claim 4, characterized in that, The dynamic adjustment process of the memory access time slot of the access port is as follows: in, Indicates the adjusted access port Memory access slots, Indicates the access port queue depth, Indicates the reference queue depth. Indicates the access port average latency, Indicates the access port Target latency, Indicates the access port Number of defaults by the deadline , and These represent the first adjustment gain coefficient, the second adjustment gain coefficient, and the third adjustment gain coefficient, respectively. Indicates the access port The minimum number of guaranteed time slots, This indicates the minimum number of access slots reserved for access port B. Indicates used to A function that is limited to a minimum and a maximum value.
6. An asynchronous dual-port memory according to claim 3, characterized in that, Before triggering a read / write operation, the scheduling state machine needs to check whether there is an absolutely urgent request on the asynchronous access port. If so, it preempts the current memory access time slot and compensates for the corresponding number of memory access time slots in the next microframe cycle.
7. An asynchronous dual-port memory according to claim 3, characterized in that, When the scheduling state machine monitors the execution status of read and write operations, if it detects that the write address of an access port is read by another access port within a microframe period, it will increase the priority of the write operation or forward the data.
8. A real-time digital phase shifter system employing the asynchronous dual-port memory according to any one of claims 1-7, characterized in that, include: Asynchronous dual-port memory, adapter, digital signal processing module, synchronous clock module, digital-to-analog converter module, and I / O interface; The asynchronous dual-port memory is used to store phase and power data pairs for asynchronous read and write operations; The adapter is used to convert the phase and power data pairs of asynchronous read and write operations of the asynchronous dual-port memory into a synchronous clock domain; The synchronization clock module is used to provide synchronization clock signals and reference clock signals for the adapter, digital signal processing module, digital-to-analog converter module and I / O interface to ensure timing consistency; The digital signal processing module is used to convert the phase and power data pairs of the time-consistent asynchronous read and write operations into digital signals; The digital-to-analog converter module is used to convert digital signals into analog signals and send them to the I / O interface; The I / O interface is used to output analog signals and communicate with external systems.