Accurate-period simulation system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention particularly relates to a simulation system and method with an accurate period based on an FPGA (Field Programmable Gate Array). According to the FPGA-based simulation system with the accurate period, a virtual platform processing system module performs data interaction with a universal interface shell module, so that software side simulation, management and monitoring are realized; the DUT module is responsible for receiving external interaction data of the virtual platform processing system module, and sending a request and receiving a response to the outside through a data interface; and the universal interface shell module injects a request or a sample of the DUT module into the asynchronous FIFO cluster in a non-intrusive manner, and notifies the virtual platform processing system module to perform software processing. According to the FPGA-based simulation system and method with the accurate period, a large-scale system can be effectively decomposed into a plurality of small-scale subsystems, prototyping is carried out on the FPGA, non-interference and accurate-period co-simulation is realized on the low-cost FPGA by adopting a transaction period hybrid modeling technology, the verification efficiency is improved, and the total ownership cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of hardware verification technology, and in particular to a periodic-accurate simulation system and method based on FPGA. Background Technology

[0002] As the complexity of processor and system-on-a-chip (SoC) designs continues to increase, the cost of functional verification and performance analysis is rising sharply. Traditional methods include software simulation and FPGA prototyping, but each has its limitations.

[0003] While software simulations (such as periodic accurate simulations) allow for in-depth examination of microarchitecture, they are too time-consuming to handle long workloads. Existing accelerator solutions rely on commercial simulation platforms, such as Palladium, which are expensive. Furthermore, existing FPGA platforms require complex maintenance and proprietary software stacks, resulting in fragmented verification environments and incompatible simulation and simulation management software, leading to redundant development.

[0004] Overall, existing technologies fail to strike a balance between cost, accuracy, and flexibility, particularly when dealing with custom interfaces, fine-grained partitioning, and non-interference cycle accuracy.

[0005] To address the problems of high verification costs, low accuracy, and poor flexibility in existing technologies, this invention proposes a periodic-accurate simulation system and method based on FPGA. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, this invention provides a simple and efficient FPGA-based simulation system and method with accurate cycle time.

[0007] This invention is achieved through the following technical solution:

[0008] A periodic-accurate simulation system and method based on FPGA, including a virtual platform processing system module, a DUT module, and a general interface shell module;

[0009] The virtual platform processing system module is responsible for interacting with the general interface shell module to realize software-side simulation, management and monitoring.

[0010] The DUT module is responsible for receiving external interactive data from the virtual platform processing system module, and for initiating requests and receiving responses through the data interface.

[0011] The general interface shell module is responsible for injecting requests or samples from the DUT module into the asynchronous FIFO cluster in a non-intrusive manner, and notifying the virtual platform processing system module to perform software processing.

[0012] The virtual platform processing system module runs in the core of the PS side of the ZYNQ processor, interacts with the semi-blocking FIFO array and control and status register CSR group (CSRs) of the general interface shell, and writes the final performance data to a local file or uploads it to the host via the network.

[0013] The DUT module is deployed on the PL (Programmable Logic) side and is used to run user register transfer level (RTL) logic. It supports decomposition into multi-level sub-modules, and each sub-DUT module can run independently.

[0014] The DUT module operates in an independent clock domain and is responsible for receiving external interactions from the virtual platform processing system module. It supports initiating requests and receiving responses through high-speed or low-speed interfaces.

[0015] The general interface shell module includes a performance counter and a sampler, as well as a parameterizable data path engine, which is responsible for receiving the timing / response written back by the virtual platform processing system module, and executing the timer in the clock domain of the DUT module to send the response back to the DUT module with periodic precision.

[0016] When the virtual platform processing system module is slow, the clock of the DUT module is paused by controlling the clock gate state machine to ensure that the peripheral timing is consistent from the perspective of the DUT module.

[0017] The parameterizable data path engine includes a control and status register (CSR) group, a semi-blocking FIFO array, hardware timers, and a clock-gated state machine.

[0018] The Control and Status Register (CSR) group and the semi-blocking FIFO array are used to bridge the clock domains of the Virtual Platform Processing System (DUT) module and the DUT module.

[0019] The semi-blocking FIFO array buffers data through asynchronous FIFOs to handle uncertain back pressure; the control and status register (CSR) group synchronizes control signals through a synchronizer; in a multi-clock system environment, it ensures that high-bandwidth monitoring does not interfere with the DUT module.

[0020] The clock-gated state machine is used to monitor the reverse voltage and gate the DUT clock. When the half-blocking FIFO array is detected to be full, the DUT module is paused. When the data in the half-blocking FIFO array is exhausted, the DUT module is resumed.

[0021] The hardware timer is responsible for performing local periodic counting within the DUT module clock domain based on the delay value written back by the virtual platform processing system, and triggering a response ready event.

[0022] The performance counter and sampler support synthesized counters, single-step sampling, and proportional sampling.

[0023] The output signal of the performance counter is directly connected to the internal signal of the DUT module, or sampled during the periodic submission phase of the DUT module;

[0024] The phased sampling data includes PC sampling data, event tags, and time-proportional sampling data.

[0025] An FPGA-based method for accurate periodicity simulation, using a ZYNQ processor FPGA board, to achieve co-simulation; specifically including the following steps:

[0026] Step S1: The host sends the bit file to the ZYNQ processor FPGA board. The PS starts and loads the virtual platform processing system driver, mapping the status register CSR group of the general interface shell module to the semi-blocking FIFO array. The virtual platform processing system module initializes the sampling and coverage strategy according to the configuration sent by the host and checks whether the general interface shell module is ready.

[0027] Step S2: The DUT module writes the request to the request FIFO array of the general interface shell module in its clock domain according to the original interface, and at the same time generates a lightweight sample and writes it to the sample FIFO array.

[0028] Step S3: The general interface shell module receives the request on the PL side and increments the FIFO count. It then notifies the virtual platform of the pending events of the system module by setting or interrupting the status register.

[0029] Step S4: The virtual platform processing system module reads the request from the request FIFO array, uses the software model to calculate the required latency for the response, and prepares the response data or pointer;

[0030] Step S5: The virtual platform processing system module writes the delay value and response metadata into the status register CSR group of the general interface shell module or returns a semi-blocking FIFO array as credentials to start the local timer and response.

[0031] Step S6: In the clock domain of the DUT module, the general interface shell module uses a hardware timer to count the delays written back by the virtual platform processing system module. When the count expires and the data is ready, the response is sent back to the DUT module through the response channel to maintain the accuracy of the cycle.

[0032] If the semi-blocking FIFO array is close to saturation and the virtual platform processing system module cannot process it in time, the general interface shell module issues an early warning and safely pauses the DUT module clock through the clock gating state machine at the critical moment.

[0033] Once the queue has returned to a safe level, the clock will be released gradually.

[0034] Step S7: When an exception occurs during operation, the general interface shell module performs protocol and address validity checks and writes the exception to the error FIFO array;

[0035] If the virtual platform processing system module crashes or remains unresponsive for more than a preset time, the general interface shell module saves a circular sample buffer and notifies the host or directly triggers the restart process.

[0036] A secure prefetching device for a secure caching system includes a memory and a processor; the memory is used to store a computer program, and the processor is used to implement the above-described method when executing the computer program.

[0037] A readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0038] The beneficial effects of this invention are: the FPGA-based periodic accurate simulation system and method can effectively decompose a large system into multiple small-scale subsystems and prototype them on the FPGA. By using the transaction periodic hybrid modeling technology, non-interference, periodic accurate co-simulation can be achieved on a low-cost FPGA, which improves verification efficiency and reduces total cost of ownership. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Appendix Figure 1 This is a schematic diagram of the FPGA-based simulation system for accurate periodicity according to the present invention.

[0041] Appendix Figure 2 This is a schematic diagram of the shell module, the general interface of this invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0043] This FPGA-based, periodically accurate simulation system includes a virtual platform processing system module, a DUT (RTL design module) module, and a general interface shell module.

[0044] The virtual platform processing system module is responsible for interacting with the general interface shell module to realize software-side simulation, management and monitoring.

[0045] The DUT module is responsible for receiving external interactive data from the virtual platform processing system module, and for initiating requests and receiving responses through the data interface.

[0046] The general interface shell module is responsible for injecting requests or samples from the DUT module into the asynchronous FIFO cluster in a non-intrusive manner, and notifying the virtual platform processing system module to perform software processing.

[0047] The virtual platform processing system module runs in the core of the ZYNQ processor's PS (Processing System) side, runs necessary software models (such as DRAM timing, file system access simulation, and complex protocol processing), interacts with the semi-blocking FIFO array and control and status register CSR group (CSRs) of the general interface shell, and writes the final performance data to a local file or uploads it to the host via the network.

[0048] The DUT module is deployed on the PL (Programmable Logic) side to run user register transfer level (RTL) logic. It supports decomposition into multi-level sub-modules (such as multi-core, single-core, front-end, and cache), and each sub-DUT module supports independent operation.

[0049] The DUT module operates in an independent clock domain and is responsible for receiving external interactions from the virtual platform processing system module. It supports initiating requests and receiving responses through high-speed or low-speed interfaces such as AXI.

[0050] The general interface shell module includes a performance counter and a sampler, as well as a parameterizable data path engine, which is responsible for receiving the timing / response written back by the virtual platform processing system module, and executing the timer in the clock domain of the DUT module to send the response back to the DUT module with periodic precision.

[0051] When the virtual platform processing system module is slow, the clock of the DUT module is paused by controlling the clock gate state machine to ensure that the peripheral timing is consistent from the perspective of the DUT module.

[0052] The parameterizable data path engine includes a control and status register (CSR) group, a semi-blocking FIFO array, hardware timers, and a clock-gated state machine.

[0053] The Control and Status Register (CSR) group and the semi-blocking FIFO array are used to bridge the clock domains of the Virtual Platform Processing System (DUT) module and the DUT module.

[0054] The semi-blocking FIFO array buffers data through asynchronous FIFOs to handle uncertain back pressure; the control and status register (CSR) group synchronizes control signals through a synchronizer; in a multi-clock system environment, it ensures that high-bandwidth monitoring (such as submitting information every cycle) does not interfere with the DUT module;

[0055] The clock-gated state machine is used to monitor the reverse voltage and gate the DUT clock. When the half-blocking FIFO array is detected to be full, the DUT module is paused. When the data in the half-blocking FIFO array is exhausted, the DUT module is resumed. This mechanism allows the software on the PS side and the logic of the DUT to be unaware of each other's existence, which greatly simplifies the timing constraints in a multi-clock system.

[0056] The hardware timer is responsible for performing local periodic counting within the DUT module clock domain based on the delay value written back by the virtual platform processing system, and triggering a response ready event.

[0057] The performance counter and sampler support synthesized counters, single-step sampling, and proportional sampling.

[0058] The output signal of the performance counter is directly connected to the internal signal of the DUT module, or sampled during the periodic submission phase of the DUT module;

[0059] The phased sampling data includes PC sampling data, event tags, and time-proportional sampling data.

[0060] This FPGA-based method for accurate periodic simulation, using a ZYNQ processor FPGA board, achieves co-simulation; specifically, it includes the following steps:

[0061] Step S1: The host sends the bit file to the ZYNQ processor FPGA board. The PS starts and loads the virtual platform processing system driver, mapping the status register CSR group of the general interface shell module to the semi-blocking FIFO array. The virtual platform processing system module initializes the sampling and coverage strategy according to the configuration sent by the host and checks whether the general interface shell module is ready.

[0062] Step S2: The DUT module writes the request to the request FIFO array of the general interface shell module in its clock domain according to the original interface (such as AXI or ready / valid), and at the same time generates a lightweight sample and writes it to the sample FIFO array.

[0063] Step S3: The general interface shell module receives the request on the PL side and increments the FIFO count. It then notifies the virtual platform of the pending events of the system module by setting or interrupting the status register.

[0064] Step S4: The virtual platform processing system module reads the request from the request FIFO array, calculates the required latency for the response using a software model (such as DRAM timing, file system agent), and prepares the response data or pointer.

[0065] Step S5: The virtual platform processing system module writes the delay value and response metadata into the status register CSR group of the general interface shell module or returns a semi-blocking FIFO array as credentials to start the local timer and response.

[0066] Step S6: In the clock domain of the DUT module, the general interface shell module uses a hardware timer to count the delays written back by the virtual platform processing system module. When the count expires and the data is ready, the response is sent back to the DUT module through the response channel to maintain the accuracy of the cycle.

[0067] If the semi-blocking FIFO array is close to saturation and the virtual platform processing system module cannot process it in time, the general interface shell module issues an early warning and safely pauses the DUT module clock through the clock gating state machine at the critical moment.

[0068] Once the queue has returned to a safe level, the clock will be released gradually.

[0069] Step S7: When an exception occurs during operation, the general interface shell module performs protocol and address validity checks and writes the exception to the error FIFO array;

[0070] If the virtual platform processing system module crashes or remains unresponsive for more than a preset time, the general interface shell module saves a circular sample buffer and notifies the host or directly triggers the restart process.

[0071] The secure prefetching device of the secure caching system includes a memory and a processor; the memory is used to store a computer program, and the processor is used to implement the above-described method when executing the computer program.

[0072] The readable storage medium stores a computer program that, when executed by a processor, implements the method described above.

[0073] This invention provides a periodically accurate simulation system and method based on FPGA, constructing a low-cost, scalable, easy-to-maintain, and periodically accurate local FPGA co-simulation platform. This platform achieves efficient, periodically accurate, accelerated co-simulation by decomposing complex designs into independent sub-components and prototyping them on the FPGA while maintaining non-interference in interface timing.

[0074] Furthermore, this method requires only a low-cost Zynq FPGA board and, through non-interference clock gating technology and precise interface timing modeling, ensures cyclic accuracy during simulation, thereby achieving a high degree of precision in functional verification and performance analysis. This innovation not only improves the verification efficiency of hardware designs but also promotes technological progress and development in related fields.

[0075] The core advantage of this invention lies in its ability to effectively decompose large systems into multiple smaller subsystems, each of which can be prototyped on an FPGA. After iterative optimization, these subsystems can be easily extended back to the entire system, ensuring input-output consistency across the entire system. Furthermore, through precise interface modeling, this method can predict deviations across the entire system, providing designers with more accurate design references. Compared to traditional full-production environment simulation, the cost of this invention is only a fraction of its cost, significantly lowering the barrier to hardware design and promoting innovation and widespread adoption in the field.

[0076] The embodiments described above are merely one specific implementation of the present invention. Ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. A cycle-accurate simulation system based on FPGA, characterized in that: The simulation system comprises a virtual platform processing system module, a DUT module and a general interface shell module. The virtual platform processing system module is responsible for realizing software simulation, management and monitoring through data interaction with the general interface shell module. The DUT module is responsible for receiving external interaction data of the virtual platform processing system module, and initiating requests and receiving responses externally through a data interface. The general interface shell module is responsible for injecting the requests or samples of the DUT module into an asynchronous FIFO cluster in a non-invasive manner, and notifying the virtual platform processing system module for software processing.

2. The FPGA-based cycle-accurate simulation system according to claim 1, wherein: The virtual platform processing system module runs in the core of the PS end of the ZYNQ processor, interacts with the semi-blocked FIFO array and the control and state register CSR group of the general interface shell, and writes the final performance data into a local file or uploads the data to the host through a network. The DUT module is deployed on the PL end, and is used for running user register transfer level RTL logic, supports decomposition into multiple sub-modules, and each sub-DUT module supports independent running. The DUT module runs in an independent clock domain, is responsible for receiving external interaction of the virtual platform processing system module, and supports initiating requests and receiving responses externally through a high-speed or low-speed interface.

3. The FPGA-based cycle-accurate simulation system according to claim 1, wherein: The general interface shell module comprises a performance counter and a sampler, and a parameterizable data path engine, is responsible for receiving the timing / response written back by the virtual platform processing system module, and executing a timer in the clock domain of the DUT module to send the response back to the DUT module with cycle accuracy; When the virtual platform processing system module processes slowly, the clock of the DUT module is paused through a clock gating state machine, so that the DUT module sees consistent peripheral timing.

4. The FPGA-based cycle-accurate simulation system according to claim 3, wherein: The parameterizable data path engine comprises a control and state register CSR group, a semi-blocked FIFO array, a hardware timer and a clock gating state machine; The control and state register CSR group and the semi-blocked FIFO array are used for bridging the clock domains of the virtual platform processing system module and the DUT module; The semi-blocked FIFO array buffers data through an asynchronous FIFO, and handles uncertain back pressure; the control and state register CSR group synchronizes control signals through a synchronizer; in a multi-clock system environment, high-bandwidth monitoring does not interfere with the DUT module; The clock gating state machine is used for monitoring back pressure and gating the DUT clock, and pauses the DUT module when detecting that the semi-blocked FIFO array is full, and resumes execution of the DUT module when the data of the semi-blocked FIFO array is exhausted; The hardware timer is responsible for performing local cycle-level counting in the clock domain of the DUT module according to the delay value written back by the virtual platform processing system, and triggering a response ready event.

5. The FPGA-based cycle-accurate simulation system according to claim 3, characterized in that: the performance counter and sampler support synthetic counter, single-step sampling and proportional sampling; wherein the output signal of the performance counter is directly connected to the internal signal of the DUT module, or the stage sampling data is sampled during the periodic submission stage of the DUT module; the stage sampling data includes PC sampling data, event tag and time proportional sampling data.

6. A cycle-accurate simulation method based on FPGA at all times, characterized in that: Based on the ZYNQ processor FPGA board, the cooperative simulation is realized; specifically comprising the following steps: Step S1, the host end downloads the bit file to the ZYNQ processor FPGA board, the PS end starts and loads the virtual platform processing system driver, and maps the state register CSR group and the semi-blocked FIFO array of the general interface shell module; The virtual platform processing system module initializes the sampling and coverage strategy according to the configuration issued by the host end, and checks whether the general interface shell module is ready; Step S2, the DUT module writes the request to the request FIFO array of the general interface shell module through the original interface in its clock domain, and simultaneously generates a lightweight sample and writes it to the sample FIFO array; Step S3, the general interface shell module receives the request on the PL side and increases the FIFO count, and notifies the virtual platform processing system module of the pending event by setting or interrupting the state register; Step S4, the virtual platform processing system module reads the request from the request FIFO array, calculates the required delay for response, and prepares response data or a pointer; Step S5, the virtual platform processing system module writes the delay value and response metadata into the state register CSR group of the general interface shell module or returns the semi-blocked FIFO array as a credential for starting the local timer and responding; Step S6, the general interface shell module in the DUT module clock domain, by the hardware timer according to the delay count written back by the virtual platform processing system module, when the count expires and the data is ready, the response is sent back to the DUT module through the response channel, and the cycle accuracy is maintained; If the semi-blocked FIFO array is close to saturation, and the virtual platform processing system module cannot be processed in time, the general interface shell module issues a warning, and safely suspends the DUT module clock through the clock gating state machine at the critical time; When the queue returns to a safe water level, the clock is gradually released; Step S7, when an exception occurs during operation, the general interface shell module performs protocol and address legality detection, and writes the exception into the error FIFO array; If the virtual platform processing system module crashes or does not respond for more than a preset time, the general interface shell module saves the ring sample buffer and notifies the host end or directly triggers the restart process.

7. A secure prefetching device of a secure cache system, characterized by: The memory is used for storing a computer program, and the processor is used for executing the computer program to realize the method of claim 6.

8. A readable storage medium characterized by: The computer program is stored on the readable storage medium, and the computer program is executed by the processor to realize the method of claim 6.

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