FPGA (Field Programmable Gate Array) configurable segmented wiring structure and test method thereof
By employing segmented routing structures and testing methods, the flexibility and scalability issues of FPGA routing resources are resolved, achieving high-efficiency routing test coverage and a shortened test cycle.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2025-12-17
- Publication Date
- 2026-04-10
AI Technical Summary
Existing FPGA routing resources suffer from limited flexibility, poor scalability, and high testing complexity.
It adopts a segmented wiring structure, with each group containing multiple twisted segmented wirings, and can achieve arbitrary wiring configuration through configurable switches. It is equipped with open circuit and short circuit test methods, including test procedures for pre-charge, floating, excitation and readback signals.
It achieves 100% coverage of cabling functionality tests while reducing test time to approximately 51% of traditional exhaustive testing, thus improving testing efficiency and flexibility.
Smart Images
Figure CN121835548A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and in particular to a configurable segmented routing structure for FPGA and its testing method. Background Technology
[0002] Field-Programmable Gate Arrays (FPGAs), as a key semi-custom integrated circuit, play an irreplaceable role in fields such as communications, artificial intelligence, and industrial control due to their high flexibility and reconfigurability. The core architecture of an FPGA consists of configurable logic blocks (CLBs), input / output units (I / O), and abundant programmable routing resources. Among these, the routing resources are responsible for implementing the electrical connections between all functional units, and their design directly determines the performance, area utilization, and cost of the FPGA chip.
[0003] Currently, most mainstream FPGAs adopt an island-type interconnect structure based on the classified routing concept. In this structure, routing resources consist of various predefined metal segments of different lengths, connected by programmable switches. While this design balances the delay of long-distance routing with the flexibility of local routing to some extent, it still has several inherent drawbacks: limited routing flexibility, poor scalability, and high testing complexity.
[0004] Therefore, a new FPGA routing structure and its testing method are needed, which can provide better scalability without sacrificing routing flexibility, and be equipped with a high-efficiency, high-coverage testing scheme, thereby systematically improving the overall competitiveness of FPGA products. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a testing method for a configurable segmented routing structure for an FPGA. The segmented routing structure includes multiple routing groups, each group containing multiple segmented routing lines connected in a twisted manner, and includes the following:
[0006] Open circuit test procedure: Connect multiple segmented wires into a complete electrical path through corresponding configurable switches, precharge the path to a predetermined level and then float it; apply an excitation signal of opposite level to the first end of the target wire and read back the response signal from its second end; if the read-back signal is at the same level as the excitation signal, it is determined that the target wire has good connectivity; if the read-back signal remains at the predetermined level, it is determined that the target wire has an open circuit fault.
[0007] Short-circuit test procedure: Connect multiple segmented wires into a complete electrical path through corresponding configurable switches, precharge the path to a predetermined level, and then float it; apply an excitation signal of opposite level to the first end of at least one adjacent wire physically adjacent to the target wire, and read back the response signal from the second end of the target wire; if the readback signal remains at the predetermined level, it is determined that there is no short circuit between the target wire and the adjacent wire; if the readback signal is pulled low, it is determined that there is a short circuit fault between the target wire and the adjacent wire.
[0008] In one embodiment of the present invention, in the short-circuit test step, an exhaustive test of adjacent lines is performed, that is, for each target wiring, the short-circuit condition between it and all physically adjacent wirings is tested. The physically adjacent wirings include: wire sequence adjacent wirings within the same group, all wirings in the previous wiring group, and all wirings in the next wiring group.
[0009] In one embodiment of the present invention, 100% wiring function test coverage is achieved through the adjacent line exhaustive test, and the total number of test combinations is reduced by 40% to 50% compared to the indiscriminate full exhaustive test.
[0010] In one embodiment of the present invention, the predetermined level is a high level, and the opposite level is a low level.
[0011] The present invention also provides an FPGA configurable segmented routing structure, comprising:
[0012] Multiple configurable logic modules arranged in an array;
[0013] Segmented routing resources are provided between rows and / or columns of the configurable logic module, and the segmented routing resources have a consistent structure in both the vertical and horizontal directions;
[0014] The segmented cabling resources are divided into multiple cabling groups, and each cabling group contains multiple segmented cablings.
[0015] The segmented cabling within each cabling group is interconnected by a twisted connection between different metal layers, enabling the cabling within the group to achieve multiple fixed lengths of cyclical alternation.
[0016] Multiple configurable switches, set at specific locations in the segmented wiring, are used to control the connection status and effective length of the segmented wiring to achieve arbitrary length wiring configurations from 1 to n.
[0017] In one embodiment of the present invention, the configurable switch is a one-time programmable antifuse switch or an NMOS transistor switch controlled by a configuration memory.
[0018] In one embodiment of the present invention, the segmented wiring structure is constructed using a cascading expansion method, and its total wiring length can be adapted to the expansion of the configurable logic module array size by increasing the number of basic wiring units.
[0019] In one embodiment of the present invention, for the wiring with a wire sequence of m in the xth group within the segmented wiring, different wiring lengths are achieved by setting a configurable switch on the wiring with a wire sequence of m+a, wherein:
[0020] If the configurable switch is set at the end of two rows of CLBs, the achieved wiring length is 2a; if the configurable switch is set in the middle of two rows of CLBs, the achieved wiring length is 2a-1.
[0021] In one embodiment of the present invention, the physical layout of the twisted connection is achieved by the crossing of wires on different metal layers, wherein solid line segments represent wiring within the same metal layer, and dashed line segments represent wiring across layers by connecting to adjacent metal layers through vias.
[0022] The present invention also provides an FPGA chip comprising the configurable segmented routing structure as described above.
[0023] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The wiring structure and its test scheme of the present invention, by pre-charging, applying an excitation signal after floating and reading back the response, respectively performs open circuit test and short circuit exhaustive test for all physically adjacent wiring, which can reduce the test time to about 51% of the traditional full exhaustive test while ensuring 100% wiring function test coverage, thus significantly improving the test efficiency. Attached Figure Description
[0024] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0025] Figure 1 This is a schematic block diagram of the basic architecture of the FPGA in this invention;
[0026] Figure 2 This is a specific configuration example diagram of the FPGA configurable segmented routing structure described in this invention;
[0027] Figure 3 This is a schematic diagram of the physical layout implementation of the "twisted connection" in this invention.
[0028] Figure 4 This is a schematic diagram illustrating the principle of the wiring open circuit test method described in this invention.
[0029] Figure 5 This is a schematic diagram illustrating the principle of the wiring short-circuit test method described in this invention.
[0030] Figure 6 This is a schematic diagram of the anti-fuse switch AF described in the configurable switch of the present invention.
[0031] Figure 7 This is a schematic diagram of the NOMS tube switch described in the configurable switch of the present invention. Detailed Implementation
[0032] This invention provides a configurable segmented routing structure and testing method for an FPGA; as shown in the appendix. Figure 1 As shown, the basic architecture of the FPGA chip of this invention mainly consists of a configurable logic module (CLB) array, configurable input / output units (IOBs) distributed around the chip, and configurable routing resources filling the spaces between the CLB array. The core of this invention lies in the innovative design of the configurable routing resources, particularly the segmented routing structure.
[0033] The specific implementation of the segmented cabling structure is shown in the attached document. Figure 2 The diagram illustrates a basic implementation unit of the segmented cabling structure of this invention. CLB modules in different rows (e.g., CLB row 1 and CLB row 2) are connected by vertical segmented cabling. To achieve flexible connections, the segmented cabling is designed with multiple lengths, such as length 1 (spanning one CLB row), length 2 (spanning two CLB rows), etc. Each cabling is assigned a unique wire sequence number (0, 1, 2, ..., n). For systematic management, these wire sequences are divided into multiple cabling groups.
[0034] Grouping and twisted connections: as shown in the appendix Figure 3 As shown, the attached Figure 2 The basic unit shown is cascaded and expanded vertically to form a grouped twisted connection structure. Taking group 1 as an example, it contains two wirings, wire sequence 1 and wire sequence 2. The initial length of wire sequence 1 is 2, and a configurable switch is placed at the end of every two rows of CLBs; the initial length of wire sequence 2 is 1, and a configurable switch is placed in the middle of every two rows of CLBs. Through this alternating arrangement, after cascading expansion, the wiring in group 1 can achieve a cyclical alternating connection mode with lengths of 1 or 3. Similarly, group 2 can contain three wirings (e.g., wire sequences 2, 3, and 4), achieving a cyclical alternation of lengths of 2 or 4. This physical layout method of crossing between different metal layers to achieve alternating wire lengths constitutes a "twisted connection," as shown in the attached diagram. Figure 5 As shown, solid lines represent wiring within the same metal layer, while dashed lines represent cross-layer wiring connected to adjacent metal layers via vias.
[0035] General rule for wire length configuration: For a given wiring group x, the first wire in the group (wire sequence m, initial length 2) is used as the reference. If other wire lengths need to be configured, a configurable switch can be added to the wire with wire sequence m+a. Specifically:
[0036] If the switch is set at the end of two rows of CLB, this wiring can achieve a connection of length 2a.
[0037] If the switch is placed in the middle of two rows of CLBs, this wiring can achieve a connection of length 2a-1.
[0038] This rule allows for the flexible generation of any desired wiring length from 1 to n, based on the circuit's specific requirements for delay, load, and wiring efficiency.
[0039] Implementation of the configurable switch: The specific implementation of the configurable switch is shown in the supplementary document. Figure 6 , Figure 7 As shown. There are two main implementation methods:
[0040] One type is a one-time programmable (OTP) device, such as an antifuse (AF) switch. During the testing phase, to facilitate connectivity testing, an NMOS transistor (controlled by the test signal) can be connected in parallel as a test path.
[0041] The second method is to directly use NMOS transistors as programmable switches, with their on / off state controlled by the FPGA's configuration memory (SRAM or Flash memory, etc.).
[0042] The segmented wiring structure in the horizontal direction is the same as that in the vertical direction, and will not be described again here.
[0043] Furthermore, regarding the specific implementation of the testing method, based on the aforementioned segmented wiring structure, this invention provides a corresponding wiring function testing method, mainly including open-circuit testing and short-circuit testing. The basic principle of the test is as follows: First, by configuring appropriate switches, the multiple segments of wiring to be tested are connected into a complete electrical path. Then, a "pre-charge-float-excite-readback" operation sequence is performed on this path.
[0044] Open-circuit test (connectivity test): This test verifies whether a single cable has an open-circuit fault. The procedure is detailed in the appendix. Figure 4 The test circuit structure shown is used.
[0045] ①Preparation phase: Control all pre-charge transistors to conduct, and charge multiple wires under test to a high level (logic '1') simultaneously.
[0046] ② Floating stage: Turn off the pre-charge tube to put the wiring in a floating state, and rely on the wiring capacitor to maintain a high level.
[0047] ③ Excitation and Detection Phase: For the target wiring (e.g., test line 1), a low-level (logic '0') excitation signal is applied to its bottom (first end) through the driving circuit. Simultaneously, the response signal is read back through the sensing circuit at the top (second end) of the target wiring.
[0048] ④ Result Judgment: If the readback signal is low, it indicates that the excitation signal has been successfully transmitted to the top through the entire wiring, the wiring has good connectivity, and the test passes. If the readback signal remains high, it indicates that there is an open circuit fault somewhere in the target wiring, the excitation signal failed to reach the top, and the test fails.
[0049] Short circuit test: This test is used to verify whether there is a short circuit (bridging) fault between any two physically adjacent wires.
[0050] ①Preparation and floating phase: Similar to the open circuit test, multiple wirings, including the target wiring and all its adjacent wirings, are precharged to a high level and then floated.
[0051] ② Excitation and Detection Phase: Instead of applying an excitation to the target wiring itself, a physically adjacent wiring is selected (e.g., for target wiring sequence 0, its adjacent wiring sequence 1 is selected), and a low-level excitation signal is applied to the bottom of this adjacent wiring. Simultaneously, a response signal is read back from the top of the target wiring.
[0052] ③ Result Judgment: If the readback signal remains high, it indicates that the electrical isolation between the target wiring and the adjacent wiring being excited is good, and there is no short circuit fault. If the readback signal is pulled low, it indicates that there is a short circuit fault between the target wiring and the adjacent wiring, and the charge is discharged through the short circuit point.
[0053] Efficient Exhaustive Testing Strategy: Due to the grouped twisted structure of this invention, the physical adjacency relationships of the wiring are regular, eliminating the need for indiscriminate exhaustive testing of short-circuit connections. Instead, an efficient "adjacent group wire exhaustive search" method can be employed. The core of this method is that for any target wiring, all possible physical short-circuit points exist only in a finite, definable set of adjacent wirings. This set explicitly includes: sequentially adjacent wirings within the same group, all wirings in the previous wiring group, and all wirings in the next wiring group.
[0054] The following is an example of test combination calculation, assuming there are three cabling groups in a cabling resource instance:
[0055] Group 1: Contains 2 wires (wire sequence 1, 2)
[0056] Group 2: Contains 3 wires (wire sequence 3, 4, 5)
[0057] Group 3: Contains 9 wires (wire sequence 6-14)
[0058] To achieve 100% short-circuit fault coverage, it is necessary to exhaustively test the short-circuit conditions of each cable with all adjacent cables within the defined range. The following example demonstrates a combined calculation:
[0059] Test Group 1 wiring: It is necessary to test whether there are short circuits between adjacent wirings within the group and all wiring in the entire Group 2.
[0060] Test Group 2 wiring: It is necessary to test whether there is a short circuit between adjacent wiring in the group, all wiring in the entire Group 1, and all wiring in the entire Group 3.
[0061] Test Group 3 wiring: It is necessary to test whether there are short circuits between adjacent wirings within the group and all wiring in Group 2.
[0062] By exhaustively applying the above rules to all wiring, the total number of test combinations can be calculated. Statistically, the total number of test combinations in this example is 4+3+2+9+1+9+9+2+1+1+1+1+1+1+1=46.
[0063] In contrast, if the adjacency pattern of this cabling structure is not utilized, and instead the traditional indiscriminate exhaustive method is used—that is, testing the short-circuit conditions of each cabling with all other cablings in the cabling resource—the total number of test combinations will increase dramatically. In this example, the total number of cablings is 2+3+9=14, and the number of test combinations for indiscriminate exhaustive testing is as high as 1+2+3+...+13=91.
[0064] This "adjacent group exhaustive search" method ensures 100% coverage of all possible physically adjacent short-circuit fault points. Calculations show that the total number of test cases using this method is only about 51% of the total number of test cases obtained through indiscriminate exhaustive search, reducing the testing cycle by nearly half and significantly improving testing efficiency while maintaining test coverage.
[0065] This invention, through the collaborative design of the aforementioned configurable segmented routing structure and its testing method, achieves high flexibility and scalability of FPGA routing resources while solving the industry problems of high testing complexity and long testing cycles, thus achieving significant technical benefits.
[0066] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. A test method for configurable segmented routing structures in FPGAs, characterized in that, The segmented cabling structure includes multiple cabling groups, each group containing multiple segmented cablings connected in a twisted manner, and includes the following: Open circuit test procedure: Connect multiple segmented wires into a complete electrical path through corresponding configurable switches, precharge the path to a predetermined level, and then float it. Apply an excitation signal of opposite level to the first end of the target wiring and read back the response signal from its second end; if the read-back signal is at the same level as the excitation signal, the target wiring is determined to have good connectivity. If the readback signal remains at the predetermined level, it is determined that there is an open circuit fault in the target wiring. Short circuit test procedure: Connect multiple segmented wires into a complete electrical path through corresponding configurable switches, precharge the path to a predetermined level, and then float it. An excitation signal of opposite level is applied to the first end of at least one adjacent wiring that is physically adjacent to the target wiring, and a response signal is read back from the second end of the target wiring; if the read-back signal remains at the predetermined level, it is determined that there is no short circuit between the target wiring and the adjacent wiring; if the read-back signal is pulled low, it is determined that there is a short circuit fault between the target wiring and the adjacent wiring.
2. The test method according to claim 1, characterized in that, In the short-circuit test step, an exhaustive test of adjacent lines is performed, that is, for each target cabling, the short-circuit condition between it and all physically adjacent cablings is tested. The physically adjacent cablings include: sequentially adjacent cablings within the same group, all cablings in the previous cabling group, and all cablings in the next cabling group.
3. The test method according to claim 2, characterized in that, By using the adjacent line exhaustive test, 100% wiring function test coverage is achieved, and the total number of test combinations is reduced by 40% to 50% compared to the indiscriminate full exhaustive test.
4. The test method according to claim 1, characterized in that, The predetermined level is a high level, and the opposite level is a low level.
5. A configurable segmented routing structure for an FPGA, tested using the test method described in any one of claims 1 to 4, characterized in that, include: Multiple configurable logic modules arranged in an array; Segmented routing resources are provided between rows and / or columns of the configurable logic module, and the segmented routing resources have a consistent structure in both the vertical and horizontal directions; The segmented cabling resources are divided into multiple cabling groups, and each cabling group contains multiple segmented cablings. The segmented cabling within each cabling group is interconnected by a twisted connection between different metal layers, enabling the cabling within the group to achieve multiple fixed lengths of cyclical alternation. Multiple configurable switches, set at specific locations in the segmented wiring, are used to control the connection status and effective length of the segmented wiring to achieve arbitrary length wiring configurations from 1 to n.
6. The FPGA configurable segmented routing structure according to claim 5, characterized in that, The configurable switch is a one-time programmable antifuse switch or an NMOS transistor switch controlled by a configuration memory.
7. The FPGA configurable segmented routing structure according to claim 5, characterized in that, The segmented cabling structure is constructed using a cascading expansion method, and its total cabling length can be adapted to the expansion of the configurable logic module array size by increasing the number of basic cabling units.
8. The FPGA configurable segmented routing structure according to claim 5, characterized in that, Within segmented routing, for the wiring with sequence m in group x, different wiring lengths can be achieved by setting a configurable switch on the wiring with sequence m+a, where: If the configurable switch is set at the end of two rows of CLBs, the achieved wiring length is 2a; if the configurable switch is set in the middle of two rows of CLBs, the achieved wiring length is 2a-1.
9. The FPGA configurable segmented routing structure according to claim 5, characterized in that, Furthermore, the physical layout of the twisted connection is achieved by the crossing of wires on different metal layers. Solid line segments represent wiring within the same metal layer, while dashed line segments represent wiring across layers by connecting to adjacent metal layers through vias.
10. An FPGA chip, characterized in that, It includes a configurable segmented cabling structure as described in any one of claims 5 to 9.