Vector-free method for testing of tested device

Abstract

A method and related system for testing a plurality of devices under test using an internal stimulus source is provided. The method feeds back outputs of the plurality of devices under test as inputs to the plurality of devices under test, wherein the fed-back outputs are internal stimulus sources and represent information entropies of each device under test. The method provides a drive signal to each of a plurality of devices under test. The method collects results output from each of the plurality of devices under test provided with the driving signal and compares the results between the plurality of devices under test. The method identifies a device that passes the test as a device that results in a consistent behavior.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a device testing system and method. Background Technology

[0002] As described in U.S. Patent No. 6,714,035 (the entire contents of which are incorporated herein by reference), the evaluation of the reliability and quality of digital integrated circuits (ICs) typically employs several different testing phases. These testing phases include verification testing, parameter testing, and defect testing.

[0003] The verification testing phase is the initial stage of testing the first prototype chip to ensure it matches its functional specifications, thus verifying the correctness of the design. The verification testing phase checks whether everything from layout to electrical parameters conforms to all design rules. The parameter testing phase ensures that the component meets design specifications for delay, voltage, power, etc.

[0004] The defect testing phase ensures that only defect-free production chips are packaged and shipped. This phase involves testing for a relatively large number of different physical defects that may be present.

[0005] One of the most practical methods for defect testing is to use a fault model of a physical defect, which can appear at a high level of abstraction in the IC, often at the logical level, and then develop algorithms for the modeled fault, often referred to as a functional test vector (FTV) set. Depending on the quality of the fault model and the FTV set, the FTV set can cover a high percentage of actual physical defects.

[0006] Automated fault testing for large-scale integrated circuits typically employs a so-called "stuck" fault model to simulate permanent faults that may occur during the manufacturing process of the integrated circuit under test. In this model, the circuit description is modified or otherwise presented to correspond to a stuck fault state, i.e., a series of logic states of logic low "0" or logic high "1". In a process known as fault simulation, a set of test vectors developed based on the stuck fault model is applied to the IC, and the corresponding response values ​​are compared to expected response values. After simulating numerous faults and running multiple test vectors, an indication of the fault coverage of the applied test vector set is provided. If the fault coverage is unacceptably low, the test vector set can be modified to test (exercise) parts of the circuit where faults that were previously undetectable exist. Summary of the Invention

[0007] In one embodiment of the present invention, a method is provided for testing multiple devices under test using internal stimuli. The method feeds back the outputs of the multiple devices under test as inputs to the multiple devices under test, wherein the feedback outputs are internal stimuli and represent the information entropy of each device under test. The method provides a driving signal to each of the multiple devices under test. The method collects the results from the outputs of each of the multiple devices under test to which the driving signals have been provided and compares the results between the multiple devices under test. The method identifies devices that pass the test as those exhibiting homogeneous behavior.

[0008] In one embodiment of the invention, a system is provided for testing multiple devices under test using internal stimuli. The system includes multiple devices under test, each comprising: a switching board for connecting a data stream between the output of the device under test and an input returned to the device under test; a controller configured to provide a drive signal to the device under test; a register configured to collect test results over time from the multiple devices under test provided with corresponding drive signals; and a comparator configured to compare the results between the multiple devices under test. The data stream between the output of the device under test and the input returned to the device under test provides an internal stimuli and represents the information entropy of the device under test.

[0009] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0010] Figure 1 This is a block diagram of a typical automated testing device.

[0011] Figure 2 This is a diagram of a typical test vector used in automated testing equipment.

[0012] Figure 3 This is a block diagram of a system for testing a device under test using internal sources of stimulation, according to an embodiment of the present invention.

[0013] Figure 4 This is a block diagram of a comparator for testing multiple devices under test according to another embodiment of the present invention;

[0014] Figure 5 This is a block diagram of another comparator for testing multiple devices under test according to yet another embodiment of the present invention.

[0015] Figure 6 This is a flowchart illustrating a method for testing multiple devices under test using an internal stimulus source according to another embodiment of the present invention. Detailed Implementation

[0016] Various embodiments are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and therefore should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. Throughout this disclosure, the same reference numerals denote the same parts in the drawings and embodiments of the invention.

[0017] This invention can be embodied in many ways, including as a process; an apparatus; a system; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by a memory coupled to the processor. In this specification, these embodiments or any other form in which the invention may take may be referred to as technology. Generally, the order of steps of the disclosed methods may be varied within the scope of this invention. Unless otherwise stated, components described as suitable for performing a task, such as processors or memory, may be implemented as general components temporarily configured to perform a task at a given time or manufactured as specific components for performing a task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0018] The following appendices illustrate various aspects of the invention. Figure 1 The present invention provides a detailed description of embodiments thereof. The invention has been described in conjunction with such embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims. The invention includes many alternatives, modifications, and equivalents within the scope of the claims. To provide a thorough understanding of the invention, numerous specific details are set forth in the following description. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail, so as not to unnecessarily obscure the invention.

[0019] like Figure 1As shown in the block diagram and as described in U.S. Patent No. 6,732,312 (the entire contents of which are incorporated herein by reference), a typical automated test apparatus (ATE) 10 includes a central processing unit (CPU) 14, memory 12, input / output (I / O) 16 hardware, and typically some form of operator interface 18. The CPU 14 uses test vectors stored in memory 12 to control the operation of the ATE 10. Test vectors, typically generated by an external source 20, are transferred to the ATE and loaded into memory 12 using the I / O hardware 16. During automated testing, the CPU 14 reads test vectors from memory and controls the I / O hardware 16 to influence the testing of the device under test (DUT) 30. The operator interacts with the ATE through the operator interface 18. For simplicity, the system under test or IC will be referred to as the device under test (DUT) hereinafter.

[0020] Typical automated testing in ATE 10 employs test vectors. A test vector is a sequence of test operations and / or test values ​​performed by the ATE on the system under test (SUT) or IC. In most modern ATEs, due to the extensive use of digital computers and memory and the fact that complex systems tend to be largely digitized, test vectors are binary sequences. Each test vector used by the ATE is typically generated by first querying a design database or specification that identifies the functionality of the system or IC being tested. A test vector for a given DUT is generated by “mapping” or converting the expected functional tests of the DUT into the functional test capabilities of the ATE. The test vector is then typically transferred to the ATE and stored in the ATE's memory. The test vector then controls the ATE's testing of the DUT.

[0021] Figure 2 An example of a typical test vector used with ATE 10 is shown. Figure 2 The first line, 81, shows a sequence generated by the Automatic Test Pattern Generator (ATPG), including an "irrelevant" state described as X. The next line, 82, shows a random binary sequence that can be generated by a random sequence generator. Finally, in Figure 2 The last line, 83, shows the fully specified test vector that exists after the corresponding bit from the random sequence is replaced with the "irrelevant" state. Figure 2 The last sequence of the last line 83 is typically transferred to the ATE's memory and stored there. The filled test vector is often referred to as a "fully specified" test vector to distinguish it from test vectors that include "irrelevant" states.

[0022] Typically, fully specified test vectors are transferred to and stored in the ATE's memory. Test vectors can be very large and can occupy a significant amount of memory within the ATE. In many cases, as detailed in the '312 patent, the memory required to store test vectors can account for up to 50% of the ATE's cost. Furthermore, even when the ATE's memory cost is not a critical factor, the time associated with transferring test vectors to the ATE's memory can be significant. Additionally, the apparatus may require more memory than is available in a given ATE to store test vectors.

[0023] Generally, existing techniques for device testing can be categorized into two main types: a) deterministic stimuli generated by an ATPG tool applied to the input of the DUT, and b) non-deterministic stimuli generated by a pseudo-random number generator. Regardless of the input, a forced comparison is made directly with the expected value of the DUT output or the expected characteristics collected by a multi-input shift register (MISR). Both methods require significant time and / or resources, especially considering the size of today's silicon chips.

[0024] Device testing of the present invention

[0025] This disclosure provides a method and system for device testing without requiring test vectors generated by ATPG tools. Therefore, the method and system for device testing eliminate the need for test vector verification (especially the verification portion).

[0026] For illustrative purposes, this invention can be considered to have two parts. In the first part, the information entropy of the DUT itself is used as a stimulus source. A switchboard connects the DUT's own output to its input, and control circuitry drives continuous signals to the DUT (including but not limited to clock, reset, shift enable, etc.). In this case, information entropy is generated by shifting the states of all flip-flops in the DUT due to pseudo-random values, and this random-type output (information entropy) is fed back to the DUT's input. In the second part, the invention utilizes the inventors' observation that, assuming only manufacturing defects, "good" or "healthy" devices behave in the same way during testing and produce the same response on the output. The output is captured on the MISR.

[0027] In one embodiment, the behavior of a “good” or “healthy” device is identified by those devices that have similar results, i.e., those that have the same or nearly identical results. Therefore, the novel method and system for device testing eliminates the need for mandatory use of ATPG tools as both a stimulus and a predictor, and eliminates the need for continuous vector validation. This makes the method and system useful for scanning chains (where triggers are sequentially connected to form a shift register of a given length to perform shift-in / shift-out operations) and for production testing.

[0028] Figure 3 This is a diagram of a single Device Test Unit (SDTU) 300 used in this disclosure for device testing. The SDTU 300 operates as follows: During operation, the DUT 302 generates a data output stream indicated by the arrow departing from the DUT 302. A switching board 304 exchanges the data stream back to the DUT input, forming a recursive entropy stream. The switching board 304 has two operating modes: a) plain-static commutation that is not intentionally altered during testing; b) featured-dynamic commutation controlled by the recursive entropy stream, where the input data is scrambled to provide an additional degree of randomization (i.e., increasing the randomness of the DUT's input data). Control circuitry 306 provides critical continuous signals to the DUT 302. It has operating modes: a) a plain-static relationship of control signals; b) a featured-dynamic (random) relationship of control signals via the recursive entropy stream. Figure 3 As shown, a continuous-action (or variable) factor is applied as an input to control circuit 306. Multi-input shift register (MISR) 308 collects signatures during testing. Figure 3 As shown, the MOUT signal 310 from MISR 308 is provided for the analysis of the DUT. (As...) Figure 3 As shown, an OUT signal 312 from the DUT 302 can also be provided for DUT analysis. The control circuitry 306 and MISR 308 may include memory elements for storing the output from the test.

[0029] from Figure 4 The following is an explanation of the detection of a "good" DUT, starting with the diagram. Figure 4 A comparator 400 is shown that compares the outputs of multiple single units 402. The multiple single units 402 have... Figure 3 The SDTU 300 uses the same components. Multiple individual units 402 provide the MOUT signal to the comparator 400.

[0030] The detection of a “good” DUT (a DUT with the same output) is performed as follows: a) the MOUT signals of all SDTU 402 (with a single DUT) are provided to comparator 400, b) the MOUT signals of each MISR of each SDTU 402 are compared with each other, and c) the always identical MOUT signals of multiple SDTU 402 are picked.

[0031] like Figure 4 As shown, a whole population of multiple SDTU 402s can be compared. However, in one embodiment, this disclosure does not require comparing the entire population to assess whether the SDTU population as a whole has acceptable quality (i.e., if all are tested, the entire population will be expected to show “good” results). In some cases, comparing the results of all multiple SDTU 402s may be impractical due to external computing resource requirements, tool limitations, etc. In one embodiment, the number N of multiple SDTU 402s (compared to the entire population that needs to be tested to assess the quality of the entire population) will depend on the yield. For example, if the manufacturing process is very mature, for example, with a fab yield of 99%, then even if the sample size is only 5% of the total population size, only 8.09E-06 errors can be predicted, which means that statistically, only this portion of the total population does not have “good” results, which is acceptable. On the other hand, if the yield is 77%, then for the same sample size of 5% of the total population, the probability of error increases to 7.19E-02 (or 7%), which is quite large and unacceptable. With a yield of 77% and a sample size of 25% of the total population, the probability of error decreases to 1.05E-03, which may be unacceptable for OEM customers and may require a larger sample size.

[0032] In another embodiment, the method for sampling and comparing which of the multiple SDRU 402s is based on yield information. Figure 5 The document provides a diagram illustrating this sampling method. Figure 5 A comparator 500 is shown that compares the outputs of N SDTUs 502 out of a plurality of SDTUs 502. The plurality of SDTUs 502 have... Figure 3 The SDTU 300 uses the same components. Multiple SDTU 502s provide OUT signals to comparator 500.

[0033] In one embodiment, the detection operation is as follows:

[0034] a) Select N sample sizes from multiple SUs.

[0035] b) Perform the detection of the entire sample size one detection step in advance.

[0036] c) At the end of the test step, compare the output.

[0037] d) Select a set of "good" units (where most units are expected to be "good" units, and a few units are expected to have different outputs) by means of output similarity (or consistency) and selection strategies such as yield.

[0038] e) Store the identifier (e.g., identification number) of each device in the set of devices defined in step “c” => STORAGE(n),

[0039] f) Compare the identifier of the current group with the identifier in the previous test step <= STORAGE(n-1).

[0040] g) Take the intersection of two groups with the same "good" attribute, and store the identifiers of the same devices with the same "good" attribute in the two groups in the current storage device: STORAGE(n) ∩ STORAGE(n-1) => STORAGE(n), and

[0041] h) Continue executing "b".

[0042] In this embodiment, the choice of N is an important factor. One factor influencing the size of N is the maturity of device manufacturing, and therefore the manufacturing yield of the group of devices under test (as shown in the examples above for yield and sample size N). Another factor influencing the strategy (or criteria) for choosing the size of N is based on the majority or minority of “good devices” and instrument performance. Instrument performance (such as the number of DUTs that can be tested simultaneously) can be limited by the available tester channels, thus limiting the size of N that can be actually sampled.

[0043] Since a sample represents only a portion or part of the entire population, a probabilistic model can be used in one embodiment to make a correct approximation of the sample representation. The probability of an error in a sample can be used to define the sample size (N). The following equation defines this probability in the case of a majority of good devices (i.e., most devices show the same result) in a given selected population.

[0044]

[0045] in,

[0046] – A combination of n items chosen from m items;

[0047] m tot – The total number of devices;

[0048] n sample - The sample size must be an odd number to avoid the 50 / 50 rule;

[0049] Y – Real-time production yield;

[0050] m d The total number of defective devices in the entire group is obtained from the following yield rate:

[0051]

[0052] n d – The number of defective devices in the sample size. Due to the majority strategy, a violation (and therefore an error) occurs when the number of defective devices in the sample is dominant or greater than the number of good devices. Therefore, n d Defined as:

[0053]

[0054] m g – The total number of good devices in the entire population, derived from the yield rate, is shown below:

[0055]

[0056] n g – The number of good devices in the sample, defined as follows:

[0057] ng = nsample - nd

[0058] The table below shows the calculation results when the parts per million defects (DPPM) requirement is set to 10:

[0059]

[0060] Operating method

[0061] Figure 6 This is a flowchart illustrating a method for testing multiple devices under test using internal stimuli. At 601, the method feeds back the outputs of the multiple devices under test as inputs, wherein the fed-back outputs are internal stimuli and represent the information entropy of each device under test. At 603, the method provides a driving signal to each of the multiple devices under test. At 605, the method collects the results from the outputs of each of the multiple devices under test to which driving signals have been provided and compares the results between the multiple devices under test. At 607, the method identifies the devices that pass the test as those exhibiting consistent behavior.

[0062] In one embodiment, the feedback output can use a switchboard to connect the data stream between the output of the device under test and the input returning to the device under test. In this embodiment, the switchboard can provide dynamic commutation of the feedback to increase the randomness of the feedback.

[0063] In one method embodiment, a controller that provides continuous signals is used to drive the device under test (DUT). In another method embodiment, collecting the results from each of the multiple DUTs can utilize registers to collect the results of the DUTs changing over time.

[0064] In one method embodiment, the results collected from the outputs of each of the plurality of devices under test can be collected from a group of devices being manufactured. The collected results can come from the entire group. In another method embodiment, the collected results can come from a portion of the group. The portion of the collected results from the group can be determined at least based on the total number of devices in the group and the expected manufacturing yield.

[0065] In one method embodiment, it is identified that a device that passes the test does not utilize the expected output value obtained from an external source.

[0066] System Implementation

[0067] In one embodiment of the invention, a system is provided for testing multiple devices under test using internal stimuli from a device under test. The system includes multiple devices under test, each of which includes a) a switching board connecting a data stream between the output of the device under test and an input returned to the device under test; b) a controller configured to provide a drive signal to the device under test; c) a register configured to collect test results over time from the multiple devices under test provided with corresponding drive signals; and d) a comparator configured to compare the results between the multiple devices under test. In this system, the data stream between the output of the device under test and the input returned to the device under test provides an internal stimuli and represents the information entropy of the device under test.

[0068] In one system embodiment, the comparator can be configured to collect results from the outputs of each of a plurality of devices under test and compare the results between the plurality of devices under test. The comparator can be configured to identify devices that pass the test as those exhibiting consistent behavior.

[0069] In one system embodiment, the switching board can be configured to provide dynamic commutation with feedback to increase the randomness of the feedback.

[0070] In one system embodiment, the controller can be configured to provide continuous signals to drive the device under test.

[0071] In one system embodiment, the comparator can be configured to collect results from a group of devices being manufactured. The comparator can be configured to collect results for the entire group. Alternatively, the comparator can be configured to collect results only for a portion of the group. The portion of results collected from the group can be determined based at least on the total number of devices in the group and the expected manufacturing yield.

[0072] In one system embodiment, the comparator can be configured not to use the expected output value of the device under test from an external source (i.e., a source outside the system described above).

[0073] The system described above allows the use of the inherent information entropy of the DUT to drive the input stimulus and eliminates the need for deterministic and non-deterministic expectation generation, as is done with other industrial tools. In one embodiment, a “good device” is selected by the consistent behavior of the “good device”, eliminating the need to compare the output from the device under test with the expected value, as is done with other industrial tools.

[0074] Although the embodiments described in detail above have been provided for clarity and understanding, the invention is not limited to the details provided. As will be understood by those skilled in the art based on the above disclosure, many alternatives to the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to include all modifications and alternatives recognized by those skilled in the art.

[0075] The embodiments of the subject matter and functional operation described in this patent application can be implemented in various systems, digital electronic circuits, or in computer software, firmware, or hardware including the structures disclosed in this specification and their equivalents, or in combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium for execution by a data processing device or for controlling the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination thereof. The devices, apparatuses, and machines for processing data in this invention, in addition to hardware, include code that creates an operating environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination thereof.

[0076] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program under discussion, or in multiple coordinating files (e.g., a file storing parts of one or more modules, subroutines, or code). A computer program can be deployed to run on a single computer, located in one place, or distributed across multiple locations and interconnected via a communication network. A computer program can be implemented as a computer program product comprising computer-readable media as described above.

[0077] The processes and logic flows described in this specification can be executed by one or more programmable processors, which run one or more computer programs to perform functions by manipulating input data and generating output. The processes and logic flows can also be executed by dedicated logic circuitry, and the device can be implemented as dedicated logic circuitry, such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit).

[0078] Processors suitable for running computer programs include, for example, general-purpose and special-purpose microprocessors, and any one or more processors in any type of digital computer. Typically, a processor receives instructions and data from read-only memory or random access memory, or both. The fundamental elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer also includes one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or is operatively coupled to one or more mass storage devices to receive data from or send data to, or both simultaneously. However, a computer does not need to have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including semiconductor memory devices such as EPROM, EEPROM, and flash memory devices. The processor and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0079] Although this patent application includes numerous details, these details should not be construed as limiting the scope of any invention or potentially claimed protection, but rather as a description of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of different embodiments in this patent application may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although the features above may be described as functioning in certain combinations, one or more features from the claimed combination may be removed from the combination in certain circumstances, thus the combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. A method for testing multiple test devices using internal stimuli, the method comprising: The outputs of the plurality of tested devices are fed back to the plurality of tested devices as inputs, wherein each of the fed-back outputs is an internal stimulus source and represents the information entropy of each tested device; Provide a drive signal to each of the plurality of devices under test; Collect the results from the output of each of the plurality of devices under test that are provided with the drive signal and compare the results between the plurality of devices under test; as well as Devices that pass the test are identified as those that exhibit consistent behavior.

2. The method according to claim 1, wherein, Feedback outputs include a data stream between the output of each of the plurality of devices under test connected by a switching board and the input returned to each of the plurality of devices under test.

3. The method according to claim 2, wherein, The switching board provides dynamic commutation feedback to increase the randomness of the feedback.

4. The method according to claim 2, wherein, Providing drive signals includes driving the plurality of devices under test using a controller that provides continuous signals.

5. The method according to claim 4, wherein, Collecting the results from the outputs of each of the plurality of devices under test includes using registers to collect the test results of the plurality of devices under test over time.

6. The method according to claim 1, wherein, Collecting results from the outputs of each of the plurality of tested devices includes collecting results from the group of devices being manufactured.

7. The method according to claim 6, wherein, Collecting results from the device group includes collecting results from the entire device group.

8. The method according to claim 6, wherein, Collecting results from the group of devices includes collecting results from a portion of the group of devices.

9. The method according to claim 7, wherein, The portion of the collected results in the device group is determined based at least on the total number of devices in the device group and the expected manufacturing yield.

10. The method according to claim 1, wherein, The device that passes the test does not use the expected output value of the device under test obtained from an external source.

11. A system for testing multiple test devices using internal stimuli, the system comprising: Multiple devices under test, each of the multiple devices under test comprising: A switching board connects the data stream between the output of each of the plurality of devices under test and the input returned to each of the plurality of devices under test; The controller provides drive signals to each of the plurality of devices under test; Registers that collect test results over time from the plurality of devices under test, which are provided with corresponding drive signals; and The comparator compares the results among the multiple tested devices. The data stream between the output of each of the plurality of tested devices and the input returned to each of the plurality of tested devices provides an internal stimulus source and represents the information entropy of each tested device.

12. The system according to claim 11, wherein, The comparator collects the results from the outputs of each of the plurality of devices under test and compares the results between the plurality of devices under test.

13. The system according to claim 11, wherein, The comparator identifies the tested device as one that exhibits consistent behavior.

14. The system according to claim 11, wherein, The switching board provides dynamic commutation feedback to increase the randomness of the feedback.

15. The system according to claim 11, wherein, The controller provides continuous signals to drive the plurality of devices under test.

16. The system according to claim 11, wherein, The comparator collects results from the group of devices being manufactured.

17. The system according to claim 16, wherein, The comparator collects results from the entire group of devices.

18. The system according to claim 16, wherein, The comparator collects results from a portion of the group of devices.

19. The system according to claim 18, wherein, The portion of the collected results in the device group is determined based at least on the total number of devices in the device group and the expected manufacturing yield.

20. The system according to claim 11, wherein, The comparator does not use the expected output value of the device under test obtained from an external source.

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