Chip detection method and device, terminal equipment and storage medium

Abstract

The invention is suitable for the technical field of image processing, and provides a chip detection method and device, terminal equipment and a storage medium, and the method comprises the steps: recognizing a body region of a chip body in a chip image through a chip detection segmentation size model, and carrying out the image alignment through an image alignment method, and aligning a body frame of a chip body in the chip detection segmentation size model with a body area in the chip image, determining a pin position range in the chip image according to a pin frame in the chip detection segmentation size model, identifying a chip pin in the pin position range, and then detecting the chip pin to obtain a detection result. According to the method, the predefined chip detection segmentation size model is introduced, the position of each chip pin is determined through the chip detection segmentation size model, each chip pin corresponds to one pin frame, and the chip pins are positioned according to the pin frames, so that the interference of a non-pin area in the image is effectively eliminated; and the probability that an interferent is misjudged as a pin is obviously reduced, so that the detection precision and reliability are greatly improved.

Description

Technical Field

[0001] This application belongs to the field of image processing technology, and in particular relates to a chip detection method, apparatus, terminal device and storage medium. Background Technology

[0002] Chip packaging is the process of cutting tested bare wafers, placing them on a substrate / lead frame, connecting the chip's interface to external circuits using sophisticated interconnection techniques, and finally wrapping and sealing them with a protective shell to form the final finished chip.

[0003] After chip packaging, chip quality requires testing, and the size and positional accuracy of the chip pins directly affect chip reliability. Currently, chip testing generally uses image processing methods. First, an image of the chip is acquired, and then image segmentation is performed based on the pixel values ​​to achieve chip testing. However, interference may exist during chip manufacturing, such as solder paste residue, stretching burrs, or dust. During image segmentation, these interferences may be identified as chip pins, leading to inaccurate chip testing. Summary of the Invention

[0004] This application provides a chip detection method, apparatus, terminal device, and storage medium, which can solve the problem of inaccurate chip detection.

[0005] In a first aspect, embodiments of this application provide a chip detection method, including: Acquire a chip image of the chip to be tested, wherein the chip to be tested includes a chip body and chip pins; Obtain the chip detection segmentation size model of the chip to be detected, wherein the chip detection segmentation size model is marked with the body frame of the chip body and the pin frame of each chip pin, and different chip pins correspond to different pin frames; The chip detection segmentation size model of the chip to be detected is matched with the chip image to determine the body region of the chip body in the chip image; Align the body frame with the body region, and obtain the pin position range of each chip pin in the chip image based on the position of the pin frame on the chip image; The chip pins are identified within the pin position range, the size of the chip pins is detected, and the detection result of the chip pins is obtained.

[0006] In this application, the chip body region in the chip image is first identified by a chip detection and segmentation size model. Then, the chip body bounding box in the chip detection and segmentation size model is aligned with the chip body region in the chip image by an image alignment method. The pin position range in the chip image is determined according to the pin bounding box in the chip detection and segmentation size model. The chip pins are identified within the pin position range, and then the chip pins are detected to obtain the detection result.

[0007] This application accelerates chip localization in chip images by introducing predefined template images and prioritizing matching larger chip body regions. Then, chip pins are located based on the chip body, yielding the position of each pin. Since each pin corresponds to a pin frame, locating the pins based on these frames effectively eliminates interference from non-pin areas in the image (such as solder paste residue, stretching burrs, or dust), significantly reducing the probability of misidentifying interference as pins, thereby greatly improving detection accuracy and reliability.

[0008] In one possible implementation of the first aspect, the step of matching a preset chip detection segmentation size model of the chip to be detected with the chip image to determine the body region of the chip body in the chip image includes: The chip detection segmentation size model of the chip to be detected is matched with the chip image to determine the candidate region and confidence level of the chip body in the chip image; If the confidence level is greater than or equal to a preset threshold, then the candidate region is determined to be the body region of the chip body in the chip image.

[0009] In one possible implementation of the first aspect, after matching the chip detection segmentation size model of the chip to be detected with the chip image to determine the candidate region and confidence level of the chip body in the chip image, the method further includes: If the confidence level is less than the preset threshold, the chip image is input into the trained neural network model to obtain the body region of the chip body in the chip image.

[0010] In one possible implementation of the first aspect, identifying the chip pin within the pin location range, detecting the size of the chip pin, and obtaining the detection result of the chip pin includes: Perform grayscale detection on the pixels within the pin position range to obtain the grayscale value of the pixels within the pin position range; Obtain the preset grayscale ranges corresponding to different sub-regions of the chip pin, wherein the chip pin is divided into different sub-regions and the preset grayscale ranges corresponding to different sub-regions are preset. Find the pixel corresponding to the gray value within the preset gray range to obtain the target pixel; Connect the target pixels to obtain the pin area of ​​the chip pin within the pin position range; The size of the chip pin is determined based on the pin area, and the detection result of the chip pin is obtained.

[0011] In one possible implementation of the first aspect, determining the size of the chip pin based on the pin region and obtaining the detection result of the chip pin includes: Edge detection is performed at different locations in the pin area using calipers to obtain the distance values ​​between edge point pairs at different locations in the pin area; The detection size of the chip pin in the pin region is determined based on the distance values ​​of edge point pairs at different locations; The detection size is compared with the preset size to obtain the detection result of the chip pin.

[0012] In one possible implementation of the first aspect, after using a caliper tool to perform edge detection at different locations in the pin region to obtain the distance values ​​of edge point pairs at different locations in the pin region, the method further includes: Extract the root point from the edge point pairs of multiple pin regions, wherein the root point is the edge point in the pin region that connects with the body region; A straight line is obtained by fitting a straight line based on the positions of all the root points; Based on the distance between the root point and the fitted line, outlier points are removed to obtain normal points. The outlier point is the root point whose distance from the fitted line is greater than a preset distance, and the normal point is the root point after removing the outlier point. Based on multiple target point pairs in the same pin region, multiple normal lines of the pin region are obtained, wherein the target point pair is the edge point pair where the normal point is located, and the normal line is the line connecting two points in the target point pair; The tilt of the chip pin corresponding to the pin region is determined based on the angle between the multiple normal lines and the fitted line. The detection result of the chip pin is obtained based on the tilt of the chip pin.

[0013] In one possible implementation of the first aspect, acquiring the chip image of the chip to be tested includes: Acquire multiple initial images of the chip to be tested, wherein the different initial images are images taken under different lighting conditions; Multiple initial images are fused to obtain a chip image of the chip to be detected.

[0014] Secondly, embodiments of this application provide a chip detection device, comprising: The image acquisition module is used to acquire a chip image of the chip to be tested, wherein the chip to be tested includes a chip body and chip pins; The model acquisition module is used to acquire the chip detection segmentation size model of the chip to be detected, wherein the chip detection segmentation size model is marked with the body frame of the chip body and the pin frame of each chip pin, and different chip pins correspond to different pin frames; The image matching module is used to match the chip image with a preset chip detection segmentation size model of the chip to be detected to determine the body region of the chip body in the chip image; The pin region determination module is used to align the body frame with the body region and obtain the pin position range of each chip pin in the chip image based on the position of the pin frame on the chip image; A pin detection module is used to identify the chip pins within the pin position range, detect the size of the chip pins, and obtain the detection results of the chip pins.

[0015] Thirdly, embodiments of this application provide a terminal device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the chip detection method described in any one of the first aspects above.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the chip detection method described in any one of the first aspects above.

[0017] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the chip detection method described in any of the first aspects above. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart of a chip detection method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a chip image provided in an embodiment of this application; Figure 3 This is a schematic diagram of a chip detection and segmentation size model of a chip provided in an embodiment of this application; Figure 4 This is a flowchart illustrating a method for determining the body region in a chip image according to an embodiment of this application; Figure 5 This is a schematic diagram of the pin frame and body frame provided in an embodiment of this application; Figure 6 This is a schematic flowchart of a chip pin detection method provided in an embodiment of this application; Figure 7 This is a schematic diagram of a pin area provided in an embodiment of this application; Figure 8 This is a schematic flowchart of a chip pin dimension detection method provided in an embodiment of this application; Figure 9 This is a schematic diagram illustrating the measurement of the width of a chip area using calipers, provided in an embodiment of this application. Figure 10 This is a schematic diagram illustrating the measurement of the length of a chip region using calipers, provided in an embodiment of this application. Figure 11 This is a schematic flowchart of a method for detecting the tilt of chip pins according to an embodiment of this application; Figure 12 This is a schematic diagram of a fitted straight line provided in an embodiment of this application; Figure 13 This is a schematic diagram of the normal line provided in an embodiment of this application; Figure 14 This is a schematic diagram of the structure of a chip detection device provided in an embodiment of this application; Figure 15 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0020] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0023] The size and positional accuracy of chip pins directly affect chip reliability. Differences in pin length, width, etc., can lead to cold solder joints, bridging, or open circuits. Therefore, after chip packaging, it is necessary to inspect the chip's dimensions to determine its quality.

[0024] Currently, the accuracy of chip detection is low because the dimensions of the chip pins are not accurately identified.

[0025] Based on this, this application proposes a chip detection method. This application pre-sets chip detection segmentation size models for different chips, marking the chip body and chip pins within these models, with different chip pins marked separately. The chip detection segmentation size model determines the region containing the chip body and the regions containing each chip pin in the acquired chip image. By identifying the grayscale values ​​of pixels in the regions containing the chip pins, the shape of the chip pins is determined, and then the size and tilt of the chip pins are detected. By separately marking different chip pins in the chip detection segmentation size model, this application effectively avoids inaccurate chip pin detection caused by process contamination such as pin shearing surface roughness, stretching burrs, solder paste residue, flux residue, oxide layer, fingerprints, and dust, thus improving the accuracy of chip detection.

[0026] The following combination Figure 1 The chip detection method of this application embodiment will be described in detail.

[0027] Figure 1 A schematic flowchart of the chip detection method provided in this application is shown, with reference to... Figure 1 The method is described in detail below: S101, acquire the chip image of the chip to be tested, wherein the chip to be tested includes the chip body and chip pins.

[0028] In this embodiment, the chip to be tested is a packaged chip.

[0029] In one approach, if a chip image is acquired under a single light source, the edge extraction error may be large due to the unclear chip image. To improve the quality of the chip image, multiple images can be acquired under different light sources and then fused together to obtain the final chip image.

[0030] Specifically, multiple initial images of the chip to be tested are acquired, wherein the different initial images are images taken under different lighting conditions; the multiple initial images are fused to obtain a chip image of the chip to be tested.

[0031] The specific implementation steps are as follows: The chip to be tested is placed at the image acquisition position, and multiple illumination lamps are set around the image acquisition position, for example, illumination lamps are set above, to the left, to the right, to the front, and to the rear of the image acquisition position. The illumination lamps at different positions are controlled to light up, and then an image of the chip to be tested is acquired to obtain an initial image. An image fusion algorithm is used to fuse the multiple acquired initial images to obtain a fused image, which is referred to as the chip image in this application.

[0032] For example, such as Figure 2 The image shown is a chip image resulting from the fusion of multiple initial images taken under different lighting conditions.

[0033] S102, obtain the chip detection segmentation size model of the chip to be detected, wherein the chip detection segmentation size model is marked with the body frame of the chip body and the pin frame of each chip pin, and different chip pins correspond to different pin frames.

[0034] In this embodiment, the chip detection segmentation size model is a wireframe size model, which explicitly defines the detection area size, relative position, dimensional tolerance, and tolerance range of each part of the chip. For example, the chip detection segmentation size model may include a chip detection segmentation size model for a square flat leadless package chip, a chip detection segmentation size model for a double-sided / square flat leadless package chip, and a chip detection segmentation size model for a small outline transistor package chip, etc.

[0035] The chip inspection and segmentation size model includes grayscale features and shape contour features of regions such as chip pins and body. Both grayscale features and shape contour features are used to determine the regions of the chip body and chip pins.

[0036] In the chip detection and segmentation size model, the chip body and each chip pin are distinguished, for example, Figure 3The diagram shows chip detection segmentation size models for different chips. These models define the detection range for chip pins, isolate burrs and solder paste on the pins, and optimize the identification area for subsequent chip pins, resulting in more accurate identification of candidate chip pins.

[0037] S103, the chip detection segmentation size model of the chip to be detected is matched with the chip image to determine the body region of the chip body in the chip image.

[0038] In one approach, a chip detection and segmentation size model and a chip image are input into a trained neural network model, and the chip detection and segmentation size model and the chip image are matched to obtain the body region of the chip body in the chip image.

[0039] In another approach, a template matching method is used to match the chip detection segmentation size model with the chip image to obtain the body region of the chip body in the chip image.

[0040] Specifically, the chip detection and segmentation size model is slid across the chip image. At each sliding position, the similarity between the region within the body bounding box of the chip detection and segmentation size model and the target region of the chip image is calculated. The target region is the area covered by the body bounding box of the chip detection and segmentation size model. The position with the highest similarity is found, and the target region with the highest similarity is determined as the body region.

[0041] In another way, such as Figure 4 As shown, the method for determining the ontology region may also include: S11, the chip detection segmentation size model is matched with the chip image to determine the candidate region and confidence level of the chip body in the chip image.

[0042] In this embodiment, the confidence score represents the degree of certainty about the prediction result. The confidence score is a numerical value used to quantify the similarity between the candidate region and the chip detection segmentation size model. The confidence score can be calculated using the squared difference matching algorithm. This algorithm calculates the sum of squares of the pixel differences between the chip detection segmentation size model and the chip image. Of course, in practical applications, other existing methods can also be used to calculate the confidence score, and this is not a limitation.

[0043] S12, if the confidence level is greater than or equal to a preset threshold, then the candidate region is determined to be the body region of the chip body in the chip image.

[0044] In this embodiment, if the confidence level is greater than or equal to a preset threshold, it indicates that the reliability of the chip body region determined by the chip detection segmentation size model is high, and the candidate region can be directly determined as the body region. The preset threshold can be set as needed and is not limited here.

[0045] S13, if the confidence level is less than the preset threshold, the chip image is input into the trained neural network model to obtain the body region of the chip body in the chip image.

[0046] In this embodiment, if the confidence level is less than a preset threshold, it indicates that the chip body region obtained by matching the chip detection segmentation size model is not accurate enough. In order to obtain a more accurate body region, a trained neural network is used to identify the chip image to obtain the body region of the chip body.

[0047] The neural network model is trained using sample images. These sample images are collected from different chips, and the ontology regions are labeled within them. The sample images are input into the neural network model, which outputs predicted ontology regions. These predicted regions are compared with the actual ontology regions labeled in the sample images, and a loss function is calculated. The parameters of the neural network model are then adjusted based on the loss function. This process is repeated until a preset number of training iterations are reached, resulting in the trained neural network model.

[0048] S104, Align the body frame with the body region, and obtain the pin position range of each chip pin in the chip image according to the position of the pin frame on the chip image.

[0049] In this embodiment, the body frame and the pin frame are mapped onto the chip image, the body frame is aligned with the body area, and the pin frame is located within the pin position range.

[0050] For example, such as Figure 5 As shown, the rectangle in the middle is the body frame of the body area. There are 4 frames on the top and bottom sides of the body area. Each frame is a pin frame. The area within the 4 frames is the pin position range.

[0051] S105, Identify the chip pin within the pin position range, detect the size of the chip pin, and obtain the detection result of the chip pin.

[0052] In this embodiment, the image within the pin location range is segmented based on the grayscale values ​​of the pixels within the pin location range to determine the outline of the chip pin. The size of the chip pin is then determined based on the outline of the chip pin to obtain the detection result of the chip pin.

[0053] The dimensions of the chip pins can include their width and length. The detection results can include width, length, and tilt measurements, among others.

[0054] Specifically, such as Figure 6 As shown, the implementation process of step S105 may specifically include: S1051, perform grayscale detection on the pixels in the pin position range to obtain the grayscale value of the pixels in the pin position range.

[0055] S1052, obtain the preset grayscale range corresponding to different sub-regions of the chip pin, wherein the chip pin is divided into different sub-regions and the preset grayscale range corresponding to different sub-regions is preset.

[0056] In this embodiment, to ensure more accurate identification of chip pins, different preset grayscale ranges can be set for different pin positions. The chip pin numbers are marked on the pin frame of the chip detection segmentation size model, and different correspondences between these numbers and preset grayscale ranges are pre-defined. The preset grayscale ranges can be marked on the chip detection segmentation size model; alternatively, they can be stored in a table in memory, containing the correspondence between the numbers and the preset grayscale ranges.

[0057] Furthermore, since chip pins may have connection points, different regions of the chip pins will exhibit different grayscale values ​​in the image. To handle the complex imaging situations of pins in actual production and to make the detection of chip pins more accurate, different preset grayscale ranges are set for different regions of the chip pins. The pixel points corresponding to the chip pins are determined based on the preset grayscale ranges corresponding to different regions, and these pixel points are recorded as target pixel points.

[0058] S1053, find the pixel corresponding to the gray value within the preset gray range to obtain the target pixel.

[0059] S1054, connect the target pixels in the same pin position range to obtain the pin area of ​​the chip pin in the pin position range.

[0060] For example, such as Figure 7 As shown, four pin areas are marked on the upper side of the body area, and the pin position range that has not yet been identified is marked on the lower side of the body area.

[0061] S1055, determine the size of the chip pin based on the pin area, and obtain the detection result of the chip pin.

[0062] In one approach, edge detection is performed on the pin area to determine the edges of the pin area, and the size of the chip pins is determined based on the edges of the pin area.

[0063] In another approach, a caliper edge detection algorithm can be used to calculate the distance between edge point pairs at different locations on the pin area, and the size of the chip pin can be determined based on the distance between the edge point pairs.

[0064] Specifically, such as Figure 8 As shown, the implementation of step S1054 may also include: S21, use calipers to perform edge detection at different positions in the pin area to obtain the distance values ​​of edge point pairs at different positions in the pin area.

[0065] In this embodiment, the chip pins are generally square; therefore, the pin area is generally square. Using a caliper edge detection method, a caliper tool is placed at different positions within the pin area to measure dimensions, resulting in multiple edge point pairs. Each position corresponds to one edge point pair, and each edge point pair corresponds to a distance value. Specifically, the edge point pairs can include multiple edge point pairs along the length direction and multiple edge point pairs along the width direction on the pin area. The edge point pairs along the length direction correspond to the length value of the pin area, and the edge point pairs along the width direction correspond to the width value of the pin area.

[0066] An edge point pair consists of two edge points, and the distance between the two edge points is the distance value of the edge point pair.

[0067] For example, such as Figure 9 As shown, the caliper tool is placed in the width direction of the pin area to detect the width of different positions in the pin area.

[0068] like Figure 10 As shown, the caliper tool is placed along the length of the pin area to measure the length at different positions in the pin area.

[0069] S22, determine the detection size of the chip pin in the pin area based on the distance values ​​of edge point pairs at different locations.

[0070] In this embodiment, a preset calibration range for the dimensions of the chip pins is obtained. Distance values ​​outside the calibration range are removed to obtain the target value, which is the distance value within the calibration range. The calibration range can be determined based on the actual dimensions of the chip pins.

[0071] In one approach, the average of multiple target values ​​along the length direction is calculated to obtain the length of the pin region, which is the length of the corresponding chip pin. Similarly, the average of multiple target values ​​along the width direction is calculated to obtain the width of the pin region, which is the width of the corresponding chip pin.

[0072] S23, compare the detected size with the preset size to obtain the detection result of the chip pin.

[0073] In this embodiment, the measured size is subtracted from the preset size to obtain the size difference. If the size difference is within the preset deviation range, it indicates that the size of the chip pins of the chip under test is qualified, and the test result of the chip pins is qualified. If the size difference is not within the preset deviation range, it indicates that the size of the chip pins of the chip under test is unqualified, and the test result of the chip pins is unqualified.

[0074] In another implementation, after obtaining the width and length of the pin region at different positions based on the distance values ​​of edge point pairs at different locations in step S12, a preset size threshold range corresponding to each position is obtained. If all widths are within the corresponding size threshold range and all lengths are within the corresponding size threshold range, then the detection result of the chip pin is determined to be dimensionally acceptable.

[0075] If at least one width is outside the corresponding size threshold range, and / or at least one length is outside the corresponding size threshold range, then the chip pin detection result is determined to be dimensionally unqualified.

[0076] For example, the width of the pin area is measured at positions 1, 2 and 3 in the width direction of the pin area; and the length of the pin area is measured at positions 4, 5 and 6 in the length direction of the pin area.

[0077] If the width of position 1 is within the corresponding size threshold range, the width of position 2 is not within the corresponding size threshold range, and the width of position 3 is not within the corresponding size threshold range, then the detection result of the chip pin is determined to be dimensionally unqualified.

[0078] If the width of position 1 is within the corresponding size threshold range, the width of position 2 is within the corresponding size threshold range, the width of position 3 is within the corresponding size threshold range, the length of position 4 is within the corresponding size threshold range, the length of position 5 is within the corresponding size threshold range, and the length of position 6 is within the corresponding size threshold range, then the detection result of the chip pin is determined to be dimensionally qualified.

[0079] The above describes the detection of length and width. After obtaining the edge point pairs, the tilt of the chip pins can also be detected based on the detected edge point pairs. Specifically, for example... Figure 11 As shown, the methods for detecting tilt include: S24, extract the root point from the edge point pairs of the plurality of pin regions, wherein the root point is the edge point in the pin region that connects with the body region.

[0080] In this embodiment, a caliper tool is used to determine the position of the edge point at the connection between the pin area and the body area, thus obtaining the root point.

[0081] S25, perform line fitting based on the positions of all the root points to obtain a fitted line.

[0082] In this embodiment, the root point is linearly fitted using the least squares method or Turkey regression fitting method to obtain a fitted straight line.

[0083] For example, such as Figure 12 As shown, the straight line at the junction of the pin area and the body area is the fitted straight line.

[0084] S26, based on the distance between the root point and the fitted straight line, remove outlier points to obtain normal points, wherein the outlier point is the root point whose distance from the fitted straight line is greater than a preset distance, and the normal point is the root point after removing the outlier point from the root points.

[0085] S27. Based on multiple target point pairs in the same pin region, multiple normal lines of the pin region are obtained, wherein the target point pair is the edge point pair where the normal point is located, and the normal line is the line connecting two points in the target point pair.

[0086] In this embodiment, multiple target point pairs exist within the same pin region. A line connecting a pair of target points forms a normal line, and multiple target point pairs result in multiple normal lines. In practical use, the method for determining the normal line can further include: selecting any two first point pairs from multiple first point pairs, and connecting the midpoints of the selected two first point pairs to obtain the normal line. Here, the first point pairs are the edge point pairs collected when the caliper tool is placed along a first direction, where the first direction is the same as the direction of the fitted line. In practical use, multiple sets of first point pairs can be selected to obtain multiple normal lines.

[0087] Alternatively, a straight line can be fitted to the midpoints of multiple first point pairs to obtain the normal line.

[0088] For example, such as Figure 13 As shown in the figure, the first point pair, the fitted line, and the normal line for each pin region are illustrated.

[0089] S28, determine the tilt of the chip pin corresponding to the pin region based on the angle between the normal line and the fitted line.

[0090] In this embodiment, if there are multiple normal lines, the angle between each normal line and the fitted line is calculated; the average or median of all angles is calculated to obtain the tilt of the chip pin corresponding to the pin area; or, multiple normal lines are compared to determine the direction of the normal lines, and normal lines whose direction does not meet the requirements are deleted to obtain the target line. The tilt of the chip pin is determined based on the angle between the target line and the fitted line.

[0091] S29, Based on the tilt of the chip pin, obtain the detection result of the chip pin.

[0092] In this embodiment, if the tilt is within the threshold range, the detection result is determined to be acceptable. If the tilt is not within the threshold range, the detection result is determined to be unacceptable.

[0093] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0094] Corresponding to the chip detection method described in the above embodiments, Figure 14 A structural block diagram of a chip detection device provided in an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0095] Reference Figure 14 The device 300 may include: an image acquisition module 310, a model acquisition module 320, an image matching module 330, a pin region determination module 340, and a pin detection module 350.

[0096] The image acquisition module 310 is used to acquire a chip image of the chip to be tested, wherein the chip to be tested includes a chip body and chip pins. The model acquisition module 320 is used to acquire the chip detection segmentation size model of the chip to be detected, wherein the chip detection segmentation size model is marked with the body frame of the chip body and the pin frame of each chip pin, and different chip pins correspond to different pin frames; Image matching module 330 is used to match the chip detection segmentation size model with the chip image to determine the body region of the chip body in the chip image; The pin region determination module 340 is used to align the body frame with the body region and obtain the pin position range of each chip pin in the chip image based on the position of the pin frame on the chip image. The pin detection module 350 is used to identify the chip pins within the pin position range, detect the size of the chip pins, and obtain the detection result of the chip pins.

[0097] In one possible implementation, the image matching module 330 can specifically be used for: The chip detection segmentation size model of the chip to be detected is matched with the chip image to determine the candidate region and confidence level of the chip body in the chip image; If the confidence level is greater than or equal to a preset threshold, then the candidate region is determined to be the body region of the chip body in the chip image.

[0098] In one possible implementation, the image matching module 330 can specifically be used for: If the confidence level is less than the preset threshold, the chip image is input into the trained neural network model to obtain the body region of the chip body in the chip image.

[0099] In one possible implementation, the pin detection module 350 can specifically be used for: Perform grayscale detection on the pixels within the pin position range to obtain the grayscale value of the pixels within the pin position range; Obtain the preset grayscale ranges corresponding to different sub-regions of the chip pin, wherein the chip pin is divided into different sub-regions and the preset grayscale ranges corresponding to different sub-regions are preset. Find the pixel corresponding to the gray value within the preset gray range to obtain the target pixel; Connect the target pixels within the same pin position range to obtain the pin region of the chip pin within the pin position range; The size of the chip pin is determined based on the pin area, and the detection result of the chip pin is obtained.

[0100] In one possible implementation, the pin detection module 350 can specifically be used for: Edge detection is performed at different locations in the pin area using calipers to obtain the distance values ​​between edge point pairs at different locations in the pin area; The detection size of the chip pin in the pin region is determined based on the distance values ​​of edge point pairs at different locations; The detection size is compared with the preset size to obtain the detection result of the chip pin.

[0101] In one possible implementation, the pin detection module 350 can specifically be used for: Extract the root point from the edge point pairs of multiple pin regions, wherein the root point is the edge point in the pin region that connects with the body region; A straight line is obtained by fitting a straight line based on the positions of all the root points; Based on the distance between the root point and the fitted line, outlier points are removed to obtain normal points. The outlier point is the root point whose distance from the fitted line is greater than a preset distance, and the normal point is the root point after removing the outlier point. Based on multiple target point pairs in the same pin region, multiple normal lines of the pin region are obtained, wherein the target point pair is the edge point pair where the normal point is located, and the normal line is the line connecting two points in the target point pair; The tilt of the chip pin corresponding to the pin region is determined based on the angle between the normal line and the fitted line. The detection result of the chip pin is obtained based on the tilt of the chip pin.

[0102] In one possible implementation, the image acquisition module 310 can specifically be used for: Acquire multiple initial images of the chip to be tested, wherein the different initial images are images taken under different lighting conditions; Multiple initial images are fused to obtain a chip image of the chip to be detected.

[0103] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0105] This application also provides a terminal device, see [link to relevant documentation] Figure 15 The terminal device 400 may include: at least one processor 410, a memory 420, and a computer program stored in the memory 420 and executable on the at least one processor 410. When the processor 410 executes the computer program, it implements the steps in any of the above method embodiments, for example... Figure 1 Steps S101 to S105 in the illustrated embodiment. Alternatively, when the processor 410 executes the computer program, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 14 The image acquisition module 310 to the pin detection module 350 shown have the following functions.

[0106] For example, a computer program may be divided into one or more modules / units, one or more of which are stored in memory 420 and executed by processor 410 to complete this application. The one or more modules / units may be a series of computer program segments capable of performing a specific function, which are used to describe the execution process of the computer program in terminal device 400.

[0107] Those skilled in the art will understand that Figure 15 This is merely an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, buses, etc.

[0108] The processor 410 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0109] The memory 420 can be an internal storage unit of the terminal device or an external storage device, such as a plug-in hard drive, a smart media card (SMC), a secure digital (SD) card, or a flash card. The memory 420 is used to store the computer program and other programs and data required by the terminal device. The memory 420 can also be used to temporarily store data that has been output or will be output.

[0110] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0111] The chip detection method provided in this application embodiment can be applied to terminal devices such as computers, tablets, laptops, netbooks, and personal digital assistants (PDAs). This application embodiment does not impose any restrictions on the specific type of terminal device.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] In the embodiments provided in this application, it should be understood that the disclosed terminal devices, apparatuses, and methods can be implemented in other ways. For example, the terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, apparatuses, or units, and may be electrical, mechanical, or other forms.

[0115] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0117] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by one or more processors, it can implement the steps of the various method embodiments described above.

[0118] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by one or more processors, it can implement the steps of the various method embodiments described above.

[0119] Similarly, as a computer program product, when the computer program product is run on a terminal device, it enables the terminal device to implement the steps in the above-described method embodiments.

[0120] The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0121] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for detecting a chip, characterized in that, include: Acquire a chip image of the chip to be tested, wherein the chip to be tested includes a chip body and chip pins; Obtain the chip detection segmentation size model of the chip to be detected, wherein the chip detection segmentation size model is marked with the body frame of the chip body and the pin frame of each chip pin, and different chip pins correspond to different pin frames; The chip detection segmentation size model is matched with the chip image to determine the body region of the chip body in the chip image; Align the body frame with the body region, and obtain the pin position range of each chip pin in the chip image based on the position of the pin frame on the chip image; The chip pins are identified within the pin position range, the size of the chip pins is detected, and the detection result of the chip pins is obtained.

2. The chip detection method as described in claim 1, characterized in that, The step of matching the chip detection segmentation size model with the chip image to determine the body region of the chip body in the chip image includes: The chip detection segmentation size model of the chip to be detected is matched with the chip image to determine the candidate region and confidence level of the chip body in the chip image; If the confidence level is greater than or equal to a preset threshold, then the candidate region is determined to be the body region of the chip body in the chip image.

3. The chip detection method as described in claim 2, characterized in that, After matching the chip detection segmentation size model of the chip to be detected with the chip image to determine the candidate region and confidence level of the chip body in the chip image, the method further includes: If the confidence level is less than the preset threshold, the chip image is input into the trained neural network model to obtain the body region of the chip body in the chip image.

4. The chip detection method according to any one of claims 1 to 3, characterized in that, The process of identifying the chip pins within the pin position range, detecting the size of the chip pins, and obtaining the detection result of the chip pins includes: Perform grayscale detection on the pixels within the pin position range to obtain the grayscale value of the pixels within the pin position range; Obtain the preset grayscale ranges corresponding to different sub-regions of the chip pin, wherein the chip pin is divided into different sub-regions and the preset grayscale ranges corresponding to different sub-regions are preset. Find the pixel corresponding to the gray value within the preset gray range to obtain the target pixel; Connect the target pixels within the same pin position range to obtain the pin region of the chip pin within the pin position range; The size of the chip pin is determined based on the pin area, and the detection result of the chip pin is obtained.

5. The chip detection method as described in claim 4, characterized in that, The step of determining the size of the chip pin based on the pin region and obtaining the detection result of the chip pin includes: Edge detection is performed at different locations in the pin area using calipers to obtain the distance values ​​between edge point pairs at different locations in the pin area; The detection size of the chip pin in the pin region is determined based on the distance values ​​of the edge point pairs at different locations; The detection size is compared with the preset size to obtain the detection result of the chip pin.

6. The chip detection method as described in claim 5, characterized in that, After using calipers to perform edge detection at different locations in the pin area and obtaining the distance values ​​between edge point pairs at different locations in the pin area, the method further includes: Extract the root point from the edge point pairs of multiple pin regions, wherein the root point is the edge point in the pin region that connects with the body region; A straight line is obtained by fitting a straight line based on the positions of all the root points; Based on the distance between the root point and the fitted line, outlier points are removed to obtain normal points. The outlier point is the root point whose distance from the fitted line is greater than a preset distance, and the normal point is the root point after removing the outlier point. Based on multiple target point pairs in the same pin region, multiple normal lines of the pin region are obtained, wherein the target point pair is the edge point pair where the normal point is located, and the normal line is the line connecting two points in the target point pair; The tilt of the chip pin corresponding to the pin region is determined based on the angle between the normal line and the fitted line. The detection result of the chip pin is obtained based on the tilt of the chip pin.

7. The chip detection method as described in claim 1, characterized in that, The acquisition of the chip image of the chip to be tested includes: Acquire multiple initial images of the chip to be tested, wherein the different initial images are images taken under different lighting conditions; Multiple initial images are fused to obtain a chip image of the chip to be detected.

8. A chip detection device, characterized in that, include: The image acquisition module is used to acquire a chip image of the chip to be tested, wherein the chip to be tested includes a chip body and chip pins; The model acquisition module is used to acquire the chip detection segmentation size model of the chip to be detected, wherein the chip detection segmentation size model is marked with the body frame of the chip body and the pin frame of each chip pin, and different chip pins correspond to different pin frames; The image matching module is used to match the chip image with a preset chip detection segmentation size model of the chip to be detected to determine the body region of the chip body in the chip image; The pin region determination module is used to align the body frame with the body region and obtain the pin position range of each chip pin in the chip image based on the position of the pin frame on the chip image; A pin detection module is used to identify the chip pins within the pin position range, detect the size of the chip pins, and obtain the detection results of the chip pins.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the chip detection method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the chip detection method as described in any one of claims 1 to 7.

Images