Phase difference determination method, slave power supply module and power supply parallel operation system

Abstract

The embodiment of the invention provides a phase difference determination method, a slave power supply module and a power supply parallel operation system. The slave power supply module is used for being in communication connection with a main power supply module in the power supply parallel operation system; the slave power supply module comprises a first peripheral; the method comprises the following steps: acquiring a first count value from a first peripheral; the first count value is the current count when the first peripheral detects the synchronizing signal sent by the main power supply module; the synchronizing signal is used for describing the change opportunity of the first PWM carrier wave; the first PWM carrier wave is output by the main power supply module; determining a phase difference between the first PWM carrier and a second PWM carrier according to the first count value, the second PWM carrier being output from the power supply module; the phase difference is used for managing the power supply parallel operation system. The method can improve the accuracy of determining the phase difference between the master and slave power supply modules.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and in particular to a phase difference determination method, a power supply module, and a power supply parallel system. Background Technology

[0002] In high-power applications, there are two power supply schemes: one is to use a single high-power power module to meet the load requirements, and the other is to use multiple low-power power modules connected in parallel to form a high-power power supply system to meet the load requirements. For the first scheme, a single power module failure can easily affect the power supply of the entire system; therefore, the second power supply scheme is currently more commonly used.

[0003] In scenarios where multiple power supply modules operate in parallel, slight differences in crystal oscillator timing can occur due to factors such as crystal oscillator errors and temperature drift in the main control chips of each module. Therefore, it is necessary to use pulse width modulation (PWM) counting of each power supply module for power synchronization. Without this power synchronization process, a phase difference will exist between the PWM carrier waves output by each power supply module, resulting in current ripple in the power supply system and affecting the power supply performance.

[0004] The commonly used approach is to calculate the phase difference between the master and slave power modules and achieve power synchronization based on the phase difference. However, the current phase difference determination method has certain drawbacks. Summary of the Invention

[0005] This application provides a phase difference determination method, a power supply module, and a power supply parallel system, which can improve the accuracy of phase difference determination between master and slave power supply modules.

[0006] In a first aspect, embodiments of this application provide a phase difference determination method applied to a slave power module in a power supply parallel system, wherein the slave power module is communicatively connected to a master power module; the slave power module includes a first peripheral device; the method includes: acquiring a first count value from the first peripheral device; the first count value being the current count when the first peripheral device detects a synchronization signal emitted by the master power module; the synchronization signal being used to describe the timing of changes in a first PWM carrier; the first PWM carrier being output by the master power module; determining the phase difference between the first PWM carrier and a second PWM carrier based on the first count value, wherein the second PWM carrier is output by the slave power module; the phase difference being used to manage the power supply parallel system.

[0007] The phase difference determination method provided in this application embodiment has a first peripheral device in the power module that has both the function of detecting the synchronization signal emitted by the main power module and a counting function. Thus, when the first peripheral device receives the synchronization signal, it can record the current count value as the first count value, without needing to additionally trigger the power module to read the first count value from the second peripheral device. This avoids the problem that the count value read by the power module from the second peripheral device may be inaccurate due to the power module's inability to respond to the action triggered by the first peripheral device in a timely manner, leading to a deviation and inaccurate phase difference determination. Therefore, through the independent counting of the first peripheral device, the power module can obtain a more accurate first count value from it. Since this first count value reflects the moment the synchronization signal is received, the power module can more accurately determine the phase difference between the second PWM carrier and the first PWM carrier based on the first count value. Managing the power parallel system based on a more accurate phase difference ensures the power supply effect of the power parallel system.

[0008] In one possible implementation, the power supply module further includes a second peripheral device. This second peripheral device controls the waveform of the second PWM carrier output by the power supply module via a counting function. Determining the phase difference between the first PWM carrier and the second PWM carrier based on a first count value includes: determining the phase relationship between the first PWM carrier and the second PWM carrier based on the first count value and the maximum count value of the second peripheral device; and determining the phase difference based on the first count value and the phase relationship. Since the first count value can reflect the waveform change position of the first PWM carrier, and the maximum count value of the second peripheral device in the power supply module determines the waveform of the second PWM carrier, the power supply module can accurately determine the phase difference between the first PWM carrier and the second PWM carrier based on the first count value and the maximum count value of the second peripheral device.

[0009] In another possible implementation, the counting method of the first peripheral is unidirectional. Based on the first count value and the maximum count value of the second peripheral, the phase relationship is determined, including: determining whether the second PWM carrier leads the first PWM carrier, or whether the second PWM carrier lags behind the first PWM carrier, based on the magnitude of the first count value and the maximum count value of the second peripheral. By setting the counting method to unidirectional, the phase relationship can be determined through simple numerical comparison, reducing the computational burden on the device and improving the efficiency of power synchronization.

[0010] In another possible implementation, where the counting method of the first peripheral is rising and the synchronization signal is transmitted at a zero-crossing point: if the first count value is less than the maximum count value of the second peripheral, the phase relationship is that the second PWM carrier leads the first PWM carrier; if the first count value is greater than the maximum count value of the second peripheral, the phase relationship is that the second PWM carrier lags behind the first PWM carrier. Through the above steps, a specific implementation method for determining the phase relationship is provided, improving the feasibility of this solution.

[0011] In another possible implementation, the phase difference is determined based on the first count value and the phase relationship, including: when the second PWM carrier leads the first PWM carrier, determining the ratio between the first count value and the counting frequency of the second peripheral as the phase difference; when the second PWM carrier lags the first PWM carrier, determining the ratio between the difference between the maximum count value of the first peripheral and the first count value, and the counting frequency of the second peripheral as the phase difference. Through the above steps, a specific implementation method for determining the phase difference is provided, improving the feasibility of this solution.

[0012] In another possible implementation, where the counting method of the first peripheral is rising and the synchronization signal is transmitted periodically: if the first count value is greater than the maximum count value of the second peripheral, the phase relationship is that the second PWM carrier leads the first PWM carrier; if the first count value is less than the maximum count value of the second peripheral, the phase relationship is that the second PWM carrier lags behind the first PWM carrier. Through the above steps, a specific implementation method for determining the phase relationship is provided, improving the feasibility of this solution.

[0013] In another possible implementation, the phase difference is determined based on the first count value and the phase relationship, including: when the second PWM carrier leads the first PWM carrier, determining the ratio between the difference between the first count value and the maximum count value of the second peripheral device, and the counting frequency of the second peripheral device, as the phase difference; when the second PWM carrier lags the first PWM carrier, determining the ratio between the difference between the maximum count value of the second peripheral device and the first count value, and the counting frequency of the second peripheral device, as the phase difference. These steps provide a specific implementation method for determining the phase difference, improving the feasibility of this solution.

[0014] In another possible implementation, the power configuration between the master power module and the slave power module includes: the maximum count value of the slave power module's second peripheral is the same as the maximum count value of the master power module's second peripheral; the counting method of the slave power module's second peripheral is the same as the counting method of the master power module's second peripheral; and the counting frequency of the slave power module's second peripheral is the same as the counting frequency of the master power module's second peripheral. By configuring the power configurations of the master and slave power modules to be consistent, the inherent differences between the power modules can be eliminated from the source, ensuring the accuracy of subsequent power synchronization.

[0015] In another possible implementation, the method further includes: when the phase difference is greater than a preset threshold, adjusting the maximum count value of the second peripheral device from the power module according to the phase difference, so that the second PWM carrier is synchronized with the first PWM carrier.

[0016] Secondly, embodiments of this application provide a power synchronization device, which includes one or more functional modules for implementing the phase difference determination method described in the first aspect above.

[0017] Thirdly, embodiments of this application provide a power supply module, including a controller and a first peripheral device; the controller is electrically connected to the first peripheral device; the first peripheral device is used to detect a synchronization signal emitted by the main power supply module and record a first count value when the synchronization signal is detected; the synchronization signal is used to describe the timing of the change of a first PWM carrier; the first PWM carrier is output by the main power supply module; the controller is used to obtain the first count value from the first peripheral device and determine the phase difference between the first PWM carrier and a second PWM carrier based on the first count value, wherein the second PWM carrier is output from the power supply module.

[0018] Fourthly, embodiments of this application provide a power supply parallel system, including a main power supply module and a slave power supply module, the slave power supply module being communicatively connected to the main power supply module; the slave power supply module includes a first peripheral device; the main power supply module is used to send a synchronization signal to the first peripheral device; the synchronization signal is used to describe the timing of changes in a first PWM carrier; the first PWM carrier is output by the main power supply module; the slave power supply module is used to: obtain a first count value from the first peripheral device; the first count value is the current count when the first peripheral device detects the synchronization signal; and determine the phase difference between the first PWM carrier and a second PWM carrier based on the first count value, the second PWM carrier being output by the slave power supply module.

[0019] Fifthly, embodiments of this application provide a computer-readable storage medium comprising: computer software instructions; when the computer software instructions are executed in a computing device, they cause the computing device to implement the method described in the first aspect.

[0020] In a sixth aspect, embodiments of this application provide a computer program product that, when run on a computing device, causes the computing device to execute the steps of the related method described in the first aspect above, so as to implement the method of the first aspect above.

[0021] The beneficial effects of the second to sixth aspects mentioned above can be referred to the corresponding descriptions in the first aspect, and will not be repeated here. Attached Figure Description

[0022] Figure 1 This application provides a schematic diagram illustrating the relationship between PWM counting and PWM carrier wave in an embodiment of the present application. Figure 2 A schematic diagram of the composition of a power supply parallel system 200 provided in an embodiment of this application; Figure 3 A schematic flowchart illustrating a phase difference determination method provided in an embodiment of this application; Figure 4 This application provides a schematic diagram of a configuration process. Figure 5 This is a schematic diagram of another configuration process provided in an embodiment of this application; Figure 6 A flowchart illustrating another phase difference determination method provided in an embodiment of this application; Figure 7 A schematic diagram of a phase relationship provided for an embodiment of this application; Figure 8 A schematic diagram illustrating another phase relationship provided in an embodiment of this application; Figure 9 A schematic diagram illustrating yet another phase relationship provided in an embodiment of this application; Figure 10 A schematic diagram illustrating yet another phase relationship provided in an embodiment of this application; Figure 11 A schematic diagram illustrating yet another phase relationship provided in an embodiment of this application; Figure 12 A flowchart illustrating another phase difference determination method provided in this application embodiment; Figure 13 A schematic diagram illustrating a PWM carrier adjustment process provided in an embodiment of this application; Figure 14 This is a schematic diagram of another PWM carrier adjustment process provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] It should be noted that in the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0025] To facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish the same or similar items with essentially the same function and effect. Those skilled in the art can understand that the terms "first" and "second" are not intended to limit the quantity or execution order.

[0026] The following is a brief explanation of the technical terms used in the embodiments of this application: 1. Digital Power Supply: Hereinafter referred to as a power module (or simply power supply), this refers to a power supply that delivers power through software programming. Compared to traditional power supplies, digital power supplies allow users to easily modify operating parameters and optimize the power supply performance of the module.

[0027] 2. Capture peripheral: A component of the power supply module. In a parallel power supply system, the capture peripheral adjusts its own parameters by detecting the synchronization signals of other power supply modules to achieve synchronization among the power supplies in the parallel system.

[0028] 3. PWM Peripheral: A component of the power supply module, it has a counting function, such as a PWM counter. By performing PWM counting, the waveform of the PWM carrier output by the power supply module is controlled. The PWM counting is performed periodically, with one PWM count value corresponding to a timing position of the PWM carrier output by the power supply module. The current PWM count value can be represented by cnt.

[0029] 4. PWM Register: Also known as the automatic reinstall register (ARR) in the power module. The value set in the PWM register is the maximum count value of the aforementioned PWM peripheral, which can be used to determine the single-cycle duration of the PWM carrier output by the power module. Therefore, the value set in the PWM register is also called the PWM counting period. The PWM counting period can be represented by arr.

[0030] 5. Counting Mode: Used to configure the counting mode of the timer. For example, the counting mode is divided into one-way and center-aligned. One-way mode means that the timer counts in an incrementing (or rising) or decrementing (or falling) manner. Center-aligned mode means that the timer counts in an ascending-then-descending or descending-then-ascending manner.

[0031] The "rising-then-falling" counting method involves the timer first incrementing to a certain value, then decrementing. For example, the timer first increments from zero to a certain value (e.g., from 0 to 100), then decrements from that value back to zero (e.g., from 100 to 0). Of course, after counting to zero, it can enter the next cycle and start counting again in the same incrementing-then-decrementing manner. The "falling-then-rising" counting method is similar and will not be repeated.

[0032] Figure 1 This is a schematic diagram illustrating the relationship between PWM counting and PWM carrier wave, provided as an embodiment of this application. This application uses a square wave as an example for illustration. Figure 1 As shown, the PWM counter counts in a rising-falling manner, that is, it counts from 0 to arr, and then from arr back to 0. Correspondingly, the PWM carrier is at a high level within the range of 0-arr. When the PWM count reaches arr, the PWM carrier goes low, that is, the PWM carrier goes low within the range of arr-0.

[0033] This application provides a phase difference determination method, which can improve the accuracy of power supply synchronization and ensure the power supply effect of the power supply parallel system.

[0034] In some embodiments, the phase difference determination method provided in this application includes a first peripheral device in the power module that has both the function of detecting the synchronization signal emitted by the main power module and a counting function. Thus, when the first peripheral device receives the synchronization signal, it can record the current count value as the first count value, without needing to additionally trigger the power module to read the first count value from the second peripheral device. This avoids the problem that the count value read by the power module from the second peripheral device might be inaccurate due to the power module's inability to respond promptly to the action triggered by the first peripheral device, leading to a deviation in the count value and subsequent inaccurate phase difference determination. Therefore, through independent counting by the first peripheral device, the power module can obtain a more accurate first count value. Since this first count value reflects the moment the synchronization signal is received, the power module can more accurately determine the phase difference between the second PWM carrier and the first PWM carrier based on the first count value. Managing the power parallel system based on a more accurate phase difference ensures the power supply effect of the power parallel system.

[0035] The embodiments provided in this application will now be described in detail with reference to the accompanying drawings.

[0036] Figure 2 This is a schematic diagram illustrating the composition of a power supply parallel system 200 provided in an embodiment of this application. Figure 2 As shown, the power parallel system 200 includes a main power module 201 and a slave power module 202. The main power module 201 and the slave power module 202 are communicatively connected.

[0037] In the power parallel system 200, the power supply used as a synchronization reference is called the master power supply module 201. The power supply used for synchronization adjustment based on the master power supply module 201 is called the slave power supply module 202.

[0038] In some implementations, the power parallel system 200 may include multiple slave power modules 202 to enable the power parallel system 200 to provide high-power supply capabilities. Each slave power module 202 can be synchronized with the master power module 201 as a synchronization reference. This embodiment uses one slave power module as an example for illustration.

[0039] The main power module 201 may include a controller and a second peripheral (the main power module serving as a synchronization reference may not include the first peripheral). The slave power module 202 may include a controller, a first peripheral, and a second peripheral. The first and second peripherals may be communicatively connected to the controller or directly integrated into the controller. This application embodiment mainly uses the slave power module 202 as an example for illustration.

[0040] As the core of the power module, the controller is programmable and can adjust the power supply's operating parameters according to user needs, thereby controlling the power module to adapt to the power supply requirements of different scenarios. The controller can be a microcontroller unit (MCU) or a digital signal processor (DSP). The first peripheral device can be a capture peripheral device, which is used by the power module 202 to communicate with the main power module 201 and detect the synchronization signal from the main power module 201. This synchronization signal describes the timing of the change in the first PWM carrier wave output by the main power module and is used for power synchronization. When the synchronization signal is received, the controller is triggered to enter an interrupt (capture interrupt) to process the synchronization signal. This synchronization signal is used for power synchronization.

[0041] In this embodiment, since the main power module 201 serves as the power source for synchronization, power synchronization is not required. Therefore, the main power module 201 does not need to acquire a synchronization signal, and thus the first peripheral may not be included.

[0042] The second peripheral device can be a PWM peripheral device used to perform PWM counting to control the waveform of the PWM carrier output from the power module 202.

[0043] In some implementations, the power configurations of each power module in the power parallel system 200 are made consistent. In the power parallel system 200, a first peripheral device of the power module 202 is used to count and detect the synchronization signal of the main power module 201. When the first peripheral device receives the synchronization signal, it records its current count value to obtain a first count value, which reflects the phase of the first PWM carrier output by the main power module 201. Then, the controller of the power module 202 obtains the first count value from the first peripheral device and determines the phase difference between the first PWM carrier output by the main power module 201 and the second PWM carrier output by the power module 202 based on the first count value. Finally, the controller can adjust the maximum count value of the second peripheral device according to the phase difference to synchronize the second PWM carrier with the first PWM carrier.

[0044] It should be noted that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0045] Figure 3This is a schematic flowchart illustrating a phase difference determination method provided in an embodiment of this application. Exemplarily, the phase difference determination method provided in this embodiment can be applied to... Figure 2 The power supply parallel system shown is implemented in the slave power supply module. Specifically, the method can be executed by the controller in the slave power supply module.

[0046] For example, to facilitate understanding of this solution, the configuration process of the main power module and the configuration process of the slave power module are described below.

[0047] Among them, such as Figure 4 As shown, the configuration process for the main power module may include the following steps: 1. Set the PWM counting mode of the second peripheral device included in the main power module to center-aligned (e.g., rising then falling). 2. Set the duty cycle of the synchronization signal (e.g., pulse synchronization signal) (determining the effective time of the synchronization signal). The duty cycle is configured to be greater than a first threshold, which is determined based on the transmission link loss time between the main power module and the slave power module, to ensure that the high-level duration of the synchronization signal (i.e., the effective time of the synchronization signal) is at least greater than the transmission link loss time between the main power module and the slave power module, so that the slave power module can effectively detect the synchronization signal. 3. Set the transmission period of the synchronization signal. The transmission period of the synchronization signal is less than a second threshold, by increasing the transmission frequency to reduce interference in the transmission link. 4. Set the timing of the synchronization signal transmission. For example, set the synchronization signal to be transmitted at the point where the first PWM carrier level changes (high to low, or low to high). Through the above configuration, the main power module can periodically send the synchronization signal, enabling the slave power module to perform power synchronization based on the synchronization signal. The above configurations for different parameters do not have a necessary order; the labels are only used to distinguish different parameters and do not constitute a restriction on the order.

[0048] like Figure 5 As shown, the configuration process for the slave power module can include the following steps: 1. Set the PWM counting mode to be the same as the master power module, both being center-aligned (e.g., rising / falling). 2. Set the PWM counting period of the slave power module to be the same as the PWM counting period of the master power module, e.g., both being arr. 3. Set the PWM counting frequency of the slave power module to be the same as the PWM counting frequency of the master power module, e.g., both being f. 4. Configure the first peripheral. For example, if the counting mode is rising, the counting frequency is f, and the maximum count value is twice the PWM counting period. After the settings are completed, enable the capture interrupt function so that after the first peripheral detects the synchronization signal, the slave power module can synchronize its power supply according to the synchronization signal. Note that the above configuration of different parameters does not have a necessary order; the labels are only used to distinguish different parameters and do not constitute a sequential restriction.

[0049] like Figure 3As shown, the phase difference determination method provided in this application embodiment may include the following steps: S301. Obtain the first count value from the first peripheral device.

[0050] The first count value is the current count when the first peripheral device detects the synchronization signal emitted by the main power module. The synchronization signal describes the timing of the change of the first PWM carrier, which is output by the main power module.

[0051] In this embodiment, an additional counting function (such as a capture counting function) is added to the first peripheral (i.e., the capture peripheral). The counting frequency of the first peripheral can be set to be the same as that of the second peripheral, so that both peripherals count at the same frequency. This allows the power supply module to adjust the maximum count value of the second peripheral based on the count value of the first peripheral. Alternatively, a mapping relationship can be established between the counting frequencies of the first and second peripherals, allowing the power supply module to convert the count value from the first peripheral to the count value of the second peripheral based on this mapping.

[0052] In this embodiment, the main power module sends a synchronization signal at regular intervals when the first external design count included in the main power module reaches a preset value, enabling other slave power modules to synchronize their power supply according to the synchronization signal. The timing of the synchronization signal transmission can correspond to the waveform change position of the first PWM carrier output by the main power module; for example, the transmission timing includes zero-crossing point transmission and periodic point transmission. The zero-crossing point refers to the position where the PWM count starts changing from zero, and the periodic point refers to the position where the PWM count starts changing from the maximum count value. Figure 1 In the PWM carrier wave shown, points a and b are the waveform change points of the PWM carrier wave. Point a can be called the zero-crossing point of the waveform corresponding to the PWM counting process (changing from zero), and point b can be called the period point of the waveform corresponding to the PWM counting process (counting to the maximum value).

[0053] For the slave power module, the first peripheral in the slave power module periodically counts, and locks the current count value when a synchronization signal is detected, obtaining a first count value. This first count value can reflect when the waveform of the first PWM carrier of the master power module changes, so that the slave power module can subsequently realize power synchronization based on the first count value.

[0054] In some implementations, to reduce interference in the transmission link, the period of the synchronization signal sent by the main power module can be shorter than the period of the PWM carrier.

[0055] S302. Determine the phase difference between the first PWM carrier and the second PWM carrier based on the first count value.

[0056] This phase difference, also known as the phase time difference, represents the time offset between two PWM carriers. The phase difference is used to manage power supply parallel systems.

[0057] The first PWM carrier wave is output from the main power module, and the second PWM carrier wave is output from the power module.

[0058] It should be noted that if the phase difference is less than the preset threshold, it means that the first PWM carrier and the second PWM carrier can be considered to be approximately synchronized, and there is no need to perform the subsequent power synchronization process.

[0059] In related technologies, the first peripheral device only has the function of detecting synchronization signals. When the first peripheral device detects a synchronization signal, it triggers an interrupt, causing the controller to read the current count value from the second peripheral device. However, the controller may be processing other higher-priority tasks and may not respond to the interrupt in time, resulting in a delay in reading the count value from the second peripheral device. This causes the controller to be unable to accurately determine the timing of receiving the synchronization signal, thus determining an inaccurate phase difference. In contrast, the embodiment of this application sets the first peripheral device to have its own counting capability. When the first peripheral device detects a synchronization signal, it can record a first count value. In this way, even if the controller delays in obtaining the first count value, the first count value will accurately reflect the timing of detecting the synchronization signal, avoiding errors in phase difference calculation.

[0060] In one possible implementation, such as Figure 6 As shown, the above S302 can be specifically implemented as follows: S3021. Determine the phase relationship between the first PWM carrier and the second PWM carrier based on the first count value and the maximum count value of the second peripheral device.

[0061] The maximum count value of the second peripheral is the maximum count value of the second peripheral. Alternatively, the maximum count value of the second peripheral is half the maximum count value of the first peripheral.

[0062] As mentioned earlier, the first count value can be used to reflect the waveform change position of the first PWM carrier, and the count value of the second peripheral in the power supply module determines the waveform of the second PWM carrier. Therefore, the power supply module can determine the phase relationship between the first PWM carrier and the second PWM carrier based on the first count value and the maximum count value of the second peripheral.

[0063] For example, the phase relationship includes the first PWM carrier leading the second PWM carrier, that is, the rising and falling edges of the first PWM carrier occur earlier than those of the second PWM carrier. Figure 7 As shown in (a), the first rising edge of the first PWM carrier is earlier than that of the second PWM carrier.

[0064] The phase relationship also includes the first PWM carrier lagging behind the second PWM carrier, meaning the rising and falling edges of the first PWM carrier occur later than those of the second PWM carrier. For example... Figure 7 As shown in (b), the first rising edge of the first PWM carrier is later than that of the second PWM carrier.

[0065] In some implementations, the first peripheral uses a unidirectional counting method (taking rising as an example), while the second peripheral uses a center-aligned counting method. Therefore, a complete counting cycle for the second peripheral is considered to be from 0 to arr and then from arr back to 0. A complete counting cycle for the first peripheral is considered to be from 0 to the maximum value Tcap. Therefore, to ensure that the counting cycles of the first and second peripherals are consistent, Tcap can be set to 2arr. Thus, the maximum count value of the second peripheral can be half the maximum count value of the first peripheral, i.e., 0.5Tcap. In this way, the power module can calculate the phase relationship between the first PWM carrier and the second PWM carrier based on the first count value of the first peripheral and half of the maximum count value of the first peripheral.

[0066] Specifically, S3021 can be implemented as follows: Based on the magnitude of the first count value and the maximum count value of the second peripheral device, determine the phase relationship as either the second PWM carrier leading the first PWM carrier, or the second PWM carrier lagging behind the first PWM carrier. Wherein, "the second PWM carrier leading the first PWM carrier" means that the phase of the second PWM carrier leads the phase of the first PWM carrier; "the second PWM carrier lagging behind the first PWM carrier" means that the phase of the second PWM carrier lags behind the phase of the first PWM carrier.

[0067] S3022. Determine the phase difference based on the first count value and the phase relationship.

[0068] After obtaining the first count value and phase relationship from the power module, the phase difference between the first PWM carrier and the second PWM carrier can be further determined, which facilitates subsequent power synchronization.

[0069] The process of determining the phase relationship in S3021 above will be explained below in the context of specific situations.

[0070] Case 1: When the counting mode of the first peripheral is rising and the synchronization signal is sent at the zero-crossing point: 1.1 If the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier; For example, such as Figure 8As shown, the main power module sends a synchronization signal at the zero-crossing point (point a in the figure), and the first count value obtained from the power module is T1 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is earlier than the start position of the PWM count from the main power module (i.e., the second PWM carrier leads the first PWM carrier), the first count value T1 is less than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier.

[0071] 1.2 If the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0072] For example, such as Figure 9 As shown, the main power module sends a synchronization signal at the zero-crossing point (point a in the figure), and the first count value obtained from the power module is T1 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is later than the start position of the PWM count from the main power module (i.e., the second PWM carrier lags behind the first PWM carrier), the first count value T1 is greater than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0073] Case 2: When the counting mode of the first peripheral is rising and the synchronization signal is sent at periodic points: 2.1 If the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier; For example, continue as Figure 8 As shown, the main power module sends a synchronization signal at the periodic point (point b in the figure), and the first count value obtained from the power module is T2 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is earlier than the start position of the PWM count from the main power module (i.e., the second PWM carrier leads the first PWM carrier), the first count value T2 is greater than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier.

[0074] 2.2 If the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0075] For example, continue as Figure 9As shown, the main power module sends a synchronization signal at the periodic point (point b in the figure), and the first count value obtained from the power module is T2 in the figure. It can be seen that when the start position (0) of the PWM count from the power module in the figure is later than the start position of the main power module (i.e., the second PWM carrier lags behind the first PWM carrier), the first count value T2 is less than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0076] Case 3: When the counting mode of the first peripheral is falling, and the synchronization signal is sent at the zero-crossing point: When the counting method of the first peripheral is descending, the judgment logic of case 3 is the opposite of that of case 1, that is: 3.1 If the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier; For example, such as Figure 10 As shown, the main power module sends a synchronization signal at the zero-crossing point (point a in the figure), and the first count value obtained from the power module is T1 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is earlier than the start position of the PWM count from the main power module (i.e., the second PWM carrier leads the first PWM carrier), the first count value T1 is greater than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier.

[0077] 3.2 If the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0078] For example, such as Figure 11 As shown, the main power module sends a synchronization signal at the zero-crossing point (point a in the figure), and the first count value obtained from the power module is T1 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is later than the start position of the PWM count from the main power module (i.e., the second PWM carrier lags behind the first PWM carrier), the first count value T1 is less than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0079] Case 4: When the counting mode of the first peripheral is falling, and the synchronization signal is sent at periodic points: When the counting method of the first peripheral is descending, the judgment logic of case 4 is the opposite of that of case 2 above, that is: 4.1 If the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier; For example, continue as Figure 10 As shown, the main power module sends a synchronization signal at the periodic point (point b in the figure), and the first count value obtained from the power module is T2 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is earlier than the start position of the PWM count from the main power module (i.e., the second PWM carrier leads the first PWM carrier), the first count value T2 is less than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier.

[0080] 4.2 If the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier leads the first PWM carrier.

[0081] For example, continue as Figure 11 As shown, the main power module sends a synchronization signal at the periodic point (point b in the figure), and the first count value obtained from the power module is T2 in the figure. It can be seen that when the start position (0) of the PWM count from the power module is later than the start position of the main power module (i.e., the second PWM carrier lags behind the first PWM carrier), the first count value T2 is greater than the maximum count value of the second peripheral device, 0.5Tcap. Therefore, if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

[0082] The process of determining the phase difference will be explained below for each of the different situations described above.

[0083] Regarding scenario 1 above, where the counting method of the first peripheral is rising and the synchronization signal is sent at the zero-crossing point: 1.1 When the second PWM carrier leads the first PWM carrier, the ratio between the first count value and the counting frequency of the second peripheral is determined as the phase difference; For example, in combination Figure 8 The phase difference is determined by the following expression:

[0084] Where T1 is the first count value and f is the counting frequency of the second peripheral.

[0085] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 8As can be seen from the above expression, the second PWM carrier leads the first PWM carrier by T1 count units. Therefore, the duration corresponding to T1 count units can be determined as the phase difference using the above expression.

[0086] 1.2 When the second PWM carrier lags behind the first PWM carrier, the ratio between the difference between the maximum count value of the first peripheral and the first count value and the count frequency of the second peripheral is determined as the phase difference.

[0087] For example, in combination Figure 9 The phase difference is determined by the following expression:

[0088] Where T1 is the first count value, and f is the counting frequency of the second peripheral device. This is the maximum count value of the first peripheral.

[0089] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 9 As can be seen from the above, the second PWM carrier leads the first PWM carrier by (Tcap-T1) count units. Therefore, the duration corresponding to (Tcap-T1) count units can be determined as the phase difference using the above expression.

[0090] Regarding scenario 2 above, where the counting method of the first peripheral is ascending and the synchronization signal is sent at periodic points: 2.1 When the second PWM carrier leads the first PWM carrier, the difference between the first count value and the maximum count value of the second peripheral is determined, and the ratio between the difference and the counting frequency of the second peripheral is the phase difference.

[0091] For example, in combination Figure 8 The phase difference is determined by the following expression:

[0092] Where T2 is the first count value, and f is the counting frequency of the second peripheral device. This is the maximum count value of the first peripheral.

[0093] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 8 As can be seen, the second PWM carrier leads the first PWM carrier. There are several counting units, therefore, the above expression can be used to determine... The duration corresponding to each counting unit is the phase difference.

[0094] 2.2 When the second PWM carrier lags behind the first PWM carrier, the difference between the maximum count value of the second peripheral and the first count value is determined, and the ratio between this difference and the counting frequency of the second peripheral is the phase difference.

[0095] For example, in combination Figure 9 The phase difference is determined by the following expression:

[0096] Where T2 is the first count value, and f is the counting frequency of the second peripheral device. This is the maximum count value of the first peripheral.

[0097] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 9 As can be seen, the second PWM carrier lags behind the first PWM carrier. There are several counting units, therefore, the above expression can be used to determine... The duration corresponding to each counting unit is the phase difference.

[0098] Regarding scenario 3 above, where the counting method of the first peripheral is descending and the synchronization signal is sent at the zero-crossing point: 3.1 When the second PWM carrier leads the first PWM carrier, the ratio between the difference between the maximum count value of the first peripheral and the first count value and the count frequency of the second peripheral is determined as the phase difference.

[0099] For example, in combination Figure 10 The phase difference is determined by the following expression:

[0100] Where T1 is the first count value, and f is the counting frequency of the second peripheral device. This is the maximum count value of the first peripheral.

[0101] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 10 As can be seen, the second PWM carrier leads the first PWM carrier. There are several counting units, therefore, the above expression can be used to determine... The duration corresponding to each counting unit is the phase difference.

[0102] 3.2 When the second PWM carrier lags behind the first PWM carrier, the ratio between the first count value and the counting frequency of the second peripheral is determined as the phase difference.

[0103] For example, in combination Figure 11 The phase difference is determined by the following expression:

[0104] Where T1 is the first count value and f is the counting frequency of the second peripheral.

[0105] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 11 As can be seen, the second PWM carrier lags behind the first PWM carrier. There are several counting units, therefore, the above expression can be used to determine... The duration corresponding to each counting unit is the phase difference.

[0106] Regarding scenario 4 above, where the counting method of the first peripheral is descending and the synchronization signal is sent periodically: 4.1 When the second PWM carrier leads the first PWM carrier, the ratio between the difference between the maximum count value of the second peripheral and the first count value is determined, and the ratio between the difference and the counting frequency of the second peripheral is the phase difference.

[0107] For example, in combination Figure 10 The phase difference is determined by the following expression:

[0108] Where T2 is the first count value, and f is the counting frequency of the second peripheral device. This is the maximum count value of the first peripheral.

[0109] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 10 As can be seen, the second PWM carrier leads the first PWM carrier. There are several counting units, therefore, the above expression can be used to determine... The duration corresponding to each counting unit is the phase difference.

[0110] 4.2 When the second PWM carrier lags behind the first PWM carrier, the difference between the first count value and the maximum count value of the second peripheral is determined, and the ratio between this difference and the counting frequency of the second peripheral is the phase difference.

[0111] For example, in combination Figure 11 The phase difference is determined by the following expression:

[0112] Where T2 is the first count value, and f is the counting frequency of the second peripheral device. This is the maximum count value of the first peripheral.

[0113] It can be understood that the counting frequency f represents the time required for each count value to increase or decrease by 1. From Figure 11 As can be seen, the second PWM carrier lags behind the first PWM carrier. There are several counting units, therefore, the above expression can be used to determine... The duration corresponding to each counting unit is the phase difference.

[0114] The specific application scenarios of phase difference are explained below. In one scenario, phase difference can be used for power synchronization, that is, the power module also performs the following: S303, when the phase difference is greater than a preset threshold, adjust the maximum count value of the second peripheral according to the phase difference so that the second PWM carrier is synchronized with the first PWM carrier.

[0115] In this embodiment of the application, after the power module obtains the phase difference, if the phase difference is greater than a preset threshold, the maximum count value of the second peripheral can be adjusted according to the phase difference to change the waveform of the second PWM carrier, so that the second PWM carrier is synchronized with the first PWM carrier.

[0116] In one possible implementation, the power module can employ a one-time compensation revision method, modifying the current count value of the second peripheral based on the phase difference. For example, when the second PWM carrier leads the first PWM carrier, the current count value is decreased by the count value corresponding to the phase difference. When the second PWM carrier lags behind the first PWM carrier, the current count value is increased by the count value corresponding to the phase difference. Through this revision method, alignment between the second PWM carrier and the first PWM carrier is forced, achieving power synchronization.

[0117] In another possible implementation, compensation can be performed periodically from the power module. For example... Figure 12 As shown, the above S303 can be implemented as follows: S3031. Determine the target number of times based on the phase difference and the preset adjustment range.

[0118] For example, the target number can be determined using the following expression;

[0119] Where M is the target number of times. Where N is the phase difference and N is the adjustment amplitude. This is the counting frequency of the second peripheral.

[0120] If the final value of M is not an integer, the adjustment range can be reduced, and / or M can be rounded up. The goal is to ensure the adjusted phase difference is within the expected range.

[0121] S3032. Determine the adjusted value based on the phase relationship and adjustment amplitude between the first PWM carrier and the second PWM carrier.

[0122] Specifically, when the phase relationship is that the second PWM carrier leads the first PWM carrier, the adjusted value is determined to be the sum of the initial value of the PWM register of the second peripheral and the adjustment amplitude (e.g., arr+N).

[0123] When the phase relationship is such that the second PWM carrier lags behind the first PWM carrier, the adjusted value is determined to be the difference between the initial value of the PWM register of the second peripheral and the adjustment amplitude (e.g., expressed as arr+N).

[0124] S3033, maintain the maximum count value of the second peripheral at the adjusted value for the target number of PWM cycles.

[0125] Specifically, when the phase relationship is that the second PWM carrier leads the first PWM carrier, if the maximum count value of the second peripheral is increased from arr to arr+N, the PWM period of the second carrier is lengthened, and the target number of cycles is maintained.

[0126] like Figure 13 As shown, the second PWM carrier leads the first PWM carrier. Therefore, by lengthening the PWM period of the second PWM carrier, after maintaining the target number of PWM periods M, the second PWM carrier can be aligned with the first PWM carrier. At this point, the PWM period of the second PWM carrier can be restored to its initial value (the maximum count value of the second peripheral can be restored to arr).

[0127] Specifically, when the phase relationship is that the second PWM carrier leads the first PWM carrier, if the maximum count value of the second peripheral is reduced from arr to arr-N, the PWM period of the second carrier is shortened, while maintaining the target number of cycles.

[0128] like Figure 14 As shown, the second PWM carrier lags behind the first PWM carrier. Therefore, by shortening the PWM period of the second PWM carrier, after maintaining the target number of PWM periods M, the second PWM carrier can be aligned with the first PWM carrier. At this point, the PWM period of the second PWM carrier can be restored to its initial value (the maximum count value of the second peripheral can be restored to arr).

[0129] The aforementioned periodic adjustment method can distribute the phase difference over at least one PWM cycle for phase compensation. This avoids circuit ripple caused by large changes in the PWM carrier wave during power synchronization within a single PWM cycle. Specifically, the smaller the adjustment amplitude N, the smaller the waveform change of the PWM carrier wave. In scenarios with multiple power supplies in parallel, this method can effectively achieve power synchronization and improve the power supply performance of the parallel power supply system.

[0130] For example, when N=1, power synchronization can be achieved with almost no change in the operating frequency (switching frequency) of the power module, thereby ensuring that the functional performance (stability and reliability) of the power module is not affected.

[0131] In other scenarios, phase difference can be used to determine the operational stability of a parallel power supply system. The power module can provide early warnings based on the magnitude of the phase difference (e.g., through the flashing frequency of warning lights, buzzers, etc.). A larger phase difference indicates poorer operational stability of the parallel power supply system, resulting in a higher level of warning output (e.g., a higher flashing frequency of warning lights, a louder buzzer), prompting users to make timely adjustments to avoid losses.

[0132] The phase difference determination method provided in this application embodiment has a first peripheral device in the power module that has both the function of detecting the synchronization signal emitted by the main power module and a counting function. Thus, when the first peripheral device receives the synchronization signal, it can record the current count value as the first count value, without needing to additionally trigger the power module to read the first count value from the second peripheral device. This avoids the problem that the count value read by the power module from the second peripheral device may be inaccurate due to the power module's inability to respond to the action triggered by the first peripheral device in a timely manner, leading to a deviation and inaccurate phase difference determination. Therefore, through the independent counting of the first peripheral device, the power module can obtain a more accurate first count value from it. Since this first count value reflects the moment the synchronization signal is received, the power module can more accurately determine the phase difference between the second PWM carrier and the first PWM carrier based on the first count value. Managing the power parallel system based on a more accurate phase difference ensures the power supply effect of the power parallel system.

[0133] As can be seen, the above mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, the embodiments of this application provide corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the modules and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0134] In an exemplary embodiment, this application also provides a power synchronization device. This power synchronization device may be the aforementioned slave power module. The power synchronization may include one or more functional modules for implementing the phase difference determination method of the above method embodiments.

[0135] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be executed by computer instructions instructing related hardware; for example, the related hardware can be a processor of a computing device. The program instructions can be stored in the above-described computer-readable storage medium, and when executed, they can implement the processes of the above method embodiments. The computer-readable storage medium can be memory. The above-described computer-readable storage medium can also be an external storage device, such as a hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. Further, the above-described computer-readable storage medium can include both memory and external storage devices. The above-described computer-readable storage medium is used to store the above-described computer program instructions and other programs and data required for the above-described software package translation.

[0136] This application also provides a computer program product, which includes a computer program that, when run on a computing device, causes the computing device to execute any of the phase difference determination methods provided in the above embodiments.

[0137] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0138] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

[0139] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A phase difference determination method, characterized by, A slave power module applied to a power parallel system, the slave power module is used for communication connection with a master power module in the power parallel system; the slave power module comprises a first peripheral device; the method comprises: obtaining a first count value from the first peripheral device; the first count value is a current count when the first peripheral device detects a synchronization signal sent by the master power module; the synchronization signal is used to describe a change timing of a first pulse width modulation (PWM) carrier; the first PWM carrier is output by the master power module; determining a phase difference between the first PWM carrier and a second PWM carrier according to the first count value, the second PWM carrier is output by the slave power module; the phase difference is used for management of the power parallel system.

2. The method of claim 1, wherein, The slave power module further comprises a second peripheral device, the second peripheral device is used for controlling a waveform of the second PWM carrier output by the slave power module through a counting function; The method further comprises: determining a phase relationship between the first PWM carrier and the second PWM carrier according to the first count value and a maximum count value of the second peripheral device; determining the phase difference according to the first count value and the phase relationship.

3. The method of claim 2, wherein, The counting mode of the first peripheral device is unidirectional; The method further comprises: determining the phase relationship according to a size of the first count value and the maximum count value of the second peripheral device, the phase relationship is that the second PMW carrier leads the first PWM carrier, or the second PWM carrier lags behind the first PWM carrier.

4. The method of claim 3, wherein, In a case that the counting mode of the first peripheral device is rising type, and in a case that the sending timing of the synchronization signal is zero-crossing point sending: if the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PMW carrier leads the first PWM carrier; if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PMW carrier lags behind the first PWM carrier.

5. The method of claim 4, wherein, The method further comprises: in a case that the second PMW carrier leads the first PWM carrier, determining a ratio between the first count value and a counting frequency of the second peripheral device as the phase difference; in a case that the second PMW carrier lags behind the first PWM carrier, determining a ratio between a difference between the maximum count value of the first peripheral device and the first count value and the counting frequency of the second peripheral device as the phase difference.

6. The method of claim 3, wherein, In a case that the counting mode of the first peripheral device is rising type, and in a case that the sending timing of the synchronization signal is period point sending: if the first count value is greater than the maximum count value of the second peripheral device, the phase relationship is that the second PMW carrier leads the first PWM carrier; If the first count value is less than the maximum count value of the second peripheral device, the phase relationship is that the second PWM carrier lags behind the first PWM carrier.

7. The method of claim 6, wherein, The determining the phase difference according to the first count value and the phase relationship comprises: In the case that the second PWM carrier leads the first PWM carrier, determining the ratio between the difference between the first count value and the maximum count value of the second peripheral device and the count frequency of the second peripheral device as the phase difference; In the case that the second PWM carrier lags behind the first PWM carrier, determining the ratio between the difference between the maximum count value of the second peripheral device and the first count value and the count frequency of the second peripheral device as the phase difference.

8. The method according to any one of claims 1 to 7, characterized in that, The power supply configuration between the master power supply module and the slave power supply module comprises: The maximum count value of the second peripheral device of the slave power supply module is the same as the maximum count value of the second peripheral device of the master power supply module; The count mode of the second peripheral device of the slave power supply module is the same as the count mode of the second peripheral device of the master power supply module; The count frequency of the second peripheral device of the slave power supply module is the same as the count frequency of the second peripheral device of the master power supply module.

9. A power module from a power supply module, characterized by The master power supply module comprises a controller and a first peripheral device; the controller is electrically connected with the first peripheral device; The first peripheral device is configured to detect a synchronization signal sent by the master power supply module and record a first count value when the synchronization signal is detected; the synchronization signal is used to describe the change timing of a first PWM carrier; the first PWM carrier is output by the master power supply module; The controller is configured to acquire the first count value from the first peripheral device and determine the phase difference between the first PWM carrier and a second PWM carrier according to the first count value; the second PWM carrier is output by the slave power supply module.

10. A power parallelization system, characterized by, The master power supply module and the slave power supply module are connected in communication; the slave power supply module comprises a first peripheral device; The master power supply module is configured to send a synchronization signal to the first peripheral device; the synchronization signal is used to describe the change timing of a first PWM carrier; the first PWM carrier is output by the master power supply module; The slave power supply module is configured to acquire a first count value from the first peripheral device; the first count value is the current count of the first peripheral device when the synchronization signal is detected; The slave power supply module is configured to acquire a first count value from the first peripheral device; the first count value is the current count of the first peripheral device when the synchronization signal is detected; The slave power supply module is configured to acquire a first count value from the first peripheral device; the first count value is the current count of the first peripheral device when the synchronization signal is detected;

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