Circuit board manufacturing method, circuit board and laser processing equipment

Abstract

The invention provides a manufacturing method of a circuit board, the circuit board and laser processing equipment. The manufacturing method comprises the following steps: preparing a dielectric layer on a substrate; preparing a first sacrificial layer on the main surface of the dielectric layer, and selectively removing the first sacrificial layer to form a first pattern; providing laser with a preset condition on the first sacrificial layer on which the first pattern is formed so as to etch a circuit pattern along the thickness direction of the dielectric layer based on the first pattern; and filling metal in the circuit pattern to form a target circuit. According to the circuit board, the problem that refinement, lightness, thinness, low cost and high production yield cannot be considered at the same time during circuit manufacturing in an existing circuit board is solved.

Description

Technical Field

[0001] This application relates to the field of circuit board manufacturing technology, and in particular to a method for manufacturing a circuit board, as well as the circuit board and laser processing equipment. Background Technology

[0002] In related technologies, circuit board (PCB) fabrication mainly employs subtractive processes, semi-additive processes (SAP), and modified semi-additive processes (mSAP). For example, subtractive processes have technological limitations and cannot meet the requirements for fine circuitry (line width / spacing < 50μm); semi-additive processes have difficulty controlling copper thickness uniformity and cannot meet the demand for thinner and lighter designs; modified semi-additive processes have a high risk of over-etching and are costly. Therefore, how to balance fineness, thinness, low cost, and high production yield in the fabrication of PCB circuitry has become an urgent technical problem to be solved. Summary of the Invention

[0003] This application provides a method for manufacturing a circuit board, as well as the circuit board and laser processing equipment, which solves the problem that the manufacturing of circuits in existing circuit boards cannot simultaneously achieve precision, thinness, low cost, and high production yield.

[0004] This application is implemented as follows: a method for manufacturing a circuit board, comprising: A dielectric layer is fabricated on a substrate; A first sacrificial layer is prepared on the main surface of the dielectric layer, and the first sacrificial layer is selectively removed to form a first pattern; A laser with preset conditions is applied to the first sacrificial layer on which the first pattern is formed, so as to etch a circuit pattern along the thickness direction of the dielectric layer based on the first pattern. Metal is filled into the circuit pattern to form the target circuit.

[0005] In some embodiments, the first sacrificial layer includes a photosensitive material layer; The process of preparing a first sacrificial layer on the main surface of the dielectric layer and selectively removing the first sacrificial layer to form a first pattern includes: A photosensitive material layer is formed on the main surface of the dielectric layer, and the photosensitive material layer is selectively removed by exposure and development to form a first pattern, wherein the dielectric layer is exposed from the first pattern.

[0006] In some embodiments, the first sacrificial layer includes a photosensitive material layer and a metal blocking layer; The process of preparing a first sacrificial layer on the main surface of the dielectric layer and selectively removing the first sacrificial layer to form a first pattern includes: The metal barrier layer is formed on the main surface of the dielectric layer, and the photosensitive material layer is formed on the metal barrier layer; The photosensitive material layer is selectively removed by exposure and development to form a second pattern, wherein the metal barrier layer is exposed from the second pattern; Based on the second pattern, the metal barrier layer is selectively removed by chemical etching to form a first pattern, wherein the dielectric layer can be exposed from the first pattern.

[0007] In some embodiments, a laser with preset conditions includes a laser with a preset energy density, a preset number of pulses, or a preset processing time.

[0008] In some embodiments, the laser beam with preset conditions applied to the first sacrificial layer on which the first pattern is formed has a flat-topped beam shape.

[0009] In some embodiments, the laser with preset conditions is a deep ultraviolet laser; And / or, the laser output with preset conditions is a pulsed laser or a continuous laser.

[0010] In some embodiments, filling the circuit pattern with metal includes: A metal seed layer is prepared on the dielectric layer, the metal seed layer covering the main surface and the bottom and side surfaces of the circuit pattern, wherein the metal seed layer on the side surface of the circuit pattern is electrically connected to the metal seed layer on the bottom surface of the circuit pattern and the metal seed layer on the main surface, respectively. A metal conductive layer is prepared on each of the metal seed layers; Remove the metal seed layer and the metal conductive layer from the main surface.

[0011] In some embodiments, after providing a laser with preset conditions to etch a circuit pattern along the thickness direction of the dielectric layer based on the first pattern in the first sacrificial layer, and before filling the circuit pattern with metal, the method further includes: Remove the first sacrificial layer from the main surface; The circuit pattern and the main surface are cleaned.

[0012] In some embodiments, after cleaning the circuit pattern and the main surface, the method further includes: A second sacrificial layer is prepared on the main surface, and a third pattern is processed on the second sacrificial layer; According to the third pattern, a laser with preset conditions is provided to the second sacrificial layer on which the third pattern is formed, so as to etch at least a portion of the circuit pattern along the thickness direction of the dielectric layer based on the third pattern; Remove the second sacrificial layer from the main surface; The circuit pattern and the main surface are cleaned.

[0013] This application also provides a circuit board, which is manufactured using the manufacturing method described in any of the above embodiments. It includes a substrate, a dielectric layer, and a target circuit. The substrate has conductive circuits. The dielectric layer is disposed on the substrate and covers the conductive circuits. The main surface of the dielectric layer has a circuit pattern, and the main surface is the surface facing away from the substrate. The target circuit is filled within the circuit pattern.

[0014] This application also provides a laser processing device for fabricating circuit boards using the fabrication method described in any of the above embodiments. The device includes a laser emitting device, a shaping component, and a control component. The laser emitting device is configured to emit deep ultraviolet laser light. The shaping component is configured to shape the deep ultraviolet laser light into a flat-top spot. The control component is configured to control the energy density, number of pulses, or processing time based on processing requirements.

[0015] The beneficial effects of the circuit board manufacturing method, circuit board, and laser processing equipment provided in this application are as follows: Compared with the prior art, when manufacturing the target circuit, this application first forms a first pattern on the sacrificial layer, and then etches the circuit pattern on the dielectric layer according to the first pattern. This can improve the etching accuracy of the circuit pattern, making the target circuit formed by filling the circuit pattern with metal more refined and thinner. This method of etching the circuit pattern does not require highly precise etching tools, which greatly reduces the etching cost. In addition, laser etching of the dielectric layer can more accurately control the shape and size of the etching, making the processing parameters of the circuit pattern more controllable, thereby obtaining a more accurate target circuit, effectively improving the production yield of the circuit board and reducing production costs. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a method for manufacturing a circuit board according to an embodiment of this application; Figure 2 This is a flowchart of another method for manufacturing a circuit board provided in an embodiment of this application; Figure 3 This is a flowchart of another method for manufacturing a circuit board provided in an embodiment of this application; Figure 4 yes Figure 1 A schematic diagram of the device after step S101 is executed; Figure 5 yes Figure 2 A schematic diagram of the device after step S202 is executed; Figure 6 yes Figure 2 A schematic diagram of the device after step S203 is executed; Figure 7 yes Figure 2 A schematic diagram of the device after step S204 is executed; Figure 8 yes Figure 3 A schematic diagram of the device after step S302 is executed; Figure 9 yes Figure 3 A schematic diagram of the device after step S303 is executed; Figure 10 yes Figure 3 A schematic diagram of the device after step S304 is executed; Figure 11 yes Figure 3 A schematic diagram of the device after step S305 is executed; Figure 12 yes Figure 1 Flowchart of the specific implementation method of step S104; Figure 13 yes Figure 12 A schematic diagram of the device after step S1041 is executed; Figure 14 yes Figure 12 A schematic diagram of the device after step S1042 is executed; Figure 15 yes Figure 12 A schematic diagram of the device after step S1043 is executed; Figure 16 This is a flowchart of another method for manufacturing a circuit board provided in an embodiment of this application; Figure 17 This is a schematic diagram of the circuit board structure provided in the embodiments of this application.

[0017] Reference numerals: 10, substrate; 11, conductive line; 20, dielectric layer; 201, main surface; 30, first sacrificial layer; 301, first pattern; 31, photosensitive material layer; 310, second pattern; 32, metal barrier layer; 40, circuit pattern; 50, target circuit; 51, metal seed layer; 52, metal conductive layer. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] It should also be noted that in the embodiments of this application, the same reference numerals are used to represent the same component or part. For the same part in the embodiments of this application, the reference numerals may only be used to mark one part or component as an example. It should be understood that the reference numerals are also applicable to other identical parts or components.

[0023] This application provides a method for manufacturing a circuit board, as well as the circuit board and laser processing equipment, which solves the problem that the manufacturing of circuits in existing circuit boards cannot simultaneously achieve precision, thinness, low cost, and high production yield.

[0024] refer to Figure 1 The method for manufacturing a circuit board provided in this application includes the following steps: S101. Prepare a dielectric layer 20 on the substrate 10.

[0025] refer to Figure 4 , Figure 4 This is a schematic diagram of the device after step S101 is executed.

[0026] The substrate 10 includes at least one insulating layer structure and at least one conductive layer structure. The substrate 10 can be formed by combining the at least one insulating layer structure and at least one conductive layer structure together by applying mechanical pressure and / or heat. The substrate 10 can serve as the basis for fabricating a board-shaped circuit board, which can provide a large mounting surface for other components. The substrate 10 can be very thin and compact, which is beneficial for making the overall circuit board thinner and lighter.

[0027] It should be noted that the dielectric layer 20 can be made of insulating materials, such as ABF (Ajinomoto Build-up Film / ABF epoxy resin), PI (Polyimide / polyimide resin), PTFE (polytetrafluoroethylene) and other resins. This facilitates the fabrication of conductive lines 11 within the dielectric layer 20.

[0028] S102. A first sacrificial layer 30 is prepared on the main surface 201 of the dielectric layer 20, and the first sacrificial layer 30 is selectively removed to form a first pattern 301.

[0029] Here, the main surface 201 of the dielectric layer 20 refers to the side surface of the dielectric layer 20 facing away from the substrate 10.

[0030] It should be noted that after step S102 is executed, a first sacrificial layer 30 with a first pattern 301 is obtained, so that the dielectric layer 20 can be etched according to the first pattern 301 to obtain the circuit pattern 40. Here, the first sacrificial layer 30 with the first pattern 301 can be understood as a mask layer with a mask pattern, which makes the circuit pattern 40 obtained by etching the dielectric layer 20 more accurate. After the dielectric layer 20 is etched, the first sacrificial layer 30 is removed.

[0031] It is understandable that the formation of the first pattern 301 is to provide a reference for the laser etching of the dielectric layer 20 in step 103, thereby forming a refined circuit pattern 40. Therefore, selective removal of the first sacrificial layer 30 to form the first pattern 301 can be achieved by removing a portion of the first sacrificial layer 30, which will form the first pattern 301. The first pattern 301 can be a through-hole that penetrates the first sacrificial layer 30, in which case the dielectric layer 20 will be exposed from the first pattern 301. Alternatively, the first pattern 301 can be a blind via that does not penetrate the first sacrificial layer 30, meaning that the first pattern 301 is formed only on the first sacrificial layer 30 and does not penetrate it. When the first pattern 301 is a blind via, by precisely preserving the thickness of the first sacrificial layer 30 at the bottom of the first pattern 301, controlling the thickness of the first sacrificial layer 30, and precisely controlling the laser parameters, it is possible to simultaneously thin the first sacrificial layer 30 in the non-patterned area to the surface of the dielectric layer 20 while forming the circuit pattern 40 at the first pattern 301, thus eliminating the need for the step of removing the first sacrificial layer 30.

[0032] In this application embodiment, the structure of the first sacrificial layer 30 can be varied, and the type of the first pattern 301 will also differ depending on the structure of the first sacrificial layer 30. Optionally, the first sacrificial layer 30 includes a photosensitive material layer 31, which can be photoresist or a dry film. In this case, the first pattern 301 can be a pattern formed by exposure and development. Optionally, the first sacrificial layer 30 includes a photosensitive material layer 31 and a metal barrier layer 32. In this case, the first pattern 301 can be a through-hole or blind hole formed by exposure and development and laser drilling. Of course, the first sacrificial layer 30 can also be a specially made photoresist material without photosensitive components, or other specially made materials that can be selectively removed in a specific solution. The specific solution is one that can remove the first sacrificial layer 30 without damaging the dielectric layer 20 and the conductive material.

[0033] S103. A laser with preset conditions is provided on a first sacrificial layer 30 on which a first pattern 301 is formed, so as to etch a circuit pattern 40 along the thickness direction of the dielectric layer 20 based on the first pattern 301.

[0034] Laser etching is a precision machining technique that uses a high-energy laser beam to remove portions of the material surface, thereby forming predetermined patterns or text. Before using laser etching of the dielectric layer 20 in this embodiment, preliminary preparations are required, mainly consisting of the following core steps: Based on the material type (metal, plastic, ceramic, glass, etc.), thickness, and etching requirements (depth, precision), key parameters such as laser power, frequency, scanning speed, spot diameter, and pulse width are set; the material surface is cleaned to ensure it is free of oil, oxides, or other contaminants to avoid uneven etching or defects.

[0035] The principle of laser etching is that a laser beam is irradiated onto the surface of a material through an optical system (such as a galvanometer or lens). The high energy density causes the material to undergo the following chemical changes: the high photon energy of the deep ultraviolet laser breaks the chemical bonds in the dielectric layer material, thereby achieving etching and forming the desired pattern, and the processing depth can be accurately controlled.

[0036] It is understandable that, since the laser does not affect the first sacrificial layer 30 when it acts on it, or the laser etching rate of the first sacrificial layer 30 is less than or much less than the etching rate of the dielectric layer 20, the area protected by the first sacrificial layer 30 is not affected by the laser, while the area not protected by the first sacrificial layer is rapidly etched by the laser.

[0037] It should be noted that during step S103, depending on the circuit requirements, the laser may act on only a portion of the first sacrificial layer 30, or it may act on the entire first sacrificial layer 30. Based on the dielectric layer 20 exposed by the first pattern on the first sacrificial layer 30, the area of ​​the dielectric layer 20 scanned by the laser will be etched with a circuit pattern 40. It is understood that the circuit pattern 40 can be a blind trench or a blind via, meaning that the circuit pattern 40 does not penetrate the dielectric layer 20 in the thickness direction (i.e., the arrangement direction of the substrate 10 and the dielectric layer 20). It is also understood that the circuit pattern 40 can be a through-hole penetrating the dielectric layer 20, forming a connection with the conductive layer (or the pads of the conductive layer) in the substrate 10, serving as the basis for forming an interlayer connection structure.

[0038] Step S103 uses laser etching technology to form the circuit pattern 40, which can achieve the effect of non-contact processing of the circuit pattern 40, with higher etching efficiency, and no mechanical stress is applied to the dielectric layer 20, which will not affect the processing fineness of the circuit pattern 40, and makes the circuit pattern 40 more refined, and the processing of the circuit pattern 40 is also more automated.

[0039] Furthermore, to ensure the etching quality of the circuit pattern 40, preliminary tests can be conducted before etching based on the material type and thickness of the dielectric layer 20 to determine the optimal laser processing parameters. The laser used to etch the circuit pattern 40 using these parameters is the laser with preset conditions in step S103, which may include a laser with preset energy density, preset number of pulses, or preset processing time. The laser with preset energy density determines how much material can be removed in a single pulse; the laser with preset number of pulses determines the amount of material removed, i.e., the depth of the circuit pattern 40; and the laser with preset processing time determines the depth of the etched circuit pattern 40. By using a laser with preset conditions to etch the circuit pattern 40, the etching of the circuit pattern 40 can be more precise and achieve a higher degree of refinement.

[0040] In this embodiment, the laser etching of the dielectric layer 20 requires extremely high uniformity and precision. Optionally, the laser spot shape applied to the first sacrificial layer 30 with the first pattern 301 under preset conditions can be a flat-topped spot.

[0041] A flat-top laser spot is a laser spot shape in which energy (or power density) is uniformly distributed within the effective area of ​​the spot. When the laser spot shape is flat-topped, the energy within the laser-acting area is made consistent, ensuring that every point of the dielectric layer 20 within the spot's coverage area receives the same laser energy. This achieves "one exposure, uniform etching," resulting in a circuit pattern 40 with consistent depth and a flat bottom surface. Furthermore, because a flat-topped laser spot has the characteristics of "flat top and steep edges," the transition of energy from the uniform area to zero is very rapid, resulting in very sharp and clear processing boundaries (line edges). This allows for minimizing the heat-affected zone during laser etching of the dielectric layer 20, avoiding damage to adjacent areas that do not require processing, improving processing resolution and accuracy, and making the circuit pattern 40 more refined. The energy uniformity of a flat-topped laser spot means that as long as the energy density exceeds the etching threshold of the dielectric layer 20, the entire area will be uniformly removed. This significantly reduces the stringent requirements for the stability of the laser output energy, improving the stability and yield of the production process.

[0042] In this embodiment, the laser type used to etch the dielectric layer 20 to obtain the circuit pattern 40 can include various types. In some embodiments, the laser with preset conditions is a deep ultraviolet laser. Deep ultraviolet lasers have high photon energy, which can directly break the chemical bonds of most organic materials and some inorganic materials. This results in a very small heat-affected zone, less edge carbonization, and high etching precision, which is beneficial for etching a fine circuit pattern 40. Moreover, the laser energy of deep ultraviolet lasers can be efficiently absorbed by the material surface, which is beneficial for quickly etching away part of the dielectric layer 20. In addition, the spot size of deep ultraviolet lasers can be focused very small, which is suitable for etching micron-level fine lines and windows, making the etched circuit pattern 40 even finer.

[0043] Of course, a laser with preset conditions can also output pulsed or continuous laser light. This can increase the etching speed, thereby improving the processing efficiency of the circuit pattern 40.

[0044] S104. Fill the circuit pattern 40 with metal to form the target circuit 50.

[0045] The schematic diagram of the device after step S104 can be referenced. Figure 15 .

[0046] In this embodiment, a first pattern 301 is first formed on the sacrificial layer, and then a circuit pattern 40 is etched on the dielectric layer 20 according to the first pattern 301. This can improve the etching accuracy of the circuit pattern 40, making the target circuit 50 formed by filling the circuit pattern 40 with metal more refined and thinner. This method of etching the circuit pattern 40 does not require highly precise etching tools, which greatly reduces the etching cost. In addition, laser etching of the dielectric layer 20 can more precisely control the shape and size of the etching, making the processing parameters of the circuit pattern 40 more controllable, thereby obtaining a more accurate target circuit 50, effectively improving the production yield of the circuit board and reducing production costs.

[0047] It is understood that the above steps can prepare the first layer of circuitry on the circuit board. If it is necessary to prepare a circuit board with multiple layers of circuitry, the above steps can be repeated to prepare the second layer, third layer, and so on. In the embodiments of this application, when preparing a multilayer circuit board, a dielectric layer 20 is directly provided on the substrate 10, and then a circuit pattern 40 is provided on the dielectric layer 20. Metal is then filled into the circuit pattern 40 to form other layers of circuitry (i.e., the target circuitry 50). There is no need to stack multiple single / double-layer circuit boards, which not only reduces processing steps and improves production efficiency, but also makes the circuitry of each layer of the circuit board more aligned.

[0048] In this application embodiment, there are multiple specific implementations of the above step S102, that is, there are multiple ways to form the first pattern 301. When the structure of the first sacrificial layer 30 is different, the way to form the first pattern 301 is also different.

[0049] When the first sacrificial layer 30 includes a photosensitive material layer 31, reference Figure 2 The method for manufacturing a circuit board provided in this application includes the following steps: S201. Prepare a dielectric layer 20 on the substrate 10.

[0050] refer to Figure 4 The schematic diagram of the device after step S201 is as follows: Figure 4 As shown.

[0051] S202. A photosensitive material layer 31 is formed on the main surface 201 of the dielectric layer 20. The photosensitive material layer 31 is selectively removed by exposure and development to form a first pattern 301, wherein the dielectric layer 20 is exposed from the first pattern 301.

[0052] refer to Figure 5 , Figure 5 This is a schematic diagram of the device after step S202 is executed.

[0053] It should be noted that selectively removing the photosensitive material layer 31 to form the first pattern 301 can make the preparation process of the first pattern 301 simpler, more efficient, and less costly.

[0054] S203, A laser with preset conditions is applied to a photosensitive material layer 31 on which a first pattern 301 is formed, so as to etch a circuit pattern 40 along the thickness direction of the dielectric layer 20 based on the first pattern 301.

[0055] refer to Figure 6 , Figure 6 This is a schematic diagram of the device after step S203 is executed.

[0056] S204. Remove the photosensitive material layer 31 on the main surface 201.

[0057] refer to Figure 7 , Figure 7 This is a schematic diagram of the device after step S204 is executed.

[0058] It should be noted that the processes of exposure, development, etching of photosensitive material layer 31 and removal of photosensitive material layer 31 are sufficient to ensure that the dielectric layer 20 is exposed at the position corresponding to the circuit pattern 40 in the first pattern 301, and no restrictions are imposed here.

[0059] It should be noted that by executing step S204, the photosensitive material layer 31 on the main surface 201 can be removed, so that step S206, when filling metal in the circuit pattern 40, will not be affected by the photosensitive material layer 31 on the main surface 201.

[0060] Of course, in order to reduce the number of implementation steps, step S206 can be executed directly after step S203 is completed.

[0061] S205. Clean the circuit pattern 40 and the main surface 201.

[0062] It should be noted that after step S205 is performed, the circuit pattern 40 and the main surface 201 can be kept clean so that subsequent steps can be performed smoothly. That is, it ensures that the metal filling the circuit pattern 40 is not easily detached from the circuit pattern 40.

[0063] S206. Fill the circuit pattern 40 with metal to form the target circuit 50.

[0064] The schematic diagram of the device after step S206 can be referenced. Figure 15 .

[0065] When the first sacrificial layer 30 includes a photosensitive material layer 31 and a metal blocking layer 32, reference Figure 3 The method for manufacturing a circuit board provided in this application includes the following steps: S301. Prepare a dielectric layer 20 on the substrate 10.

[0066] refer to Figure 4 The schematic diagram of the device after step S301 is as follows: Figure 4 As shown.

[0067] S302. A metal barrier layer 32 is formed on the main surface 201 of the dielectric layer 20, and a photosensitive material layer 31 is formed on the metal barrier layer 32.

[0068] refer to Figure 8 , Figure 8 This is a schematic diagram of the device after step S302 is executed.

[0069] It should be noted that the metal barrier layer 32 formed on the main surface 201 of the dielectric layer 20 can be implemented by physical vapor deposition (PVD), mainly including magnetron sputtering and electron beam evaporation, or by chemical vapor deposition (CVD) or electroless plating. Of course, it can also be formed by attaching an ultrathin copper foil (2um-3um). The attachment of the ultrathin copper foil is to first attach a release layer to the carrier copper foil, then attach the ultrathin copper foil to the release layer to form a carrier, attach the entire carrier to the dielectric layer 20, and then peel off the carrier copper foil and the release layer to allow the ultrathin copper foil to be attached to the dielectric layer 20.

[0070] S303. The photosensitive material layer 31 is selectively removed by exposure and development to form a second pattern 310, wherein the metal barrier layer 32 is exposed from the second pattern 310.

[0071] refer to Figure 9 , Figure 9 This is a schematic diagram of the device after step S303 is executed.

[0072] S304. Based on the second pattern 310, the metal barrier layer 32 is selectively removed by chemical etching to form the first pattern 301, wherein the dielectric layer 20 can be exposed from the first pattern 301.

[0073] refer to Figure 10 , Figure 10 This is a schematic diagram of the device after step S304 is executed.

[0074] S305. A laser with preset conditions is provided on a metal barrier layer 32 and a photosensitive material layer 31 on which a first pattern 301 is formed, so as to etch a circuit pattern 40 along the thickness direction of the dielectric layer 20 based on the first pattern 301.

[0075] refer to Figure 11 , Figure 11 This is a schematic diagram of the device after step S305 is executed.

[0076] S306. Remove the photosensitive material layer 31 and the metal barrier layer 32 from the main surface 201.

[0077] refer to Figure 7 The schematic diagram of the device after step S306 is shown below. Figure 7 As shown.

[0078] It should be noted that by executing step S306, the photosensitive material layer 31 and the metal barrier layer 32 on the main surface 201 can be removed, so that when filling the circuit pattern 40 with metal in step S308, it will not be affected by the photosensitive material layer 31 and the metal barrier layer 32 on the main surface 201.

[0079] Of course, in order to reduce the number of implementation steps, step S308 can be executed directly after step S305 is completed.

[0080] S307. Clean the circuit pattern 40 and the main surface 201.

[0081] S308. Fill the circuit pattern 40 with metal to form the target circuit 50.

[0082] The schematic diagram of the device after step S308 can be referenced. Figure 15 .

[0083] Further reference Figure 12 Step S104 above includes the following steps: S1041. A metal seed layer 51 is prepared on the dielectric layer 20, and the metal seed layer 51 covers the main surface 201 and the bottom and side surfaces of the circuit pattern 40.

[0084] refer to Figure 13 , Figure 13 This is a schematic diagram of the device after step S1041 is executed.

[0085] In step S1041, the metal seed layer 51 can be set by chemical copper plating, sputtering, or other methods. Its main purpose is to provide a conductive layer to facilitate the formation of the metal conductive layer 52 by electroplating in subsequent step S1042. The metal seed layer 51 on the side of the circuit pattern 40 is electrically connected to the metal seed layer 51 on the bottom surface of the circuit pattern 40 and the metal seed layer 51 on the main surface 201, thus achieving electrical connection between the metal seed layer 51 on the bottom surface of the circuit pattern 40 and the metal seed layer 51 on the main surface 201. By energizing the metal seed layer 51 on the main surface 201, the metal seed layer 51 on the bottom surface of the circuit pattern 40 can be energized. Compared to directly energizing the metal seed layer 51 on the bottom surface of the circuit pattern 40, this operation in this embodiment is more convenient.

[0086] In actual production, the metal seed layer 51 can completely cover the main surface 201, the bottom surface of the circuit pattern 40, and the sides of the circuit pattern 40, or it can partially cover the main surface 201, the bottom surface of the circuit pattern 40, and the sides of the circuit pattern 40, as long as it can ensure that a suitable metal conductive layer 52 is electroplated within the circuit pattern 40.

[0087] S1042. Prepare a metal conductive layer 52 on each metal seed layer 51.

[0088] refer to Figure 14 , Figure 14 This is a schematic diagram of the device after step S1042 is executed.

[0089] In step S1042, each metal seed layer 51 refers to all the metal seed layers 51 formed on the dielectric layer 20. The thickness of the electroplated metal conductive layer 52 is greater than the thickness of the metal seed layers 51. Specifically, the thickness of the metal conductive layer 52 within the circuit pattern 40 is greater than the thickness of the metal seed layers 51 within the circuit pattern 40. For example, the thickness of the metal seed layer 51 can range from 0.2 micrometers to 1 micrometer, and the thickness of the metal conductive layer 52 can range from 10 micrometers to 20 micrometers.

[0090] In actual production, the thickness of each area of ​​the circuit pattern 40 is the same, but the metal growth rate of each area will be different during the electroplating process. In order to ensure that the thickness of the conductive metal layer 52 filled in each area of ​​the circuit pattern 40 meets the requirements, the metal in each area of ​​the circuit pattern 40 must be completely filled during electroplating.

[0091] In addition, the materials of the metal seed layer 51 and the metal conductive layer 52 can be the same or different. The materials of the two can be selected from copper, silver, aluminum and other materials according to actual needs.

[0092] S1043. Remove the metal seed layer 51 and the metal conductive layer 52 from the main surface 201.

[0093] refer to Figure 15 , Figure 15 This is a schematic diagram of the device after step S1043 is executed.

[0094] In step S1043, the metal seed layer 51 and the metal conductive layer 52 on the main surface 201 can be removed by chemical mechanical polishing or other operations, so that only the metal seed layer 51 and the metal conductive layer 52 in the circuit pattern 40 are retained. The metal seed layer 51 and the metal conductive layer 52 in the circuit pattern 40 constitute the target circuit 50.

[0095] In the above embodiments of this application, multiple circuit patterns 40 can be processed simultaneously by laser etching the dielectric layer 20. Each circuit pattern 40 has the same depth. If it is necessary to process circuit patterns 40 of different depths on the same dielectric layer 20, the following manufacturing method can be used.

[0096] refer to Figure 16 The method for manufacturing a circuit board provided in this application includes the following steps: S401. Prepare a dielectric layer 20 on the substrate 10.

[0097] refer to Figure 4 The schematic diagram of the device after step S401 is as follows: Figure 4 As shown.

[0098] S402. A first sacrificial layer 30 is prepared on the main surface 201 of the dielectric layer 20, and the first sacrificial layer 30 is selectively removed to form a first pattern 301.

[0099] S403, A laser with preset conditions is provided on a first sacrificial layer 30 on which a first pattern 301 is formed, so as to etch a circuit pattern 40 along the thickness direction of the dielectric layer 20 based on the first pattern 301.

[0100] S404, Remove the first sacrificial layer 30 on the main surface 201.

[0101] It should be noted that after etching the circuit pattern 40 on the dielectric layer 20, the first sacrificial layer 30 on the main surface 201 can be removed. Since the first pattern 301 is formed on the first sacrificial layer 30, the first sacrificial layer 30 needs to be removed in order to re-prepare the second sacrificial layer on the main surface 201, thereby forming the third pattern on the second sacrificial layer. This facilitates the laser etching of part of the circuit pattern 40 according to the third pattern, resulting in different depths of the circuit pattern 40.

[0102] Furthermore, after performing step S404, the main surface 201 can be cleaned so that step S405 can successfully prepare the second sacrificial layer on the main surface 201.

[0103] S405. Prepare a second sacrificial layer on the main surface 201, and process a third pattern on the second sacrificial layer.

[0104] Optionally, the material of the second sacrificial layer can be the same as that of the first sacrificial layer 30, and the structure of the second sacrificial layer can also be the same as that of the first sacrificial layer 30. This application does not impose specific limitations on the embodiments.

[0105] S406. According to the third pattern, a laser with preset conditions is provided on the second sacrificial layer on which the third pattern is formed, so as to etch at least a portion of the circuit pattern 40 based on the third pattern along the thickness direction of the dielectric layer 20.

[0106] It should be noted that, based on the preparation of multiple circuit patterns 40 of the same depth, in order to achieve different depths of different circuit patterns 40, some circuit patterns 40 can be further etched so that the depth of this part of the circuit pattern 40 is greater than the depth of other circuit patterns 40. Through step S405, a third pattern can be formed on the second sacrificial layer. The third pattern can be a via. The circuit pattern 40 that needs to be further etched is exposed from the third pattern. In this way, the laser can etch the dielectric layer 20 based on the third pattern, thereby further etching the circuit pattern 40 exposed from the third pattern, so that the depth of this part of the circuit pattern 40 becomes deeper.

[0107] S407, Remove the second sacrificial layer on the main surface 201.

[0108] S408. Clean the circuit pattern 40 and the main surface 201.

[0109] S409. Fill the circuit pattern 40 with metal to form the target circuit 50.

[0110] A schematic diagram of the device after step S409 is shown below. Figure 17 .

[0111] refer to Figure 15 and Figure 17 This application also provides a circuit board, which is manufactured using the manufacturing method of any of the above embodiments, including a substrate 10, a dielectric layer 20, and a target line 50. The substrate 10 is provided with conductive lines 11; the dielectric layer 20 is disposed on the substrate 10 and covers the conductive lines 11. The main surface 201 of the dielectric layer 20 is provided with a line pattern 40, the main surface 201 is the surface facing away from the substrate 10, and the line pattern 40 is a blind slot or a blind via; the target line 50 is filled in the line pattern 40.

[0112] Among them, the circuit pattern 40 is a blind slot or blind via, which means that the circuit pattern 40 does not penetrate the dielectric layer 20 in the thickness direction of the dielectric layer 20 (that is, in the arrangement direction of the substrate 10 and the dielectric layer 20).

[0113] In this embodiment, the dielectric layer 20 is an insulating layer, and the conductive line 11 and the target line 50 are two circuit layers of the circuit board. The dielectric layer 20 can separate the conductive line 11 and the target line 50 to prevent direct electrical contact. In addition, since the target line 50 is filled within the circuit pattern 40, the dielectric layer 20 can protect the target line 50 and effectively prevent it from being damaged.

[0114] Optionally, the dielectric layer 20 may completely cover the conductive line 11, thereby preventing the conductive line 11 from making electrical contact with a foreign object on the side closest to the dielectric layer 20.

[0115] Of course, the dielectric layer 20 can also partially cover the conductive line 11. This arrangement can include one or a combination of the following two methods: First, the dielectric layer 20 has connecting holes. After the circuit pattern 40 is fabricated, connecting holes penetrating the dielectric layer 20 can be formed within the circuit pattern 40, with the connecting holes facing the conductive line 11. In this case, the circuit board also includes connecting wires, which fill the connecting holes, and both ends of the connecting wires are electrically connected to the conductive line 11 and the target line 50, respectively. This shortens the path of electrical connection between the conductive line 11 and the target line 50, improving electrical connection performance.

[0116] In the second method, the substrate 10 has a first region and a second region. A portion of the conductive lines 11 is located in the first region, and another portion is located in the second region. The dielectric layer 20 is disposed in the first region and covers the portion of the conductive lines 11 located in the first region. The portion of the conductive lines 11 in the second region can be used to connect electronic components, etc. This reduces the amount of material used to manufacture the dielectric layer 20, and the portion of the conductive lines 11 in the second region is exposed, making it easier to connect electronic components.

[0117] This application also provides a laser processing device for fabricating circuit boards using the manufacturing method of any of the above embodiments. The device includes a laser emitting device, a shaping component, and a control component. The laser emitting device is configured to emit deep ultraviolet laser light. The shaping component is configured to shape the deep ultraviolet laser light into a flat-top spot. The control component is configured to control the energy density, number of pulses, or processing time based on processing requirements.

[0118] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: A dielectric layer (20) is prepared on a substrate (10); A first sacrificial layer (30) is prepared on the main surface (201) of the dielectric layer (20), and the first sacrificial layer (30) is selectively removed to form a first pattern (301). A laser with preset conditions is applied to the first sacrificial layer (30) on which the first pattern (301) is formed, so as to etch a circuit pattern (40) along the thickness direction of the dielectric layer (20) based on the first pattern (301). Metal is filled into the circuit pattern (40) to form the target circuit (50).

2. The method for manufacturing a circuit board according to claim 1, characterized in that, The first sacrificial layer (30) includes a photosensitive material layer (31); The process of preparing a first sacrificial layer (30) on the main surface (201) of the dielectric layer (20) and selectively removing the first sacrificial layer (30) to form a first pattern (301) includes: A photosensitive material layer (31) is formed on the main surface (201) of the medium layer (20), and the photosensitive material layer (31) is selectively removed by exposure and development to form a first pattern (301), wherein the medium layer (20) is exposed from the first pattern (301).

3. The method for manufacturing a circuit board according to claim 1, characterized in that, The first sacrificial layer (30) includes a photosensitive material layer (31) and a metal blocking layer (32). The process of preparing a first sacrificial layer (30) on the main surface (201) of the dielectric layer (20) and selectively removing the first sacrificial layer (30) to form a first pattern (301) includes: The metal barrier layer (32) is formed on the main surface (201) of the dielectric layer (20), and the photosensitive material layer (31) is formed on the metal barrier layer (32). The photosensitive material layer (31) is selectively removed by exposure and development to form a second pattern (310), wherein the metal barrier layer (32) is exposed from the second pattern (310); Based on the second pattern (310), the metal barrier layer (32) is selectively removed by chemical etching to form a first pattern (301), wherein the dielectric layer (20) is exposed from the first pattern (301).

4. The method for manufacturing a circuit board according to claim 1, characterized in that, Lasers with preset conditions include lasers with preset energy density, preset number of pulses, or preset processing time.

5. The method for manufacturing a circuit board according to claim 1, characterized in that, The laser beam with preset conditions acts on the first sacrificial layer (30) on which the first pattern (301) is formed, and the light spot shape is a flat-topped light spot.

6. The method for manufacturing a circuit board according to claim 1, characterized in that, The laser with the preset conditions is a deep ultraviolet laser; And / or, the laser output with preset conditions is a pulsed laser or a continuous laser.

7. The method for manufacturing a circuit board according to any one of claims 1-6, characterized in that, The metal filling within the circuit pattern (40) includes: A metal seed layer (51) is prepared on the dielectric layer (20), the metal seed layer (51) covering the main surface (201) and the bottom and side surfaces of the circuit pattern (40), wherein the metal seed layer (51) on the side surface of the circuit pattern (40) is electrically connected to the metal seed layer (51) on the bottom surface of the circuit pattern (40) and the metal seed layer (51) on the main surface (201), respectively. A metal conductive layer (52) is prepared on each of the metal seed layers (51); Remove the metal seed layer (51) and the metal conductive layer (52) from the main surface (201).

8. The method for manufacturing a circuit board according to any one of claims 1-6, characterized in that, After the laser with preset conditions is used to etch a circuit pattern (40) along the thickness direction of the dielectric layer (20) based on the first pattern (301) in the first sacrificial layer (30) having the first pattern (301), and before the metal is filled into the circuit pattern (40), the method further includes: Remove the first sacrificial layer (30) on the main surface (201); The circuit pattern (40) and the main surface (201) are cleaned.

9. The method for manufacturing a circuit board according to claim 8, characterized in that, After cleaning the circuit pattern (40) and the main surface (201), the process further includes: A second sacrificial layer is prepared on the main surface (201), and a third pattern is processed on the second sacrificial layer; According to the third pattern, a laser with preset conditions is provided on the second sacrificial layer on which the third pattern is formed, so as to etch at least a portion of the circuit pattern (40) along the thickness direction of the dielectric layer (20) based on the third pattern; Remove the second sacrificial layer on the main surface (201); The circuit pattern (40) and the main surface (201) are cleaned.

10. A circuit board, characterized in that, The product is manufactured using the manufacturing method described in any one of claims 1-9, comprising: A substrate (10) having conductive lines (11) on it. A dielectric layer (20) is disposed on the substrate (10) and covers the conductive lines (11). A circuit pattern (40) is provided on the main surface (201) of the dielectric layer (20). The main surface (201) is the surface facing away from the substrate (10). The target line (50) is filled within the line pattern (40).

11. A laser processing device, characterized in that, The circuit board is fabricated using the fabrication method described in any one of claims 1-9, comprising: A laser emitting device configured to emit deep ultraviolet laser light; A shaping component, configured to shape the deep ultraviolet laser into a flat-topped spot; A control component, which is configured to control the energy density, number of pulses, or processing time based on processing requirements.

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