Signal transmitter circuit including a main full unit interval (UI) transmission driver and

Abstract

An apparatus and method of generating an output transmit signal, comprising generating a first portion of an output transmit signal (TXo) based on an input transmit signal (TXi), where the first portion (TXo1) of the output transmit signal comprises a first set of pulses each spanning a unit interval (UI); generating a second portion (TXo2) of the output transmit signal based on the input transmit signal, wherein the second portion of the output signal comprises a second set of pulses each spanning an intermediate sub-interval of the UI; and combining the first portion with the second portion to generate an output transmit signal.

Description

Cross Reference to Related Applications

[0001] This patent application claims priority to pending U.S. Non-Provisional Application No. 18 / 478,011, filed September 29, 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated by reference herein as if fully set forth below and for all applicable purposes. TECHNICAL FIELD

[0002] Aspects of the present disclosure generally relate to data communication links, and in particular to a signal transmitter circuit including a main (full unit interval (UI)) transmit driver and an intermediate sub-UI boost driver. BACKGROUND

[0003] Data communication links, such as serializer / deserializer (SERDES) links, are used to communicate data / clock signals between integrated circuits (ICs) and other components. When the signal rate or frequency of the data / clock signals is sufficiently high (e.g., > one (1) gigahertz (GHz)), signal reflections can occur along the transmission of the data / clock signals between ICs. To reduce such signal reflections, a termination resistor is employed at both the signal transmitter circuit and the signal receiver circuit, where the resistance of each of the termination resistors is set to the characteristic impedance (e.g., 50 ohms (Q)) of the transmission line by the signal propagation. However, the termination resistors can cause the data communication link to consume a higher power. SUMMARY

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] One aspect of the present disclosure relates to an apparatus. The apparatus includes a first transmit driver including an input coupled to a signal input, a first delay circuit including an input coupled to the signal input, a second delay circuit including an input coupled to the signal input or an output of the first delay circuit, an inverter circuit including an input coupled to an output of the second delay circuit, a logic gate including inputs coupled to an output of the first delay circuit and an output of the inverter circuit, respectively, and a second transmit driver including an input coupled to an output of the logic gate and an output coupled to an output of the first transmit driver.

[0006] Another aspect of the disclosure relates to an apparatus. The apparatus includes a full unit interval (UI) transmit driver including an input coupled to a signal input, and an intermediate sub-UI boost driver including an input coupled to the signal input and an output coupled to an output of the full UI transmit driver.

[0007] Another aspect of the disclosure relates to an apparatus. The apparatus includes a full UI transmit driver configured to generate a first portion of an output transmit signal based on an input transmit signal, where the first portion of the output transmit signal includes a first set of pulses each spanning a unit interval (UI); and an intermediate sub-UI boost driver configured to generate a second portion of the output transmit signal based on the input transmit signal, where the second portion of the output transmit signal includes a second set of pulses each spanning a middle sub-interval of the UI.

[0008] Another aspect of the disclosure relates to a method. The method includes generating a first portion of an output transmit signal based on an input transmit signal, where the first portion of the output transmit signal includes a first set of pulses each spanning a unit interval (UI); generating a second portion of the output transmit signal based on the input transmit signal, where the second portion of the output transmit signal includes a second set of pulses each spanning a middle sub-interval of the UI; and combining the first portion with the second portion to generate the output transmit signal.

[0009] To the accomplishment of the foregoing and related aspects, one or more specific embodiments implement the features recited in the claims using one or more of the accompanying drawings. The following detailed description, therefore, is best deemed in conjunction with the drawings, of which: BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A block diagram of an example data / clock communication apparatus is illustrated in accordance with an aspect of the disclosure.

[0011] Figure 2 A block diagram / schematic of an example signal communication apparatus is illustrated in accordance with another aspect of the disclosure.

[0012] Figure 3 Another block diagram / schematic of another example signal communication apparatus is illustrated in accordance with another aspect of the disclosure.

[0013] Figure 4A block diagram / schematic diagram of another example signal communication device is illustrated in accordance with another aspect of the present disclosure.

[0014] Figure 5 A block diagram of an example signal transmitter circuit is illustrated in accordance with another aspect of the present disclosure.

[0015] Figures 6A-6B Block diagrams of several example variations of a signal transmitter circuit are illustrated in accordance with another aspect of the present disclosure.

[0016] Figure 7 A block diagram of another example signal transmitter circuit is illustrated in accordance with another aspect of the present disclosure.

[0017] Figure 8 A block diagram of another example signal transmitter circuit is illustrated in accordance with another aspect of the present disclosure.

[0018] Figure 9 A block diagram of another example signal transmitter circuit is illustrated in accordance with another aspect of the present disclosure.

[0019] Figure 10 A flow diagram of an example method of generating an output transmit signal is illustrated in accordance with another aspect of the present disclosure. DETAILED DESCRIPTION

[0020] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. As used herein, the term "coupled" can mean electrically coupled.

[0021] To reduce signal reflections, a terminating resistor at the transmitter circuit and receiver circuit is employed, which can result in a higher power consumption for the data communication link. In the case where the receiver circuit does not include a receiver terminating resistor, it can have a power saving advantage, but signal reflections can occur at the receiver circuit. Such signal reflections can impair the signal integrity of the received signal at the receiver circuit. For example, the received signal includes a high side dip and a low side bump that are substantially centered in a unit interval (UI) of the received signal. The high side dip and the low side bump that are co-located in the UI tend to reduce the height of an eye diagram corresponding to the received signal, which makes it more difficult for the receiver circuit to detect the transmitted data / clock.

[0022] A signal transmitter circuit is presented that includes a main (full UI) transmit driver and an intermediate sub-UI transmit boost driver. The intermediate sub-UI transmit boost driver is configured to amplify and / or voltage level shift a middle sub-interval of a UI of an input transmit signal to generate a second boosted portion of the transmit signal. The boosted portion of the transmit signal substantially coincides with a high-side dip that would otherwise be present in a receive signal, the high-side dip being reduced or substantially eliminated from the receive signal. This opens up or increases the height of an eye diagram, which improves the detectability of data / clock in the receive signal without increasing the supply voltage of the main transmit driver.

[0023] Figure 1 A block diagram of an example data / clock communication device 100 is illustrated in accordance with an aspect of the present disclosure. The data / clock communication device 100 can facilitate serialiser-deserialiser (SERDES) type data / clock communication, as in a low power double data rate (LPDDR) memory (e.g., dynamic random access memory (DRAM)) interface or other type of input / output (I / O) data / clock interface.

[0024] In particular, the data / clock communication device 100 includes a first integrated circuit (IC) 110 and a second IC 130, both of which can be securely mounted on a printed circuit board (PCB) 120. The first IC 110 can include a set of one or more signal transmitter (Tx) circuits 112-1 to 112-M. To enable bidirectional data / clock communication, the first IC 110 can also include a set of one or more signal receiver (Rx) circuits 114-1 to 114-N. Although the data / clock communication device 100 is described as bidirectional, it should be appreciated that the data / clock communication device 100 can be configured for unidirectional data communication. In such a case, the first IC 110 can not include a set of one or more signal receiver circuits 114-1 to 114-N. Further, it should be appreciated that the signal transmitter circuits 112-1 to 112-M can share the same transmit line as the signal receiver circuits 114-1 to 114-N in a time division multiplexed (TDM) manner (e.g., where N = M).

[0025] The set of one or more signal transmitter circuits 112-1 to 112-M is configured to receive a set of one or more input transmit data / clock signals TX I11 to TX I1M and generate a set of one or more output transmit data / clock signals TX I11 to TX I1M based on the set of one or more input transmit data / clock signals TX O11 to TXO1M A set of one or more signal transmitter circuits 112-1 to 112-M is coupled to a first set of one or more transmit lines (e.g., metal traces) 122-1 to 122-M on PCB 120 for transmitting one or more output transmit data / clock signals TX, respectively. O11 To TX O1M The collection is sent to the second IC 130.

[0026] A set of one or more signal receiver circuits 114-1 to 114-N is coupled to a second set of one or more transmit lines (e.g., metal traces) 124-1 to 124-N on PCB 120 to receive one or more input receive data / clock signals RX from a second IC 130, respectively. I21 To RX I2N The set of signals (e.g., one signal may be a clock signal and the remaining signals may be data signals). A set of one or more signal receiver circuits 114-1 to 114-N is configured to receive data / clock signals RX respectively based on (e.g., by processing) one or more inputs. I21 To RX I2N A set of signals is used to generate one or more output receive data / clock signals RX. O21 To RX O2N A set of.

[0027] The second IC 130 may include a set of one or more signal receiver (Rx) circuits 132-1 to 132-M. To enable bidirectional data communication, as discussed, the second IC 130 may also include a set of one or more signal transmitter (Tx) circuits 134-1 to 134-N. Furthermore, as discussed, although the data / clock communication device 100 is described as bidirectional, it should be understood that the data / clock communication device 100 can be configured for unidirectional data communication. In such a case, the second IC 130 may not include a set of one or more signal transmitter circuits 134-1 to 134-N.

[0028] A set of one or more signal receiver circuits 132-1 to 132-M is coupled to a first set of one or more data transmission lines 122-1 to 122-M to transmit data / clock signals TX based on one or more outputs, respectively. O11 To TX O1M The set of inputs is used to receive one or more input data / clock signals RX from the first IC 110. I11 To RX I1M A set of one or more signal receiver circuits 132-1 to 132-M are configured to receive data / clock signals RX based on (e.g., by processing) one or more input data / clock signals respectively.I11 To RX I1M A set of signals is used to generate one or more output receive data / clock signals RX. O11 To RX O1M A set of.

[0029] A set of one or more signal transmitter circuits 134-1 to 134-N is configured to receive one or more input transmit data / clock signals TX I21 To TX I2N The set, and transmits data signals TX based on one or more inputs respectively. I21 To TX I2N The set generates one or more output data / clock signals TX O21 To TX O2N A set of one or more signal transmitter circuits 134-1 to 134-N is coupled to a second set of one or more transmit lines 124-1 to 124-N for transmitting one or more output transmit data signals TX, respectively. I21 To TX I2N The collection is sent to the first IC 110. One or more inputs receive data / clock signals RX. I21 To RX I2N The sets of data signals TX are transmitted based on one or more outputs respectively. I21 To TX I2N A set of.

[0030] Figure 2 A block diagram / schematic representation of an example signal communication device 200 according to another aspect of this disclosure is illustrated. The signal communication device 200 may be an example implementation of any of the M+N data / clock channels (e.g., transmitter circuitry-transmit line-receiver circuitry) of the data / clock communication device 100. The signal communication device 200 may also be an example of "terminating" a signal communication link, as further discussed herein.

[0031] Specifically, the signal communication device 200 includes a signal transmitter circuit 210, a signal receiver circuit 230, and a transmission line 220 coupling the signal transmitter circuit 210 to the signal receiver circuit 230. The signal transmitter circuit 210 further includes a transmit (Tx) driver 212 and a transmitter terminating resistor R. TX and transmitter shunt capacitor C TX A transmit driver 212, which can be coupled to and receives power from a high-voltage rail Vdd and a low-voltage rail Vss (e.g., ground), is configured to receive an input transmit signal TX. I And based on (e.g., by amplification and / or voltage level shift) the input signal TX. I To generate the output transmission signal TXO .

[0032] Transmitter terminating resistor R TX Coupled between the output of the transmitter driver 212 and the transmitter line 220, and the transmitter shunt capacitor C TX Coupled between the first end of the transmitting line 220 and ground. Due to the transmitted signal TX... O It can have a relatively high frequency or data / clock rate (e.g., > -1 GHz), so the transmitted signal TX O Signal reflection may occur due to impedance mismatch. Therefore, to prevent or reduce signal reflection at the signal transmitter circuit 210, the transmitter terminating resistor R... TX The characteristic impedance Z that can be used with transmitting line 220 O (For example, 50 ohms (Ω)) is achieved with essentially the same resistance.

[0033] The signal receiver circuit 230 may include a load, which is represented as a load capacitor C coupled between a second terminal of the transmitting line 220 and a low voltage rail Vss (e.g., ground). L Load capacitor C L Configured to receive input receive signal RX via transmit line 220 I (For example, based on the output transmitted signal TX) O The signal receiver circuit 230 also includes a receiver terminating resistor R coupled between the second terminal of the transmitting line 220 and ground. RX Similarly, to prevent or reduce signal reflection at the signal receiver circuit 230, the receiver terminating resistor R... RX The characteristic impedance Z that can be used with transmitting line 220 O (For example, 50Ω) It can be achieved with essentially the same resistance.

[0034] When the signal communication device 200 is "terminated" (e.g., by including terminating resistors R at the transmitter circuit 210 and the receiver circuit 230, respectively). TX and R RX ), receive signal RX I Signal integrity relative to the transmitted signal TX O The fundamental structure remains unchanged (e.g., both are essentially square waves, as indicated by the corresponding eye diagram). A disadvantage of the "termination" signal communication device 200 is that it can consume a significant amount of direct current (DC) power via the transmit driver 212 and the transmitter termination resistor R. TX Transmitter line 220 and receiver terminating resistor R RXThe current flows from the high supply voltage rail Vdd to the low supply voltage rail Vss (e.g., ground) in the form of DC current. Additionally, the received signal RX is compared to the voltage swing of the transmitted signal (e.g., Vdd to zero (0) volts (V)). I The voltage swing can be essentially half (e.g., Vdd / 2 to 0V).

[0035] Figure 3 A block diagram / schematic representation of another example signal communication device 300 according to another aspect of this disclosure is illustrated. Signal communication device 300 is similar to the previously discussed signal communication device 200 and includes many of the same / similar elements, as indicated by the same labels and reference numerals, but the highest significant digit in signal communication device 300 is “3”, while the highest significant digit in signal communication device 200 is “2”. Similarly, signal communication device 300 may be an example embodiment of any of the data / clock channels of data / clock communication device 100.

[0036] In contrast, the signal communication device 300 can be an example of an "unterminated" signal communication link because the signal receiver circuit 330 does not include a receiver terminating resistor R. RX Therefore, via the transmit driver 312 and the transmitter termination resistor R TX In the transmitting line 320, there is typically no DC current path between the transmitter supply voltage rail Vdd and the receiver low supply voltage rail Vss (e.g., ground). Therefore, the signal communication device 300 can have the advantage of power saving because it does not consume DC power due to the absence of DC current flowing between the transmitter circuit 310 and the receiver circuit 330.

[0037] However, since the receiver circuit 330 does not include a receiver terminating resistor R RX Therefore, signal reflection may occur at receiver circuit 330. Such signal reflection may impair the received signal R at receiver circuit 330. XI Signal integrity. For example, as corresponding to the received signal R XI The eye diagram depicts the received signal R. XI Including basically located in the received signal R XI The unit interval (UI) has a high-side drop and a low-side bulge in the middle. The high-side drop and low-side bulge of the UI tend to reduce the eye diagram height (EH1), making it more difficult for the receiver circuit 330 to detect transmitted data / clock. In some cases, a solution to increase the eye diagram height EH1 is to increase the transmitter supply voltage Vdd. However, this solution has the disadvantage of increasing the power consumption of the signal communication device 300, which is contrary to the expectation of reducing the transmitter supply voltage Vdd for power saving purposes.

[0038] Figure 4 A block diagram / schematic representation of another example signal communication device 400 according to another aspect of this disclosure is illustrated. As discussed in further detail herein, the signal communication device 400 includes signal transmitter circuitry configured to generate an output transmission signal TX. O The output transmitted signal includes an intermediate UI voltage boost to reduce or substantially eliminate the received signal RX at the unterminated signal receiver circuitry. I The high side of the drop. Similarly, the signal communication device 400 can be an example implementation of any of the data / clock channels of the data / clock communication device 100.

[0039] Specifically, the signal communication device 400 includes a signal transmitter circuit 410, a signal receiver circuit 430, and a transmission line 420 coupling the signal transmitter circuit 410 to the signal receiver circuit 430. The signal transmitter circuit 410 further includes a main (full UI) transmitter driver 412, an intermediate sub-UI transmitter boost driver 414, and a transmitter termination resistor R. TX and transmitter shunt capacitor C TX A master (full UI) transmit driver 412, which can be coupled to and receives power from the high voltage rail Vdd1 and the low voltage rail Vss (e.g., ground), is configured to receive the input transmit signal TX. I And based on the input signal TX I To generate the output transmission signal TX O Part 1 TX O1 In other words, the input transmission signal TX I This can be data or a clock signal with a specific unit interval (UI) (e.g., half a cycle of a clock signal). Therefore, the main transmit driver 412 is configured to amplify and / or level-shift the input transmit signal TX. I To generate the output transmission signal TX O1 Part 1 TX O1 This makes it have the same characteristics as the input transmitted signal TX. I The UI is essentially the same, as indicated by the solid lines in the corresponding eye diagram.

[0040] The intermediate sub-UI, which can be coupled to the high-voltage rail Vdd2 and the low-voltage rail Vss (e.g., ground) and receives power from them, transmits boost driver 414, which is configured to receive input transmit signal TX. I And based on the input signal TX I To generate the second part TX of the output transmission signal O2 The intermediate sub-UI transmit boost driver 414 is configured to amplify and / or level-shift the voltage input transmit signal TX. IThe intermediate sub-interval of the UI is used to generate the second part of the output transmission signal TX. O2 As indicated by the dashed line in the corresponding eye diagram. The intermediate sub-space of the UI can be connected to the received signal RX that would originally be located at the signal receiver circuit 430. I The high-side descent that occurred in the middle was basically consistent.

[0041] In this example, the intermediate boost cell spacing of the UI can be 0.25. It starts at the UI and can be done at 0.75. The UI ends at the input level. However, it should be understood that the intermediate boost interval of the UI can begin and end at different positive percentages of the UI and does not need to be symmetrical with respect to the middle of the UI. Although identified differently, the high supply voltage rail Vdd1 of the main transmit driver 412 can be the same as or different from the high supply voltage rail Vdd2 of the intermediate sub-UI transmit boost driver 414. If different, the supply voltage Vdd2 for the intermediate sub-UI transmit boost driver 414 can be set higher than the supply voltage Vdd1 of the main transmit driver 412, as indicated in the corresponding eye diagram. The outputs of the main transmit driver 412 and the intermediate sub-UI boost driver 414 are coupled together, such that the first signal portion TX O1 Second signal section TX O2 Combine or sum to form the output transmitted signal TX O Therefore, the output signal TX is sent. O It includes a set of positive pulses, which is a combination of a first set of full UI positive pulses generated by the main transmitter driver 412 and a second set of overlapping intermediate sub-UI positive pulses generated by the intermediate sub-UI transmitter boost driver 414.

[0042] The remaining circuitry of the signal communication device 400 may be substantially the same as or similar to that of the previously discussed signal communication device 300. That is, the transmitter terminating resistor R... TX It can be coupled between the output of the main transmitter driver 412 / intermediate sub-UI boost driver 414 and the first terminal of the transmitter line 420. Transmitter capacitor C TX It can be coupled between the first terminal of the transmit line 420 and the low-voltage rail Vss (e.g., ground). Transmitter terminating resistor R TX The characteristic impedance Z of the transmitting line 420 can be used. O It is achieved using essentially the same resistance.

[0043] The signal receiver circuit 430 includes a load, which is represented as a load capacitor C coupled between the second terminal of the transmitting line 420 and the low voltage rail Vss (e.g., ground). LSince the signal receiver circuit 430 is unterminated, it is based on the transmitted signal TX received from the transmitter circuit 410 via the transmitting line 420. O Received signal RX I It presents some signal integrity issues, as previously discussed. However, due to the transmission of signal TX... O TX boost section O2 With the original signal RX that would exist in the received signal I The high-side descents in the signals essentially overlap, therefore the high-side descents from the received signal RX... I This reduces or essentially eliminates the eye, as depicted in the corresponding eye diagram. This opens or increases the height of the eye diagram EH2 (e.g., EH2 > EH1) compared to EH1 in the signal communication device 300, which improves the received signal RX. I The data / clock is detectable without increasing the supply voltage Vdd1 of the main transmit driver 412 (or even reducing it for power saving purposes).

[0044] Figure 5 A block diagram illustrating an example signal transmitter circuit 500 according to another aspect of this disclosure is shown. The signal transmitter circuit 500 may be a more detailed implementation of the signal transmitter circuit 410 of the signal communication device 400. Specifically, the signal transmitter circuit 500 includes a main (full UI) transmit (Tx) driver 510 and an intermediate sub-UI transmit boost driver 520. The main transmit driver 510 and the intermediate sub-UI boost driver 520 include signal input terminals coupled to the transmitter circuit 500 to receive an input transmit signal TX. I The corresponding input terminals, and coupled together to transmit the input signal TX. I To jointly generate the output transmission signal TX O The corresponding output terminal.

[0045] The main transmit driver 510 is configured to transmit based on the input transmit signal TX. I To generate the output transmission signal TX O Part 1 TX O1 That is, the main transmitter driver 510, which can be coupled to and receives power from the high supply voltage rail Vdd1 and the low supply voltage rail Vss (e.g., ground), is configured to amplify and / or voltage level shift the input transmitter signal TX. I To generate the output transmission signal TX O Part 1 TX O1 This allows each of them to transmit its own input signal TX. I A positive pulse across the entire UI, such as Figure 4 The diagram shown corresponds to TX. O1 The solid line in the eye diagram indicates this.

[0046] The intermediate sub-UI, which can be coupled to and receives power from the high-voltage rail Vdd2 and the low-voltage rail Vss (e.g., ground), transmits boost driver 520 based on the input transmit signal TX. I To generate the output transmission signal TX O Part 2 TX O2 The intermediate sub-UI transmit boost driver 520 is configured to amplify and / or level-shift the voltage input transmit signal TX. I The intermediate sub-interval of the UI is used to generate the output transmission signal TX. O Part 2 TX O2 (For example, the intermediate sub-UI coincides with a positive pulse), such as Figure 4 The diagram shown corresponds to TX. O2 As indicated by the dashed lines in the eye diagram. As discussed, the intermediate sub-spacing of the UI can be connected to the received signal RX that would originally be received at the unterminated signal receiver circuit. I The high-side descent that occurred in the middle was basically consistent.

[0047] More specifically, the intermediate sub-UI transmit boost driver 520 includes a boost pulse rising edge initiation circuit 522, a boost pulse falling edge initiation circuit 524, and a transmit boost driver 530. The boost pulse rising edge initiation circuit 522 and the boost pulse falling edge initiation circuit 524 include signal input terminals coupled to the transmitter circuit 500 to receive the input transmit signal TX. I The corresponding input terminals of the boost pulse rising edge initiation circuit 522 and the boost pulse falling edge initiation circuit 524 include corresponding output terminals coupled to the input terminals of the transmit boost driver 530. The transmit boost driver 530, which can be coupled to and receives power from the high voltage rail Vdd2 and the low voltage rail Vss (e.g., ground), is configured to generate a second or boost portion TX based on the rising edge initiation signal and the falling edge initiation signal. O2 As previously discussed, the supply voltage Vdd2 for the transmit boost driver 530 may be substantially equal to or higher than the supply voltage Vdd1 for the main transmit driver 510. As previously indicated, the transmit boost driver 530 includes an output coupled to the output of the main transmit driver 510.

[0048] In operation, the boost pulse rising edge initiation circuit 522 is configured to respond to the input transmit signal TX. I The rising edge is used to generate a rising edge trigger signal. In response to the rising edge trigger signal, the boost driver 530 generates an output transmit signal TX. O The second or boost section TX O2 The rising edge of the boost pulse. The rising edge initiation circuit 522 can initiate the transmission of the input signal TX. I The first time interval after the rising edge (e.g., 0.25) The UI generates a rising edge initiation signal. Similarly, the boost pulse falling edge initiation circuit 524 is configured to respond to the input transmit signal TX. I The rising edge of the signal is used to generate a falling edge initiation signal. In response to the falling edge initiation signal, the boost driver 530 generates an output transmit signal TX. O The second or boost section TX O2 The falling edge of the boost pulse. The falling edge initiation circuit 524 can transmit the signal TX at input. I The second time interval after the rising edge (e.g., 0.75) The UI generates a falling edge initiation signal (e.g., it is converted to a coincident full UI positive pulse 0.25 seconds before the falling edge generated by the main transmit driver 510). The UI time interval). Because the output of the main transmit driver 510 and the output of the transmit boost driver 530 are coupled together, the first part TX O1 Part 2 TX O2 Combine or sum to form the output transmitted signal TX O .

[0049] Figure 6A A block diagram illustrating another signal transmitter circuit 600 according to another aspect of this disclosure is shown. Signal transmitter circuit 600 may be a more detailed implementation of signal transmitter circuit 500. Specifically, signal transmitter circuit 600 includes a main (full UI) transmit (Tx) driver 610 and an intermediate sub-UI transmit boost driver 620. The main transmit driver 610 and the intermediate sub-UI transmit boost driver 620 include signal input terminals coupled to transmitter circuit 600 to receive input transmit signals TX. I The corresponding input terminals, and coupled together to transmit the input signal TX. I Together generate the output transmission signal TX O The corresponding output terminal.

[0050] The main transmitter driver 610 is configured to transmit based on the input transmitter signal TX. I To generate the output transmission signal TX O Part 1 TX O1 That is, the main transmitter driver 610, which can be coupled to and receives power from the high supply voltage rail Vdd1 and the low supply voltage rail Vss (e.g., ground), is configured to amplify and / or voltage level shift the input transmitter signal TX. I To generate the output transmission signal TX O Part 1 TX O1 This allows each of them to transmit its own input signal TX. I A positive pulse across the entire UI, such as Figure 4The diagram shown corresponds to TX. O1 The solid line in the eye diagram indicates this.

[0051] The intermediate sub-UI, which can be coupled to and receives power from the high-voltage rail Vdd2 and the low-voltage rail Vss (e.g., ground), transmits boost driver 620 based on the input transmit signal TX. I To generate the output transmission signal TX O Part 2 TX O2 The intermediate sub-UI boost driver 620 is configured to amplify and / or level-shift the voltage input transmission signal TX. I The intermediate sub-interval of the UI is used to generate the output transmission signal TX. O Part 2 TX O2 (For example, the intermediate sub-UI coincides with a positive pulse), such as Figure 4 The diagram shown corresponds to TX. O2 As indicated by the dashed lines in the eye diagram. As discussed, the intermediate sub-spacing of the UI can be connected to the received signal RX that would originally be received at the unterminated signal receiver circuit. I The high-side descent that occurred in the middle was basically consistent.

[0052] More specifically, the intermediate sub-UI transmit boost driver 620 includes a first delay circuit 622, a second delay circuit 624, an inverting circuit (e.g., an inverter, a NAND gate with an input fixed to logic one (1), a NOR gate with an input fixed to logic zero (0), etc.) 626, a logic gate (e.g., an AND, AND function, XNOR, or others) 628, and a transmit boost driver 630. Comparing the intermediate sub-UI transmit boost driver 620 with the intermediate sub-UI transmit boost driver 520, the first delay circuit 622 may correspond to the boost pulse rising edge initiation circuit 522, and the cascaded second delay circuit 624 and inverting circuit 626 may correspond to the boost pulse falling edge initiation circuit 524. Logic gate 628 is configured to perform a logical AND operation on a rising edge initiation signal generated by the first delay circuit 622 and a falling edge initiation signal generated by the cascaded second delay circuit 624 and the inverting circuit 626 to generate a boost pulse initiation signal for transmitting the boost driver 630.

[0053] The first delay circuit 622 and the second delay circuit 624 include signal input terminals coupled to the transmitter circuit 600 to receive the input transmission signal TX. IThe corresponding input terminals. The first delay circuit 622 and the second delay circuit 624 include output terminals respectively coupled to the input terminals of the logic gate 628. The logic gate 628 includes an output terminal coupled to the input terminal of the transmit boost driver 630. The transmit boost driver 630, which can be coupled to and receives power from the high voltage rail Vdd2 and the low voltage rail Vss (e.g., ground), is configured to generate a second or boost portion TX based on a boost pulse initiation signal generated by the logic gate 628. O2 As previously discussed, the supply voltage Vdd2 for the transmit boost driver 630 may be substantially equal to or higher than the supply voltage Vdd1 for the main transmit driver 610. As previously indicated, the transmit boost driver 630 includes an output coupled to the output of the main transmit driver 610.

[0054] In operation, the first delay circuit 622 is configured to transmit the input signal TX. I The rising edge is delayed by a first delay D1 to generate the rising edge initiation signal. The first delay D1 can be set to the first sub-UI (e.g., 0.25). Similarly, the second delay circuit 624 is configured to transmit the input signal TX. I The rising edge is delayed by a second delay D2 to generate a falling edge initiation signal via the inverting circuit 626. The second delay D2 can be set to a second sub-UI (e.g., 0.75). When the first delay circuit 622 generates a rising edge initiation signal, the cascaded second delay circuit 624 and inverter circuit 626 output a logic high signal. In response, AND gate 628 transmits / outputs the rising edge initiation signal, which causes the transmit boost driver 630 to generate an output transmit signal TX. O The second or boost section TX O2 The rising edge. When the cascaded second delay circuit 624 and inverter circuit 626 generate the falling-rising edge initiation signal, the first delay circuit 622 is outputting a logic high signal. In response, AND gate 628 transmits / outputs the falling-edge initiation signal, which causes the transmit boost driver 630 to generate the output transmit signal TX. O The second or boost section TX O2 The falling edge. Because the output of the main transmit driver 510 and the output of the transmit boost driver 530 are coupled together, the first part TX O1 Part 2 TX O2 Combine or sum to form the output transmitted signal TX O .

[0055] Figure 6BA block diagram of another signal transmitter circuit 660 according to another aspect of this disclosure is illustrated. Signal transmitter circuit 660 is a variation of the previously discussed signal transmitter circuit 600 and includes many of the same / similar elements, as indicated by the same reference numerals. The difference in signal transmitter circuit 660 is that the intermediate sub-UI transmit boost driver 650 includes a second delay circuit 624, which includes an input coupled to the output of the first delay circuit 622. The second delay circuit 624 can implement a third delay D3 (e.g., 0.5). UI), where the sum of the first and third delays is D1+D3 (e.g., 0.25). UI +0.5 UI=0.75 UI) controls the cascaded second delay circuit 654 and inverter circuit 626 in response to the input transmit signal TX. I The rising edge is used to generate the falling edge initiation signal.

[0056] Figure 7 A block diagram illustrating another example of a signal transmitter circuit 700 according to another aspect of this disclosure is shown. The signal transmitter circuit 700 may be an example of any of the M+N signal transmitter circuits of the data / clock communication device 100. As further discussed herein, the second transmit driver of the signal transmitter circuit 700 may be selectively reused for the previously discussed intermediate sub-UI boost operation, or for another operating mode (e.g., changing the output impedance of the signal transmitter circuit 700 to increase the output transmit signal TX). O The edge / transition rate, and / or others).

[0057] Specifically, the signal transmitter circuit 700 includes a first transmit driver 710, a demultiplexer 720, an intermediate sub-UI pulse initiator 730, other operating mode circuitry 740, a multiplexer 750, and a second transmit driver 760. The first transmit driver 710, which can be coupled to and receives power from the high voltage rail Vdd1 and the low voltage rail Vss (e.g., ground), includes a signal input terminal coupled to the transmitter circuit 700 to receive the input transmit signal TX. I The input terminal. The first transmit driver 710 is configured to amplify and / or voltage level shift the input transmit signal TX. I To generate the output transmission signal TX O At least a part of it.

[0058] Demultiplexer 720 includes a signal input coupled to signal transmitter circuit 700 to receive input transmit signal TX. IThe demultiplexer 720 includes an input terminal and a selection input terminal configured to receive a mode signal. The demultiplexer 720 includes output terminals coupled to the input terminals of the intermediate sub-UI boost pulse initiator 730 and other operation mode circuits 740, respectively. The intermediate sub-UI boost pulse initiator 730 and other operation mode circuits 740 include output terminals coupled to the input terminals of the multiplexer 750, respectively. The multiplexer 750 includes a selection input terminal configured to receive a mode signal. The multiplexer 750 includes an output terminal coupled to the input terminal of the second transmit driver 760. The second transmit driver 760, which can be coupled to and receives power from the high voltage rail Vdd2 and the low voltage rail Vss (e.g., ground), is configured to amplify and / or voltage level shift the selected signal received from the multiplexer 750 to generate an output transmit signal TX. O Another part. Similarly, as previously discussed, the supply voltage Vdd2 for the second transmit driver 760 may be the same as or different from the supply voltage Vdd1 for the first transmit driver 710.

[0059] In operation, if the mode signal indicates intermediate sub-UI boost operation, demultiplexer 720 reliably couples its input to the output coupled to intermediate sub-UI pulse initiator 730, and multiplexer 750 reliably couples the input coupled to intermediate sub-UI pulse initiator 730 to its output. In this operating mode, signal transmitter circuit 700 operates to execute the output transmission signal TX. O The intermediate sub-UI is boosted, as previously discussed in reference signal transmitter circuits 410, 500, 600, and 660. If the mode signal indicates another operating mode (e.g., not intermediate sub-UI boost operation), demultiplexer 720 reliably couples its input to the output coupled to the other operating mode circuit 740, and multiplexer 750 reliably couples the input coupled to the other operating mode circuit 740 to its output. In this operating mode, signal transmitter circuit 700 operates according to the other operating mode. The other operating mode circuit 740 may be used only for transmitting the input transmit signal TX. I Directly routed to the electrical conductor of the second transmit driver 760, or for input transmit signal TX. I The circuitry that processes the input transmission signal before it is transmitted to the second transmission driver 760.

[0060] Figure 8A block diagram illustrating another example of a signal transmitter circuit 800 according to another aspect of this disclosure is shown. Any of the previously discussed signal transmitter circuits 410, 500, 600, 660, and 700 (and the signal transmitter circuit 900 discussed further herein) may include one or more pre-drivers to amplify and / or voltage-level shift the input transmit signal TX in one or more stages before the signal is applied to the inputs of the main (full UI) transmit driver and the intermediate sub-UI transmit boost driver. I .

[0061] In this regard, the signal transmitter circuit 800 includes a first set 810 of one or more pre-drivers, a second set 820 of one or more pre-drivers, a third set 830 of one or more pre-drivers, a main (full UI) transmit driver 840, and an intermediate sub-UI transmit boost driver 850. The first set 810 of one or more pre-drivers includes a signal input coupled to the transmitter circuit 800 to receive an input transmit signal TX. I The input terminals of the pre-drivers are coupled to the input terminals of a second set 820 of the pre-drivers and the input terminals of a third set 830 of the pre-drivers, respectively. The second set 820 of one or more pre-drivers includes an output terminal coupled to the input terminal of the main (full UI) transmit driver 840. The third set 830 of one or more pre-drivers includes an output terminal coupled to the input terminal of the intermediate sub-UI transmit boost driver 850. The main (full UI) transmit driver 840 and the intermediate sub-UI transmit boost driver 850 together include corresponding output terminals. The main (full UI) transmit driver 840 and the intermediate sub-UI boost driver 850 may be coupled to the same supply voltage rail (Vdd1 or Vdd2) or different supply voltage rails Vdd1 and Vdd2 and Vss (e.g., ground).

[0062] In operation, a first set 810 of one or more pre-drivers is configured to execute the input transmission signal TX. I The first stage amplification and / or voltage level shift. A second set 820 of one or more pre-drivers is configured to perform input transmit signal TX for the master (full UI) transmit driver 840. I The second stage amplification and / or voltage level shift. A third set 830 of one or more pre-drivers is configured to execute the input transmit signal TX for the intermediate sub-UI transmit boost driver 850. I The second stage amplification and / or voltage level shifting. The main (full UI) transmit driver 840 is configured to amplify and / or voltage level shift the signal generated by the second set 820 of one or more pre-drivers to transmit the signal TX at the output. O Part 1 TX O1The intermediate sub-UI transmit boost driver 850 is configured to amplify and / or horizontally shift the signal generated by the third set 830 of one or more pre-drivers to transmit the signal TX at the output. O Part 2 TX O2 Generated at [location]. Part 1 (TX) O1 Part 2 TX O2 The output transmit signal TX is generated by combining or summing the common output of the main (full UI) transmit driver 840 and the intermediate sub-UI transmit boost driver 850. O .

[0063] Figure 9 A block diagram illustrating another example of a signal transmitter circuit 900 according to another aspect of this disclosure is shown. The previously discussed signal transmitter circuits 410, 500, 600, 660, 700, and 800 focus on outputting a transmitted signal TX. O The intermediate sub-UI boost is provided to reduce the input received signal RX at the unterminated signal receiver circuit. I The high side of the middle decreases. However, as with Figures 2-5 The input received signal RX is depicted in the figure. I As shown in the corresponding eye diagram, the input received signal RX I It also exhibits a low-side bulge that tends to close or reduce the eye diagram height. Therefore, the signal transmitter circuit 900 is configured to reduce the input received signal RX. I The low-side protrusions in the eye diagram are used to open or increase the height of the eye diagram, thereby improving the detectability of data / clock.

[0064] Specifically, the signal transmitter circuit 900 may be similar to the signal transmitter circuit 410, including a main (full UI) transmit driver 920 and an intermediate sub-UI transmit boost driver 930. Drivers 920 and 930 are coupled together at the signal input terminals of the signal transmitter circuit 900 to receive the input transmit signal TX. I The corresponding input terminals. Drivers 920 and 930 similarly include those coupled together to jointly generate the output transmit signal TX. O The corresponding output terminals are as previously discussed. In addition, the signal transmitter circuit 900 includes a pull-down strength control circuit 910, which includes an input terminal coupled to the signal input terminal of the signal transmitter circuit 900, and an output terminal coupled to one or more control input terminals respectively coupled to the main (full UI) transmit driver 920 and the intermediate sub-UI transmit boost driver 930.

[0065] In operation, the pull-down strength control circuit 910 is configured to respond to the input transmit signal TX. IThe falling edge of the signal is used to generate a control or configuration signal (CS) to increase the strength of the pull-down circuitry in the master (full UI) transmit driver 920 and / or the intermediate sub-UI transmit boost driver 930. For example, the CS signal may cause an increase in the effective size or number of pull-down devices (e.g., field-effect transistors (FETs)) in drivers 920 and 930 to increase the output transmit signal TX. O The switching rate of the falling edge. Therefore, in the output transmitted signal TX O In this context, the slewing rate of the falling edge can be greater than that of the rising edge. The increased slewing rate of the falling edge consequently reduces the input received signal RX. I The low-side bumps in the eye diagram are used to open or increase the height of the eye diagram, thereby improving the detectability of data / clock at the signal receiver circuit.

[0066] Figure 10 A flowchart illustrating an example method 1000 for generating an output transmission signal according to another aspect of this disclosure is provided. Method 1000 includes generating a first portion of an output transmission signal based on an input transmission signal, wherein the first portion of the output transmission signal comprises a first set of pulses, each spanning a unit interval (UI) (block 1010). Examples of components for generating the first portion of the output transmission signal based on the input transmission signal include any one of main (full UI) transmission drivers 412, 510, 610, 710, 840, and 920, wherein the first portion of the output transmission signal comprises a first set of pulses, each spanning a unit interval (UI).

[0067] Method 1000 further includes a second portion of generating an output transmission signal based on an input transmission signal, wherein the second portion of the output transmission signal comprises a second set of pulses, each spanning an intermediate sub-interval of the UI (box 1020). Examples of components for generating the second portion of the output transmission signal based on the input transmission signal include any of intermediate sub-UI transmission boost drivers 414, 520, 620, 650, 760, 850, and 930, wherein the second portion of the output transmission signal comprises a second set of pulses, each spanning an intermediate sub-interval of the UI.

[0068] Additionally, method 1000 includes combining the first portion with the second portion to generate an output transmission signal (block 1030). Examples of components for combining the first portion with the second portion to generate the output transmission signal include the output of any of the master (full UI) transmit drivers 412, 510, 610, 710, 840, and 920 coupled to the output of any of the intermediate sub-UI boost drivers 414, 520, 620, 650, 760, 850, and 930.

[0069] The following provides an overview of the various aspects of this disclosure: Aspect 1: An apparatus comprising: a first transmit driver including an input coupled to the signal input; a first delay circuit including an input coupled to the signal input; a second delay circuit including an input coupled to the signal input or an output of the first delay circuit; an inverting circuit including an input coupled to the output of the second delay circuit; a logic gate including inputs coupled to the outputs of the first delay circuit and the inverting circuit; and a second transmit driver including an input coupled to the output of the logic gate and an output coupled to the output of the first transmit driver.

[0070] Aspect 2: The apparatus according to aspect 1, wherein the logic gate includes an AND function, an AND gate, or an XNOR gate.

[0071] Aspect 3: The apparatus according to aspect 1 or 2, wherein the input terminal of the second delay circuit is coupled to the signal input terminal via the first delay circuit.

[0072] Aspect 4: The apparatus according to aspect 1 or 2, wherein the input terminal of the second delay circuit is coupled to the input terminal of the first delay circuit.

[0073] Aspect 5: The apparatus according to any one of Aspects 1 to 4, the apparatus further comprising a control circuit, the control circuit including an input terminal respectively coupled to the signal input terminal and an output terminal coupled to one or more control input terminals of the first transmitting driver or the second transmitting driver.

[0074] Aspect 6: The apparatus according to any one of Aspects 1 to 5, further comprising: a demultiplexer including: an input coupled to the signal input; a selection input configured to receive a mode signal; a first output coupled to the input of the first delay circuit or the input of the first delay circuit and the input of the second delay circuit; and a second output coupled to the input of another operating mode circuit; and a multiplexer including: a first input coupled to the output of the logic gate; a second input coupled to the output of the other operating mode circuit; a selection input configured to receive the mode signal; and an output coupled to the input of the second transmit driver.

[0075] Aspect 7: The apparatus according to any one of Aspects 1 to 6, the apparatus further comprising a first set of one or more pre-drivers, the first set of one or more pre-drivers including an input coupled to the signal input and an output coupled to the input of the first transmit driver and the input of the first delay circuit.

[0076] Aspect 8: The apparatus according to aspect 7, the apparatus further comprising: a second set of one or more pre-drivers, the second set of one or more pre-drivers including an input coupled to the output of the first set of one or more pre-drivers and an output coupled to the input of the first transmit driver; and a third set of one or more pre-drivers, the third set of one or more pre-drivers including an input coupled to the output of the first set of one or more pre-drivers and an output coupled to the input of the first delay circuit.

[0077] Aspect 9: The apparatus according to any one of Aspects 1 to 8, the apparatus further comprising: a high power supply voltage rail coupled to the first transmit driver and the second transmit driver; and a low power supply voltage rail coupled to the first transmit driver and the second transmit driver.

[0078] Aspect 10: The apparatus according to any one of Aspects 1 to 8, the apparatus further comprising: a first high power supply voltage rail coupled to the first transmit driver; a second high power supply voltage rail coupled to the second transmit driver; and a low power supply voltage rail coupled to the first transmit driver and the second transmit driver.

[0079] Aspect 11: The apparatus according to any one of Aspects 1 to 10, the apparatus further comprising: a terminating resistor including a first terminal coupled to the output terminal of the first transmitting driver and the output terminal of the second transmitting driver; and a capacitor including a first terminal coupled to a second terminal of the terminating resistor and a second terminal coupled to a power supply voltage rail.

[0080] Aspect 12: An apparatus comprising: a full unit interval (UI) transmit driver including an input coupled to a signal input; and an intermediate sub-UI boost driver including an input coupled to the signal input and an output coupled to an output of the full UI transmit driver.

[0081] Aspect 13: The apparatus according to aspect 12, wherein the intermediate sub-UI boost driver comprises: a boost rising edge initiation circuit, the boost rising edge initiation circuit including an input coupled to the signal input; and / or a boost falling edge initiation circuit, the boost falling edge initiation circuit including an input coupled to the signal input; and a transmit boost driver, the transmit boost driver including an input coupled to the output of the boost rising edge initiation circuit and the output of the boost falling edge initiation circuit, respectively.

[0082] Aspect 14: The apparatus according to aspect 13, wherein the boost rising edge initiation circuit includes a delay circuit.

[0083] Aspect 15: The apparatus according to aspect 13 or 14, wherein the boost falling edge initiation circuit includes a delay circuit cascaded with the inverting circuit.

[0084] Aspect 16: The apparatus according to aspect 12, wherein the intermediate sub-UI boost driver comprises: a boost pulse initiation circuit, the boost pulse initiation circuit including an input coupled to the signal input; and a transmit boost driver, the transmit boost driver including an input coupled to the output of the boost pulse initiation circuit.

[0085] Aspect 17: The apparatus according to aspect 16, wherein the boost pulse initiation circuit comprises: a first delay circuit including an input coupled to the signal input; a second delay circuit including an input coupled to the signal input; an inverting circuit including an input coupled to the output of the second delay circuit; and a logic gate including an input coupled to the output of the first delay circuit and the output of the inverting circuit, and an output coupled to the input of the transmitting boost driver.

[0086] Aspect 18: The apparatus according to aspect 17, wherein the logic gate includes an AND function, an AND gate, or an XNOR gate.

[0087] Aspect 19: The apparatus according to aspect 17 or 18, wherein the input terminal of the second delay circuit is coupled to the signal input terminal via the first delay circuit.

[0088] Aspect 20: The apparatus according to aspect 17 or 18, wherein the input terminal of the second delay circuit is coupled to the input terminal of the first delay circuit.

[0089] Aspect 21: An apparatus comprising: a full UI transmit driver configured to generate a first portion of an output transmit signal based on an input transmit signal, wherein the first portion of the output transmit signal comprises a first set of pulses each spanning a unit interval (UI); and an intermediate sub-UI boost driver configured to generate a second portion of the output transmit signal based on the input transmit signal, wherein the second portion of the output transmit signal comprises a second set of pulses each spanning an intermediate sub-interval of the UI.

[0090] Aspect 22: The apparatus according to aspect 21, wherein the intermediate sub-UI boost driver comprises: a first delay circuit configured to generate a rising edge at a first delay following the rising edge of the input transmission signal of each pulse in the second set of pulses; a second delay circuit configured to generate a falling edge at a second delay following the rising edge of the input transmission signal of each pulse in the second set of pulses; and a boost driver configured to generate each pulse in the second set of pulses based on the rising edge and the falling edge generated by the first delay circuit and the second delay circuit, respectively.

[0091] Aspect 23: The apparatus according to aspect 22, wherein the intermediate sub-UI boost driver further comprises: an inverting circuit including an input coupled to the output of the second delay circuit; and a logic gate including an input coupled to the output of the first delay circuit and the output of the inverting circuit, and an output coupled to the input of the boost driver.

[0092] Aspect 24: The apparatus according to aspect 22 or 23, wherein the boost driver includes an output coupled to the output of the full UI transmit driver.

[0093] Aspect 25: A method comprising: generating a first portion of an output transmission signal based on an input transmission signal, wherein the first portion of the output transmission signal comprises a first set of pulses each spanning a unit interval (UI); generating a second portion of the output transmission signal based on the input transmission signal, wherein the second portion of the output transmission signal comprises a second set of pulses each spanning an intermediate sub-interval of the UI; and combining the first portion and the second portion to generate the output transmission signal.

[0094] Aspect 26: According to the method of aspect 25, wherein the first set of pulses coincides with the second set of pulses respectively.

[0095] Aspect 27: According to the method of aspect 26, wherein: the rising edge of each pulse in the second set occurs after a first time interval following the rising edge of each overlapping pulse in the first set; and the falling edge of each pulse in the second set occurs before a second time interval following the falling edge of each overlapping pulse in the first set.

[0096] Aspect 28: According to the method of aspect 27, wherein the first time interval and the second time interval are each substantially 0.25. UI.

[0097] Aspect 29: The method according to aspect 27 or 28, wherein the transition rate of the falling edge of each of the first set and the second set of pulses is greater than the transition rate of the rising edge of each of the first set and the second set of pulses.

[0098] Aspect 30: The method of claim 25, wherein the second portion of generating the output transmission signal is based on a first operating mode, and the method further comprises: generating a third portion of the output transmission signal based on the input transmission signal and a second operating mode, wherein the third portion is different from the second portion; and combining the first portion and the third portion according to the second operating mode to generate the output transmission signal.

[0099] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: A first transmitting driver, the first transmitting driver including an input coupled to a signal input; A first delay circuit, the first delay circuit including an input terminal coupled to the signal input terminal; The second delay circuit includes an input terminal coupled to the signal input terminal or the output terminal of the first delay circuit; An inverting circuit, the inverting circuit including an input terminal coupled to the output terminal of the second delay circuit; A logic gate, the logic gate including an input terminal respectively coupled to the output terminal of the first delay circuit and the output terminal of the inverting circuit; and The second transmit driver includes an input coupled to the output of the logic gate and an output coupled to the output of the first transmit driver.

2. The apparatus of claim 1, wherein the logic gate comprises an AND function, an AND gate, or an XNOR gate.

3. The apparatus of claim 1, wherein the input terminal of the second delay circuit is coupled to the signal input terminal via the first delay circuit.

4. The apparatus of claim 1, wherein the input terminal of the second delay circuit is coupled to the input terminal of the first delay circuit.

5. The apparatus of claim 1, further comprising a control circuit, the control circuit including an input terminal respectively coupled to the signal input terminal and an output terminal coupled to one or more control input terminals of the first transmitting driver or the second transmitting driver.

6. The apparatus according to claim 1, further comprising: Demultiplexer, the demultiplexer comprising: The input terminal coupled to the signal input terminal; The input terminal is configured to receive mode signals; A first output terminal, the first output terminal being coupled to the input terminal of the first delay circuit or the input terminal of the first delay circuit and the input terminal of the second delay circuit; and The second output terminal coupled to the input terminal of another operating mode circuit; and A multiplexer, the multiplexer comprising: The first input terminal coupled to the output terminal of the logic gate; The second input terminal coupled to the output terminal of the other operating mode circuit; The selection input terminal is configured to receive the mode signal; and The output terminal is coupled to the input terminal of the second transmitting driver.

7. The apparatus of claim 1, further comprising a first set of one or more pre-drivers, the first set of one or more pre-drivers including an input coupled to the signal input and an output coupled to the input of the first transmit driver and the input of the first delay circuit.

8. The apparatus of claim 7, further comprising: A second set of one or more pre-drivers, the second set of one or more pre-drivers including an input coupled to the output of the first set of one or more pre-drivers, and an output coupled to the input of the first transmit driver; and A third set of one or more pre-drivers, the third set of one or more pre-drivers including an input coupled to the output of the first set of one or more pre-drivers, and an output coupled to the input of the first delay circuit.

9. The apparatus according to claim 1, further comprising: A high power supply voltage rail, which is coupled to the first transmit driver and the second transmit driver; and A low power supply voltage rail is coupled to the first transmit driver and the second transmit driver.

10. The apparatus according to claim 1, further comprising: A first high-voltage rail is coupled to the first transmitter driver; A second high-supply voltage rail is coupled to the second transmit driver; and A low power supply voltage rail is coupled to the first transmit driver and the second transmit driver.

11. The apparatus of claim 1, further comprising: A terminating resistor, the terminating resistor including a first terminal coupled to the output terminal of the first transmitting driver and the output terminal of the second transmitting driver; and The capacitor includes a first terminal coupled to a second terminal of the terminating resistor and a second terminal coupled to a power supply voltage rail.

12. An apparatus comprising: A full unit interval (UI) transmit driver, the full unit interval (UI) transmit driver including an input coupled to a signal input; and An intermediate sub-UI boost driver, the intermediate sub-UI boost driver including an input terminal coupled to the signal input terminal and an output terminal coupled to the output terminal of the full UI transmit driver.

13. The apparatus of claim 12, wherein the intermediate sub-UI boost driver comprises: A boost rising edge initiation circuit, the boost rising edge initiation circuit including an input terminal coupled to the signal input terminal; and / or A boost-falling-edge initiation circuit, the boost-falling-edge initiation circuit including an input terminal coupled to the signal input terminal; as well as A transmit boost driver, the transmit boost driver including input terminals respectively coupled to the output terminal of the boost rising edge initiation circuit and the output terminal of the boost falling edge initiation circuit.

14. The apparatus of claim 13, wherein the boost rising edge initiation circuit includes a delay circuit.

15. The apparatus of claim 13, wherein the boost falling edge initiation circuit includes a delay circuit cascaded with the inverting circuit.

16. The apparatus of claim 12, wherein the intermediate sub-UI boost driver comprises: A boost pulse initiation circuit, the boost pulse initiation circuit including an input terminal coupled to the signal input terminal; and A transmit boost driver, the transmit boost driver including an input coupled to the output of the boost pulse initiation circuit.

17. The apparatus of claim 16, wherein the boost pulse initiation circuit comprises: A first delay circuit, the first delay circuit including an input terminal coupled to the signal input terminal; A second delay circuit, the second delay circuit including an input terminal coupled to the signal input terminal; An inverting circuit, the inverting circuit including an input terminal coupled to the output terminal of the second delay circuit; and The logic gate includes an input terminal coupled to the output terminal of the first delay circuit and the output terminal of the inverting circuit, respectively, and an output terminal coupled to the input terminal of the transmitting boost driver.

18. The apparatus of claim 17, wherein the logic gate comprises an AND function, an AND gate, or an XNOR gate.

19. The apparatus of claim 17, wherein the input terminal of the second delay circuit is coupled to the signal input terminal via the first delay circuit.

20. The apparatus of claim 17, wherein the input terminal of the second delay circuit is coupled to the input terminal of the first delay circuit.

21. An apparatus comprising: A full UI transmit driver, the full UI transmit driver being configured to generate a first portion of an output transmit signal based on an input transmit signal, wherein the first portion of the output transmit signal comprises a first set of pulses, each spanning a unit interval (UI); and An intermediate sub-UI boost driver is configured to generate a second portion of the output transmission signal based on the input transmission signal, wherein the second portion of the output transmission signal includes a second set of pulses, each spanning an intermediate sub-interval of the UI.

22. The apparatus of claim 21, wherein the intermediate sub-UI boost driver comprises: A first delay circuit is configured to generate a rising edge at a first delay following the rising edge of the input transmission signal of each pulse in the second set of pulses; A second delay circuit is configured to generate a falling edge at a second delay following the rising edge of the input transmission signal of each pulse in the second set of pulses; and A boost driver configured to generate each pulse in the second set of pulses based on the rising edge and the falling edge generated by the first delay circuit and the second delay circuit, respectively.

23. The apparatus of claim 22, wherein the intermediate sub-UI boost driver further comprises: An inverting circuit, the inverting circuit including an input terminal coupled to the output terminal of the second delay circuit; and The logic gate includes an input terminal coupled to the output terminal of the first delay circuit and the output terminal of the inverting circuit, respectively, and an output terminal coupled to the input terminal of the boost driver.

24. The apparatus of claim 22, wherein the boost driver includes an output coupled to the output of the full UI transmit driver.

25. A method, the method comprising: A first portion of an output transmission signal is generated based on an input transmission signal, wherein the first portion of the output transmission signal comprises a first set of pulses, each spanning a unit interval (UI); The second portion of the output transmission signal is generated based on the input transmission signal, wherein the second portion of the output transmission signal includes a second set of pulses, each spanning an intermediate sub-interval of the UI; as well as The first part and the second part are combined to generate the output transmission signal.

26. The method of claim 25, wherein the first set of pulses coincides with the second set of pulses.

27. The method of claim 26, wherein: The rising edge of each pulse in the second set occurs within a first time interval following the rising edge of each overlapping pulse in the first set; and The falling edge of each pulse in the second set occurs at a second time interval preceding the falling edge of each overlapping pulse in the first set.

28. The method of claim 27, wherein the first time interval and the second time interval are each substantially 0.

25. UI.

29. The method of claim 27, wherein the transition rate of the falling edge of each of the first set and the second set of pulses is greater than the transition rate of the rising edge of each of the first set and the second set of pulses.

30. The method of claim 25, wherein the second portion of generating the output transmission signal is based on a first operating mode, and the method further comprises: A third part of the output transmission signal is generated based on the input transmission signal and the second operating mode, wherein the third part is different from the second part; as well as The first part and the third part are combined according to the second operating mode to generate the output transmission signal.

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