Body source connected standard cell implementation in semiconductor-on-insulator (SOI) technology

Abstract

An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first type diffusion region. The IC device also includes a first first type transistor located on the first type diffusion region. The IC device also includes a second first type transistor on the first type diffusion region. The IC device also includes a first second type implant region. The first second type implant region includes a gate overlap region partially overlapping a gate region of the second first type transistor to provide a body contact of the second first type transistor and couple in series a source region of the second first type transistor to a drain region of the first first type transistor.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 477,508, filed September 28, 2023, entitled "BODY TIED TO SOURCESTANDARD CELL IMPLEMENTATIONS IN SEMICONDUCTOR-ON-INSULATOR (SOI) TECHNOLOGY", the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuits (ICs). More specifically, this disclosure relates to a specific implementation of a body-source interconnected standard cell in semiconductor-on-insulator (SOI) technology. Background Technology

[0004] The design complexity of mobile integrated circuits (ICs) is compounded by the additional circuitry needed to support enhanced communications. Designing mobile ICs may involve using semiconductor-on-insulator (SOI) technology. SOI technology replaces conventional semiconductor (e.g., silicon) substrates with layered semiconductor-insulator-semiconductor substrates to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional silicon devices because the silicon junction is located above an electrical isolator (typically a buried oxide (BOX) layer). However, the reduced thickness of the BOX layer may be insufficient to reduce artificial harmonics caused by the proximity of active devices on the SOI layer to the SOI substrate supporting the BOX layer.

[0005] For example, high-performance transistors are currently fabricated using SOI substrates. Additionally, traditional floating-body transistors exhibit excellent radio frequency (RF)-SOI performance but are affected by the floating-body effect, in which the transistor body collects charge generated at the junction of the transistor device. As described, this floating-body effect is called the kink effect. IC performance is core and critical for product development, and the kink effect affects the supported switching speed and maximum frequency. As communication protocols become increasingly stringent, there is a need for faster switching. This switching speed is limited by the inherent design process of transistor devices. Furthermore, switching delay cannot be completely resolved through design or software. Summary of the Invention

[0006] An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The IC device also includes a first first-type transistor located on the first-type diffusion region. The IC device further includes a second first-type transistor located on the first-type diffusion region. The IC device also includes first and second-type implantation regions. The first and second-type implantation regions include a gate overlap region that partially overlaps with the gate region of the second first-type transistor to provide a body contact for the second first-type transistor and to couple the source region of the second first-type transistor to the drain region of the first first-type transistor in series.

[0007] A method for constructing a polysilicon masked implanted body source-connected (BTS) integrated circuit (IC) device is described. The method includes forming a first type diffusion region on a semiconductor-on-insulator (SOI) substrate. The method further includes forming a first type transistor on the first type diffusion region. The method further includes forming a second type transistor on the first type diffusion region. The method further includes forming a first and second type implanted region. The first and second type implanted regions include a gate overlap region that partially overlaps with the gate region of the second type transistor to provide a body contact of the second type transistor and to couple the source region of the second type transistor to the drain region of the first type transistor in series.

[0008] This has broadly outlined the features and technical advantages of this disclosure in order to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for performing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0009] To gain a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings.

[0010] Figure 1 This is a schematic diagram of a wireless device having a wireless LAN module and a radio frequency (RF) front-end (RFFE) module for the chipset.

[0011] Figure 2A cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) including an RF insulator-on-insulator (SOI) device is shown.

[0012] Figure 3 This is a schematic top view illustrating various aspects of a multifinite floating body (FB) transistor according to the present disclosure.

[0013] Figure 4A This is a schematic diagram illustrating a layout view of a polysilicon masked implanted body source-to-transistor (BTS) integrated circuit (IC) device according to various aspects of this disclosure.

[0014] Figure 4B This illustrates various aspects of this disclosure. Figure 4A The diagram shown is an exploded view of a polysilicon-masked BTS IC device.

[0015] Figure 5A and Figure 5B These are schematic diagrams illustrating various aspects of this disclosure, which further illustrate... Figure 4A and Figure 4B The diagram shows the tangent aa' of the polysilicon masking implanted in the BTS IC device and the corresponding cross-sectional view.

[0016] Figure 6 This is a schematic diagram illustrating a layout view of a polysilicon masked implanted body source interconnect (BTS) transistor according to various aspects of this disclosure.

[0017] Figure 7 This is a schematic diagram illustrating a layout view of an integrated circuit (IC) including a polysilicon masked implanted body source-connected (BTS) transistor according to various aspects of this disclosure.

[0018] Figure 8 This is a schematic top view illustrating various aspects of the present disclosure of a polysilicon masked implanted body source-connected transistor.

[0019] Figure 9 This is a process flowchart illustrating various aspects of the present disclosure for constructing a masked implanted body source-to-source (BTS) integrated circuit (IC) device.

[0020] Figure 10 This is a block diagram illustrating an exemplary wireless communication system in which the configurations of this disclosure may be advantageously employed.

[0021] Figure 11 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components according to one configuration. Detailed Implementation

[0022] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0023] As described herein, the term “and / or” is used to indicate “inclusive or”, and the term “or” is used to indicate “exclusive or”. As described herein, the term “exemplary” as used throughout the description means “serving as an example, instance, or illustration” and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” as used throughout the description means “direct or indirectly connected via an intermediate connection (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, a connection can result in objects being permanently or releasably connected. Connections can be made via switches. As described herein, the term “proximity” as used throughout the description means “adjacent, very close, adjacent, or near.” As described herein, the term “on” as used throughout the description means “directly on” in some configurations and “indirectly on” in others.

[0024] The design complexity of mobile integrated circuits (ICs) is compounded by the additional circuitry needed to support enhanced communication. Designing mobile ICs may involve using semiconductor-on-insulator (SOI) technology. SOI technology replaces conventional semiconductor (e.g., silicon) substrates with layered semiconductor-insulator-semiconductor substrates to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional silicon devices because the silicon junctions are located above the electrical isolators (typically buried oxide (BOX) layers).

[0025] Active devices on the SOI layer can include high-performance complementary metal-oxide-semiconductor (CMOS) transistors. For example, high-performance CMOS integrated circuit (IC) technology is currently fabricated using SOI substrates. Mobile ICs rely on these high-performance CMOS IC technologies for successful operation. Therefore, the process for fabricating mobile ICs involves costly SOI wafer integration to support these high-performance CMOS IC technologies. For example, mobile ICs can include transistors fabricated using SOI wafers. Unfortunately, transistors fabricated using SOI technology can be affected by the floating body (FB) effect. The FB effect is the phenomenon where the transistor body collects a minority of charge carriers in the inversion region of the transistor device's operation. In this case, the accumulated charge in the body produces undesirable effects such as parasitic transistors in the structure and leakage current in the off-state. Furthermore, the accumulated charge can cause the transistor's threshold voltage to become dependent on (reduced) its previous state.

[0026] For example, standard cell transistors are currently manufactured using SOI substrates. Additionally, standard cell transistors exhibit excellent integrated circuit (IC)-SOI performance, but are affected by the aforementioned floating body (FB) effect. As described, this FB effect is referred to as the kink effect. IC performance is core and critical for product development, and the kink effect adversely affects switching time. As communication protocols become more stringent, faster switching is required. This switching speed is inherently limited by the transistor device design process. Furthermore, switching delays cannot be completely resolved through design or software.

[0027] Various aspects of this disclosure provide techniques for polysilicon masked implanted body source-interconnect (BTS) integrated circuit (IC) devices. The semiconductor manufacturing process for polysilicon masked implanted BTS IC devices may include front-end process (FEOL), mid-end process (MOL), and back-end process (BEOL). It should be understood that the term "layer" includes films and will not be construed as indicating vertical or horizontal thickness unless otherwise stated. As described herein, the term "substrate" may refer to the substrate of a diced wafer or the substrate of an undicated wafer. Similarly, the terms "chip" and "die" are used interchangeably.

[0028] Various aspects of this disclosure relate to polysilicon masked implanted BTS IC devices. Specifically, various aspects of this disclosure employ a second type of implantation region that partially overlaps with the gate region to provide a body contact for a second transistor and couple the source region of the second transistor to the drain region of a first transistor. Various aspects of this disclosure utilize polysilicon masking to form the body contact, which eliminates conventional body contact formation using polysilicon notches. Eliminating conventional body contact formation using polysilicon notches advantageously reduces parasitic capacitance associated with a gate length that is significantly larger than a portion of the IC device width (e.g., an average reduction of about 22%). Additionally, the elimination of polysilicon notches reduces the total area specific to the IC device (e.g., an average reduction of about 40%).

[0029] Various aspects of this disclosure further integrate and create shielding body contacts for both N-type and P-type transistors by utilizing shallow trench isolation (STI) spacing regions for appropriate edge implantation. The STI spacing regions enable a unique implementation that takes into account the minimum area of ​​the shielding opening specified by the manufacturing process. Additionally, edge implantation is implemented by forming a series of transistors with low effective capacitance (Ceff) penalty through a unique layout that shares source / drain / body (S / D / B) connections between adjacent transistors. Sharing connections between adjacent transistors reduces area consumption and improves effective capacitance (Ceff). Various aspects of this disclosure also align the body contact N-polysilicon layers and P-polysilicon layers together to create a minimum area implementation similar to a floating body (FB) device.

[0030] Figure 1 This is a schematic diagram of a wireless device 100 (e.g., a cellular phone or smartphone) including a polysilicon-masked implanted body source-connected standard cell transistor device according to various aspects of this disclosure. The wireless device 100 has a wireless local area network (WLAN) (e.g., Wi-Fi) module 150 and a radio frequency (RF) front-end (RFFE) module 170 for a chipset 110. The Wi-Fi module 150 includes a first duplexer 160 that communicatively couples an antenna 162 to the WLAN module (e.g., the WLAN module 152). The RFFE module 170 includes a second duplexer 190 that communicatively couples the antenna 192 to a wireless transceiver (WTR) 120 via a duplexer (DUP) 180. An RF switch 172 communicatively couples the second duplexer 190 to the duplexer 180. In the receiving path, antenna 192 receives communication signals and provides received RF signals, which are routed through second duplexer 190, RF switch 172, duplexer 180 and provided to LNA 124 of WTR 120.

[0031] In this example, the WLAN module 152 of the wireless transceiver 120 and the Wi-Fi module 150 is coupled to a modem (MSM, e.g., a baseband modem) 130, which is powered by a power supply 102 via a power management integrated circuit (PMIC) 140. The chipset 110 also includes capacitors 112 and 114, and an inductor 116, to provide signal integrity. The PMIC 140, modem 130, wireless transceiver 120, and WLAN module 152 each include capacitors (e.g., 142, 132, 122, and 154) and operate according to a clock 118. The geometry and arrangement of the various inductor and capacitor assemblies in the chipset 110 reduce electromagnetic coupling between components.

[0032] The WTR 120 of the wireless device 100 includes a mobile RF transceiver for transmitting and receiving data for bidirectional communication. The mobile RF transceiver may include a transmitting section for data transmission and a receiving section for data reception. For data transmission, the transmitting section can modulate an RF signal with data to obtain a modulated RF signal, amplify the modulated RF signal using a power amplifier (PA) to obtain an amplified RF signal with an appropriate output power level, and transmit the amplified RF signal to the base station via antenna 192. For data reception, the receiving section of the WTR 120 can obtain the received RF signal via antenna 192, and can amplify the received RF signal using an LNA 124, and process the received RF signal to recover the data transmitted by the base station in the communication signal.

[0033] The WTR 120 may include one or more circuits for amplifying these communication signals. The amplifier circuitry (e.g., an LNA / PA) may include one or more amplifier stages, which may have one or more driver stages and one or more amplifier output stages. Each amplifier stage includes one or more transistors configured in various ways to amplify the communication signals. Various options exist for manufacturing transistors configured to amplify the communication signals transmitted and received by the WTR 120.

[0034] The WTR 120 and RFFE module 170 can be implemented using semiconductor-on-insulator (SOI) technology, which is used to fabricate the transistors in the WTR 120, thereby helping to reduce high-order harmonics in the RFFE 170. SOI technology replaces conventional semiconductor substrates with layered semiconductor-insulator-semiconductor substrates to reduce parasitic device capacitance and improve performance. SOI-based devices differ from conventional silicon devices because the silicon junction is located above the electrical isolator (typically a buried oxide (BOX) layer). Figure 2 An active device manufactured using SOI technology is shown.

[0035] Figure 2 A cross-sectional view of a radio frequency (RF) integrated circuit (RFIC) 200 is shown. (As shown) Figure 2 As shown, an RF-SOI device includes an active device 210 on a buried oxide (BOX) layer 220 supported by an SOI substrate 202 (e.g., a silicon wafer). The RF-SOI device can be fabricated as a complementary metal-oxide-semiconductor (CMOS) transistor using CMOS processes. The RF-SOI device also includes interconnects 250 coupled to the active device 210 within a first dielectric layer 206. In this configuration, the parasitic capacitance of the RF-SOI device is proportional to the thickness of the BOX layer 220, which determines the distance between the active device 210 and the SOI substrate 202.

[0036] The active device 210 on the BOX layer 220 can be a CMOS transistor. For example, high-performance CMOS RF switching technology is currently fabricated using an SOI substrate. RFFE module 170 ( Figure 1 Successful operation relies on these high-performance CMOS RF technologies. Therefore, the process for manufacturing the RFFE module 170 involves SOI wafer integration to support these high-performance CMOS RF technologies. Furthermore, support for future RF performance enhancements involves increasing device isolation while reducing RF losses. RFIC 200 can be used to implement this. Figure 1 The RFFE module 170 in the example. For example, the active device 210 can be a switching field-effect transistor (FET) of the LNA 124 of the WTR 120.

[0037] One technique for increasing device isolation and reducing RF losses is to use SOI wafers to fabricate RFFEs. For example, RF devices (e.g., RF low-noise amplifier (LNA) devices) may include transistors fabricated using SOI wafers. Unfortunately, transistors fabricated using SOI technology can be affected by the floating body effect. The floating body effect is the phenomenon where the transistor body collects charge generated at the junction of the transistor device. In this case, the charge accumulated in the body can produce undesirable effects such as parasitic transistors in the structure and leakage current in the off-state. Furthermore, the accumulated charge can cause the transistor's threshold voltage to become dependent on its previous state. In this example, the active device 210 could be... Figure 1 The WTR 120 is an LNA 124 field-effect transistor (FET).

[0038] High-performance standard cell transistors are currently fabricated using SOI substrates. Additionally, standard cell transistors fabricated using SOI substrates currently exhibit excellent IC-SOI performance, but are affected by the aforementioned floating body (FB) effect. As described, this FB effect is referred to as the kink effect. Integrated circuit (IC) performance is core and critical for product development. As communication protocols become more stringent, requirements necessitate faster switching. This switching speed is inherently limited by the transistor device design process. Furthermore, switching delays cannot be completely resolved through design or software.

[0039] Figure 3 This is a schematic top view illustrating a standard cell transistor 300 according to various aspects of the present disclosure. In this configuration, the standard cell transistor 300 includes first-type (e.g., N-type) diffusion regions (e.g., N+ diffusion) in which various source (S) regions and drain (D) regions are formed and separated by various gate (G) regions. In this example, the standard cell transistor 300 is a high-performance integrated circuit (IC) device fabricated using a semiconductor-on-isolation (SOI) substrate 302. While the standard cell transistor 300 exhibits excellent IC-SOI performance, it is affected by the mentioned FB effect. As described, this FB effect is referred to as the kink effect.

[0040] Various aspects of this disclosure relate to polysilicon-masked implanted body source-connected (BTS) IC devices. Specifically, various aspects of this disclosure employ a second type of implanted region that partially overlaps with the gate region to provide a body contact for a second transistor and couple the source region of the second transistor to the drain region of a first transistor. Various aspects of this disclosure utilize polysilicon masking to form the body contact, which eliminates conventional body contact formation using polysilicon notches. Eliminating conventional body contact formation using polysilicon notches advantageously reduces parasitic capacitance associated with a gate length that is significantly larger than a portion of the IC device width (e.g., an average reduction of about 22%). Additionally, the elimination of polysilicon notches reduces the total area specific to the IC device (e.g., an average reduction of about 40%), for example, as... Figure 4A and Figure 4B As shown.

[0041] Figure 4AThis is a schematic diagram illustrating a layout view of a polysilicon masked implanted body source-connected (BTS) integrated circuit (IC) device 400 according to various aspects of the present disclosure. In this example, the polysilicon masked implanted BTS IC device 400 includes a semiconductor-on-insulator (SOI) substrate 402 having a first-type diffusion region 404 (e.g., P-type). The polysilicon masked implanted BTS IC device 400 also includes a first transistor 410 having a source (S) region and a drain region in the first-type diffusion region 404 of the SOI substrate 402. The first transistor 410 includes a gate (G) region between the source (S) region and the drain (D) region. In various aspects of the present disclosure, the polysilicon masked implanted BTS IC device 400 includes a first second-type implanted region 420 (e.g., N-type) that partially overlaps with the gate (G) region and the source (S) region in the first-type diffusion region 404 to couple the body region of the first transistor 410 to the source (S) region.

[0042] like Figure 4A As shown, the polysilicon masked implanted BTS IC device 400 further includes a second transistor 412 having a source (S) region and a drain (D) region in a first-type diffusion region 404 of the SOI substrate 402. The second transistor 412 includes a gate (G) region between the source (S) region and the drain (D) region. In various aspects of this disclosure, the polysilicon masked implanted BTS IC device 400 includes a second second-type implantation region 422 (e.g., N-type) that partially overlaps with the gate (G) region and source (S) region in the first-type diffusion region 404 to couple the body region of the second transistor 412 to the source (S) region. In various aspects of this disclosure, the second second-type implantation region 422 provides a series connection between the first transistor 410 and the second transistor 412 by sharing a drain / source (D / S) region. In various aspects of this disclosure, the drain (D) of the first transistor 410 is merged with the source (S) of the second transistor 412 to create a series configuration of the first transistor 410 and the second transistor 412, thereby achieving low resistance, improved area, and improved capacitance.

[0043] Figure 4A Further examples include a first type 1 implantation region 470 and a second type 1 implantation region 472, which overlap with a shallow trench isolation (STI) region, a second type diffusion region 464, and the gate regions of a third transistor and a fourth transistor, the third transistor and the fourth transistor having polarities opposite to those of the first transistor 410 and the second transistor 412.

[0044] Figure 4B This illustrates various aspects of this disclosure. Figure 4AThis is a schematic diagram of an exploded view 450 of a polysilicon masked implanted BTS IC device 400. The same reference numerals are used to indicate the exploded view 450 of the polysilicon masked implanted BTS IC device 400. Figure 4B As shown, the series connection of the first transistor 410 and the second transistor 412 using the first second type implantation region 420, the second second type implantation region 422 and the common drain / source (D / S) region resembles a mesh pattern.

[0045] Figure 5A and Figure 5B The schematic diagrams based on various aspects of this disclosure further illustrate... Figure 4A and Figure 4B The diagram shows the tangent aa' of the polysilicon masked implanted BTS IC device 400, along with the corresponding layout view 520 and cross-sectional view 550. Figure 5A Layout view 520 shows a tangent aa' through the first transistor 410 and the second transistor 412, as well as the first second-type implantation region 420 and the second second-type implantation region 422 (which are shown within the standard cell 500). In this example, the first second-type implantation region 420 is provided near the edge of the first transistor 410 to partially overlap with the gate (G) region and the source (S) region to provide a body contact shorted to the source region and a body connection to the body region of the channel below the gate of the gate (G) region.

[0046] Additionally, a second type II implantation region 422 is provided near the edge of the second transistor 412 to partially overlap with the gate (G) region and the source (S) region, providing a body connection to the body region of the short-circuit to the source (S) region and to the channel below the gate of the gate (G) region of the second transistor 412. In this example of series-connected transistors, the source of the second transistor 412 is shared with the drain of the first transistor 410. Cross-sectional view 550 further illustrates this. Figure 5B The first type II implantation region 420 near the edge of the first transistor 410 and the second type II implantation region 422 near the edge of the second transistor 412.

[0047] Figure 5B This is an example of aspects according to this disclosure. Figure 5A The layout view shows a schematic cross-sectional view 550 of the first transistor 410 and the second transistor 412 of the polysilicon masked implanted BTSIC device 400. (See diagram 550 for details.) Figure 5BAs shown, a cross-sectional view 550 of a polysilicon-masked implanted BTS IC device 400 along tangent aa' is illustrated. In this example, an SOI substrate 402 is shown, which includes a silicon layer 401 supporting a buried oxide (BOX) layer 403. In various aspects of this disclosure, a first second-type implantation region 420 is shown as an N+ implantation region formed on the surface of the BOX layer 403 and adjacent to a device channel well 430 (e.g., an N-well) of the gate (G) region of a first transistor 410.

[0048] In various aspects of this disclosure, the second type II implantation region 422 is also shown as an N+ implantation region formed on the surface of the BOX layer 403 and adjacent to the device channel well 432 (e.g., an N-well) of the gate (G) region of the second transistor 412. Figure 5B As shown, the second type implantation region 422 partially overlaps with the gate (G) region and source (S) region in the first type diffusion region 404 to couple the body region of the second transistor 412 to the source (S) region of the second transistor 412. Figure 5B As shown, the source of the second transistor 412 is shared with the drain of the first transistor 410. In various aspects of this disclosure, a second type II implantation region 422 provides a series connection between the first transistor 410 and the second transistor 412 by sharing a drain / source (D / S) region. This gate-masking implantation technique advantageously defines the body structure along the width of the gate (G) region. Maintaining the same gate length (Lg) across the entire width of the gate (G) region is beneficial for reducing capacitance with respect to the process or recording (POR) device. Specifically, eliminating the gate notch in the POR device structure results in a significant reduction in capacitance (e.g., approximately 22%).

[0049] Figure 6 This is a schematic diagram illustrating a layout view of a masked implanted body source-connected (BTS) transistor device 600 according to various aspects of this disclosure. Figure 6 As shown, the masked implanted BTS transistor device 600 includes a P-type region 610 (e.g., a P-type metal-oxide-semiconductor (PMOS) region) and an N-type region 660 (e.g., an N-type metal-oxide-semiconductor (NMOS) region). In this example, the P-type region 610 includes a first second-type implantation region 620 and a second second-type implantation region 622, as shown in the P-type region 610. Additionally, a first first-type implantation region 670 and a second first-type implantation region 672 are shown to overlap with a second-type diffusion region 664 of the N-type region 660 and a shallow trench isolation (STI) region between the N-type region 660 and the P-type region 610.

[0050] In various aspects of this disclosure, the first second-type implantation region 620 and the second second-type implantation region 622, as well as the first first-type implantation region 670 and the second first-type implantation region 672, are formed to overlap in an overlap region 690. In this example, the overlap of the N+ / P+ implants (e.g., 620, 622, 670, 672) in the overlap region 690 of the STI region satisfies the mask opening area specification while providing a reduced-size body contact. Additionally, the first second-type implantation region 620 and the second second-type implantation region 622 formed in the first-type diffusion region 612 form a first mesh-frame implantation region 640 to support a body-source-connected P-type metal-oxide-semiconductor (PMOS) transistor. Similarly, the first first-type implantation region 670 is formed in the second-type diffusion region 664 and the second mesh-frame implantation region 680 is formed in the second first-type implantation region 672 to support an N-type metal-oxide-semiconductor (NMOS) transistor.

[0051] By combining the first rhomboid implantation region 640 and the second rhomboid implantation region 680 with the fully implanted overlap in the STI region (e.g., 690), a masked implanted BTS transistor device 600 with a floating (FB)-shaped polysilicon structure is formed, thereby achieving reduced capacitance, a reduced area, and a well-defined body potential. In various aspects of this disclosure, the masked implanted BTS transistor device 600 can be configured as a logic device, such as an inverter, an inverted AND (NAND) logic device, an inverted OR (NOR) logic device, or other similar logic device positioned in a standard cell size.

[0052] Figure 7 This is a schematic diagram illustrating a layout view of an integrated circuit (IC) 700 including a polysilicon masked implanted body source-connected (BTS) transistor 600 according to various aspects of this disclosure. Figure 7 As shown, IC 700 is composed of Figure 6 A shielded implanted BTS transistor device 600 is formed and described using similar reference numerals. In this example, a first set of shielded implanted BTS transistor devices 600 (600-1, 600-2, 600-3, 600-4) is coupled between a first power rail VDD1 and a ground rail VSS. Additionally, a second set of shielded implanted BTS transistor devices 600 (600-5, 600-6, 600-7, 600-8) is coupled between a second power rail VDD2 and a ground rail VSS. In various aspects of this disclosure, specific implementations of the shielded implanted BTS transistor device 600 are contained within a standard cell and are independent of rail height.

[0053] Figure 8 This is a schematic top view illustrating an aligned polysilicon masked implanted body source-connected (BTS) transistor device 800 according to various aspects of this disclosure. Figure 8 As shown, the masked implanted BTS transistor device 800 includes a first P-type transistor 810 (e.g., a P-type metal-oxide-semiconductor (PMOS) region) and a second P-type transistor 812, which are series-coupled through a common drain / source (D / S) region in a P-type diffusion region 804. The masked implanted BTS transistor device 800 also includes a first N-type transistor 860 (e.g., an N-type metal-oxide-semiconductor (NMOS) region) and a second N-type transistor 862 located in an N-type diffusion region 864, wherein the first N-type transistor and the second N-type transistor are connected in parallel.

[0054] In various aspects of this disclosure, the P-type diffusion region 804 includes a first second-type implantation region 820 and a second second-type implantation region 822, which together form a common drain / source (D / S) region of the P-type diffusion region 804. Additionally, a first first-type implantation region 870 and a second first-type implantation region 872 are shown to overlap with an N-type diffusion region 864 and a shallow trench isolation (STI) region between the P-type diffusion region 804 and the N-type diffusion region 864. Aligning the gate (G) regions of the first P-type transistor 810 and the second P-type transistor 812 with the gate (G) regions of the first N-type transistor 860 and the second N-type transistor 862 creates a specific implementation with reduced area (e.g., an area reduction of 44%), similar to a floating body (FB) device. Figure 9 Methods for constructing polysilicon masked implanted BTS integrated circuit (IC) devices according to various aspects of this disclosure are shown.

[0055] Figure 9 This is a process flowchart illustrating various aspects of the present disclosure for constructing a polysilicon masked implanted body source-to-source (BTS) integrated circuit (IC) device. Method 900 begins at block 902, wherein a first-type diffusion region is formed on a semiconductor-on-insulator (SOI) substrate. For example, as... Figure 4A As shown, the polysilicon masked implanted BTS IC device 400 includes a semiconductor-on-insulator (SOI) substrate 402 having a first-type diffusion region 404 (e.g., P-type).

[0056] At frame 904, a first type-1 transistor is formed on the first type-1 diffusion region. For example, as... Figure 4A As shown, the polysilicon masked implanted BTS IC device 400 also includes a first transistor 410 having a source (S) region and a drain region in a first-type diffusion region 404 of the SOI substrate 402. The first transistor 410 includes a gate (G) region between the source (S) region and the drain (D) region.

[0057] At block 906, a second type-1 transistor is formed on the type-1 diffusion region. For example, as... Figure 4AAs shown, the polysilicon masked implanted BTS IC device 400 also includes a second transistor 412 having a source (S) region and a drain (D) region in a first-type diffusion region 404 of the SOI substrate 402. The second transistor 412 includes a gate (G) region between the source (S) region and the drain (D) region.

[0058] At frame 908, a first and second type implantation region is formed, the first and second type implantation region including a gate overlap region that partially overlaps with the gate region of the second first type transistor to provide a body contact of the second first type transistor and to couple the source region of the second first type transistor to the drain region of the first first type transistor in series. For example, as Figure 4A As shown, the polysilicon masked implanted BTS IC device 400 includes a second type II implantation region 422 (e.g., N-type) that partially overlaps with the gate (G) region and source (S) region in the first type diffusion region 404 to couple the body region of the second transistor 412 to the source (S) region. In various aspects of this disclosure, the second type II implantation region 422 provides a series connection between the first transistor 410 and the second transistor 412 by sharing a drain / source (D / S) region. In various aspects of this disclosure, the drain (D) of the first transistor 410 is merged with the source (S) of the second transistor 412 to create a series configuration of the first transistor 410 and the second transistor 412, thereby achieving low resistance, improved area, and improved capacitance.

[0059] Figure 10 This is a block diagram illustrating an exemplary wireless communication system 1000 in which aspects of this disclosure may be advantageously employed. For illustrative purposes, Figure 10 Three remote units 1020, 1030, and 1050 and two base stations 1040 are shown. It should be understood that the wireless communication system may have more remote units and base stations. Remote units 1020, 1030, and 1050 include IC devices 1025A, 1025C, and 1025B, which include the disclosed polysilicon masked implant body source-connected devices. It will be appreciated that other devices may also include the disclosed polysilicon masked implant body source-connected devices, such as base stations, handover devices, and network devices. Figure 10 The forward link signal 1080 from base station 1040 to remote units 1020, 1030 and 1050 and the reverse link signal 1090 from remote units 1020, 1030 and 1050 to base station 1040 are shown.

[0060] exist Figure 10In the diagram, remote unit 1020 is shown as a mobile phone, remote unit 1030 is shown as a portable computer, and remote unit 1050 is shown as a fixed-location remote unit in a wireless local loop system. For example, a remote unit can be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit (such as a personal digital assistant (PDA)), a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed-location data unit (such as a meter reading device), or other communication devices that store or retrieve data or computer instructions, or combinations thereof. Figure 10 Remote units according to aspects of this disclosure are illustrated, but this disclosure is not limited to such exemplary units. Aspects of this disclosure can be suitably used in a variety of devices, including the disclosed polysilicon masked implant body source interconnect device.

[0061] Figure 11 This is a block diagram illustrating a design workstation for circuit, layout, and logic design of semiconductor components, such as the switching field-effect transistor (FET) and polysilicon masked implant-body source-connected device disclosed above. Design workstation 1100 includes a hard disk 1101 containing operating system software, support files, and design software (such as Cadence or OrCAD). Design workstation 1100 also includes an indicator 1102 to facilitate circuit design 1110 or IC 1112. Storage medium 1104 is provided for tangibly storing circuit design 1110 or IC 1112. Circuit design 1110 or IC 1112 can be stored on storage medium 1104 in file formats such as GDSII or GERBER. Storage medium 1104 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, design workstation 1100 includes a drive device 1103 for accepting input from storage medium 1104 or writing output to storage medium 1104.

[0062] Data recorded on storage medium 1104 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial writing tools such as electron beam lithography. Data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulations. Providing data on storage medium 1104 facilitates the design of circuit design 1110 or IC 1112 by reducing the number of processes used to design semiconductor wafers.

[0063] Specific implementation examples are described in the following numbered clauses:

[0064] 1. An integrated circuit (IC) device, the integrated circuit (IC) device comprising:

[0065] A semiconductor-on-insulator (SOI) substrate having a first-type diffusion region;

[0066] A first type transistor, wherein the first type transistor is located on a first type diffusion region;

[0067] A second first-type transistor, the second first-type transistor being located on the first-type diffusion region; and

[0068] A first and second type implantation region, the first and second type implantation region including a gate overlap region that partially overlaps with the gate region of the second first type transistor, to provide a body contact of the second first type transistor and to couple the source region of the second first type transistor to the drain region of the first first type transistor in series.

[0069] 2. The IC device according to Clause 1, the IC device further comprising a first second-type transistor, the first second-type transistor being located on a second-type diffusion region of the SOI substrate and having a gate region aligned with the gate region of the first first-type transistor.

[0070] 3. The IC device according to Clause 2, wherein the first second-type transistor comprises an N-type metal-oxide-semiconductor (NMOS) transistor, and the first first-type transistor comprises a P-type metal-oxide-semiconductor (PMOS) transistor.

[0071] 4. The IC device according to Clause 2 or Clause 3, wherein the SOI substrate includes a shallow trench isolation (STI) region located between the first type diffusion region and the second type diffusion region.

[0072] 5. The IC device according to any one of Clauses 2 to 4, wherein the first second type transistor includes a first type implantation region, the first type implantation region including a gate overlap region that partially overlaps with the gate region of the first second type transistor to provide a body contact of the first second type transistor.

[0073] 6. The IC device according to any one of Clauses 2 to 5, the IC device further comprising a second type II transistor, the second type II transistor being located on a type II diffusion region of the SOI substrate and having a gate region aligned with the gate region of the second type I transistor.

[0074] 7. The IC device according to any one of Clauses 1 to 6, wherein the first type diffusion region includes a P+ diffusion region.

[0075] 8. The IC device according to any one of Clauses 1 to 7, wherein the second type implantation region includes the N+ implantation region.

[0076] 9. The IC device according to any one of Clauses 1 to 8, wherein the IC device includes a logic device.

[0077] 10. The IC device according to Clause 9, wherein the logic device is integrated into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

[0078] 11. A method for constructing a polysilicon masked implanted body source-to-spot (BTS) integrated circuit (IC) device, the method comprising:

[0079] A type-1 diffusion region is formed on a semiconductor-on-insulator (SOI) substrate;

[0080] A first type-1 transistor is formed on the first type-1 diffusion region;

[0081] A second first-type transistor is formed on the first-type diffusion region; and

[0082] A first and second type implantation region is formed, the first and second type implantation region including a gate overlap region that partially overlaps with the gate region of the second first type transistor to provide a body contact of the second first type transistor and to couple the source region of the second first type transistor to the drain region of the first first type transistor in series.

[0083] 12. The method according to Clause 11, the method further comprising forming a first second-type transistor located on a second-type diffusion region of the SOI substrate and having a gate region aligned with the gate region of the first first-type transistor.

[0084] 13. The method according to Clause 12, wherein the first second-type transistor comprises an N-type metal-oxide-semiconductor (NMOS) transistor, and the first first-type transistor comprises a P-type metal-oxide-semiconductor (PMOS) transistor.

[0085] 14. The method according to Clause 12 or Clause 13, wherein the SOI substrate includes a shallow trench isolation (STI) region located between the first type diffusion region and the second type diffusion region.

[0086] 15. The method according to any one of Clauses 12 to 14, wherein the first second-type transistor includes a first-type implantation region, the first-type implantation region including a gate overlap region that partially overlaps with the gate region of the first second-type transistor to provide a body contact of the first second-type transistor.

[0087] 16. The method according to any one of clauses 12 to 15, the method further comprising forming a second type-two transistor located on a type-two diffusion region of the SOI substrate and having a gate region aligned with the gate region of the second type-two transistor.

[0088] 17. The method according to any one of Clauses 11 to 16, wherein the first type diffusion region includes a P+ diffusion region.

[0089] 18. The method according to any one of Clauses 11 to 17, wherein the second type of implantation area includes the N+ implantation area.

[0090] 19. The method according to any one of Clauses 11 to 18, wherein the polysilicon masked implanted BTS IC device includes a logic device.

[0091] 20. The method according to Clause 19, further comprising integrating the logic device into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

[0092] For firmware and / or software implementations, these methods can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media that tangibly embody instructions can be used to implement the methods described herein. For example, software code can be stored in memory and executed by a processor unit. Memory can be implemented within or outside the processor unit. As used herein, the term "memory" refers to any type of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to a particular type of memory or a particular number of memories, or the type of medium for storing information in memory.

[0093] If implemented in firmware and / or software, functionality may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoding data structures and computer-readable media encoding computer programs. Computer-readable media include physical computer storage media. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disks and optical discs include compact optical discs (CDs), laser optical discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs utilize lasers to optically reproduce data. Combinations of the above should also be included within the scope of computer-readable media.

[0094] In addition to being stored on a computer-readable medium, instructions and / or data may also be provided as signals included on a transmission medium in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicating instructions and data. These instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0095] Although this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the technology of this disclosure as defined in the appended claims. For example, relational terms such as “above” and “below” are used for substrates or electronic devices. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Additionally, if it is laterally oriented, above and below may refer to the sides of the substrate or electronic device. Furthermore, the scope of this application is not intended to be limited to the specific configurations of the processes, machines, manufactures, and material compositions, components, methods, and steps described in the specification. As will be readily understood by those skilled in the art from this disclosure, processes, machines, manufactures, material compositions, components, methods, or steps that currently exist or will be developed later can be utilized to perform the same function or achieve the same result as the corresponding configuration described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

Claims

1. An integrated circuit (IC) device, the integrated circuit (IC) device comprising: A semiconductor-on-insulator (SOI) substrate having a first-type diffusion region; A first type transistor, wherein the first type transistor is located on a first type diffusion region; A second first-type transistor, the second first-type transistor being located on the first-type diffusion region; and A first and second type implantation region, the first and second type implantation region including a gate overlap region that partially overlaps with the gate region of the second first type transistor, to provide a body contact of the second first type transistor and to couple the source region of the second first type transistor to the drain region of the first first type transistor in series.

2. The IC device of claim 1, further comprising a first second-type transistor, the first second-type transistor being located on a second-type diffusion region of the SOI substrate and having a gate region aligned with the gate region of the first first-type transistor.

3. The IC device of claim 2, wherein the first second-type transistor comprises an N-type metal-oxide-semiconductor (NMOS) transistor, and the first first-type transistor comprises a P-type metal-oxide-semiconductor (PMOS) transistor.

4. The IC device of claim 2, wherein the SOI substrate includes a shallow trench isolation (STI) region located between the first type diffusion region and the second type diffusion region.

5. The IC device of claim 2, wherein the first second-type transistor includes a first-type implantation region, the first-type implantation region including a gate overlap region that partially overlaps with the gate region of the first second-type transistor to provide a body contact of the first second-type transistor.

6. The IC device of claim 2, further comprising a second type II transistor, the second type II transistor being located on a type II diffusion region of the SOI substrate and having a gate region aligned with the gate region of the second type I transistor.

7. The IC device according to claim 1, wherein the first type of diffusion region includes a P+ diffusion region.

8. The IC device of claim 1, wherein the second type of implantation region includes an N+ implantation region.

9. The IC device according to claim 1, wherein the IC device includes a logic device.

10. The IC device of claim 9, wherein the logic device is integrated into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

11. A method for constructing a polysilicon masked implanted body source-to-spot (BTS) integrated circuit (IC) device, the method comprising: A type-1 diffusion region is formed on a semiconductor-on-insulator (SOI) substrate; A first type-1 transistor is formed on the first type-1 diffusion region; A second first-type transistor is formed on the first-type diffusion region; as well as A first and second type implantation region is formed, the first and second type implantation region including a gate overlap region that partially overlaps with the gate region of the second first type transistor to provide a body contact of the second first type transistor and to couple the source region of the second first type transistor to the drain region of the first first type transistor in series.

12. The method of claim 11, further comprising forming a first second-type transistor located on a second-type diffusion region of the SOI substrate and having a gate region aligned with the gate region of the first first-type transistor.

13. The method of claim 12, wherein the first second-type transistor comprises an N-type metal-oxide-semiconductor (NMOS) transistor, and the first first-type transistor comprises a P-type metal-oxide-semiconductor (PMOS) transistor.

14. The method of claim 12, wherein the SOI substrate includes a shallow trench isolation (STI) region located between the first type diffusion region and the second type diffusion region.

15. The method of claim 12, wherein the first second-type transistor includes a first-type implantation region, the first-type implantation region including a gate overlap region that partially overlaps with the gate region of the first second-type transistor to provide a body contact of the first second-type transistor.

16. The method of claim 12, further comprising forming a second type-two transistor located on a type-two diffusion region of the SOI substrate and having a gate region aligned with the gate region of the second type-two transistor.

17. The method of claim 11, wherein the first type of diffusion region comprises a P+ diffusion region.

18. The method of claim 11, wherein the second type of implantation region includes an N+ implantation region.

19. The method of claim 11, wherein the polysilicon masked implanted BTS IC device includes a logic device.

20. The method of claim 19, further comprising integrating the logic device into at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

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