Package including substrate having interconnect blocks

Abstract

A substrate, the substrate comprising: a core layer; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; a plurality of interconnects at least partially located in the at least one first dielectric layer; a region including a plurality of block interconnects interconnecting the blocks; and a solder resist layer coupled to the at least one first dielectric layer.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to U.S. Nonprovisional Application Serial No. 18 / 470,148, filed September 19, 2023, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0002] Various features are involved in the package and substrate. Background Technology

[0003] The package may include a substrate and an integrated device. The substrate may include multiple interconnects. The integrated device may be coupled to the interconnects of the substrate. There is a ongoing need to improve the electrical connectivity of the integrated device through the substrate, while also providing a smaller package with improved performance. Summary of the Invention

[0004] Various features are involved in the package and substrate.

[0005] One example provides a substrate comprising: a core layer; at least one first dielectric layer coupled to a first surface of the core layer; at least one second dielectric layer coupled to a second surface of the core layer; a plurality of interconnects at least partially located in the at least one first dielectric layer; a region comprising a plurality of block interconnects of interconnect blocks; and a solder resist layer coupled to the at least one first dielectric layer.

[0006] Another example provides a package comprising: a substrate; a first integrated device coupled to the substrate via a first plurality of bump interconnects; and a second integrated device coupled to the substrate via a second plurality of bump interconnects. The substrate includes: a core layer; at least one first dielectric layer coupled to a first surface of the core layer; at least one second dielectric layer coupled to a second surface of the core layer; a plurality of interconnects at least partially located within the at least one first dielectric layer; a region comprising a plurality of block interconnects of interconnect blocks; and a solder resist layer coupled to the at least one first dielectric layer.

[0007] Another example provides a method for manufacturing a substrate. The method provides a core layer. The method forms at least one first dielectric layer coupled to a first surface of the core layer. The method forms at least one second dielectric layer coupled to a second surface of the core layer. The method forms a plurality of interconnects at least partially located within the at least one first dielectric layer. The method couples an interconnect block comprising a plurality of block interconnects to the at least one first dielectric layer. The method forms an additional first dielectric layer around and over the interconnect block. The method forms a solder resist layer coupled to the at least one first dielectric layer. Attached Figure Description

[0008] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0009] Figure 1 An exemplary cross-sectional view of a substrate having interconnect blocks is shown.

[0010] Figure 2 An exemplary cross-sectional view of a package including integrated devices and a substrate having interconnect blocks is shown.

[0011] Figure 3 A close-up view of an example of a package including integrated devices and a substrate with interconnect blocks is shown.

[0012] Figure 4 A close-up view of an example of a package including integrated devices and a substrate with interconnect blocks is shown, illustrating exemplary electrical paths.

[0013] Figures 5A to 5G An exemplary process for manufacturing a substrate having interconnect blocks is illustrated.

[0014] Figure 6 An exemplary process for manufacturing a substrate having interconnect blocks is illustrated.

[0015] Figures 7A to 7C An exemplary process for manufacturing interconnect blocks is illustrated.

[0016] Figure 8 An exemplary process for manufacturing interconnect blocks is illustrated.

[0017] Figure 9 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0018] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0019] This disclosure describes a package comprising: a substrate; a first integrated device coupled to the substrate via a first plurality of bump interconnects; and a second integrated device coupled to the substrate via a second plurality of bump interconnects. The substrate includes: a core layer; at least one first dielectric layer coupled to a first surface of the core layer; at least one second dielectric layer coupled to a second surface of the core layer; a plurality of interconnects at least partially located within the at least one first dielectric layer; a region including a plurality of block interconnects of interconnect blocks; and a solder resist layer coupled to the at least one first dielectric layer.

[0020] Exemplary package having a substrate including interconnect blocks Figure 1 A cross-sectional view of a substrate 100 including interconnect blocks is illustrated. The substrate 100 may be part of a package including integrated devices. The substrate 100 includes a core layer 101, dielectric layers 102a, 102b, 103a, 103b, 104a, 104b, solder mask layers 107 and 109, interconnect blocks 110, a plurality of via interconnects 114, a plurality of interconnects 132, a plurality of interconnects 142, and a plurality of interconnects 152. The interconnect blocks 110 may include at least one block dielectric layer 112 and a plurality of block interconnects 113. The interconnect blocks 110 may be at least partially embedded in the substrate 100. The interconnect blocks 110 may be at least partially located in dielectric layers 102a, 103a, and / or 104a. The substrate 100 includes a region 108 (e.g., an interconnect block region, a bridging region) that includes interconnect block 110 or components of interconnect block 110. Region 108 may include interconnect block 110 and a plurality of interconnects 152. Region 108 may include a portion of dielectric layer 104a (e.g., a portion of dielectric layer 104a above interconnect block 110). As will be further described below, in some embodiments, the dielectric layer of interconnect block 110 may be indistinguishable from dielectric layer 104a, dielectric layer 103a, and / or dielectric layer 102a.

[0021] Multiple via interconnects 114 may be located in the core layer 101. The multiple via interconnects 114 may extend through the core layer 101. Different embodiments may use different types of via interconnects. In some embodiments, the multiple via interconnects extending through the core layer 101 may have via walls and multiple fillers located within the via walls. In some embodiments, a portion of the wall of the via interconnect may be tapered (e.g., may have diagonal walls).

[0022] Dielectric layer 102a is coupled to a first surface (e.g., top surface) of core layer 101. Dielectric layer 103a is coupled to dielectric layer 102a. Interconnect block 110 is coupled to dielectric layer 103a. Dielectric layer 104a is coupled to dielectric layer 103a and interconnect block 110. A plurality of interconnects 132 are located at least in dielectric layers 102a, 103a, and / or 104a. A plurality of interconnects 132 are coupled to a plurality of via interconnects 114. A plurality of via interconnects 152 are located at least partially in dielectric layer 104a. A plurality of interconnects 152 are coupled to a plurality of block interconnects 113. A plurality of interconnects 152 may be coupled to a plurality of interconnects 132. In some specific embodiments, a plurality of interconnects 152 may be considered as part of a plurality of interconnects 132. A plurality of interconnects 152 are located above interconnect block 110. Solder mask layer 107 is located above the surface of dielectric layer 104a. The solder mask 107 may have different portions with different thicknesses. For example, a first portion of the solder mask 107 that does not vertically overlap with the interconnect block 110 may have a first thickness, and a second portion of the solder mask 107 that vertically overlaps with the interconnect block 110 may have a second thickness less than the first thickness. Therefore, despite the presence of interconnect blocks 110 with increased thickness of the dielectric layer above the core layer 101, the overall thickness of the substrate 100 is kept relatively constant by using a variable thickness for the solder mask 107. Thus, for example, although the thickness of the dielectric layer increases and the number of metal layers increases, the thickness of the solder mask 107 does not increase. As will be further described below, the interconnect block 110 may be configured as a bridge to provide an electrical path between two or more integrated devices.

[0023] Dielectric layer 102b is coupled to a second surface (e.g., bottom surface) of core layer 101. Dielectric layer 103b is coupled to dielectric layer 102b. Dielectric layer 104b is coupled to dielectric layer 103b. A plurality of interconnects 142 are located at least in dielectric layers 102b, 103b, and / or 104b. The plurality of interconnects 142 are coupled to a plurality of via interconnects 114. Solder mask layer 109 is located above the surface (e.g., bottom surface) of dielectric layer 104b.

[0024] Multiple via interconnects 114 extend through the core layer 101. Multiple fillers 116 may be located within the multiple via interconnects 114. A dielectric layer 102 is coupled to a first surface (e.g., top surface) and a second surface (e.g., bottom surface) of the core layer 101. The dielectric layer 102 may comprise a different material than the core layer 101.

[0025] Different embodiments may use different materials for dielectric layers 102a, 102b, 103a, 103b, 104a, and / or 104b. In some embodiments, dielectric layers 102a, 102b, 103a, 103b, 104a, and / or 104b may include prepreg and / or Ajinomoto laminate (ABF). In some embodiments, dielectric layers 102a, 102b, 103a, 103b, 104a, and / or 104b may include polymers. Dielectric layers 102a, 102b, 103a, 103b, 104a and / or 104b may include dielectrics of a different type than the core layer 101.

[0026] The dielectric layer 104a may be formed in a stepped shape above the interconnect block 110. For example, the dielectric layer 104a may have (i) a first horizontal surface that is generally parallel to the surface of the core layer 101, and (ii) a second horizontal surface that is generally parallel to the same surface of the core layer 101, wherein the distance between the second horizontal surface of the dielectric layer 104a and the first surface of the core layer 101 is greater than the distance between the first horizontal surface of the dielectric layer 104a and the first surface of the core layer. The first horizontal surface of the dielectric layer 104a may be a surface that does not vertically overlap with the interconnect block 110, and the second horizontal surface of the dielectric layer 104a may be a surface that vertically overlaps with the interconnect block 110.

[0027] The solder mask 107 may include a first horizontal surface that is generally parallel to the surface of the core layer 101. Although the dielectric layer 104a has a stepped shape, the solder mask 107 may have a first horizontal surface that is generally parallel to the first surface of the core layer 101, wherein the distance between a portion of the first horizontal surface of the solder mask 107 (the portion that does not vertically overlap with the interconnect block 110) and the first surface of the core layer 101 is approximately the same as the distance between another portion of the first horizontal surface of the solder mask 107 (the portion that vertically overlaps with the interconnect block 110) and the first surface of the core layer. This configuration and / or structure can provide an efficient path for device-to-device connectivity while still maintaining a relatively thin overall package thickness.

[0028] Figure 2An example is illustrated of a package 200 including a substrate comprising interconnect blocks. Package 200 includes a substrate 100, an integrated device 202, and an integrated device 204. The substrate 100 may include, for example: Figure 1 Interconnect block 110 is described. Integrated device 202 is coupled to substrate 100 via a plurality of bump interconnects. Integrated device 204 is coupled to substrate 100 via a plurality of bump interconnects.

[0029] Figure 3 A close-up view of a package 200 including a substrate comprising interconnect blocks is shown. As mentioned above, the package 200 includes a substrate 100, an integrated device 202, and an integrated device 204. The substrate 100 includes interconnect blocks 110.

[0030] Integrated device 202 is coupled to substrate 100 via a plurality of bump interconnects 220. The plurality of bump interconnects 220 may include a plurality of pillar interconnects 222 and / or a plurality of solder interconnects 224. Integrated device 202 may be coupled to a plurality of interconnects 132 and / or a plurality of interconnects 152 via the plurality of bump interconnects 220. The plurality of pillar interconnects 222 may be coupled to integrated device 202 (e.g., pad interconnects of integrated device 204). The plurality of solder interconnects 224 may be coupled to the plurality of pillar interconnects 222. In some embodiments, the plurality of pillar interconnects 222 and / or the plurality of solder interconnects 224 may be considered part of integrated device 202. The plurality of solder interconnects 224 may be coupled to the plurality of interconnects 132 and / or the plurality of interconnects 152. The plurality of solder interconnects 224 may include a plurality of solder interconnects 224a and / or a plurality of solder interconnects 224b. In some embodiments, the plurality of pillar interconnects 222 may not be present. Therefore, multiple solder interconnects 224 can be coupled to the pad interconnects of the integrated device 202.

[0031] Integrated device 204 is coupled to substrate 100 via a plurality of bump interconnects 240. The plurality of bump interconnects 240 may include a plurality of pillar interconnects 242 and / or a plurality of solder interconnects 244. Integrated device 204 may be coupled to a plurality of interconnects 132 and / or a plurality of interconnects 152 via the plurality of bump interconnects 240. The plurality of pillar interconnects 242 may be coupled to integrated device 204 (e.g., pad interconnects of integrated device 204). The plurality of solder interconnects 244 may be coupled to the plurality of pillar interconnects 242. In some embodiments, the plurality of pillar interconnects 242 and / or the plurality of solder interconnects 244 may be considered part of integrated device 204. The plurality of solder interconnects 244 may be coupled to the plurality of interconnects 132 and / or the plurality of interconnects 152. The plurality of solder interconnects 224 may include a plurality of solder interconnects 244a and / or a plurality of solder interconnects 244b. In some embodiments, the plurality of pillar interconnects 242 may not be present. Therefore, multiple solder interconnects 244 can be coupled to the pad interconnects of the integrated device 204.

[0032] Figure 3 An example is shown where the depth of an opening in the solder mask 107 above interconnect block 110 is less than the depth of an opening in the solder mask 107 not above interconnect block 110. The opening in the solder mask 107 exposes pad interconnects from a plurality of interconnects 132 and / or pad interconnects from a plurality of interconnects 152. These pad interconnects couple to and contact a plurality of solder interconnects 224 and / or a plurality of solder interconnects 244.

[0033] As will be further described below, integrated device 202 and integrated device 204 may be configured to be electrically coupled to each other via substrate 100 and interconnect block 110. Interconnect block 110 includes at least one block dielectric layer 112 and a plurality of block interconnects 113. The plurality of block interconnects 113 may include block via interconnects, block pad interconnects, and / or block trace interconnects. In some embodiments, the plurality of block interconnects 113 may have a minimum width, minimum spacing, minimum pitch, and / or minimum thickness that is less than the minimum width, minimum spacing, minimum pitch, and / or minimum thickness of the interconnects from the plurality of interconnects 132. For example, in some embodiments, the block trace interconnects and / or block pad interconnects from the plurality of block interconnects 113 may have a block thickness that is less than the thickness of the pad interconnects and / or trace interconnects from the plurality of interconnects 132. In some embodiments, some block pad interconnects and / or block trace interconnects may be located on the same horizontal plane (e.g., an imaginary horizontal plane) and / or share the same horizontal plane as the via interconnects from the plurality of interconnects 132. In some embodiments, solder interconnects from the plurality of solder interconnects 224 and / or solder interconnects from the plurality of solder interconnects 244 may be located on the same horizontal plane (e.g., an imaginary horizontal plane) as the dielectric layer 104a and the interconnects from the plurality of interconnects 152 and / or share the same horizontal plane. For example, solder interconnects from the plurality of solder interconnects 224 may be located on the same horizontal plane (e.g., an imaginary horizontal plane) and / or share the same horizontal plane as the via interconnects and / or pad interconnects from the plurality of interconnects 152.

[0034] Figure 3Examples illustrate some pad interconnects (from multiple interconnects 152) coupled to multiple solder interconnects (e.g., 224b, 244b) and some pad interconnects (from multiple interconnects 132) coupled to multiple solder interconnects (e.g., 224a, 244a) located on different metal layers. The pad interconnects (from multiple interconnects 152) coupled to the multiple solder interconnects (e.g., 224b, 244b) are located at a distance D1 from a first surface of the core layer. The pad interconnects (from multiple interconnects 132) coupled to the multiple solder interconnects (e.g., 224a, 244a) are located at a distance D2 from the first surface of the core layer, where distance D1 is greater than distance D2. In some embodiments, the size of the multiple solder interconnects (e.g., 224b, 244b) is smaller than the size of the multiple solder interconnects (e.g., 224a, 244a).

[0035] Therefore, in some specific implementations, the interconnect block may include a first interconnect on a first metal layer and a second interconnect on a second metal layer, wherein the first interconnect and / or the second interconnect are laterally located on the same plane (e.g., an imaginary horizontal plane) as the via interconnects from the plurality of interconnects and / or share the same plane.

[0036] In some specific implementations, the first surface of at least one first dielectric layer located above the interconnect block is a first distance from the surface of the core layer, and the second surface of at least one first dielectric layer not located above the interconnect block is a second distance from the surface of the core layer, wherein the first distance is greater than the second distance.

[0037] In some embodiments, the minimum width, minimum spacing, minimum pitch, and / or minimum thickness of the plurality of interconnects 152 may be less than the minimum width, minimum spacing, minimum pitch, and / or minimum thickness of the interconnects from the plurality of interconnects 132. For example, in some embodiments, the block trace interconnects and / or block pad interconnects from the plurality of interconnects 152 may have a block thickness less than the thickness of the pad interconnects and / or trace interconnects from the plurality of interconnects 132.

[0038] In some embodiments, the block dielectric layer 112 may be considered part of dielectric layers 104a, 103a, and / or 102a. This may be the case when the block dielectric layer 112 and dielectric layers 104a, 103a, and / or 102a comprise the same material. In some embodiments, the block dielectric layer 112 of the interconnect block 110 may be indistinguishable from one or more of the dielectric layers of the substrate 100 (e.g., dielectric layers 104a, 103a, and / or 102a). For example, there may be no boundary interface between the block dielectric layer 112 and dielectric layers 104a and / or 103a. In some embodiments, the interconnect block 110 may be a structure and / or configuration comprising a plurality of block interconnects, wherein the block dielectric layer 112 may be a dielectric layer considered part of the substrate 100. In some specific embodiments, block dielectric layer 112 may be considered separate from dielectric layers 104a, 103a, and / or 102a (e.g., a boundary interface may exist between block dielectric layer 112 and dielectric layer 104a). Block dielectric layer 112 may comprise the same material as or a different material from dielectric layers 104a, 103a, and / or 102a. As used herein, interconnect blocks may represent one or more components, structures of various components, and / or structural configurations.

[0039] When the overall thickness of substrate 100 includes the thickness of solder mask 107 and / or solder mask 109, the use of interconnect blocks 110 provides an efficient structure for providing high-density electrical paths between integrated devices without increasing the overall thickness of substrate 100. Interconnect blocks 110 can be a progressively rising interconnect structure that is at least partially embedded in and / or at least partially located within substrate 100. Furthermore, interconnect blocks 110 enable high-density interconnects to be located in spaces and regions that would otherwise be impossible.

[0040] Table 1 below illustrates exemplary minimum dimensions for various components of the package.

[0041] Table 1 – Exemplary Minimum Sizes The dimensions of the various components listed above are merely exemplary minimum dimensions. In some specific implementations, the dimensions may be different from and / or larger than the listed minimum dimensions. In some specific implementations, the minimum dimensions may be different sizes, including smaller sizes.

[0042] Figure 4 A close-up view of a package 200 including a substrate 100 comprising interconnect blocks 110 is shown, illustrating possible electrical paths. Figure 4The substrate 100 is illustrated to include at least one dielectric layer 430 and an interconnect block 110. The at least one dielectric layer 430 may represent dielectric layer 102a, dielectric layer 103a, and / or dielectric layer 104a. The interconnect block 110 is at least partially located within the at least one dielectric layer 430. Figure 4 Electrical paths 401, 403, and 405 are illustrated. Electrical paths 401, 403, and / or 405 can be configured as electrical paths for input / output signals between integrated devices.

[0043] Electrical path 401 may be an electrical path between integrated device 202 and integrated device 204. Electrical path 401 may include (i) pillar interconnects from a plurality of pillar interconnects 222, (ii) solder interconnects from a plurality of solder interconnects 224, (iii) at least one interconnect from a plurality of interconnects 152, (iv) solder interconnects from a plurality of solder interconnects 244 and / or (v) pillar interconnects from a plurality of pillar interconnects 242.

[0044] Electrical path 403 may be an electrical path between integrated device 202 and integrated device 204. Electrical path 401 may include (i) pillar interconnects from a plurality of pillar interconnects 222, (ii) solder interconnects from a plurality of solder interconnects 224, (iii) at least one interconnect from a plurality of interconnects 152, (iv) at least one block interconnect from a plurality of block interconnects 113, (v) at least one other interconnect from a plurality of interconnects 152, (vi) solder interconnects from a plurality of solder interconnects 244 and / or (vii) pillar interconnects from a plurality of pillar interconnects 242.

[0045] Electrical path 405 may be an electrical path between integrated device 202 and integrated device 204. Electrical path 401 may include (i) pillar interconnects from a plurality of pillar interconnects 222, (ii) solder interconnects from a plurality of solder interconnects 224, (iii) at least one interconnect from a plurality of interconnects 152, (iv) at least one block interconnect from a plurality of block interconnects 113, (v) at least one other interconnect from a plurality of interconnects 152, (vi) solder interconnects from a plurality of solder interconnects 244, and / or (vii) pillar interconnects from a plurality of pillar interconnects 242. In some specific embodiments, electrical path 405 may differ from electrical path 403 because the electrical path may pass through different metal layers of interconnect block 110.

[0046] Figure 4An example is illustrated where solder interconnect 224b is coupled to a specific pad interconnect from a plurality of interconnects 152, wherein the specific pad interconnect may be located on the same horizontal plane (e.g., an imaginary horizontal plane) as solder interconnect 224a and / or share that same horizontal plane. Solder interconnects 224a and 224b are coupled to corresponding pad interconnects on different metal layers of substrate 100. Solder interconnect 224a is coupled to pad interconnects from a plurality of interconnects 132. Solder interconnect 224a may be located on the same horizontal plane (e.g., an imaginary horizontal plane) as the via interconnects of the plurality of interconnects 152 and / or share that same horizontal plane.

[0047] Figure 4 Also illustrated is a solder interconnect 244b coupled to a specific pad interconnect from a plurality of interconnects 152, wherein the specific pad interconnect may be located on the same horizontal plane (e.g., an imaginary horizontal plane) as solder interconnect 244a and / or share that same horizontal plane. Solder interconnects 244a and 244b are coupled to corresponding pad interconnects on different metal layers of the substrate 100. Solder interconnect 244a is coupled to pad interconnects from a plurality of interconnects 132. Solder interconnect 244a may be located on the same horizontal plane (e.g., an imaginary horizontal plane) as the via interconnects of the plurality of interconnects 152 and / or share that same horizontal plane.

[0048] Integrated devices may include dies (e.g., semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors, and / or combinations thereof. Integrated devices may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include transistors. Integrated devices may be examples of electronic components and / or electronic devices. In some specific implementations, integrated devices may include chiplets. Chipslets can be manufactured using processes that provide better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some implementations, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Using several chiplets that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package.

[0049] As mentioned above, in some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, the same technology node or two or more different technology nodes may be used to manufacture one or more chiplets and / or one or more integrated devices (e.g., 202, 204) of the chiplets described in this disclosure. For example, a first technology node may be used to manufacture the integrated device, and a second technology node less advanced than the first technology node may be used to manufacture the chiplet. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes. In some embodiments, the chiplets and another chiplet of the package may be manufactured using the same or different technology nodes.

[0050] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require that specific technology node to be used. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0051] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0052] Exemplary process for manufacturing a substrate including interconnect blocks Figures 5A to 5G Exemplary steps for providing or manufacturing a substrate including interconnect blocks are illustrated. In some specific embodiments, Figures 5A to 5G The processes described herein can be used to provide or manufacture any substrate of the substrates described in this disclosure. In some specific embodiments, Figures 5A to 5G The process can be used to provide or manufacture the substrate 100 described in this disclosure.

[0053] It should be noted that Figures 5A to 5G The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. Different embodiments can manufacture the substrate in different ways.

[0054] like Figure 5A As shown, stage 1 illustrates the state after the core layer 101 is provided. The core layer 101 may include a seed layer 501 coupled to a first surface of the core layer 101 and a seed layer 503 coupled to a second surface of the core layer 101. Seed layer 501 and / or seed layer 503 may include a metal, such as copper.

[0055] Phase 2 illustrates the state after a plurality of cavities 510 (e.g., via cavities) have been formed in the core layer 101. The plurality of cavities 510 may be formed via seed layers 501 and 503. Laser processes (e.g., laser ablation) may be used to form the plurality of cavities 510. However, different processes may be used to form the plurality of cavities 510 in different embodiments. The plurality of cavities 510 may extend through the thickness of the core layer 101, seed layer 501, and / or seed layer 503.

[0056] Phase 3 illustrates the state after the formation of the plurality of via interconnects 114. The plurality of via interconnects 114 may be formed in the plurality of cavities 510. Plating and patterning processes may be used to form the plurality of via interconnects 114. In some embodiments, a portion of the plurality of cavities 510 is filled with the plurality of via interconnects 114, and a plurality of fillers may be provided in the remaining portions of the plurality of cavities 510.

[0057] Phase 3 also illustrates the state after the formation of multiple interconnects 512 and multiple interconnects 514. Multiple interconnects 512 may be formed and coupled to a first surface of the core layer 101. In some embodiments, a portion of the seed layer 501 may be a portion of the multiple interconnects 512. The multiple interconnects 512 may be coupled to multiple via interconnects 114. Multiple interconnects 514 may be formed and coupled to a second surface of the core layer 101. In some embodiments, a portion of the seed layer 503 may be a portion of the multiple interconnects 514. The multiple interconnects 514 may be coupled to multiple via interconnects 114. Plating and patterning processes can be used to form the multiple interconnects 512 and / or the multiple interconnects 514.

[0058] like Figure 5B As shown, stage 4 illustrates the state after the formation of dielectric layers 102a and 102b. Dielectric layer 102a may be coupled to a first surface of core layer 101. Dielectric layer 102a may cover a plurality of interconnects 512. Dielectric layer 102b may be coupled to a second surface of core layer 101. Dielectric layer 102b may cover a plurality of interconnects 514. Dielectric layers 102a and / or 102b may be formed using deposition and / or lamination processes. In some embodiments, dielectric layers 102a and / or 102b may comprise a polymer. In some embodiments, dielectric layers 102a and / or 102b may comprise an Ajinomoto deposited film (ABF). In some embodiments, dielectric layers 102a and / or 102b may comprise a prepreg. The dielectric layer 102a and / or the dielectric layer 102b may include the same or different dielectric materials as the core layer 101.

[0059] Phase 5 illustrates the state after the plurality of cavities 551 are formed through the surfaces (e.g., the first surface, the top surface) of the dielectric layer 102a. The plurality of cavities 551 may expose a portion of the plurality of interconnects 512. Phase 5 also illustrates the state after the plurality of cavities 553 are formed through the surfaces (e.g., the second surface, the bottom surface) of the dielectric layer 102b. The plurality of cavities 553 may expose a portion of the plurality of interconnects 514. In some embodiments, exposure and development processes may be used to form the plurality of cavities 551 and / or the plurality of cavities 553. In some embodiments, laser processes (e.g., laser ablation processes) may be used to form the plurality of cavities 551 in the dielectric layer 102a and the plurality of cavities 553 in the dielectric layer 102b. However, different embodiments may use different processes to form the plurality of cavities 551 and / or the plurality of cavities 553.

[0060] like Figure 5C As shown, stage 6 illustrates the state after forming a plurality of interconnects 552 in at least one dielectric layer 102a and a plurality of interconnects 554 in at least one dielectric layer 102b. The plurality of interconnects 552 may be coupled to a plurality of interconnects 512. The plurality of interconnects 554 may be coupled to a plurality of interconnects 514. A plating process may be used to form the plurality of interconnects 552 and / or the plurality of interconnects 554.

[0061] Phase 7 illustrates the state after the formation of dielectric layers 103a and 103b. Dielectric layer 103a may include multiple cavities 561. Dielectric layer 103b may include multiple cavities 571. Dielectric layer 103a may be formed and coupled to a first surface (e.g., top surface) of dielectric layer 102a. Dielectric layer 103b may be formed and coupled to a second surface (e.g., bottom surface) of dielectric layer 103b. In some embodiments, dielectric layer 103a and / or dielectric layer 103b may include a polymer. In some embodiments, dielectric layer 103a and / or dielectric layer 103b may include an Ajinomoto deposited film (ABF). In some embodiments, dielectric layer 103a and / or dielectric layer 103b may include a prepreg. Dielectric layer 103a and / or dielectric layer 103b may be the same as or different from dielectric layer 102a and / or dielectric layer 102b. Dielectric layers 103a and / or 103b can be formed using deposition and / or lamination processes.

[0062] Multiple cavities 561 are formed through the surface (e.g., first surface, top surface) of dielectric layer 103a. In some embodiments, exposure and / or development processes can be used to form the multiple cavities 561. In some embodiments, laser processes (e.g., laser ablation processes) can be used to form the multiple cavities 561 in dielectric layer 103a. However, different processes can be used in different embodiments to form the multiple cavities 561. Multiple cavities 571 are formed through the surface (e.g., second surface, bottom surface) of dielectric layer 103b. In some embodiments, exposure and / or development processes can be used to form the multiple cavities 571. In some embodiments, laser processes (e.g., laser ablation processes) can be used to form the multiple cavities 571 in dielectric layer 103b. However, different processes can be used in different embodiments to form the multiple cavities 571.

[0063] In some specific implementations, dielectric layer 103a, dielectric layer 103b, multiple cavities 561 and / or multiple cavities 571 may be formed by deposition process, lamination process, exposure process and / or development process.

[0064] like Figure 5D As shown, stage 8 illustrates the state after a plurality of interconnects 562 have been formed in at least the dielectric layer 103a. The plurality of interconnects 562 are coupled to a plurality of interconnects 552. Stage 8 also illustrates and describes the state after a plurality of interconnects 574 have been formed in at least the dielectric layer 103b. The plurality of interconnects 574 are coupled to a plurality of interconnects 554. The plurality of interconnects 562 and / or the plurality of interconnects 574 can be formed using plating and patterning processes.

[0065] Phase 9 illustrates the state after interconnect block 110 is coupled to the surface of dielectric layer 103a. Interconnect block 110 may include at least one block dielectric layer 112 and a plurality of block interconnects 113. At least one block dielectric layer 112 may include a material similar to and / or different from dielectric layer 103a. The plurality of block interconnects 113 may include a minimum width, minimum spacing, minimum pitch, and / or minimum thickness that is less than the minimum width, minimum spacing, minimum pitch, and / or minimum thickness of the plurality of interconnects 512, the plurality of interconnects 552, and / or the plurality of interconnects 562. Interconnect block 110 may be coupled to dielectric layer 103a using a lamination process.

[0066] like Figure 5EAs shown, stage 10 illustrates the state after the formation of dielectric layers 104a and 104b. Dielectric layer 104a may be formed and coupled to a first surface (e.g., top surface) of dielectric layer 103a. Dielectric layer 104a may be formed around and above interconnect block 110. Dielectric layer 104b may be formed and coupled to a second surface (e.g., bottom surface) of dielectric layer 103b. In some embodiments, dielectric layers 104a and / or 104b may comprise a polymer. In some embodiments, dielectric layers 104a and / or 104b may comprise an Ajinomoto deposited film (ABF). In some embodiments, dielectric layers 104a and / or 104b may comprise a prepreg. Dielectric layer 104a and / or dielectric layer 104b may be the same as or different from dielectric layer 102a, dielectric layer 102b, dielectric layer 103a and / or dielectric layer 103b.

[0067] The dielectric layer 104a may be formed in a stepped shape above the interconnect block 110. For example, the dielectric layer 104a may have (i) a first horizontal surface that is generally parallel to the surface of the core layer 101, and (ii) a second horizontal surface that is generally parallel to the same surface of the core layer 101, wherein the distance between the second horizontal surface of the dielectric layer 104a and the first surface of the core layer 101 is greater than the distance between the first horizontal surface of the dielectric layer 104a and the first surface of the core layer. The first horizontal surface of the dielectric layer 104a may be a surface that does not vertically overlap with the interconnect block 110, and the second horizontal surface of the dielectric layer 104a may be a surface that vertically overlaps with the interconnect block 110.

[0068] Stage 11 illustrates the state after forming a plurality of cavities 581 and a plurality of cavities 583 in the dielectric layer 104a. The plurality of cavities 581 are formed through surfaces of the dielectric layer 104a that do not vertically overlap with the interconnect block 110 (e.g., a first surface, a top surface). The plurality of cavities 583 are formed through surfaces of the dielectric layer 104a that vertically overlap with the interconnect block 110 (e.g., a first surface, a top surface). Laser processes (e.g., laser ablation processes) can be used to form the plurality of cavities 581 and / or the plurality of cavities 583 in the dielectric layer 104a. However, different specific implementations may use different processes to form the plurality of cavities 581 and / or the plurality of cavities 583.

[0069] Phase 11 also illustrates the state after the plurality of cavities 591 have been formed through the surface (e.g., the second surface, the bottom surface) of the dielectric layer 104b. Laser processes (e.g., laser ablation processes) can be used to form the plurality of cavities 591 in the dielectric layer 104b. However, different processes can be used to form the plurality of cavities 591 in different embodiments. In some embodiments, the dielectric layer 104a, dielectric layer 104b, plurality of cavities 581, plurality of cavities 583, and / or plurality of cavities 591 can be formed by deposition processes, lamination processes, exposure processes, and / or development processes.

[0070] like Figure 5F As shown, stage 12 illustrates the state after a plurality of interconnects 582 and a plurality of interconnects 152 have been formed in at least dielectric layer 104a. The plurality of interconnects 582 are coupled to a plurality of interconnects 562. The plurality of interconnects 152 are coupled to a plurality of block interconnects 113. Stage 12 also illustrates and describes the state after a plurality of interconnects 594 have been formed in at least dielectric layer 104b. The plurality of interconnects 594 are coupled to a plurality of interconnects 574. Plating and patterning processes can be used to form the plurality of interconnects 582 and / or the plurality of interconnects 594. It should be noted that the block dielectric layer 112 of interconnect block 110 may be indistinguishable from dielectric layers 102a, 103a, and / or 104a. In such instances, (i) the block dielectric layer 112 may be considered as part of dielectric layers 102a, 103a, and / or 104a, and / or (ii) the interconnect block 110 may represent a region of substrate 100, and / or be part of a region of substrate 100 including a plurality of block interconnects 113 and / or a plurality of interconnects 152. Therefore, in some specific embodiments, when the block dielectric layer 112 is indistinguishable from dielectric layers 102a, 103a, and / or 104a (e.g., when the same material is used), the interconnect block may represent a plurality of block interconnects 113 and / or a plurality of interconnects 152, and the block dielectric layer 112 may be considered as a dielectric layer of substrate 100.

[0071] Stage 13 illustrates the state after the solder mask 107 has been formed and patterned. The solder mask 107 may be coupled to dielectric layers 104a and 105. The solder mask 107 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. Different portions of the solder mask 107 may have different thicknesses. For example, the portion of the solder mask 107 that vertically overlaps with the interconnect block 110 may have a thinner thickness than the portion of the solder mask 107 that does not vertically overlap with the interconnect block 110. Portions of the solder mask 107 may contact the sidewalls of the interconnect block 110. For example, a portion of the solder mask 107 may contact the sidewall of at least one block dielectric layer 112 of the interconnect block 110.

[0072] Stage 13 also illustrates and describes the state after the solder mask 109 has been formed and patterned. The solder mask 109 may be coupled to the dielectric layer 104b. The solder mask 109 may be formed and patterned using deposition, lamination, exposure, development and / or etching processes. Stage 13 may illustrate a substrate 100 including interconnect blocks 110.

[0073] Phase 14 illustrates the state after multiple solder interconnects 290 are coupled to the interconnects of the substrate 100. For example, the multiple solder interconnects 290 may be coupled to multiple interconnects 594. A solder reflow process can be used to couple the multiple solder interconnects 290 to the substrate.

[0074] Phase 15 may exemplify a substrate 100 including interconnect blocks 110 and a plurality of solder interconnects 290.

[0075] Exemplary flowchart of a method for manufacturing a substrate having interconnect blocks In some specific implementations, the manufacturing of the substrate involves several processes. Figure 6 An exemplary flowchart illustrating a method 600 for providing or manufacturing a substrate having interconnect blocks is shown. In some specific embodiments, Figure 6 Method 600 can be used to provide or manufacture substrate 100.

[0076] It should be noted that Figure 6 Method 600 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture a substrate. In some embodiments, the order of the processes may be changed or modified.

[0077] The method (at 605) provides a core layer with a seed layer and forms a cavity (e.g., a through-hole cavity) in the core layer through the seed layer. Figure 5A Phase 1 illustrates and describes an example of the state after the core layer 101 is provided. The core layer 101 may include a seed layer 501 coupled to a first surface of the core layer 101 and a seed layer 503 coupled to a second surface of the core layer 101. Seed layer 501 and / or seed layer 503 may include a metal, such as copper.

[0078] Figure 5A Stage 2 illustrates and describes an example of the state following the formation of a plurality of cavities 510 (e.g., via cavities) in the core layer 101. The plurality of cavities 510 may be formed via seed layers 501 and 503. Laser processes (e.g., laser ablation) may be used to form the plurality of cavities 510. However, different specific embodiments may use different processes to form the plurality of cavities 510. The plurality of cavities 510 may extend through the thickness of the core layer 101, seed layer 501, and / or seed layer 503.

[0079] The method (at 610) forms a plurality of via interconnects extending through the core layer and forms interconnects on the surface of the core layer. Figure 5A Phase 3 illustrates and describes an example of the state after the formation of the plurality of via interconnects 114. The plurality of via interconnects 114 may be formed in the plurality of cavities 510. Plating and patterning processes may be used to form the plurality of via interconnects 114. In some specific embodiments, a portion of the plurality of cavities 510 is filled with the plurality of via interconnects 114, and a plurality of fillers may be provided in the remaining portions of the plurality of cavities 510.

[0080] Figure 5A Phase 3 also illustrates and describes examples of the states following the formation of multiple interconnects 512 and multiple interconnects 514. Multiple interconnects 512 may be formed and coupled to a first surface of core layer 101. In some embodiments, a portion of seed layer 501 may be a portion of multiple interconnects 512. Multiple interconnects 512 may be coupled to multiple via interconnects 114. Multiple interconnects 514 may be formed and coupled to a second surface of core layer 101. In some embodiments, a portion of seed layer 503 may be a portion of multiple interconnects 514. Multiple interconnects 514 may be coupled to multiple via interconnects 114. Plating and patterning processes can be used to form the multiple interconnects 512 and / or the multiple interconnects 514.

[0081] The method (at 615) forms a stacked layer coupled to the core layer, wherein the stacked layer may include at least one dielectric layer and a plurality of interconnects. Figure 5B Stage 4 to Figure 5D Stage 8 is illustrated and an example of the formation of stacked layers is described.

[0082] Figure 5B Stage 4 illustrates and describes an example of the state after the formation of dielectric layers 102a and 102b. Dielectric layer 102a may be coupled to a first surface of core layer 101. Dielectric layer 102a may cover a plurality of interconnects 512. Dielectric layer 102b may be coupled to a second surface of core layer 101. Dielectric layer 102b may cover a plurality of interconnects 514. Dielectric layers 102a and / or 102b may be formed using deposition and / or lamination processes. In some embodiments, dielectric layers 102a and / or 102b may comprise a polymer. In some embodiments, dielectric layers 102a and / or 102b may comprise an Ajinomoto deposited film (ABF). In some embodiments, dielectric layers 102a and / or 102b may comprise a prepreg. The dielectric layer 102a and / or the dielectric layer 102b may include the same or different dielectric materials as the core layer 101.

[0083] Figure 5BPhase 5 illustrates and describes an example of the state after the plurality of cavities 551 have been formed through the surfaces (e.g., the first surface, the top surface) of the dielectric layer 102a. The plurality of cavities 551 may expose a portion of a plurality of interconnects 512. Phase 5 also illustrates the state after the plurality of cavities 553 have been formed through the surfaces (e.g., the second surface, the bottom surface) of the dielectric layer 102b. The plurality of cavities 553 may expose a portion of a plurality of interconnects 514. In some embodiments, exposure and development processes may be used to form the plurality of cavities 551 and / or the plurality of cavities 553. In some embodiments, laser processes (e.g., laser ablation processes) may be used to form the plurality of cavities 551 in the dielectric layer 102a and the plurality of cavities 553 in the dielectric layer 102b. However, different embodiments may use different processes to form the plurality of cavities 551 and / or the plurality of cavities 553.

[0084] Figure 5C Stage 6 illustrates and describes an example of the state following the formation of a plurality of interconnects 552 in at least one dielectric layer 102a and a plurality of interconnects 554 in at least one dielectric layer 102b. The plurality of interconnects 552 may be coupled to a plurality of interconnects 512. The plurality of interconnects 554 may be coupled to a plurality of interconnects 514. A plating process may be used to form the plurality of interconnects 552 and / or the plurality of interconnects 554.

[0085] Figure 5C Stage 7 illustrates and describes an example of the state after the formation of dielectric layers 103a and 103b. Dielectric layer 103a may include multiple cavities 561. Dielectric layer 103b may include multiple cavities 571. Dielectric layer 103a may be formed and coupled to a first surface (e.g., top surface) of dielectric layer 102a. Dielectric layer 103b may be formed and coupled to a second surface (e.g., bottom surface) of dielectric layer 103b. In some embodiments, dielectric layer 103a and / or dielectric layer 103b may include a polymer. In some embodiments, dielectric layer 103a and / or dielectric layer 103b may include an Ajinomoto deposited film (ABF). In some embodiments, dielectric layer 103a and / or dielectric layer 103b may include a prepreg. Dielectric layer 103a and / or dielectric layer 103b may be the same as or different from dielectric layer 102a and / or dielectric layer 102b. Dielectric layers 103a and / or 103b can be formed using deposition and / or lamination processes.

[0086] Multiple cavities 561 are formed through the surface (e.g., first surface, top surface) of dielectric layer 103a. In some embodiments, exposure and / or development processes can be used to form the multiple cavities 561. In some embodiments, laser processes (e.g., laser ablation processes) can be used to form the multiple cavities 561 in dielectric layer 103a. However, different processes can be used in different embodiments to form the multiple cavities 561. Multiple cavities 571 are formed through the surface (e.g., second surface, bottom surface) of dielectric layer 103b. In some embodiments, exposure and / or development processes can be used to form the multiple cavities 571. In some embodiments, laser processes (e.g., laser ablation processes) can be used to form the multiple cavities 571 in dielectric layer 103b. However, different processes can be used in different embodiments to form the multiple cavities 571.

[0087] In some specific implementations, dielectric layer 103a, dielectric layer 103b, multiple cavities 561 and / or multiple cavities 571 may be formed by deposition process, lamination process, exposure process and / or development process.

[0088] Figure 5D Stage 8 illustrates and describes an example of the state after a plurality of interconnects 562 have been formed in at least the dielectric layer 103a. The plurality of interconnects 562 are coupled to a plurality of interconnects 552. Stage 8 also illustrates and describes the state after a plurality of interconnects 574 have been formed in at least the dielectric layer 103b. The plurality of interconnects 574 are coupled to a plurality of interconnects 554. Plating processes and patterning processes can be used to form the plurality of interconnects 562 and / or the plurality of interconnects 574.

[0089] This method (at 620) provides an interconnect block coupled to the dielectric layer. Figure 5D Phase 9 illustrates and describes an example of the state after interconnect block 110 is coupled to the surface of dielectric layer 103a. Interconnect block 110 may include at least one block dielectric layer 112 and a plurality of block interconnects 113. At least one block dielectric layer 112 may include a material similar to and / or different from dielectric layer 103a. The plurality of block interconnects 113 may include a minimum width, minimum spacing, minimum pitch, and / or minimum thickness less than the minimum width, minimum spacing, minimum pitch, and / or minimum thickness of the plurality of interconnects 512, the plurality of interconnects 552, and / or the plurality of interconnects 562. Interconnect block 110 may be coupled to dielectric layer 103a using a lamination process.

[0090] The method (at 625) forms at least one dielectric layer and a plurality of interconnects around and over the interconnect block. Figure 5E Stage 10 to Figure 5F Phase 12 illustrates an example of forming at least one dielectric layer and multiple interconnects around and above an interconnect block. Figure 5E Stage 10 illustrates and describes an example of the state after the formation of dielectric layers 104a and 104b. Dielectric layer 104a may be formed and coupled to a first surface (e.g., top surface) of dielectric layer 103a. Dielectric layer 104a may be formed around and above interconnect block 110. Dielectric layer 104b may be formed and coupled to a second surface (e.g., bottom surface) of dielectric layer 103b. In some embodiments, dielectric layers 104a and / or 104b may comprise a polymer. In some embodiments, dielectric layers 104a and / or 104b may comprise an Ajinomoto deposited film (ABF). In some embodiments, dielectric layers 104a and / or 104b may comprise a prepreg. Dielectric layer 104a and / or dielectric layer 104b may be the same as or different from dielectric layer 102a, dielectric layer 102b, dielectric layer 103a and / or dielectric layer 103b.

[0091] The dielectric layer 104a may be formed in a stepped shape above the interconnect block 110. For example, the dielectric layer 104a may have (i) a first horizontal surface that is generally parallel to the surface of the core layer 101, and (ii) a second horizontal surface that is generally parallel to the same surface of the core layer 101, wherein the distance between the second horizontal surface of the dielectric layer 104a and the first surface of the core layer 101 is greater than the distance between the first horizontal surface of the dielectric layer 104a and the first surface of the core layer. The first horizontal surface of the dielectric layer 104a may be a surface that does not vertically overlap with the interconnect block 110, and the second horizontal surface of the dielectric layer 104a may be a surface that vertically overlaps with the interconnect block 110.

[0092] Figure 5E Stage 11 illustrates and describes an example of the state after the formation of a plurality of cavities 581 and a plurality of cavities 583 in the dielectric layer 104a. The plurality of cavities 581 are formed via surfaces of the dielectric layer 104a that do not vertically overlap with the interconnect block 110 (e.g., a first surface, a top surface). The plurality of cavities 583 are formed via surfaces of the dielectric layer 104a that vertically overlap with the interconnect block 110 (e.g., a first surface, a top surface). Laser processes (e.g., laser ablation processes) can be used to form the plurality of cavities 581 and / or the plurality of cavities 583 in the dielectric layer 104a. However, different specific implementations may use different processes to form the plurality of cavities 581 and / or the plurality of cavities 583.

[0093] Figure 5EStage 11 also illustrates and describes an example of the state after the plurality of cavities 591 have been formed through the surface (e.g., the second surface, the bottom surface) of the dielectric layer 104b. Laser processes (e.g., laser ablation processes) can be used to form the plurality of cavities 591 in the dielectric layer 104b. However, different processes can be used to form the plurality of cavities 591 in different embodiments. In some embodiments, the dielectric layer 104a, dielectric layer 104b, plurality of cavities 581, plurality of cavities 583, and / or plurality of cavities 591 can be formed by deposition processes, lamination processes, exposure processes, and / or development processes.

[0094] Figure 5F Phase 12 illustrates and describes an example of the state after a plurality of interconnects 582 and a plurality of interconnects 152 have been formed in at least dielectric layer 104a. The plurality of interconnects 582 are coupled to a plurality of interconnects 562. The plurality of interconnects 152 are coupled to a plurality of block interconnects 113. Phase 12 also illustrates and describes the state after a plurality of interconnects 594 have been formed in at least dielectric layer 104b. The plurality of interconnects 594 are coupled to a plurality of interconnects 574. Plating and patterning processes can be used to form the plurality of interconnects 582 and / or the plurality of interconnects 594.

[0095] This method (at 630) forms at least one solder resist layer. Figure 5F Stage 13 illustrates and describes an example of the state after the solder mask 107 has been formed and patterned. The solder mask 107 may be coupled to the dielectric layer 104a. The solder mask 107 may be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. Different portions of the solder mask 107 may have different thicknesses. For example, the portion of the solder mask 107 that vertically overlaps with the interconnect block 110 may have a thinner thickness than the portion of the solder mask 107 that does not vertically overlap with the interconnect block 110. Portions of the solder mask 107 may contact the sidewalls of the interconnect block 110. For example, a portion of the solder mask 107 may contact the sidewall of at least one block dielectric layer 112 of the interconnect block 110.

[0096] Figure 5F Stage 13 also illustrates and describes an example of the state after the solder mask 109 has been formed and patterned. The solder mask 109 may be coupled to the dielectric layer 104b. The solder mask 109 may be formed and patterned using deposition, lamination, exposure, development and / or etching processes. Stage 14 may illustrate a substrate 100 including interconnect blocks 110.

[0097] This method (at 635) couples multiple solder interconnects to the substrate. Figure 5GStage 14 illustrates and describes an example of the state after multiple solder interconnects 290 are coupled to the interconnects of the substrate 100. For example, multiple solder interconnects 290 may be coupled to multiple interconnects 594. A solder reflow process can be used to couple the multiple solder interconnects 290 to the substrate. Stage 15 may illustrate a substrate 100 including interconnect block 110 and multiple solder interconnects 290.

[0098] Exemplary process for manufacturing interconnect blocks Figures 7A to 7C Exemplary steps for providing or manufacturing interconnect blocks are illustrated. In some specific implementations, Figures 7A to 7C The processes described herein can be used to provide or manufacture any interconnect block described in this disclosure. Figures 7A to 7C The process can be used to provide or manufacture the interconnect block 110 described in this disclosure.

[0099] It should be noted that Figures 7A to 7C The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture interconnect blocks. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. Different embodiments can manufacture interconnect blocks in different ways.

[0100] like Figure 7A As shown, stage 1 illustrates the state after the carrier 701 has been provided. The carrier 701 may include a core layer. The core layer may include a seed layer on the surface of the core layer.

[0101] Phase 2 illustrates the state following the plurality of interconnects 702 and 704. The plurality of interconnects 702 may be coupled to a first surface (e.g., top surface) of the carrier 701. The plurality of interconnects 704 may be coupled to a second surface (e.g., bottom surface) of the carrier 701. A plating process may be used to form the plurality of interconnects 702 and 704.

[0102] Phase 3 illustrates the state after dielectric layer 710 and dielectric layer 720 are provided. Dielectric layer 710 may be coupled to a first surface of carrier 701. Dielectric layer 720 may be coupled to a second surface of carrier 701. Dielectric layer 710 and / or dielectric layer 720 may be formed using deposition and / or lamination processes. Dielectric layer 710 and / or dielectric layer 720 may include prepreg, polymer, and / or Ajinomoto deposited film (ABF).

[0103] Figure 7BStage 4 illustrates the state after forming multiple cavities 711 in dielectric layer 710 and multiple cavities 721 in dielectric layer 720. Exposure and development processes can be used to form the multiple cavities 711 in dielectric layer 710 and the multiple cavities 721 in dielectric layer 720. Different specific embodiments may use different processes to form the multiple cavities.

[0104] Phase 5 illustrates the state after forming a plurality of interconnects 712 in dielectric layer 710 and a plurality of interconnects 724 in dielectric layer 720. The plurality of interconnects 712 can be coupled to a plurality of interconnects 702. The plurality of interconnects 714 can be coupled to a plurality of interconnects 704. A plating process can be used to form the plurality of interconnects 712 and / or the plurality of interconnects 714.

[0105] like Figure 7C As shown, stage 6 illustrates the state after the formation of several stacked layers, which may include several dielectric layers and multiple interconnects. For example, dielectric layer 730 may be formed and coupled to dielectric layer 710, and multiple interconnects 732 may be formed in at least dielectric layer 730. The multiple interconnects 732 may be coupled to multiple interconnects 712. Dielectric layer 740 may be formed and coupled to dielectric layer 720, and multiple interconnects 744 may be formed in at least dielectric layer 740. The multiple interconnects 744 may be coupled to multiple interconnects 724. The process and / or steps for manufacturing the stacked layers may be similar to at least the process in stage 6. Figure 7A Stage 3 to Figure 7B The processes and / or procedures shown and described in Phase 5 are repeatable iteratively in some specific implementations.

[0106] Phase 7 illustrates the state after the dielectric layer and multiple interconnects have been separated from the carrier 701 to form one or more interconnect blocks. For example, interconnect block 110a may include at least one block dielectric layer 112a and multiple block interconnects 113a that have been separated from the carrier 701. At least one block dielectric layer 112a may represent dielectric layer 710 and / or dielectric layer 730. Multiple block interconnects 113a may represent multiple interconnects 702, multiple interconnects 712, and / or multiple interconnects 732. Interconnect block 110b may include at least one block dielectric layer 112b and multiple block interconnects 113b that have been separated from the carrier 701. At least one block dielectric layer 112b may represent dielectric layer 720 and / or dielectric layer 740. Multiple block interconnects 113b may represent multiple interconnects 704, multiple interconnects 724, and / or multiple interconnects 744.

[0107] Exemplary flowchart of a method for manufacturing interconnect blocks In some specific implementations, manufacturing interconnect blocks involves several processes. Figure 8An exemplary flowchart illustrating a method 800 for providing or manufacturing interconnect blocks is shown. In some specific implementations, Figure 8 Method 800 can be used to provide or manufacture interconnect block 110.

[0108] It should be noted that Figure 8 Method 800 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture a substrate. In some implementations, the order of the processes may be changed or modified.

[0109] This method (at 805) provides a carrier. Figure 7A Phase 1 illustrates and describes an example of the state after the carrier 701 has been provided. The carrier 701 may include a core layer. The core layer may include a seed layer on the surface of the core layer.

[0110] The method (at 810) forms a stacked layer coupled to the carrier. The stacked layer may include at least one dielectric layer and multiple interconnects. Figure 7A Phase 2 to Figure 7C Stage 6 illustrates and describes an example of forming a stacked layer comprising at least one dielectric layer and multiple interconnects. Figure 7A Phase 2 illustrates and describes an example of the state following multiple interconnects 702 and multiple interconnects 704. Multiple interconnects 702 may be coupled to a first surface (e.g., top surface) of carrier 701. Multiple interconnects 704 may be coupled to a second surface (e.g., bottom surface) of carrier 701. A plating process may be used to form the multiple interconnects 702 and multiple interconnects 704.

[0111] Figure 7A Phase 3 illustrates and describes an example of the state after dielectric layer 710 and dielectric layer 720 are provided. Dielectric layer 710 may be coupled to a first surface of carrier 701. Dielectric layer 720 may be coupled to a second surface of carrier 701. Dielectric layer 710 and / or dielectric layer 720 may be formed using deposition and / or lamination processes. Dielectric layer 710 and / or dielectric layer 720 may include prepreg, polymer, and / or Ajinomoto deposited film (ABF).

[0112] Figure 7B Stage 4 illustrates and describes an example of the state after forming multiple cavities 711 in dielectric layer 710 and multiple cavities 721 in dielectric layer 720. Exposure and development processes can be used to form the multiple cavities 711 in dielectric layer 710 and the multiple cavities 721 in dielectric layer 720. Different specific implementations may use different processes to form the multiple cavities.

[0113] Figure 7BStage 5 illustrates and describes an example of the state after forming a plurality of interconnects 712 in dielectric layer 710 and a plurality of interconnects 724 in dielectric layer 720. The plurality of interconnects 712 may be coupled to a plurality of interconnects 702. The plurality of interconnects 714 may be coupled to a plurality of interconnects 704. A plating process may be used to form the plurality of interconnects 712 and / or the plurality of interconnects 714.

[0114] Figure 7C Stage 6 illustrates and describes an example of a state after the formation of several stacked layers, which may include several dielectric layers and multiple interconnects. For example, dielectric layer 730 may be formed and coupled to dielectric layer 710, and multiple interconnects 732 may be formed in at least dielectric layer 730. The multiple interconnects 732 may be coupled to multiple interconnects 712. Dielectric layer 740 may be formed and coupled to dielectric layer 720, and multiple interconnects 744 may be formed in at least dielectric layer 740. The multiple interconnects 744 may be coupled to multiple interconnects 724. The process and / or steps for manufacturing the stacked layers may be similar to at least the process in [the previous stage]. Figure 7A Stage 3 to Figure 7B The processes and / or procedures shown and described in Phase 5 are repeatable iteratively in some specific implementations.

[0115] The method (at 815) separates the dielectric layer and the plurality of interconnects from the carrier. Figure 7C Phase 7 illustrates and describes an example of the state after the dielectric layer and multiple interconnects have been separated from the carrier 701 to form one or more interconnect blocks. For example, interconnect block 110a may include at least one block dielectric layer 112a and multiple block interconnects 113a that have been separated from the carrier 701. At least one block dielectric layer 112a may represent dielectric layer 710 and / or dielectric layer 730. Multiple block interconnects 113a may represent multiple interconnects 702, multiple interconnects 712 and / or multiple interconnects 732. Interconnect block 110b may include at least one block dielectric layer 112b and multiple block interconnects 113b that have been separated from the carrier 701. At least one block dielectric layer 112b may represent dielectric layer 720 and / or dielectric layer 740. Multiple block interconnects 113b may represent multiple interconnects 704, multiple interconnects 724 and / or multiple interconnects 744.

[0116] Exemplary electronic devices Figure 9Examples are illustrated of various electronic devices that may integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 902, laptop computer device 904, fixed-location terminal device 906, wearable device 908, or motor vehicle 910 may include device 900 as described herein. For example, device 900 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 9 The illustrated devices 902, 904, 906, and 908, as well as vehicle 910, are merely exemplary. Other electronic devices may also feature device 900, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0117] Figures 1 to 4 , Figures 5A to 5G , Figure 6 , Figures 7A to 7C and / or Figures 8 to 9 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 4 , Figures 5A to 5G , Figure 6 , Figures 7A to 7C and / or Figures 8 to 9 The corresponding descriptions herein are not limited to bare dies and / or ICs. In some specific implementations, Figures 1 to 4 , Figures 5A to 5G , Figure 6 , Figures 7A to 7C and / or Figures 8 to 9The descriptions and their corresponding descriptions can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some specific implementations, the equipment may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0118] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0119] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "on top of" as used in this application in the context of one component being on top of another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component on top of second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component "in" the second component can be partially or entirely located within the second component.As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within 10% of “value X”. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0120] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0121] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0122] Further examples are described below to facilitate understanding of this disclosure.

[0123] Aspect 1: A substrate comprising: a core layer; at least one first dielectric layer coupled to a first surface of the core layer; at least one second dielectric layer coupled to a second surface of the core layer; a plurality of interconnects at least partially located in the at least one first dielectric layer; a region comprising a plurality of block interconnects of interconnect blocks; and a solder resist layer coupled to the at least one first dielectric layer.

[0124] Aspect 2: The substrate according to aspect 1, wherein the solder resist layer includes a first portion having a first thickness and a second portion having a second thickness.

[0125] Aspect 3: According to aspect 2, the second portion of the solder resist layer is vertically located above at least a portion of the interconnect block, and the second thickness of the second portion is less than the first thickness of the first portion.

[0126] Aspect 4: The substrate according to aspects 1 to 3, wherein the interconnect block includes a first interconnect on a first metal layer and a second interconnect on a second metal layer, and wherein the first interconnect and / or the second interconnect is laterally located on the same horizontal plane as the via interconnect from the plurality of interconnects.

[0127] Aspect 5: The substrate according to aspects 1 to 4, wherein a first surface of the at least one first dielectric layer located above the interconnect block is a first distance from the surface of the core layer, wherein a second surface of the at least one first dielectric layer not located above the interconnect block is a second distance from the surface of the core layer, and wherein the first distance is greater than the second distance.

[0128] Aspect 6: The substrate according to aspects 1 to 5, wherein the substrate is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0129] Aspect 7: A package comprising: a substrate; the substrate comprising: a core layer; at least one first dielectric layer coupled to a first surface of the core layer; at least one second dielectric layer coupled to a second surface of the core layer; a plurality of interconnects at least partially located in the at least one first dielectric layer; a region comprising a plurality of block interconnects of interconnect blocks; and a solder resist layer coupled to the at least one first dielectric layer; a first integrated device coupled to the substrate via a first plurality of bump interconnects; and a second integrated device coupled to the substrate via a second plurality of bump interconnects.

[0130] Aspect 8: The package according to aspect 7, wherein the solder mask layer includes a first portion having a first thickness and a second portion having a second thickness.

[0131] Aspect 9: The package according to aspect 8, wherein the second portion of the solder mask layer is vertically located above at least a portion of the interconnect block, and wherein the second thickness of the second portion is less than the first thickness of the first portion.

[0132] Aspect 10: The package according to aspects 7 to 9, wherein the interconnect block includes a first interconnect on a first metal layer and a second interconnect on a second metal layer, and wherein the first interconnect and / or the second interconnect is laterally located on the same horizontal plane as the via interconnects from the plurality of interconnects.

[0133] Aspect 11: The package according to aspects 7 to 10, wherein a first surface of the at least one first dielectric layer located above the interconnect block is a first distance from the surface of the core layer, wherein a second surface of the at least one first dielectric layer not located above the interconnect block is a second distance from the surface of the core layer, and wherein the first distance is greater than the second distance.

[0134] Aspect 12: The package according to aspects 7 to 11, wherein the first plurality of bump interconnects includes a first plurality of pillar interconnects and / or a first plurality of solder interconnects, and wherein the second plurality of bump interconnects includes a second plurality of pillar interconnects and / or a second plurality of solder interconnects.

[0135] Aspect 13: The package according to aspects 7 to 12, wherein the electrical path between the first integrated device and the second integrated device includes the interconnect block.

[0136] Aspect 14: The package according to aspect 13, wherein the electrical path between the first integrated device and the second integrated device includes at least one block interconnect from the interconnect block.

[0137] Aspect 15: The package according to aspects 7 to 14, wherein the interconnect block and the at least one first dielectric layer share the same dielectric layer.

[0138] Aspect 16: The package according to aspects 7 to 15, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0139] Aspect 17: A method for manufacturing a substrate, the method comprising: providing a core layer; forming at least one first dielectric layer coupled to a first surface of the core layer; forming at least one second dielectric layer coupled to a second surface of the core layer; forming a plurality of interconnects at least partially located in the at least one first dielectric layer; coupling an interconnect block comprising a plurality of block interconnects to the at least one first dielectric layer; forming an additional first dielectric layer around and over the interconnect block; and forming a solder resist layer coupled to the at least one first dielectric layer.

[0140] Aspect 18: According to the method of aspect 17, the solder resist layer includes a first portion having a first thickness and a second portion having a second thickness.

[0141] Aspect 19: According to the method of aspect 18, the second portion of the solder mask layer is vertically located above at least a portion of the interconnect block, and the second thickness of the second portion is less than the first thickness of the first portion.

[0142] Aspect 20: The method according to aspects 17 to 19, wherein the interconnect block includes a first interconnect on a first metal layer and a second interconnect on a second metal layer, and wherein the first interconnect and / or the second interconnect is laterally located on the same horizontal plane as the via interconnect from the plurality of interconnects.

[0143] Aspect 21: The method according to aspects 17 to 20, wherein a first surface of the at least one first dielectric layer located above the interconnect block is a first distance from the surface of the core layer, wherein a second surface of the at least one first dielectric layer not located above the interconnect block is a second distance from the surface of the core layer, and wherein the first distance is greater than the second distance.

[0144] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A substrate, the substrate comprising: Core layer; At least one first dielectric layer, said at least one first dielectric layer being coupled to a first surface of the core layer; At least one second dielectric layer, said at least one second dielectric layer being coupled to a second surface of the core layer; A plurality of interconnects, wherein the plurality of interconnects are at least partially located in the at least one first dielectric layer; A region, the region comprising a plurality of block interconnects of interconnect blocks; and A solder resist layer coupled to the at least one first dielectric layer.

2. The substrate according to claim 1, wherein the solder resist layer comprises a first portion having a first thickness and a second portion having a second thickness.

3. The substrate according to claim 2, The second portion of the solder mask layer is vertically positioned above at least a portion of the interconnect block, and The second thickness of the second part is less than the first thickness of the first part.

4. The substrate according to claim 1, The interconnect block includes a first interconnect on a first metal layer and a second interconnect on a second metal layer, and The first interconnect and / or the second interconnect are laterally located on the same horizontal plane as the via interconnects from the plurality of interconnects.

5. The substrate according to claim 1, The first surface of the at least one first dielectric layer located above the interconnect block is at a first distance from the surface of the core layer. The second surface of the at least one first dielectric layer not located above the interconnect block is at a second distance from the surface of the core layer, and The first distance is greater than the second distance.

6. The substrate of claim 1, wherein the substrate is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

7. A package, the package comprising: A substrate, the substrate comprising: Core layer; At least one first dielectric layer, said at least one first dielectric layer being coupled to a first surface of the core layer; At least one second dielectric layer, said at least one second dielectric layer being coupled to a second surface of the core layer; A plurality of interconnects, wherein the plurality of interconnects are at least partially located in the at least one first dielectric layer; Region, the region comprising a plurality of block interconnects of interconnect blocks; and A solder resist layer coupled to the at least one first dielectric layer; A first integrated device, the first integrated device being coupled to the substrate via a first plurality of bump interconnects; and The second integrated device is coupled to the substrate via a second plurality of bump interconnects.

8. The package of claim 7, wherein the solder mask layer comprises a first portion having a first thickness and a second portion having a second thickness.

9. The package according to claim 8, The second portion of the solder mask layer is vertically positioned above at least a portion of the interconnect block, and The second thickness of the second part is less than the first thickness of the first part.

10. The package according to claim 7, The interconnect block includes a first interconnect on a first metal layer and a second interconnect on a second metal layer, and The first interconnect and / or the second interconnect are laterally located on the same horizontal plane as the via interconnects from the plurality of interconnects.

11. The package according to claim 7, The first surface of the at least one first dielectric layer located above the interconnect block is at a first distance from the surface of the core layer. The second surface of the at least one first dielectric layer not located above the interconnect block is at a second distance from the surface of the core layer, and The first distance is greater than the second distance.

12. The package according to claim 7, The first plurality of bump interconnects include a first plurality of pillar interconnects and / or a first plurality of solder interconnects, and The second plurality of bump interconnects includes a second plurality of pillar interconnects and / or a second plurality of solder interconnects.

13. The package of claim 7, wherein the electrical path between the first integrated device and the second integrated device includes the interconnect block.

14. The package of claim 13, wherein the electrical path between the first integrated device and the second integrated device comprises at least one block interconnect from the interconnect block.

15. The package of claim 7, wherein the interconnect block and the at least one first dielectric layer share the same dielectric layer.

16. The package of claim 7, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

17. A method for manufacturing a substrate, the method comprising: Provide core layer; At least one first dielectric layer is formed, the at least one first dielectric layer being coupled to a first surface of the core layer; At least one second dielectric layer is formed, the at least one second dielectric layer being coupled to a second surface of the core layer; A plurality of interconnects are formed, the plurality of interconnects being at least partially located in the at least one first dielectric layer; An interconnect block comprising multiple block interconnects is coupled to the at least one first dielectric layer; An additional first dielectric layer is formed around and above the interconnect block; as well as A solder resist layer is formed, which is coupled to the at least one first dielectric layer.

18. The method of claim 17, wherein the solder resist layer comprises a first portion having a first thickness and a second portion having a second thickness.

19. The method according to claim 18, The second portion of the solder mask layer is vertically positioned above at least a portion of the interconnect block, and The second thickness of the second part is less than the first thickness of the first part.

20. The method according to claim 17, The interconnect block includes a first interconnect on a first metal layer and a second interconnect on a second metal layer, and The first interconnect and / or the second interconnect are laterally located on the same horizontal plane as the via interconnects from the plurality of interconnects.

21. The method according to claim 17, The first surface of the at least one first dielectric layer located above the interconnect block is at a first distance from the surface of the core layer. The second surface of the at least one first dielectric layer not located above the interconnect block is at a second distance from the surface of the core layer, and The first distance is greater than the second distance.

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