Local low-temperature SiC wafer thinning and polishing integrated processing device and processing method thereof

Abstract

The invention belongs to the field of wafer processing, and particularly relates to a local low-temperature SiC wafer thinning and polishing integrated processing device and a processing method thereof.The local low-temperature SiC wafer thinning and polishing integrated processing device comprises a wafer carrying table and is characterized in that the wafer carrying table is connected with the inner wall of an index plate in a clamped mode; a rotating shaft of the equipment machine table is fixedly connected with an index plate, a loading opening is formed in the surface of the equipment machine table, the upper surface of the equipment machine table is fixedly connected with a drying carrying table, the side face of the drying carrying table is fixedly connected with an air knife, and the air knife is designed by adopting N2 gas and a 45-degree angle. According to the local low-temperature SiC wafer thinning and polishing integrated machining device, the wafer carrying table and the machining device are arranged, the excellent heat conductivity of SiC is utilized, the carrying table is efficiently transferred to a wafer at low temperature, SiC crystals are plastically removed at low temperature, and subsurface damage caused by grinding is greatly reduced; and the surface temperature of the wafer stage is uniformly distributed in cooperation with the design of the spiral micro-channel in the stage body.

Description

Technical Field

[0001] This invention relates to the field of wafer processing technology, specifically to an integrated processing apparatus and method for local low-temperature SiC wafer thinning and polishing. Background Technology

[0002] In the field of semiconductor materials, SiC possesses excellent physical and chemical properties. SiC single crystal materials exhibit properties such as a wide bandgap, high thermal conductivity, high electron saturation migration rate, and high breakdown electric field, making them widely used in the manufacture of various electronic devices. However, the grinding and polishing process of SiC substrates faces numerous challenges. Significant time wastage and inefficient resource allocation during wafer grinding and polishing lead to deterioration in the final wafer's geometric parameters, all of which negatively impact the final substrate surface quality.

[0003] Currently, traditional SiC grinding and polishing methods often have several problems. For example, SiC wafers may experience positioning errors after multiple clamping operations. Furthermore, after rapid cutting, the wafer undergoes handling, pre-polishing preparation, and final polishing, resulting in a wafer resting period. During this resting period, stress release occurs, causing further deterioration of the bow value. Additionally, establishing two separate grinding and polishing processes not only increases equipment, plant operations, and human resources but also significantly reduces the process efficiency of SiC wafer manufacturing. While technologies and equipment for processing SiC wafers in a globally cryogenic environment have been proposed, maintaining such equipment at a consistently low temperature is extremely expensive, and the mechanical parts of this specialized equipment require cryogenic modifications, making maintenance complex. This technology is currently only available in research institutes and laboratories, hindering mass production. Therefore, optimizing the grinding and polishing process, reducing processing costs, and improving the processing quality and efficiency of the grinding and polishing steps represent the future trend in SiC wafer processing. In light of this, we propose an integrated processing device and method for localized cryogenic SiC wafer thinning and polishing. Summary of the Invention

[0004] The main objective of this invention is to provide an integrated processing apparatus and method for local low-temperature SiC wafer thinning and polishing, which can solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention proposes an integrated processing apparatus for local low-temperature SiC wafer thinning and polishing, comprising a wafer stage, characterized in that: the wafer stage is engaged with the inner wall of the indexing disk;

[0006] The equipment includes a rotating shaft with a fixed indexing plate, a loading port on its surface, a drying platform fixedly connected to its upper surface, and an air knife fixedly connected to the side of the drying platform. The air knife uses N2 gas and is designed at a 45° angle to quickly blow away residual coolant and polishing fluid from the back of the wafer, preventing the solution from freezing and causing scratches or corrosion to the wafer surface in low-temperature environments, while also reducing secondary pollution caused by residual droplets. The drying platform, through centrifugal force generated by high-speed swishing, deeply removes tiny droplets adhering to the wafer surface, compensating for drying blind spots that may exist in single swishing, ensuring that the wafer surface cleanliness meets the standards, and providing clean surface conditions for subsequent flipping processing or storage.

[0007] The first mechanical fork is fixedly connected to the upper surface of the equipment platform;

[0008] The second mechanical fork is fixedly connected to the upper surface of the equipment platform;

[0009] The centering platform is fixedly connected to the upper surface of the equipment platform;

[0010] A processing apparatus, which is positioned directly above the wafer stage.

[0011] Preferably, the wafer stage includes a stage body, the upper surface of which has a recessed wafer adsorption area. Through this recessed adsorption area, the SiC wafer is fixed using Coulomb force generated by electrostatics. This electrostatic adsorption method eliminates the need for mechanical clamping or vacuum adsorption, completely avoiding surface scratches and indentations caused by mechanical contact, and also avoiding potential sealing failures that may occur with vacuum adsorption at low temperatures. Its recessed structure reduces the contact area between the non-processed areas of the wafer and the wafer stage, lowering the risk of contamination from residual chemicals and debris accumulation, thus meeting high-cleanliness processing requirements. Furthermore, the wafer stage surface is coated with an alumina layer, which not only improves the tightness of the fit between the wafer and the wafer stage and enhances the stability of electrostatic adsorption, but also maintains an extremely low oxidation and corrosion rate in acidic polishing environments. The interior of the stage body has a liquid nitrogen spiral microchannel.

[0012] Preferably, the liquid nitrogen spiral microchannel has a rectangular cross-section, which maximizes the contact area between the liquid nitrogen and the inner wall of the wafer stage, significantly improving heat exchange efficiency. This allows the low temperature of the liquid nitrogen to be quickly and uniformly transferred to the surface of the wafer stage, precisely achieving a localized low-temperature environment only in the wafer contact area, thus avoiding the high cost and complex maintenance of the overall cryogenic equipment.

[0013] Preferably, the wafer stages are arranged in groups of four in an equidistant circular array.

[0014] Preferably, the processing devices are grouped into sets of three, namely, rough thinning type, fine thinning type and polishing type.

[0015] Preferably, the process includes the following steps: S1, loading the SiC wafer to be processed into a cassette, and then placing the cassette into the loading port of the equipment; the equipment identifies the number of wafers, placement slots and initial status information in the cassette through the mapping function, and completes the wafer information filing before processing;

[0016] S2. The second mechanical fork extends to pick up the corresponding wafer based on the wafer slot information identified by the equipment; it is then transported to the centering stage. The mechanical clamping structure first converges the wafer center offset, and then the centering stage rotates. The grating ruler captures the wafer center position and positioning edge angle. After calibration, the mechanical clamping structure is released.

[0017] S3. The second mechanical fork extends again, retrieves the calibrated wafer, and places it in the concave adsorption area of ​​the local low-temperature stage; the electrostatic adsorption system is activated, and high voltage is applied to create an adsorption force between the wafer and the stage electrodes to fix the wafer in place.

[0018] S4. The indexing plate rotates, causing the local low-temperature stage carrying the wafer to switch to the rough thinning station; the rough thinning spindle starts, the grinding wheel descends until it contacts the wafer surface, and the corresponding stage rotates in coordination; during the processing, the online thickness measurement system collects wafer thickness data and feeds it back to the equipment control unit, which adjusts the grinding wheel feed speed according to the thickness change; if an abnormality is detected, an alarm is triggered and processing is paused;

[0019] S5. After the rough thinning process is completed, the rough thinning spindle is lifted and reset; the indexing plate rotates again to switch the stage to the fine thinning station; after the fine thinning spindle starts, it descends to contact the wafer, and the corresponding stage rotates and operates in coordination to start the fine thinning process; the local low temperature stage and the room temperature thinning module are kept in tandem, and the online thickness measurement system monitors the thickness. After the thickness reaches the standard, the fine thinning spindle is lifted and reset.

[0020] S6. After the thinning process is completed, the indexing plate rotates to switch the stage to the polishing station; the polishing slurry supply system is activated to deliver polishing slurry to the processing area; the polishing spindle is activated, the polishing head descends to fit the wafer surface, and the corresponding stage rotates in coordination, while simultaneously oscillating linearly to remove the damaged layer through chemical-mechanical action; after polishing is completed, the polishing spindle is raised and reset, and the stage rotates to shed residual polishing slurry; subsequently, the brush above the stage descends to contact the stage surface for self-cleaning, removing debris and slurry;

[0021] S7. After the stage self-cleaning is completed, the indexing plate rotates back to the waiting position; the second mechanical fork extends, picks up the polished wafer, transports it to the drying stage, starts the air knife to blow dry the back of the wafer, and starts the drying stage at the same time. The drying stage starts and completes the spin drying.

[0022] S8. After drying is complete, the first mechanical fork picks up the wafer from the drying stage, flips it, and inserts the wafer into the corresponding slot of the cassette to complete single-sided processing. Repeat steps S2-S7 to complete single-sided processing of all wafers in the cassette. After all wafers have completed the first-sided processing, the first mechanical fork picks up the wafer from the cassette and repeats the S2-S7 process again to complete the second-sided processing. After all wafers have completed double-sided processing, the process ends.

[0023] Preferably, in step S2, the formula for calculating the wafer calibration eccentricity is:

[0024]

[0025] in, This is the eccentricity of the wafer's geometric center relative to the rotation center of the centering stage.

[0026] , These are the offsets of the geometric center relative to the rotation center of the platform on the X and Y axes, respectively.

[0027] Preferably, in step S2, the formula for calculating the positioning edge angle correction value is:

[0028]

[0029] in, This is the angle correction value for the positioning edge.

[0030] The angle at which the central stage rotates.

[0031] This refers to the angle of the actual positioning edge as captured by the grating ruler.

[0032] Positive values ​​represent clockwise rotation, and negative values ​​represent counterclockwise rotation.

[0033] Preferably, in step S3, the electrostatic adsorption calculation formula is:

[0034]

[0035] Where F is the adsorption force.

[0036] The vacuum permittivity

[0037] The dielectric constant of SiC crystal is...

[0038] A is the electrode area.

[0039] V is voltage.

[0040] d represents the distance between the SiC wafer and the electrode.

[0041] Preferably, in steps S4-S5, the formula for calculating the thinning cutting speed is:

[0042]

[0043] Where v is the current feed rate of the grinding wheel.

[0044] To reduce the initial feed rate during the initial thinning process,

[0045] λ is the attenuation coefficient.

[0046] d represents the real-time thickness of the wafer.

[0047] The target thickness for wafer thinning.

[0048] e is a natural constant.

[0049] This invention provides an integrated processing apparatus and method for localized low-temperature SiC wafer thinning and polishing. It offers the following advantages:

[0050] (1) This integrated processing device for localized low-temperature SiC wafer thinning and polishing utilizes the excellent thermal conductivity of SiC to efficiently transfer the low temperature of the stage to the wafer, enabling plastic removal of the SiC crystal at low temperatures and significantly reducing subsurface damage caused by grinding. Combined with the internal spiral microchannel design of the stage body, it achieves uniform temperature distribution on the wafer stage surface. Furthermore, electrostatic adsorption and high-precision alignment effectively suppress the thermal stress effects during the grinding and polishing process. Compared to traditional overall low-temperature processing, this device, with its low-temperature wafer stage and SiC thermal conduction, effectively reduces the processing cost of low-temperature processing.

[0051] (2) This integrated processing device for localized low-temperature SiC wafer thinning and polishing, through the coordination of the indexing plate, wafer stage, and processing device, enables the preparation, roughing, finishing, and polishing processes of SiC wafers to operate in a continuous closed-loop manner. It eliminates the need for additional wafer handling and clamping between different devices or workstations, completely avoiding positioning errors caused by multiple clamping operations in traditional processes, as well as problems such as wafer stress release and performance degradation during handling and resting. The rapid switching function of the indexing plate ensures smooth connection between each process, and the precise positioning and low-temperature control characteristics of the wafer stage are maintained throughout the entire process. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0053] Figure 1 This is a top view of the structure of the present invention;

[0054] Figure 2 This is a schematic diagram of the wafer stage structure of the present invention;

[0055] Figure 3 This is a schematic diagram of the wafer stage structure of the present invention;

[0056] Figure 4 This is a schematic diagram of a portion of the processing device of the present invention;

[0057] Figure 5 This is a schematic diagram of the structure and operation of the present invention.

[0058] Explanation of reference numerals in the attached figures: 1. Wafer stage; 2. Indexing plate; 3. Equipment platform; 4. First mechanical fork; 5. Second mechanical fork; 6. Loading port; 7. Drying stage; 8. Air knife; 9. Centering stage; 10. Processing device; 101. Stage body; 102. Wafer concave adsorption area; 103. Liquid nitrogen spiral microchannel.

[0059] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] Please see Figures 1-5This invention proposes an integrated processing apparatus for localized low-temperature SiC wafer thinning and polishing, including a wafer stage 1. The wafer stage 1 includes a stage body 101, and the upper surface of the stage body 101 has a wafer concave adsorption region 102. Through the wafer concave adsorption region 102, the SiC wafer is fixed by the Coulomb force generated by electrostatics. The electrostatic adsorption method eliminates the need for mechanical clamping or vacuum adsorption, completely avoiding surface scratches and indentations caused by mechanical contact, and also avoiding the sealing failure problem that may occur in vacuum adsorption at low temperatures. Its concave structure reduces the contact area between the non-processed area of ​​the wafer and the wafer stage 1, reducing the accumulation of residual chemicals and debris. To mitigate the risk of contamination and meet the demands of high-cleanliness processing, the wafer stage 1 is coated with an alumina layer, which not only improves the adhesion between the wafer and the wafer stage 1 and enhances the stability of electrostatic adsorption, but also maintains an extremely low oxidation and corrosion rate in acidic polishing environments. The stage body 101 has an internal liquid nitrogen spiral microchannel 103 with a rectangular cross-section. This rectangular cross-section maximizes the contact area between the liquid nitrogen and the inner wall of the wafer stage 1, significantly improving heat exchange efficiency. This allows the low temperature of the liquid nitrogen to be quickly and uniformly transferred to the surface of the wafer stage, precisely achieving a localized low-temperature environment only in the wafer contact area, avoiding the high cost and complex maintenance of overall cryogenic equipment.

[0062] The wafer stage 1 is engaged with the inner wall of the indexing disk 2. The wafer stages 1 are arranged in groups of four and form an equidistant circular array.

[0063] The equipment platform 3 has an indexing plate 2 fixedly connected to its rotating shaft, a loading port 6 is opened on the surface of the equipment platform 3, a drying platform 7 is fixedly connected to the upper surface of the equipment platform 3, and an air knife 8 is fixedly connected to the side of the drying platform 7.

[0064] The first mechanical fork 4 is fixedly connected to the upper surface of the equipment base 3;

[0065] The second mechanical fork 5 is fixedly connected to the upper surface of the equipment base 3;

[0066] The intermediate loading platform 9 is fixedly connected to the upper surface of the equipment platform 3;

[0067] The processing apparatus 10 is positioned directly above the wafer stage 1. Three processing apparatuses 10 are grouped together: a rough thinning type, a fine thinning type, and a polishing type. Through the wafer stage 1 and processing apparatus 10, the excellent thermal conductivity of SiC allows for efficient and low-temperature heat transfer from the wafer stage 1 to the wafer, enabling plastic removal of the SiC crystal at low temperatures and significantly reducing subsurface damage caused by grinding. Combined with the internal spiral microchannel design of the stage body 101, uniform surface temperature distribution is achieved on the wafer stage 1. Electrostatic adsorption and high-precision alignment effectively suppress the thermal stress effects during grinding and polishing. Compared to traditional overall low-temperature processing, the low temperature of the wafer stage 1 combined with SiC thermal conduction effectively reduces processing costs. The coordination of the indexing plate 2, wafer stage 1, and processing apparatus 10 ensures a continuous closed-loop flow in the SiC wafer processing workflow, encompassing preparation, roughing, fine finishing, and polishing. There is no need for additional handling and clamping of wafers between different equipment or workstations, completely avoiding the positioning errors caused by multiple clamping in traditional processes, as well as problems such as wafer stress release and performance degradation caused during handling and resting. The quick switching function of the indexing plate 10 ensures smooth connection between each process, and the precise positioning and low temperature control characteristics of the wafer stage 1 are maintained throughout the entire process.

[0068] In this invention, the following steps need to be followed during operation:

[0069] S1. Load the SiC wafer to be processed into the cassette, and then place the cassette into the loading port of the equipment; the equipment identifies the number of wafers, placement slots and initial status information in the cassette through the mapping function, and completes the wafer information filing before processing;

[0070] S2. The second mechanical fork extends to pick up the corresponding wafer based on the wafer slot information identified by the equipment; it is then transported to the centering stage. The mechanical clamping structure first converges the wafer center offset, and then the centering stage rotates, cooperating with the grating ruler to capture the wafer center position and positioning edge angle.

[0071] The formula for calculating wafer calibration eccentricity is:

[0072]

[0073] in, This is the eccentricity of the wafer's geometric center relative to the rotation center of the centering stage.

[0074] , These are the offsets of the geometric center relative to the rotation center of the platform on the X and Y axes, respectively.

[0075] The formula for calculating the positioning edge angle correction value is:

[0076]

[0077] in, This is the angle correction value for the positioning edge.

[0078] The angle at which the central stage rotates.

[0079] This refers to the angle of the actual positioning edge as captured by the grating ruler.

[0080] Positive values ​​represent clockwise rotation, and negative values ​​represent counterclockwise rotation.

[0081] After calibration, the mechanical clamping structure is released;

[0082] S3. The second mechanical fork extends again, retrieves the calibrated wafer, and places it in the concave adsorption area of ​​the local low-temperature stage; the electrostatic adsorption system is activated, and high voltage is applied to create an adsorption force between the wafer and the stage electrodes, fixing the wafer in place; the electrostatic adsorption calculation formula in S3 is:

[0083]

[0084] Where F is the adsorption force.

[0085] The vacuum permittivity

[0086] The dielectric constant of SiC crystal is...

[0087] A is the electrode area.

[0088] V is voltage.

[0089] d represents the distance between the SiC wafer and the electrode.

[0090] S4. The indexing plate rotates, causing the local low-temperature stage carrying the wafer to switch to the rough thinning station; the rough thinning spindle starts, the grinding wheel descends until it contacts the wafer surface, and the corresponding stage rotates in coordination; during the processing, the online thickness measurement system collects wafer thickness data and feeds it back to the equipment control unit, which adjusts the grinding wheel feed speed according to the thickness change; if an abnormality is detected, an alarm is triggered and processing is paused;

[0091] S5. After the rough thinning process is completed, the rough thinning spindle is lifted and reset; the indexing plate rotates again, switching the stage to the fine thinning station; after the fine thinning spindle starts, it descends to contact the wafer, and the corresponding stage rotates to cooperate and begin the fine thinning process; the locally low-temperature stage and the room-temperature thinning module are kept in tandem, and the online thickness measurement system monitors the thickness. After the thickness reaches the target, the fine thinning spindle is lifted and reset; the formula for calculating the thinning cutting speed in S4-S5 is:

[0092]

[0093] Where v is the current feed rate of the grinding wheel.

[0094] To reduce the initial feed rate during the initial thinning process,

[0095] λ is the attenuation coefficient.

[0096] d represents the real-time thickness of the wafer.

[0097] The target thickness for wafer thinning.

[0098] e is a natural constant.

[0099] S6. After the thinning process is completed, the indexing plate rotates to switch the stage to the polishing station; the polishing slurry supply system is activated to deliver polishing slurry to the processing area; the polishing spindle is activated, the polishing head descends to fit the wafer surface, and the corresponding stage rotates in coordination, while simultaneously oscillating linearly to remove the damaged layer through chemical-mechanical action; after polishing is completed, the polishing spindle is raised and reset, and the stage rotates to shed residual polishing slurry; subsequently, the brush above the stage descends to contact the stage surface for self-cleaning, removing debris and slurry;

[0100] S7. After the stage self-cleaning is completed, the indexing plate rotates back to the waiting position; the first mechanical fork extends, picks up the polished wafer, and transports it to the drying stage. The air knife is started to blow and dry the back of the wafer, and the drying stage is started at the same time. The drying stage starts and spins dry.

[0101] S8. After drying is complete, the first mechanical fork picks up the wafer from the drying stage, flips it, and inserts the wafer into the corresponding slot of the cassette to complete single-sided processing. Repeat steps S2-S7 to complete single-sided processing of all wafers in the cassette. After all wafers have completed the first-sided processing, the second mechanical fork picks up the wafer from the cassette and repeats the S2-S7 process again to complete the second-sided processing. After all wafers have completed double-sided processing, the process ends.

[0102] Example:

[0103] SiC wafer localized low-temperature thinning and polishing test sample (target thickness 170μm)

[0104] S1. Load the SiC wafer to be processed into the cassette, and then place the cassette into the loading port of the equipment; the equipment identifies the number of wafers, placement slots, and initial state information in the cassette through the mapping function, and completes the pre-processing wafer information filing (thickness: 430μm-460μm; diameter: 150.0mm±0.1mm; total thickness variation: ≤5μm; curvature: ≤±15μm; warpage: ≤30μm; surface roughness: ≤0.2μm).

[0105] S2. The second mechanical fork extends to pick up the corresponding wafer based on the wafer slot information identified by the equipment; it is then transported to the centering stage. The mechanical clamping structure first converges the wafer center offset, and then the centering stage rotates, cooperating with the grating ruler to capture the wafer center position and positioning edge angle.

[0106] The formula for calculating wafer calibration eccentricity is:

[0107]

[0108] in, This is the eccentricity of the wafer's geometric center relative to the rotation center of the centering stage.

[0109] , These are the offsets of the geometric center relative to the rotation center of the platform on the X and Y axes, respectively.

[0110] The formula for calculating the positioning edge angle correction value is:

[0111]

[0112] in, This is the angle correction value for the positioning edge.

[0113] The angle at which the central stage rotates.

[0114] This refers to the angle of the actual positioning edge as captured by the grating ruler.

[0115] Positive values ​​represent clockwise rotation, and negative values ​​represent counterclockwise rotation.

[0116] After calibration, the mechanical clamping structure is released.

[0117] S3. The second mechanical fork extends again, retrieves the calibrated wafer, and places it on a local low-temperature stage (diameter: 190mm ± 0.1mm; rotation speed: 1rpm / min-500rpm / min; material: AlN ceramic; thermal conductivity: 180-220W / m·K; processing environment temperature: -50℃; surface coating: CVD deposited alumina, thickness 3μm; Ra < 0.3nm, oxidation corrosion rate < 0.01μm / m² in acidic environment (pH ≥ 1). H; Internally etched spiral microchannel: cross-section 0.5mm × 0.5mm, pitch 3mm, total length 1.2m, temperature uniformity ≤ ±1℃) with a concave adsorption region (diameter 150.1mm ± 0.1mm, concave depth 80μm ± 1μm, positioning edge length 47.1mm ± 0.1mm); Activate the electrostatic adsorption system, apply high voltage (voltage: 4600V) to create an adsorption force between the wafer and the stage electrode, fixing the wafer; In S3, the electrostatic adsorption calculation formula is:

[0118]

[0119] Where F is the adsorption force.

[0120] The vacuum permittivity

[0121] The dielectric constant of SiC crystal is approximately 9.7.

[0122] A is the electrode area (calculated from the diameter of the concave adsorption region, which is 0.0177 m²).

[0123] V represents voltage (4600V).

[0124] d is the distance between the SiC wafer and the electrode (taken as 0.03 mm).

[0125] Substituting the voltage and wafer information into the electrostatic adsorption calculation formula, the adsorption pressure is found to be 18 kPa.

[0126] S4. The indexing plate rotates (90° at a rotational speed of 80° / s), causing the local low-temperature stage carrying the wafer to switch to the roughing and thinning station; the roughing and thinning spindle (power: 7kW; speed: 1900rpm / min; dynamic balance: 0.8g) starts, and the grinding wheel (grinding grit: 2500 grit, cutting edge 3.0mm, cutting edge height 5.0mm, wear ratio 0.08) descends until it contacts the wafer surface; the corresponding stage runs synchronously at a speed of 120rpm / min; during the processing, ethylene glycol (ratio) is added... The coolant (freezing point -55℃) is 20% (e.g., 20%), the processing load current is controlled at 20A, and the material removal rate is maintained at 0.6μm / s. The online thickness measurement system (laser wavelength 1450nm, sampling frequency 100Hz, measurement accuracy 0.1μm, repeatability 98.5%) is perpendicularly incident on the wafer surface, and the real-time thickness is calculated by the reflected light interference signal, which is fed back to the equipment control unit to adjust the grinding wheel feed speed. If a sudden change in thickness >3μm / s or a single-station processing time ≥10min is detected, an emergency stop and alarm are immediately triggered.

[0127] S5. After the rough thinning process is completed, the rough thinning spindle is lifted and reset; the indexing plate rotates again (90°) to switch the stage to the fine thinning station; after the fine thinning spindle (power: 3kW) is started, it descends to contact the wafer (speed: 950rpm / min, mesh size: 15000 mesh, dynamic balance: 0.8g, cutting edge: 3.0mm, cutting edge height: 5.0mm, wear ratio: 0.5), and the corresponding stage runs at 100rpm / min to start the fine thinning process; the locally low temperature stage and the room temperature thinning module are kept in tandem, using the same coolant as the rough thinning process, the processing load current is 18A, the material removal rate is maintained at 0.2μm / s, the thickness is monitored by the online thickness measurement system, and after the thickness reaches the target, the fine thinning spindle is lifted and reset; the thinning cutting speed calculation formula in S4-S5 is:

[0128]

[0129] Where v is the current feed rate of the grinding wheel.

[0130] To reduce the initial feed rate during the initial thinning process,

[0131] λ is the attenuation coefficient (0.3).

[0132] d represents the real-time thickness of the wafer.

[0133] The target thickness for wafer thinning is 170μm ± 10μm.

[0134] e is a natural constant.

[0135] After the thinning process reaches the target, the spindle is lifted and reset. The program waits for all thinning spindles to stop moving before the indexing table performs the next station switch.

[0136] S6. The indexing table rotates 90° to switch the stage to the polishing station; the polishing slurry supply system starts, delivering a polishing slurry containing alumina, 1.0wt% concentration, pH 6, and 10% PEG (400 molecular weight) to the processing area at a flow rate of 100ml / min (direct-flow CDS supply); the polishing spindle (0.5kW power) starts, the polishing head descends with a pressure of 2psi to contact the wafer surface, and runs at a speed of 120rpm / min, maintaining a speed ratio of 1.15 with the stage, while simultaneously oscillating back and forth along the X-axis with a stroke of 9mm and a frequency of 15Hz, removing the damaged layer through chemical mechanical action (the polishing pad is polyurethane-based, Shore A hardness 55); after polishing, the polishing spindle is lifted and reset, the stage rotates at 300rpm / min, using centrifugal force to shed residual polishing slurry; then the stage is in an empty state, and the brush above it descends to contact the stage surface for self-cleaning, removing debris and slurry residue;

[0137] S7. After the stage self-cleaning is completed, the indexing table rotates 90° to return to the waiting position; the first mechanical fork extends at a movement speed of 200mm / s on the X-axis, 36mm / s on the Z-axis, and 100° / s on the T-axis (positioning accuracy ±0.1mm), picks up the polished wafer, transports it to the drying stage, and starts the air knife. The air knife blows and dries the wafer with air pressure of 0.6MPa, nitrogen gas at -20℃, and at an angle of 45° to the back of the wafer. At the same time, the drying stage starts and completes the spin-drying at a spin-drying speed of 500rpm / min and an acceleration of 300rpm / s².

[0138] S8. After drying, the first mechanical fork picks up the wafer from the drying stage, rotates it 180° to flip the wafer, and inserts it into the corresponding slot of the cassette to complete single-sided processing. Repeat steps S2-S7 to complete single-sided processing of all wafers in the cassette (during continuous operation, the second mechanical fork simultaneously picks up the next wafer for centering and loading during the roughing and thinning process). After all wafers have completed the first-sided processing, the second mechanical fork picks up the wafer from the cassette and repeats the S2-S7 process to complete the second-sided processing. After all wafers have completed double-sided processing, the machine's mechanical shaft resets, a buzzer sounds to indicate the end of processing, the cassette is removed from the loading port, and the process ends.

[0139] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. An integrated processing apparatus for localized low-temperature SiC wafer thinning and polishing, comprising a wafer stage (1), characterized in that: The wafer stage (1) is engaged with the inner wall of the indexing plate (2); The equipment platform (3) has an indexing plate (2) fixedly connected to its rotating shaft. The surface of the equipment platform (3) is provided with a loading port (6). The upper surface of the equipment platform (3) is fixedly connected with a drying platform (7). The side of the drying platform (7) is fixedly connected with an air knife (8). The first mechanical fork (4) is fixedly connected to the upper surface of the equipment base (3); The second mechanical fork (5) is fixedly connected to the upper surface of the equipment base (3); The centering platform (9) is fixedly connected to the upper surface of the equipment base (3); The processing apparatus (10) is positioned directly above the wafer stage (1).

2. The integrated processing apparatus for localized low-temperature SiC wafer thinning and polishing according to claim 1, characterized in that: The wafer stage (1) includes a stage body (101), the upper surface of which is provided with a wafer concave adsorption region (102), and the interior of the stage body (101) is provided with a liquid nitrogen spiral microchannel (103).

3. The integrated processing apparatus for localized low-temperature SiC wafer thinning and polishing according to claim 1, characterized in that: The liquid nitrogen spiral microchannel (103) has a rectangular cross-section.

4. The integrated processing apparatus for localized low-temperature SiC wafer thinning and polishing according to claim 1, characterized in that: The wafer stage (1) is arranged in groups of four, forming an equidistant circular array.

5. The integrated processing apparatus for localized low-temperature SiC wafer thinning and polishing according to claim 1, characterized in that: The processing devices (10) are divided into groups of three, namely, rough thinning type, fine thinning type and polishing type.

6. The integrated processing method for localized low-temperature SiC wafer thinning and polishing according to claim 1, characterized in that, Includes the following steps: S1. Load the SiC wafer to be processed into the cassette, and then place the cassette into the loading port of the equipment; the equipment identifies the number of wafers, placement slots and initial status information in the cassette through the mapping function, and completes the wafer information filing before processing; S2. The second mechanical fork extends to pick up the corresponding wafer based on the wafer slot information identified by the equipment; it is then transported to the centering stage. The mechanical clamping structure first converges the wafer center offset, and then the centering stage rotates. The grating ruler captures the wafer center position and positioning edge angle. After calibration, the mechanical clamping structure is released. S3. The second mechanical fork extends again, retrieves the calibrated wafer, and places it in the concave adsorption area of ​​the local low-temperature stage; the electrostatic adsorption system is activated, and high voltage is applied to create an adsorption force between the wafer and the stage electrodes to fix the wafer in place. S4. The indexing plate rotates, causing the local low-temperature stage carrying the wafer to switch to the rough thinning station; the rough thinning spindle starts, the grinding wheel descends until it contacts the wafer surface, and the corresponding stage rotates in coordination; during the processing, the online thickness measurement system collects wafer thickness data and feeds it back to the equipment control unit, which adjusts the grinding wheel feed speed according to the thickness change; if an abnormality is detected, an alarm is triggered and processing is paused; S5. After the rough thinning process is completed, the rough thinning spindle is lifted and reset; the indexing plate rotates again to switch the stage to the fine thinning station; after the fine thinning spindle starts, it descends to contact the wafer, and the corresponding stage rotates and operates in coordination to start the fine thinning process; the local low temperature stage and the room temperature thinning module are kept in tandem, and the online thickness measurement system monitors the thickness. After the thickness reaches the standard, the fine thinning spindle is lifted and reset. S6. After the thinning process is completed, the indexing plate rotates to switch the stage to the polishing station; the polishing slurry supply system is started to deliver polishing slurry to the processing area; the polishing spindle is started, the polishing head descends to fit the wafer surface, and the corresponding stage rotates and runs in coordination, while making linear oscillations to remove the damaged layer through chemical mechanical action. After polishing is completed, the polishing spindle is lifted and reset, and the stage rotates to shake off the residual polishing liquid; then the brush above the stage descends and contacts the stage surface to perform self-cleaning, removing debris and liquid. S7. After the stage self-cleaning is completed, the indexing plate rotates back to the waiting position; the first mechanical fork extends, picks up the polished wafer, and transports it to the drying stage. The air knife is started to blow and dry the back of the wafer, and the drying stage is started at the same time. The drying stage starts and spins dry. S8. After drying is complete, the first mechanical fork picks up the wafer from the drying stage, flips it, and inserts the wafer into the corresponding slot of the cassette to complete single-sided processing. Repeat steps S2-S7 to complete single-sided processing of all wafers in the cassette. After all wafers have completed the first-sided processing, the second mechanical fork picks up the wafer from the cassette and repeats the S2-S7 process again to complete the second-sided processing. After all wafers have completed double-sided processing, the process ends.

7. The integrated processing method for localized low-temperature SiC wafer thinning and polishing according to claim 6, characterized in that: In S2, the formula for calculating the wafer calibration eccentricity is: ； in, This is the eccentricity of the wafer's geometric center relative to the rotation center of the centering stage. , These are the offsets of the geometric center relative to the rotation center of the platform on the X and Y axes, respectively.

8. The integrated processing method for localized low-temperature SiC wafer thinning and polishing according to claim 6, characterized in that: In S2, the formula for calculating the positioning edge angle correction value is: ； in, This is the angle correction value for the positioning edge. The angle at which the central stage rotates. This refers to the angle of the actual positioning edge as captured by the grating ruler. Positive values ​​represent clockwise rotation, and negative values ​​represent counterclockwise rotation.

9. The integrated processing method for localized low-temperature SiC wafer thinning and polishing according to claim 6, characterized in that: In S3, the formula for calculating electrostatic adsorption is: ； Where F is the adsorption force. The vacuum permittivity The dielectric constant of SiC crystal is... A is the electrode area. V is voltage. d represents the distance between the SiC wafer and the electrode.

10. The integrated processing method for localized low-temperature SiC wafer thinning and polishing according to claim 6, characterized in that: In S4-S5, the formula for calculating the thinning cutting speed is: ； Where v is the current feed rate of the grinding wheel. To reduce the initial feed rate during the initial thinning process, λ is the attenuation coefficient. d represents the real-time thickness of the wafer. The target thickness for wafer thinning. e is a natural constant.

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