Channel temperature prediction method, device and equipment of GaN HEMT chip, medium and product

Abstract

The invention discloses a channel temperature prediction method and device of a GaN HEMT chip, equipment, a medium and a product, and relates to the field of semiconductor thermal management, and the method comprises the steps: firstly carrying out a thermal test experiment, and obtaining a multi-dimensional experiment data set corresponding to the GaN HEMT chip; actual device structure parameters and cross-scale actual device structure parameters of the GaN HEMT chip are obtained; firstly, a thermal model corresponding to a chip is constructed; setting thermal boundary conditions and channel heat sources in different working states for the thermal model based on a thermal test experiment and a multi-dimensional experiment data set; constructing a cross-scale three-dimensional geometric model based on actual device structure parameters; carrying out assembly and thermal test experiments to obtain a multi-dimensional experimental data set of the three-dimensional thermal model; and constructing a multi-dimensional parameterized temperature prediction curve based on the three-dimensional thermal model and the multi-dimensional experimental data set of the three-dimensional thermal model. According to the method, the multi-scale thermal model with high simulation precision can be constructed, and the channel temperature can be accurately predicted.

Description

Technical Field

[0001] This application relates to the field of semiconductor thermal management, and in particular to a method, apparatus, device, medium, and product for predicting the channel temperature of a GaN HEMT chip. Background Technology

[0002] With the widespread application of GaN materials in high-power, high-frequency applications, gallium nitride high electron mobility transistors (GaN HEMTs) are widely used in fields such as RF power amplifiers due to their high power density and high efficiency. However, their high power density brings severe thermal management challenges, especially during high-power operation, where the chip's channel temperature (T0) increases significantly. channel It has a crucial impact on the stability and reliability of the device.

[0003] The existing methods do not consider the thermal characteristics of GaN HEMTs under different operating conditions, the heat source design is unreasonable, and the finite element models of GaN HEMTs all need to be built from scratch. When a finite element model of another device is required, the modeling work must be restarted, which is time-consuming and laborious, and difficult to adapt to diverse research and application needs. At the same time, factors such as interface thermal resistance and nonlinear thermal conduction of materials are not fully considered in cross-scale thermal modeling, resulting in insufficient simulation accuracy and restricting the improvement of device performance and reliability. Summary of the Invention

[0004] The purpose of this application is to provide a method, apparatus, device, dielectric, and product for predicting the channel temperature of GaN HEMT chips, which can construct a multi-scale thermal model with high simulation accuracy and accurately predict the channel temperature.

[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a method for predicting the channel temperature of a GaN HEMT chip, including: A thermal testing experiment was conducted on a GaN HEMT chip to obtain a multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the multi-dimensional experimental dataset includes the gate-source voltage V. gs Drain-source voltage V ds Heat dissipation conditions, surface temperature, bottom temperature, drain-source current, and heat dissipation power density per unit gate width; Obtain the actual device structure parameters and cross-scale actual device structure parameters of GaN HEMT chips; A thermal model of the thermal testing system is constructed based on the actual device structure parameters of the GaN HEMT chip. Based on the thermal test experiment and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip, thermal boundary conditions and channel heat sources are set for the thermal model under different operating conditions; the thermal boundary conditions of the thermal model are the same as those of the thermal test experiment; when the drain-source voltage of the operating state is less than or equal to the knee voltage, the channel heat source in the thermal model is a uniform surface heat source covering the channel; when the drain-source voltage of the operating state is greater than or equal to the knee voltage, the channel heat source in the thermal model is a local surface heat source covering the drain side under the gate. A cross-scale three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales. The thermal model is assembled into the multi-scale three-dimensional geometric model to obtain a three-dimensional thermal model; The three-dimensional thermal model was subjected to thermal testing experiments to obtain a multi-dimensional experimental dataset of the three-dimensional thermal model. A multidimensional parameterized temperature prediction curve is constructed based on the three-dimensional thermal model and the multidimensional experimental dataset of the three-dimensional thermal model. The multidimensional parameterized temperature prediction curve takes the operating state, power density and heat dissipation conditions as input parameters and the channel peak temperature as output parameter. The multidimensional parameterized temperature prediction curve is used to predict the channel temperature.

[0006] Secondly, this application provides a channel temperature prediction device for a GaN HEMT chip, comprising: The first thermal testing module is used to control the thermal testing of the GaN HEMT chip and obtain a multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the multi-dimensional experimental dataset includes the gate-source voltage V. gs Drain-source voltage V ds Heat dissipation conditions, surface temperature, bottom temperature, drain-source current, and heat dissipation power density per unit gate width; The acquisition module is used to acquire the actual device structure parameters of GaN HEMT chips and the actual device structure parameters across scales. The first construction module is used to construct a thermal model of the thermal testing system based on the actual device structure parameters of the GaN HEMT chip. The simulation module is used to set thermal boundary conditions and channel heat sources for the thermal model under different operating states based on the thermal test experiment and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the thermal boundary conditions of the thermal model are the same as those of the thermal test experiment; when the drain-source voltage of the operating state is less than or equal to the knee voltage, the channel heat source in the thermal model is a uniform surface heat source covering the channel; when the drain-source voltage of the operating state is greater than or equal to the knee voltage, the channel heat source in the thermal model is a local surface heat source covering the drain side under the gate. The second construction module is used to construct a cross-scale three-dimensional geometric model based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales. An assembly module is used to assemble the thermal model into the multi-scale three-dimensional geometric model to obtain a three-dimensional thermal model. The second thermal testing experiment module is used to conduct thermal testing experiments on the three-dimensional thermal model to obtain a multi-dimensional experimental dataset of the three-dimensional thermal model. The third construction module is used to construct a multi-dimensional parameterized temperature prediction curve based on the three-dimensional thermal model and the multi-dimensional experimental dataset of the three-dimensional thermal model. The multi-dimensional parameterized temperature prediction curve takes the operating state, power density and heat dissipation conditions as input parameters and the channel peak temperature as output parameter. The multi-dimensional parameterized temperature prediction curve is used to predict the channel temperature.

[0007] Thirdly, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the channel temperature prediction method for the GaN HEMT chip.

[0008] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the channel temperature prediction method for the GaN HEMT chip.

[0009] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the channel temperature prediction method for the GaN HEMT chip.

[0010] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a method, apparatus, device, dielectric, and product for predicting the channel temperature of GaN HEMT chips. First, thermal testing experiments are conducted on the GaN HEMT chip to obtain a multi-dimensional experimental dataset. Then, a thermal model is constructed. Based on the thermal testing experiments, thermal boundary conditions and channel heat sources under different operating states are set for the thermal model, achieving accurate simulation of the channel temperature under real heating conditions, resulting in more precise temperature simulation. Next, a cross-scale three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip and cross-scale actual device structure parameters. The thermal model is then integrated into the cross-scale three-dimensional geometric model, making the heat sources of the three-dimensional thermal model more closely match the actual heating characteristics of the device. This achieves unified cross-scale thermal modeling, completely reproducing the heat conduction path, constructing a high-precision multi-scale thermal model, and accurately predicting the channel temperature. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure and dimensions of a single gate finger in a GaN HEMT. Figure 2 This is a schematic diagram of the thermal testing experimental setup; Figure 3 Schematic diagram of a microfluidic module-level thermal testing fixture; Figure 4 This is a 3D geometric model diagram of a chip-level unit; Figure 5 This is a thermal simulation model diagram of the 780-4 package. Figure 6 Diagram of a microchannel module-level thermal simulation model; Figure 7 Diagram of SiC-based GaN HEMT B4 chip; Figure 8 Diagram of SiC-based GaN HEMT B7 chip; Figure 9 For B4 and B7 chips, different V values ​​are used in the 780-4 package-level model. gs T below channel Prediction curve; Figure 10 For the provided B7 chip, different V values ​​are used in the microchannel module-level model. gs V ds T under influent flow rate channel Prediction curve; Figure 11 Flowchart of a method for predicting the channel temperature of a GaN HEMT chip; Figure 12 A schematic diagram of the GaN HEMT chip thermal characteristic testing - cross-scale thermal model calibration and channel temperature prediction process. Figure 13 A schematic diagram of the functional modules of the channel temperature prediction device for a GaN HEMT chip. Figure 14 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] In one exemplary embodiment, such as Figure 11 As shown, a method for predicting the channel temperature of a GaN HEMT chip is provided. This method is executed by a computer device, specifically by a terminal or server alone, or by both a terminal and a server. In this embodiment, the method includes the following steps.

[0016] Step 101: Control the thermal testing experiment on the GaN HEMT chip to obtain the multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the multi-dimensional experimental dataset includes the gate-source voltage V. gs Drain-source voltage V ds Heat dissipation conditions, surface temperature, bottom temperature, drain-source current, and heat dissipation power density per unit gate width.

[0017] Step 102: Obtain the actual device structure parameters and cross-scale actual device structure parameters of the GaN HEMT chip.

[0018] Step 103: Construct a thermal model of the thermal testing system based on the actual device structure parameters of the GaN HEMT chip.

[0019] Step 104: Based on the thermal test experiment and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip, set thermal boundary conditions and channel heat sources for the thermal model under different operating states; the thermal boundary conditions of the thermal model are the same as those of the thermal test experiment; when the drain-source voltage of the operating state is ≤ knee voltage, the channel heat source in the thermal model is a uniform surface heat source covering the channel; when the drain-source voltage of the operating state is > knee voltage, the channel heat source in the thermal model is a local surface heat source covering the drain side under the gate.

[0020] Step 105: Construct a cross-scale three-dimensional geometric model based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales.

[0021] Step 106: Assemble the thermal model into the multi-scale three-dimensional geometric model to obtain the three-dimensional thermal model.

[0022] Step 107: Conduct thermal testing experiments on the three-dimensional thermal model to obtain a multi-dimensional experimental dataset of the three-dimensional thermal model.

[0023] Step 108: Construct a multi-dimensional parameterized temperature prediction curve based on the three-dimensional thermal model and the multi-dimensional experimental dataset of the three-dimensional thermal model; the multi-dimensional parameterized temperature prediction curve takes the operating state, power density and heat dissipation conditions as input parameters; and the channel peak temperature as the output parameter; the multi-dimensional parameterized temperature prediction curve is used to predict the channel temperature.

[0024] The above steps involve first conducting thermal testing experiments on the GaN HEMT chip to obtain a multi-dimensional experimental dataset. Then, a thermal model is constructed. Based on the thermal testing experiments, thermal boundary conditions and channel heat sources are set for the thermal model under different operating conditions, achieving accurate simulation of the channel temperature under real heating conditions, resulting in more precise temperature simulation. Next, a cross-scale three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip and cross-scale actual device structure parameters. The thermal model is then integrated into the cross-scale three-dimensional geometric model, making the heat sources in the three-dimensional thermal model more closely match the actual heating characteristics of the device. This achieves unified cross-scale thermal modeling, completely reproducing the heat conduction path, constructing a high-precision multi-scale thermal model, and accurately predicting the channel temperature.

[0025] In an exemplary embodiment, controlling the thermal testing of a GaN HEMT chip to obtain a multi-dimensional experimental dataset corresponding to the GaN HEMT chip specifically includes: controlling the GaN HEMT chip to switch on the gate-source voltage and drain-source voltage respectively, and acquiring the surface temperature; the surface temperature is acquired in real time by an infrared thermal imager aligned with the surface of the GaN HEMT chip; controlling the adjustment of the gate-source voltage and drain-source voltage to perform multiple sets of DC tests, and recording the thermal test data of the GaN HEMT chip surface temperature after steady state in each set of tests; the thermal test data of each set of tests includes the gate-source voltage, drain-source voltage, highest surface temperature, package bottom temperature, and drain-source current; and determining the multi-dimensional experimental dataset corresponding to the GaN HEMT chip based on the thermal test data of the GaN HEMT chip surface temperature after steady state in each set of tests.

[0026] In an exemplary embodiment, the actual device structure parameters and cross-scale actual device structure parameters of the GaN HEMT chip both include a geometric model and model parameters; the geometric model includes: a source electrode, a drain electrode, a gate electrode, a source field plate, a passivation layer, a barrier layer, a GaN channel layer, and a GaN buffer layer; wherein, the material of the passivation layer is SiO2 or Al2O3; the material of the barrier layer is AlGaInN, AlInN, or InAlN; the model parameters include: barrier layer thickness, Al molar mass fraction, doping concentration, GaN channel layer thickness, and GaN buffer layer thickness.

[0027] In an exemplary embodiment, the thermal model of the thermal testing system is constructed based on the actual device structure parameters of the GaN HEMT chip. Specifically, this includes: constructing an actual geometric model based on the actual device structure parameters of the GaN HEMT chip; simplifying the non-critical structures in the actual geometric model to obtain the thermal model of the thermal testing system; the simplification of the non-critical structures includes: simplifying the elliptical grounding hole into a rectangular hole with equal area and simplifying the multilayer pad structure of the source and drain into a single-layer cuboid structure.

[0028] In an exemplary embodiment, based on the thermal test experiment and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip, thermal boundary conditions and channel heat sources under different operating states are set for the thermal model. Specifically, this includes: determining the location and distribution of the channel heat source based on the drain-source voltage of the thermal test experiment; determining the thermal boundary conditions based on the multi-dimensional experimental dataset corresponding to the GaN HEMT chip; setting the boundary conditions, the location and distribution of the channel heat source on the thermal model and performing simulation; and adjusting the size of the channel heat source so that the error between the simulated surface temperature and the measured temperature is ≤10%.

[0029] In an exemplary embodiment, a cross-scale three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales. Specifically, this includes: constructing a cross-scale initial geometric model based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales; simplifying the non-critical structures of the cross-scale initial geometric model to obtain a cross-scale three-dimensional geometric model; the simplification of the non-critical structures includes: removing the alumina ceramic shell on the top of the package and retaining the molybdenum-copper substrate and the conductive silver paste layer and / or extracting the complex flow channel structure of the heat dissipation module into an equivalent heat exchange surface.

[0030] In practical applications, a cross-scale initial geometric model is constructed by combining the actual device structure parameters of the GaN HEMT chip with the cross-scale actual device structure parameters. Specifically, this includes: constructing a chip-level three-dimensional geometric model based on the actual device structure parameters of the GaN HEMT chip; when the cross-scale actual device structure parameters are the actual device structure parameters of a package-level chip, building a packaging module using SolidWorks based on the actual device structure parameters of the package-level chip; and assembling the chip-level three-dimensional geometric model into the packaging module to obtain the cross-scale initial geometric model.

[0031] In another example of practical application, a cross-scale initial geometric model is constructed using the actual device structure parameters of the GaN HEMT chip and the cross-scale actual device structure parameters. Specifically, this includes: constructing a chip-level three-dimensional geometric model based on the actual device structure parameters of the GaN HEMT chip; when the cross-scale actual device structure parameters include the actual device structure parameters of a package-level chip and a module-level chip, building a package module using SolidWorks based on the actual device structure parameters of the package-level chip; and constructing a module model using SolidWorks based on the actual device structure parameters of the module-level chip, the module model including a heat dissipation module; assembling the chip-level three-dimensional geometric model to the package module and assembling the assembled package module to the module model to obtain the cross-scale initial geometric model.

[0032] In one exemplary embodiment, the method for predicting the channel temperature of a GaN HEMT chip further includes: comparing and iterating the simulated values ​​and measured values ​​of the thermal test data obtained using the three-dimensional thermal model; and calibrating the three-dimensional thermal model when the maximum absolute deviation between the simulated values ​​and the measured values ​​does not exceed 11°C and the maximum relative deviation does not exceed 10%.

[0033] In one exemplary embodiment, a multidimensional parameterized temperature prediction curve is constructed based on the three-dimensional thermal model and its multidimensional experimental dataset. Specifically, this includes: extracting the channel peak temperature and junction-case thermal resistance under different gate-source voltages, drain-source voltages, power densities, and heat dissipation conditions based on the three-dimensional thermal model and its multidimensional experimental dataset; constructing an association database based on the channel peak temperature and junction-case thermal resistance under different gate-source voltages, drain-source voltages, power densities, and heat dissipation conditions; and performing quadratic polynomial curve fitting based on the association database, using operating state, power density, and heat dissipation conditions as input parameters and channel peak temperature as the output parameter, to obtain the multidimensional parameterized temperature prediction curve.

[0034] This application belongs to the field of semiconductor device thermal characteristic prediction technology. Addressing the problems of existing GaN HEMT thermal models, such as unreasonable heat source settings, lack of cross-scale heat transfer description, and insufficient prediction accuracy, this application constructs a three-dimensional cross-scale thermal model at the chip and package levels based on experimental measurement data. It extracts the relationship between channel peak temperature and thermal resistance as a function of power density, and establishes temperature prediction curves and a parametric modeling method. This model can accurately predict the GaN HEMT channel temperature under different operating conditions, providing support for the thermal design and reliability optimization of high-power GaN devices.

[0035] In one exemplary embodiment, such as Figure 12 As shown, it includes the following steps: Step 1: Conduct thermal testing experiments on the GaN HEMT chip under multiple heat dissipation conditions, and measure the gate-source voltage V under different conditions. gs Drain-source voltage V ds Maximum surface temperature T of the chip under different heat dissipation conditions surface Bottom temperature, drain-source current I ds And calculate the heat dissipation power density P per unit grid width. d .

[0036] Thermal testing experiments and multi-scenario data acquisition: The GaN HEMT devices in the package module are unpacked, and a thermal testing fixture scenario integrating temperature control, electrical testing, and multi-heat dissipation condition adaptation functions is built. (1) Baseline heat dissipation scenario: The packaged device is fixed to a copper water-cooled plate with conductive silver paste to achieve fixed heat dissipation conditions test.

[0037] (2) Variable heat dissipation scenario: Equip a heat dissipation module with embedded microchannels, use deionized water as the cooling medium, adjust the flow rate to 60-300mL / min, and realize the test of variable heat dissipation conditions.

[0038] Measure different bias voltages (V) using an infrared thermal imager gs -2V~3V, V ds Chip surface temperature T under different heat dissipation conditions (0V~12V): surface The bottom temperature of the package, T bottom Synchronous acquisition of drain-source current I ds Calculate the heat dissipation power density P per unit grid width d Construct a system covering the gate-source voltage V gs -Drain-source voltage V ds A multi-dimensional experimental dataset consisting of "power density, heat dissipation conditions, and surface temperature".

[0039] Step 2: Obtain the actual device structure parameters of the GaN HEMT chip, and construct a thermal model of the thermal testing system based on the actual device structure parameters.

[0040] Based on the data from the thermal test experiment, the size and location of the channel heat source under different working conditions are set for the thermal model of the thermal test system; and the boundary parameters are adapted to different heat dissipation conditions.

[0041] The thermal boundary conditions are the same as those in the thermal test experiment.

[0042] Based on the measured geometry of GaN HEMT chips, a thermal model of the thermal testing system was constructed using SolidWorks and ANSYS software. The thermal model includes the structure of each functional layer of the GaN HEMT device, sets corresponding thermophysical properties for each layer material or interlayer thermal resistance, and reasonably simplifies the thermal model structure and applies boundary conditions consistent with actual testing.

[0043] When the drain-source voltage is less than or equal to the knee voltage in the operating state, the GaN HEMT device is in the saturation region. A uniform surface heat source is applied to the channel region of the GaN HEMT die, and the heat flux density is equal to the total heat dissipation and the total channel width. When the drain-source voltage is greater than the knee voltage in the operating state, the channel heat source is a local surface heat source covering the gate-drain side. A concentrated surface heat source is applied to a local region on the gate-drain side of the GaN HEMT die, and the heat flux density is equal to the total heat dissipation and the width of the local heat source.

[0044] Furthermore, thermal model simulations were performed to obtain the surface temperature T of the GaN HEMT chip. surface Compare it with the measured T surface Fit the data and adjust the footprint of the heat source in the channel to ensure that the error between the simulated and measured values ​​is ≤10%.

[0045] Step 3: Construct a three-dimensional geometric model based on the overall packaged GaN HEMT chip, call the thermal model of the GaNHEMT chip constructed in Step 2, and combine the thermal model with the three-dimensional geometric model to construct a cross-scale three-dimensional thermal model at the package level or module level.

[0046] Construction and calibration of a cross-scale 3D thermal model: Based on measured geometric dimensions, packaged and module models were constructed using SolidWorks and ANSYS software, respectively, with the module model including a heat dissipation module. By reasonably simplifying the packaged and / or module structures, the chip-level thermal model was combined with the packaged and / or module models to complete the construction of a cross-scale thermal model at either the chip-level to the package-level or the chip-level to the package-level and module-level. The thermal efficiency (T) obtained from simulations under different operating conditions was then compared. surface The model was iteratively compared and calibrated with experimental measurements to ensure its compatibility across the full power range (P). d =0~5.28W / mm), and the simulation error under full heat dissipation scenario is controlled within 10%.

[0047] Specifically, the boundary condition adaptation conditions are as follows: for the baseline heat dissipation scenario, the experimentally measured bottom temperature of the package and the iteratively calibrated convective heat transfer coefficient are used; for the variable heat dissipation scenario, the convective heat transfer coefficient under different flow rates is extracted using FLUENT to accurately simulate the heat dissipation effect of the microchannel.

[0048] Step 4: Based on the calibrated multi-scale three-dimensional thermal model, extract the channel peak temperature T. channel With the thermal resistance R of the junction shell jc With power density P d The relationship between changes in heat dissipation conditions.

[0049] Multi-condition channel temperature and thermal resistance extraction: Based on a calibrated three-dimensional multi-scale thermal model, the system extracts different electrical biases (VT). gs V ds ), different power densities (P) d The peak channel temperature T under different heat dissipation conditions (fixed water cooling, different microchannel flow rates) and channel With the thermal resistance R of the junction shell jc Establish a database linking "bias-power-heat dissipation-temperature-thermal resistance" to provide basic data support for thermal design and reliability assessment.

[0050] Step 5: Establish a multi-dimensional parameterized temperature prediction model and output "operating state - heat dissipation conditions - power density P". d -Channel peak temperature T channel "Prediction curves are used to quickly predict different P values." d Channel temperature under different heat dissipation conditions.

[0051] Construction of a multi-dimensional parameterized temperature prediction model: Based on the correlation data extracted in step 4, the model is designed for the saturation and amplification regions, respectively, using the operating region type and power density P. d Using heat dissipation conditions as input parameters, a quadratic polynomial curve fitting is performed to establish a multidimensional parameterized T. channel -P d Predictive model. This model can predict based on known device operating conditions and P. d Under suitable heat dissipation conditions, the peak channel temperature can be directly output without the need for repeated complex finite element simulations.

[0052] In practical applications, such as Figure 1 As shown, the actual device structure parameters include the geometric model and model parameters.

[0053] The geometric model includes: source and drain electrodes S and D, gate electrode G, source field plate SFP, Si3N4 passivation layer, AlGaN barrier layer, GaN channel layer, and GaN buffer layer. Model parameters include: AlGaN barrier layer thickness 23 nm, Al molar mass fraction 0.23, and doping concentration 1 × 10⁻⁶.18 cm -3 The GaN channel layer is 10nm thick, the GaN buffer layer is 1150nm thick, the gate and AlGaN barrier layer are Schottky contacts, and the gate G and source field plate are both made of gold.

[0054] In practical applications, step 1 includes the following steps: Step 1.1: Unpack the vacuum-packaged GaN HEMT chip to expose its surface.

[0055] Step 1.2: Set up a heat dissipation scenario test fixture, including a baseline heat dissipation scenario or a variable heat dissipation scenario: (1) Baseline heat dissipation scenario: Figure 2 (a) in the figure represents the baseline heat dissipation fixture scenario, such as... Figure 2 As shown in (a), the open-packaged chip is fixed to a copper water-cooled plate with conductive silver paste, and a high thermal conductivity silicone pad and a thermocouple are placed between them.

[0056] (2) Variable heat dissipation scenario: Figure 2 (b) in the example describes a scenario with variable heat dissipation fixtures, such as... Figure 2 As shown in (b), the chip is assembled into a heat dissipation module with embedded microchannels, using deionized water as the cooling medium and a flow regulation system (60mL / min-300mL / min) is configured.

[0057] Step 1.3: Connect the electrical testing system to the infrared thermal imager and collect T data in real time. surface .

[0058] Step 1.4, at different gate-source voltages (V gs -2V~3V) and drain-source voltage (V ds DC tests were performed at 0V~12V. After maintaining a steady temperature at each test point, the temperature T was recorded. surface The bottom temperature of the package, T bottom and drain-source current I ds .

[0059] Step 1.5: For the variable heat dissipation scenario, adjust the cooling medium flow rate sequentially (60mL / min, 80mL / min, 100mL / min, 200mL / min, 300mL / min), repeat step 1.4, and complete the experimental data collection under multiple heat dissipation conditions.

[0060] In practical applications, step 2 includes the following steps: Step 2.1: Based on the measured geometric dimensions, use SolidWorks to build a 3D geometric model of the chip and simplify non-critical structures.

[0061] The measured geometric dimensions refer to the assembly parameters that support cross-scale simulations, specifically: Chip-level dimensions: The total gate width of the B4 chip, measured with an optical microscope and calipers, is 12mm (4 units, 300μm per gate) and the total gate width of the B7 chip is 16.5mm (6 units, 275μm per gate), etc.

[0062] Step 2.2: Assign thermophysical properties to each layer of material, wherein the thermal conductivity of GaN and SiC materials is set to vary with temperature, and the measured interfacial thermal resistance is set at the GaN / SiC interface.

[0063] Step 2.3: Set up heat sources of different sizes and locations for different operating states of the device.

[0064] Based on the drain-source voltage V acquired during the DC test in step 1 ds Drain-source current I ds The data is used to determine the knee voltage of the device, thereby judging the device's operating state; based on the judgment result, the corresponding heat source type is selected, and the heat flux density is calculated based on the measured data from step 1 and then input into the model. ① Saturated region heat source (V ds ≤ Knee voltage): Select a uniform surface heat source that covers the entire two-dimensional electron gas channel region between the source and drain.

[0065] Wherein, heat flux density = total heat loss / saturation region heat source width; total heat loss = measured drain-source voltage V in step 2. ds ×Measured drain source current I ds The width of the heat source in the saturation zone = the width of a single grid finger × the number of grid finger units.

[0066] ②Heat source in the amplified region (V) ds >Knee voltage: Select a localized concentrated surface heat source located below the gate and near the drain side.

[0067] Wherein, heat flux density = total heat loss / width of heat source in amplified region; total heat loss = measured drain-source voltage V in step 2. ds ×Measured drain source current I ds , the width of the heat source in the amplified area = the width of a single grid finger × the number of grid finger units. (3) Definition of heat source size: the width of the heat source is consistent with the width of a single grid finger. For example, the length of the heat source in the saturated area is set to 5.4 μm according to the actual extension range of the channel, and the length of the heat source in the amplified area is set to 0.2 μm according to the local hot spot concentration area.

[0068] Step 2.4: Compare and iterate the simulated chip surface temperature obtained under different operating conditions with the thermal test data, and adjust the size of the channel heat source so that the error between the simulated surface temperature and the measured temperature is ≤10%.

[0069] The simplification of the structure in step 3.1 includes: (1) simplifying the elliptical grounding hole of the chip into a rectangular hole with equal area; (2) simplifying the multi-layer pad structure of the source and drain into a single-layer cuboid structure.

[0070] Step 3.2 The thermophysical properties of each layer of material are defined as follows: (1) The thermal conductivity of GaN material is expressed as: 231×(300 / T) 1.4 , where T is the absolute temperature; (2) The thermal conductivity of SiC material is: 410×(300 / T) 1.49 (3) The interfacial thermal conductivity corresponding to the GaN / SiC interface thermal resistance is: 180MW / (m 2 ·K); (4) Thermal conductivity of other materials: Si3N4 is 33W / (m·K), Au is 311W / (m·K) (at 400K), conductive silver paste is 213W / (m·K), molybdenum-copper alloy is 180W / (m·K), and pure copper is 413W / (m·K).

[0071] Step 3.3 Setting up heat sources of different sizes and positions includes: (1) Saturation region heat source: a uniform planar heat source covering the entire two-dimensional electron gas channel region between the source and the drain, with a width equal to the width of a single gate finger and a length of 5.4 μm; (2) Amplification region heat source: a local area located below the gate near the drain, with a width equal to the width of a single gate finger and a length of 0.2 μm.

[0072] In practical applications, step 3 includes the following steps: Step 3.1: Based on the measured geometric dimensions, use SolidWorks to build package-level and module-level 3D geometric models, and simplify non-critical structures.

[0073] The measured geometric dimensions refer to the assembly parameters that support cross-scale simulation, specifically: ① Package-level dimensions: length, width, and thickness of the molybdenum-copper substrate of the 780-4 package, area of ​​conductive silver paste coating, dimensions of the alumina ceramic shell, and dimensions of the chip's assembly position within the package after opening.

[0074] ② Heat dissipation module dimensions: The microchannel adapter board has a channel width of 0.1mm, a height of 0.25mm, a baffle column size of 0.4mm×0.1mm×0.25mm, an RO4350B substrate thickness of 0.51mm on the PCB board, and a metallized via diameter of 0.5mm / 2mm.

[0075] Step 3.2: Integrate the simplified and parameterized chip-level model into the package-level model, or further integrate the package-level model into the module-level model. Set the corresponding boundary conditions according to the thermal test experiments of different heat dissipation scenarios to complete the construction of the cross-scale three-dimensional thermal model.

[0076] Step 3.3: Compare and iterate the simulated chip surface temperature obtained under different operating conditions with the thermal test data to ensure that the maximum absolute deviation between the simulated value and the measured value does not exceed 11℃ and the maximum relative deviation does not exceed 10%.

[0077] The simplification of the structure includes: (1) removing the alumina ceramic tube shell on the top of the package and retaining only the molybdenum copper substrate and the conductive silver paste layer; (2) extracting the complex flow channel structure of the microchannel heat dissipation module into an equivalent heat exchange surface to simplify the difficulty of mesh generation.

[0078] The specific methods for constructing the encapsulation-level multi-scale thermal model in step 3.2 include: In SolidWorks, 3D geometric models of the package and microfluidic heat dissipation module were created separately and imported into ANSYS SpaceClaim for simplification. The simplified package and heat dissipation module models were then imported into ICEPAK. A pre-parameterized single-chip thermal model was retrieved from a pre-built chip model library and precisely assembled onto the corresponding position on the package substrate, integrating and constructing a unified "chip-package" multi-scale 3D thermal model. Furthermore, after the single-chip thermal model was integrated onto the package substrate, it was further integrated with the heat dissipation module to construct a unified "chip-package-module" multi-scale 3D thermal model; for example... Figure 3 As shown, where Figure 3 (a) in the image is an exploded view. Figure 3 (b) in the diagram is the encapsulation structure diagram.

[0079] Methods for setting boundary conditions include: (1) Baseline heat dissipation scenario (water-cooled plate): The bottom temperature of the model is set according to the actual temperature of the bottom of the package measured by the thermocouple in the thermal test experiment, and the convective heat transfer coefficient calibrated by the experimental data is applied.

[0080] (2) Variable heat dissipation scenario (microchannel): The convective heat transfer coefficient under different cooling fluid flow rates was extracted by ANSYS FLUENT and assigned to the equivalent heat transfer surface of the microchannel. The inlet temperature of the cooling fluid was set to the experimental measured value.

[0081] (3) In all scenarios, all external surfaces of the model except for the heat dissipation boundary are set as adiabatic boundaries, ignoring natural air convection and radiation heat transfer.

[0082] Parameterized T channel –P d Predictive models in P dThe method is effective within the range of 0–5.28 W / mm and cooling fluid flow rate of 60–300 mL / min. The method provided in this application is applicable to GaN HEMT chips with different gate widths and cell counts, including: a B4 chip with a gate width of 300 μm, 4 cells, and a total gate width of 12 mm, and a B7 chip with a gate width of 275 μm, 6 cells, and a total gate width of 16.5 mm.

[0083] This application in the field of semiconductor device thermal management technology combines thermal testing experiments (including different heat dissipation conditions), three-dimensional package-level simulation, and multi-dimensional parameterized fitting to achieve high-precision and fast-calculation prediction of GaN HEMT channel peak temperature under different operating states and heat dissipation scenarios, providing comprehensive support for device thermal design, heat dissipation scheme optimization, and reliability assessment.

[0084] This application has the following advantages: (1) Real heat source modeling: Based on the actual GaN HEMT chip thermal test experimental data, the heat source is set independently for the thermal test system under different working conditions, so that the heat source setting of the three-dimensional thermal model fits the actual heating characteristics of the device, avoiding the prediction deviation caused by the traditional simplified heat source. After experimental calibration, the simulation-experiment error is ≤5%.

[0085] (2) Cross-scale integrated modeling: realize cross-scale unified thermal modeling from chip micro channels and packaging structure to macro heat dissipation module, fully restore the heat conduction path, and accurately reflect the influence of different levels of structure on thermal characteristics.

[0086] (3) Multi-scenario range adaptation: The model integrates experimental and simulation data under fixed and variable heat dissipation conditions, and can be adapted to various heat dissipation schemes such as water cooling and microfluidic channels to meet the temperature prediction needs of different application scenarios.

[0087] (4) High accuracy and fast prediction: The parametric prediction model does not require repeated finite element simulation and can quickly output the peak channel temperature T. channel It is suitable for thermal design optimization, heat dissipation scheme selection and rapid reliability assessment of high-power, high-frequency GaN HEMT devices.

[0088] In another exemplary embodiment, the channel temperature prediction method for GaN HEMT chips, in practical applications, includes the following steps: Step 1: Thermal Testing Experiment: The thermal response data of the chip under actual operating conditions is obtained through experiments for subsequent model calibration and verification. The GaN HEMT chip contains, for example... Figure 1 The actual device structure is shown.

[0089] Specifically, the vacuum-sealed 780-4 package chip is opened by removing the top alumina ceramic casing, directly exposing the internal chip surface. The opened chip is then soldered onto a rectangular pure copper sheet using conductive silver paste. Silicone is used to adhere a copper-plated substrate to achieve electrical isolation and wiring between the gate and drain. Isolation lines are then drawn on the copper-plated substrate using a file. Finally, a thermal testing fixture is mounted on a copper water-cooled plate, with a high thermal conductivity silicone pad and a thermocouple placed between them. The water-cooled plate is connected to a constant-temperature water bath for temperature control.

[0090] like Figure 2 As shown, where, Figure 2 (a) in the diagram is a schematic diagram of the baseline heat dissipation scenario. Figure 2 (b) in the diagram is a schematic diagram of a variable heat dissipation scenario. The experimental system mainly includes: two DC power supplies (used to apply V respectively). gs and V ds The system includes an infrared thermal imager equipped with a macro lens (model FOTRIC 248M-M20, spatial resolution 20μm, temperature range -20℃ to 650℃, measurement accuracy ±2℃) and a constant temperature water bath. The highest surface temperature of the chip is acquired and recorded in real time using AnalyzIR software connected to the infrared thermal imager via a laptop.

[0091] Specifically, before the experiment began, the external environmental conditions, the temperature of the sample assembly substrate, and the thermal boundary conditions were monitored. (1) External environmental conditions: The experiment was conducted at room temperature, and a constant temperature water bath was used to control the temperature of the cooling medium.

[0092] (2) Substrate temperature monitoring: At the contact interface between the thermal testing fixture and the water-cooled plate, a thermocouple is used to monitor and record the temperature (T) at the bottom of the assembled substrate in real time. bottom ).

[0093] (3) Extraction of thermal boundary conditions: monitoring T bottom The fluctuation range was monitored to confirm that the experiment had reached a thermal steady state; the inlet temperature and flow rate of the cooling medium were monitored and recorded simultaneously to ensure stable flow rate.

[0094] Specifically, the experiment was conducted according to the following procedure: (1) Start voltage measurement: at V gs =-5V、V ds Under the condition of 5V, V gs Scan from -5V to 2V, simultaneously record drain-source current I ds Determine the chip's turn-on voltage.

[0095] (2) DC characteristic test: set V respectively gs The voltage ratings are -2V, -1V, 0V, 1V, 2V, and 3V. At each fixed voltage level... gsNext, V ds Gradually increase the voltage from 0V to 12V (in 1V increments). After ensuring the temperature at each test point stabilizes, simultaneously record the highest surface temperature of the chip (T). surface ), tooling bottom temperature (T) bottom ) and drain-source current (I ds ), and calculate the heat dissipation power density P per unit grid width according to the formula. d =V ds ×I ds / Total grid width.

[0096] Through systematic analysis of experimental data, using T... surface -P d The relationship curve predicts the chip channel temperature and accurately reflects the effect of self-heating on temperature.

[0097] Step 2: Construction of the thermal model for the GaN HEMT chip thermal testing system.

[0098] 2.1 Constructing the 3D geometric model of the 780-4 chip: To obtain the structural features of the 780-4 chip, a three-dimensional geometric model of the chip was built using SolidWorks based on measured geometric dimension data. Figure 4 As shown, non-critical structures are simplified. This includes simplifying the elliptical grounding vias to rectangular vias of equal area, reducing the multi-layer source / drain electrode pad structure to a single layer, and decreasing the number of mesh elements.

[0099] 2.2 Assigning parameters to the 3D geometric model of the 780-4 chip: Since the simulated thermal model contains temperature-dependent material properties, these should be obtained based on experimental data first. Specifically, the thermal conductivity of GaN and SiC are defined as functions of temperature: k_GaN = 231 × (300 / T) 1.4 k_SiC = 410 × (300 / T) 1.49 The room-temperature thermal conductivity and interfacial thermal resistance parameters of the material were obtained through actual measurement using the time-domain thermal reflectometry (TDTR) method. At the interface between the SiC substrate and the GaN epitaxial layer, the interfacial thermal resistance was set based on these measurement results, with a corresponding interfacial thermal conductivity of 180 MW / (m²). 2 The thermal conductivity of other materials is as follows: Si3N4 is 33 W / (m·K), Au is 311 W / (m·K) (at 400K), conductive silver paste is 213 W / (m·K), molybdenum-copper alloy is 180 W / (m·K), and pure copper is 413 W / (m·K).

[0100] The boundary conditions of the thermal model are set as follows: Based on the simulation conditions, the bottom surface of the SiC layer is set with a corresponding temperature boundary according to the actual heat dissipation conditions; except for the bottom surface, all other outer surfaces of the model are set as adiabatic boundaries to simulate the main heat dissipation path in the experiment.

[0101] 2.3 Setting up the heat source for the 780-4 chip thermal model: Obtain the electrical bias parameters (gate-source voltage V) of the 780-4 package according to step 1. gs Drain-source voltage V ds Drain-source current I ds DC characteristic test results; set corresponding heat sources for different working states for the three-dimensional geometric model of the chip: when the drain-source voltage ≤ knee voltage, set the saturation region heat source; when the drain-source voltage > knee voltage, set the amplification region heat source.

[0102] (1) Saturation region heat source: set as a uniform planar heat source covering the entire two-dimensional electron gas channel from the source to the drain, with a length equal to the source-drain distance of 5.4 μm and a width equal to the gate width of a single gate finger.

[0103] (2) Heat source in the amplification region: It is set as a local planar heat source concentrated on the drain side below the gate, with a length of 0.2μm and a width equal to the gate width.

[0104] 2.4 Setting boundary conditions for the 780-4 chip thermal model: Based on the measured data from the thermal test experiment: (1) Bottom boundary: Based on the experimentally measured bottom temperature (T) of the package bottom Set the corresponding temperature value and add the convective heat transfer coefficient h obtained by back-deriving experimental data to accurately simulate the heat dissipation effect of the water-cooled plate.

[0105] (2) Other surfaces: Since the heat transfer from natural air convection and radiation is much smaller than the heat transfer dominated by the chip, it is considered negligible in the simulation. All outer surfaces of the model except the bottom boundary are set as adiabatic boundaries.

[0106] Specifically, the convective heat transfer coefficient h is obtained through the following iterative calibration process: a. Run the simulation: Perform a thermal simulation using the currently set h value, calculate the temperature distribution on the chip surface, and extract the highest temperature T on the chip surface obtained from the simulation. surface_sim .

[0107] b. Compare experimental data: T surface_sim The highest actual chip surface temperature T measured experimentally under the same power consumption conditions. surface_exp Compare them.

[0108] c. Judgment and Correction: If Tsurface_sim >T surface_exp This indicates that the current h value is too small, and the h value needs to be increased in the next iteration.

[0109] If T surface_sim <T surface_exp This indicates that the current h value is too large, and the h value needs to be reduced in the next iteration.

[0110] d. Iterative loop: Repeat step ac, continuously adjusting the value of h, until T. surface_sim With T surface_exp If the difference is within an acceptable error range, the current h value is extracted as the equivalent convective heat transfer coefficient.

[0111] In practical applications, a model is first constructed, and then heat sources and boundary conditions are set. Thermophysical properties, heat sources, and boundary conditions are assigned to the geometric model, and numerical solutions and calibrations are completed using simulation software. The thermal model of the single chip after parameterization is then saved as a single-chip model.

[0112] Step 3: Construction of cross-scale three-dimensional thermal models and thermal simulation methods.

[0113] 3.1 Model Construction and Integration: Based on measured chip and package geometry, a cross-scale thermal model was established and integrated using the following procedure: (1) Geometric modeling: SolidWorks software was used to create the overall encapsulated three-dimensional geometric model.

[0114] (2) Model simplification and import: Export the model as STEP format and import it into ANSYS SpaceClaim for simplification. For the encapsulation model, delete structures with little impact on heat dissipation (such as the top alumina ceramic tube shell), and retain only key heat dissipation paths such as the molybdenum copper substrate and the conductive silver paste layer.

[0115] (3) Model integration: The simplified package model is imported into ANSYS ICEPAK, and the single-chip model is retrieved through the parametric model library and precisely assembled into the specified position in the package to form a complete package-level cross-scale thermal model, i.e., a three-dimensional cross-scale thermal model.

[0116] Step 4: Extraction of thermal properties and establishment of parameterized prediction model: 4.1 Model Validation and Basic Thermal Property Extraction: Under fixed heat dissipation conditions, simulations were performed using the package-level cross-scale thermal model described in step 3, as follows: Figure 5 As shown, different electrical biases (V) are extracted. gs V ds Peak channel temperature (T) under these conditions channel ) and shell thermal resistance (R jcBy comparing the simulation results with thermal test data under corresponding conditions and iteratively calibrating the model parameters, the surface temperature (T) predicted by the simulation is improved. surface The results showed that the infrared measured values ​​were consistent with the actual values, with a maximum absolute deviation of ≤11°C and a maximum relative deviation of ≤10%, thus completing the verification of the model under the reference heat dissipation conditions.

[0117] 4.2 Extraction of thermal characteristic laws under variable heat dissipation conditions: To establish a universal temperature prediction model, the impact of changes in heat dissipation conditions needs further investigation: (1) Conduct experiments under varying heat dissipation conditions: such as Figure 2 As shown, thermal testing was performed on a single-chip module with an integrated microchannel heat sink. The flow rate of the cooling medium (deionized water) was adjusted (60-300 mL / min), and different V values ​​were measured. gs (-1V, 0V, 1V), V ds Chip surface temperature (T) at (0-10V) and flow rate surface ) and drain current (I ds ).

[0118] (2) Establish an extended simulation model: Modify the copper water-cooled plate in the model of step 3 to achieve the purpose of changing heat dissipation conditions. Use a microchannel module-level model to establish a module-level three-dimensional model including microchannels, PCB board (including metallized vias with equivalent thermal conductivity) and heat dissipation base plate, such as Figure 6 As shown, the equivalent convective heat transfer coefficients under different flow rates were extracted using ANSYS FLUENT and substituted into the thermal model for simulation. Diverse data were obtained by adjusting heat dissipation conditions to expand the parametric temperature prediction model library.

[0119] (3) Extraction of the thermal-electrical-heat dissipation coupling relationship: Based on experimental and simulation data, the system extracts the thermal-electrical-heat dissipation coupling relationship under different cooling flow rates and different operating biases. channel and R jc With unit grid width, the heat dissipation power density P d The variation pattern was observed. Similarly, under varying heat dissipation conditions, the maximum absolute deviation was kept ≤11°C and the maximum relative deviation was kept ≤10%, thus completing the verification of the three-dimensional thermal model.

[0120] Step 5: Construction of the parameterized temperature prediction model library: For the large amount of data obtained in steps 3-4 under fixed or varying heat dissipation conditions, a quadratic polynomial fitting method is used to establish a working state (saturation region / amplification region), P dThe method employs multi-dimensional parameterized temperature prediction curves with heat dissipation conditions as key input parameters. This constitutes a rapid thermal management prediction model library: in practical applications, only the device's operating area, current power consumption, and heat dissipation conditions need to be determined; by querying the corresponding parameterized relationships, the channel peak temperature can be predicted quickly and accurately without complex real-time three-dimensional finite element simulations, greatly improving the efficiency of thermal design evaluation.

[0121] In one exemplary embodiment, a method for constructing a channel temperature prediction model for a B4 chip is also provided.

[0122] like Figure 7 As shown, where, Figure 7 (a) in the image is a physical diagram of the chip. Figure 7 (b) in the diagram is a 3D geometric model diagram, showing the total gate width (W) of the B4 chip. g_B4 The size is 12 mm, consisting of 4 unit models, each containing 10 gate fingers, with a gate width of 300 μm for each gate finger; turn-on voltage: -2.8V; source-drain spacing: 5.4 μm.

[0123] Step 1: Chip input parameter settings.

[0124] Under DC characteristic testing, the knee voltage was measured to be approximately 6V.

[0125] In V gs =1 V, V ds Under the condition of =10 V, I ds =5.40A; Maximum total heat dissipation power P total =V ds ×I ds =54 W; Power density per unit grid width (P) d= P total / W g_B4 =4.5W / mm; at this time, the highest temperature T on the chip surface measured by the infrared thermal imager is... surface The temperature is 255℃.

[0126] Step 2: Establish rules for determining the working status of the B4 chip.

[0127] (1) Input electrical bias parameters: Obtain the electrical bias (gate-source voltage V) of the B4 chip in actual application. gs and drain-source voltage V ds ) and input current I ds .

[0128] (2) Calling the working state: According to the DC characteristic test results, the knee voltage is 6V; when V gs When V = 1V (> -2.8V), V ds ≤6V is the saturation region, V ds >6V is the amplification region.

[0129] (3) Execution judgment: Current V gs =1V、V ds =10V>6V, indicating that the B4 chip is operating in the amplification region.

[0130] (4) Output heat source parameters: Based on the judgment result, set the heat source parameters corresponding to the amplified area - local planar heat source, with a size of 0.2μm×300μm.

[0131] Step 3: Determine the heat dissipation boundary conditions.

[0132] 3.1 Identification of heat dissipation method: Based on the application scenario input, it was determined that the B4 chip adopts the baseline heat dissipation scenario and has no additional heat dissipation enhancement structure.

[0133] 3.2 Boundary Parameter Extraction and Calibration: (1) Determination of bottom temperature: The measured value T corresponding to similar power consumption under the same heat dissipation scenario was retrieved from the experimental database. bottom =58.6℃.

[0134] (2) Calibration of convective heat transfer coefficient h: a. Set an initial h value and perform simulation to obtain the highest temperature T on the chip surface. surface_sim .

[0135] b. Compare T under the same operating conditions in the experimental database. surface_exp .

[0136] c. Adjust the value of h iteratively until T is reached. surface_sim With T surface_exp If the deviation Δ is less than 5%, the calibration is complete.

[0137] (3) Fixed boundary parameters: The final heat dissipation boundary conditions were determined as follows: bottom temperature 58.6℃, calibrated equivalent convective heat transfer coefficient h, thermal insulation of the outer surface of the model, and GaN / SiC interface thermal conductivity 180MW / (m²). 2 ·K).

[0138] Step 4: Call up the cross-scale thermal model and match it with the database.

[0139] 4.1 Model Invocation: The package-level model of the B4 chip is retrieved from the pre-established cross-scale model library of "chip-packaging-heat dissipation".

[0140] 4.2 Parameter Matching: The simplified geometric model of the B4 chip is invoked, and the thermal conductivity function varying with temperature and the thermal conductivity of other materials are loaded. Based on the operating status judgment, a heat source (0.2μm×300μm) for the amplification region is loaded, and the current P is input. d=4.5W / mm.

[0141] Step 5: Calculate channel temperature and verify data accuracy.

[0142] 5.1 Channel temperature T channel calculate: Running the matched cross-scale thermal model, the B4 chip was extracted in V through simulation. gs =1V、V ds =10V, P d Peak channel temperature under conditions of 4.5 W / mm, such as Figure 9 As shown in (a), Figure 9 In the diagram (a), the B4 chip is represented by different V values ​​in the 780-4 package level model. gs The T-channel prediction curve below yields T channel_cal =269.63℃.

[0143] 5.2 Data accuracy assessment: (1) Comparison with calibration dataset: retrieve T under the same working conditions from the calibration dataset (simulation data verified by experiments) in the model library. channel_ref =267.77℃, calculated absolute deviation ΔT=1.86℃, relative deviation δ=0.69%; meets the accuracy requirement, T is determined to be... channel_cal =269.63℃ is a valid prediction result.

[0144] 5.3 Rapid prediction and validation of parametric models: Call the pre-established parameterized prediction model for the B4 chip amplification region: T channel =5.8596P d 2 +28.1P d +17.708 (correlation coefficient R) 2 =0.9962), substitute into P d =4.5W / mm, T is calculated channel_pred =262.8149℃, with a deviation of only 6.8151℃ from the simulation result.

[0145] In another exemplary embodiment, a method for constructing a channel temperature prediction model for the B7 chip is also employed. In this embodiment, the basic operations are the same as in the above embodiments, specifically as follows: like Figure 8 As shown, where, Figure 8 (a) in the image is a physical diagram of the chip. Figure 8 (b) in the diagram is a 3D geometric model diagram, showing the total gate width (W) of the B7 chip. g_B7The size is 16.5 mm, consisting of 6 unit models, each containing 10 gate fingers, with a gate width of 275 μm for each gate finger; turn-on voltage: -3.3V; source-drain spacing: 5.4 μm.

[0146] Step 1: Chip input parameter settings.

[0147] Under DC characteristic testing, the knee voltage was measured to be approximately 6V.

[0148] In V gs =1 V, V ds Under conditions of 10V and a flow rate of 300mL / min, I was measured ds =472.12 mA / mm; Maximum total heat dissipation power P total =77.9W; Power density per unit grid width P d= P total / W g_B7 =4.721W / mm; at this time, the highest temperature T on the chip surface measured by the infrared thermal imager is... surface It is 274℃.

[0149] Step 2: Establish rules for determining the working status of the B7 chip.

[0150] (1) Input electrical bias parameters: Obtain the electrical bias (gate-source voltage V) of the B7 chip in actual application. gs and drain-source voltage V ds ) and input current I ds .

[0151] (2) Calling the working state: According to the DC characteristic test results, the knee voltage is 6V; when V gs When V = 1V (> -3.3V), V ds ≤6V is the saturation region, V ds >6V is the amplification region.

[0152] (3) Execution judgment: Current V gs =1V、V ds =10V>6V, indicating that the B7 chip is operating in the amplification region.

[0153] (4) Output heat source parameters: Call the heat source parameters corresponding to the magnified area - local planar heat source, with a size of 0.2μm×275μm, which is compatible with the microchannel heat dissipation model.

[0154] Step 3: Determine the heat dissipation boundary conditions for the microchannel.

[0155] 3.1 Heat dissipation scenario identification: Based on the application scenario input, it was determined that the B7 chip adopts an active heat dissipation scheme with embedded microchannels, the cooling medium is deionized water, and the flow rate is set to 300mL / min.

[0156] 3.2 Boundary Parameter Extraction and Calibration: (1) Determination of convective heat transfer coefficient h: The h value corresponding to a flow rate of 300 mL / min was retrieved from the microchannel h database as h = 269565.85 W / (m³). 2 ·K).

[0157] (2) Cooling medium inlet temperature correction: The inlet water temperature of the microchannel is monitored in real time and is 20℃.

[0158] (3) Temperature T at the bottom of the package bottom Correction: Retrieve the measured value T under the same operating conditions from the experimental database. bottom =47.3℃.

[0159] (4) Final boundary conditions: Equivalent heat transfer surface of microchannel h = 269565.85 W / (m 2 ·K), inlet temperature 20℃; bottom temperature of encapsulation 47.3℃; outer surface of the model is insulated (ignoring air convection and radiation).

[0160] Step 4: Call up the cross-scale thermal model and match it with the database.

[0161] (1) Model call: retrieve the module-level model of the B7 chip (including the simplified structure of the microchannel, which is equivalent to the heat exchange surface) from the “chip-package-module” cross-scale model library.

[0162] (2) Parameter matching: Load the simplified geometric model of B7, the thermal conductivity function as a function of temperature, and the interfacial thermal conductivity; based on the working state judgment results, match the heat source for the amplification area (0.2μm×275μm), and input the current P. d =4.315 W / mm; the corresponding h for a flow rate of 300 mL / min is 269565.85 W / (m 2 ·K) and the corrected inlet temperature, T bottom .

[0163] Step 5: Calculate channel temperature and verify data accuracy.

[0164] Running the matched cross-scale thermal model, the B7 chip was extracted in V through simulation. gs =1V、V ds =10V, P d The peak channel temperature under conditions of 4.721 W / mm² and a flow rate of 300 mL / min, such as... Figure 9 As shown in (b), Figure 9 (b) in the figure represents the B7 chip in different V values ​​in the 780-4 package level model. gs The T-channel prediction curve below yields Tchannel_cal =234.63℃.

[0165] Optionally, for different V gs Further testing was conducted under different traffic conditions, and V... ds Changes on T channel Influence curve T channel_- V ds ,like Figure 10 As shown, Figure 10 (a) in the text refers to the B7 chip in V. gs When V = -1V, different V values ​​are present in the microchannel module-level model. ds T under influent flow rate channel Prediction curve, Figure 10 (b) in the text refers to the B7 chip in V. gs When V = 0V, different V values ​​are present in the microchannel module-level model. ds T under influent flow rate channel Prediction curve, Figure 10 (c) in the text refers to the B7 chip in V. gs When V = 1V, different V values ​​are present in the microchannel module-level model. ds T under influent flow rate channel Prediction curves are shown, with each curve testing the flow rate at 60 mL / min, 80 mL / min, 100 mL / min, 200 mL / min, and 300 mL / min. For example... Figure 10 As shown in (c), the flow rate was reduced to 60 mL / min (h = 78913.45 W / (m²)). 2 ·K), same as V gs =1V、V ds =10V, P d =4.721W / mm, simulation yields T channel_cal =303.74℃.

[0166] Based on the same inventive concept, this application also provides a channel temperature prediction device for a GaN HEMT chip for implementing the channel temperature prediction method for the GaNHEMT chip described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more GaNHEMT chip channel temperature prediction device embodiments provided below can be found in the limitations of the channel temperature prediction method for GaN HEMT chips described above, and will not be repeated here.

[0167] In one exemplary embodiment, such as Figure 13 As shown, a channel temperature prediction device for a GaN HEMT chip is provided, comprising: The first thermal testing module is used to conduct thermal testing experiments on the GaN HEMT chip and obtain a multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the multi-dimensional experimental dataset includes the gate-source voltage V. gs Drain-source voltage V ds Heat dissipation conditions, surface temperature, bottom temperature, drain-source current, and heat dissipation power density per unit gate width.

[0168] The acquisition module is used to obtain the actual device structure parameters of the GaN HEMT chip.

[0169] The first construction module is used to construct a thermal model of the thermal testing system based on the actual device structure parameters.

[0170] The first simulation module is used to set the thermal boundary conditions and channel heat source for the thermal model based on the multi-dimensional experimental dataset corresponding to the GaN HEMT chip. The thermal boundary conditions of the thermal model are the same as those of the thermal test experiment. When the drain-source voltage of the operating state is less than or equal to the knee voltage, the channel heat source in the thermal model is a uniform surface heat source covering the channel. When the drain-source voltage of the operating state is greater than or equal to the knee voltage, the channel heat source in the thermal model is a local surface heat source covering the drain side under the gate.

[0171] The second building module is used to construct a three-dimensional geometric model based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales.

[0172] An assembly module is used to assemble the thermal model into the multi-scale three-dimensional geometric model to obtain a three-dimensional thermal model.

[0173] The second thermal testing module is used to conduct thermal testing experiments on the three-dimensional thermal model to obtain a multi-dimensional experimental dataset of the three-dimensional thermal model.

[0174] The third construction module is used to construct a multi-dimensional parameterized temperature prediction curve based on the three-dimensional thermal model and the multi-dimensional experimental dataset of the three-dimensional thermal model. The multi-dimensional parameterized temperature prediction curve takes the operating state, power density and heat dissipation conditions as input parameters and the channel peak temperature as the output parameter. The multi-dimensional parameterized temperature prediction curve is used to predict the channel temperature.

[0175] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 14As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores channel temperature prediction data for GaN HEMT chips. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for predicting the channel temperature of GaN HEMT chips.

[0176] Those skilled in the art will understand that Figure 14 The structures shown are merely block diagrams of some structures related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method embodiments.

[0177] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the above-described method embodiments.

[0178] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method embodiments.

[0179] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0180] In this application, all actions to acquire signals, information, or data are carried out in compliance with the relevant data protection laws and policies of the country where the location is situated, and with the authorization granted by the owner of the relevant device.

[0181] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0182] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0183] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0184] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for predicting the channel temperature of a GaN HEMT chip, characterized in that, include: A thermal testing experiment was conducted on a GaN HEMT chip to obtain a multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the multi-dimensional experimental dataset includes the gate-source voltage V. gs Drain-source voltage V ds Heat dissipation conditions, surface temperature, bottom temperature, drain-source current, and heat dissipation power density per unit gate width; Obtain the actual device structure parameters and cross-scale actual device structure parameters of GaN HEMT chips; A thermal model of the thermal testing system is constructed based on the actual device structure parameters of the GaN HEMT chip. Based on the thermal test experiment and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip, thermal boundary conditions and channel heat sources are set for the thermal model under different operating conditions; the thermal boundary conditions of the thermal model are the same as those of the thermal test experiment; when the drain-source voltage of the operating state is less than or equal to the knee voltage, the channel heat source in the thermal model is a uniform surface heat source covering the channel; when the drain-source voltage of the operating state is greater than or equal to the knee voltage, the channel heat source in the thermal model is a local surface heat source covering the drain side under the gate. A cross-scale three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales. The thermal model is assembled into the multi-scale three-dimensional geometric model to obtain a three-dimensional thermal model; The three-dimensional thermal model was subjected to thermal testing experiments to obtain a multi-dimensional experimental dataset of the three-dimensional thermal model. A multidimensional parameterized temperature prediction curve is constructed based on the three-dimensional thermal model and the multidimensional experimental dataset of the three-dimensional thermal model. The multidimensional parameterized temperature prediction curve takes the operating state, power density and heat dissipation conditions as input parameters and the channel peak temperature as output parameter. The multidimensional parameterized temperature prediction curve is used to predict the channel temperature.

2. The method for predicting the channel temperature of a GaN HEMT chip according to claim 1, characterized in that, A thermal testing experiment was conducted on the GaN HEMT chip to obtain a multi-dimensional experimental dataset for the GaN HEMT chip, specifically including: The control system connects the gate-source voltage and drain-source voltage of the GaN HEMT chip respectively, and acquires the surface temperature; the surface temperature is acquired in real time by an infrared thermal imager aligned with the surface of the GaN HEMT chip. Multiple DC tests were performed by controlling and adjusting the gate-source voltage and drain-source voltage, and the thermal test data of the GaN HEMT chip surface temperature after steady state were recorded in each test. The thermal test data of each test included the gate-source voltage, drain-source voltage, highest surface temperature, bottom temperature of the package, and drain-source current. The multi-dimensional experimental dataset corresponding to the GaN HEMT chip is determined based on the thermal test data after the surface temperature of the GaN HEMT chip has reached steady state in each test group.

3. The method for predicting the channel temperature of a GaN HEMT chip according to claim 1, characterized in that, The actual device structure parameters of the GaNHEMT chip and the actual device structure parameters across scales both include geometric models and model parameters. The geometric model includes: a source electrode, a drain electrode, a gate electrode, a source field plate, a passivation layer, a barrier layer, a GaN channel layer, and a GaN buffer layer; wherein the material of the passivation layer is SiO2 or Al2O3; and the material of the barrier layer is AlGaInN, AlInN, or InAlN. The model parameters include: barrier layer thickness, Al molar mass fraction, doping concentration, GaN channel layer thickness, and GaN buffer layer thickness.

4. The method for predicting the channel temperature of a GaN HEMT chip according to claim 1, characterized in that, A thermal model for the thermal testing system is constructed based on the actual device structure parameters of the GaN HEMT chip, specifically including: Construct an actual geometric model based on the actual device structure parameters of the GaN HEMT chip; The non-critical structures in the actual geometric model are simplified to obtain the thermal model of the thermal testing system. The simplification of the non-critical structures includes: simplifying the elliptical grounding hole into a rectangular hole with equal area and simplifying the multi-layer pad structure of the source and drain into a single-layer cuboid structure.

5. The method for predicting the channel temperature of a GaN HEMT chip according to claim 1, characterized in that, Based on the thermal testing experiments and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip, thermal boundary conditions and channel heat sources under different operating conditions are set for the thermal model, specifically including: The location and distribution of the channel heat source are determined based on the drain-source voltage of the thermal test experiment. The thermal boundary conditions are determined based on the multi-dimensional experimental dataset corresponding to the GaN HEMT chip. The boundary conditions, the location and distribution of the channel heat source are set on the thermal model and simulated. The size of the channel heat source is adjusted so that the error between the simulated surface temperature and the measured temperature is ≤10%.

6. The method for predicting the channel temperature of a GaN HEMT chip according to claim 1, characterized in that, Based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales, a cross-scale three-dimensional geometric model is constructed, specifically including: Construct a cross-scale initial geometric model using the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales; The non-critical structures of the initial cross-scale geometric model are simplified to obtain a cross-scale three-dimensional geometric model. The simplification of the non-critical structures includes: removing the alumina ceramic tube shell on the top of the package and retaining the molybdenum copper substrate and the conductive silver paste layer and / or extracting the complex flow channel structure of the heat dissipation module into an equivalent heat exchange surface.

7. The method for predicting the channel temperature of a GaN HEMT chip according to claim 6, characterized in that, Constructing a cross-scale initial geometric model using the actual device structure parameters of the GaNHEMT chip and the cross-scale actual device structure parameters specifically includes: A chip-level three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip. When the actual device structure parameters of the cross-scale are the actual device structure parameters of the packaged chip, SolidWorks is used to build the packaging module based on the actual device structure parameters of the packaged chip. The chip-level three-dimensional geometric model is assembled into the packaging module to obtain a cross-scale initial geometric model.

8. The method for predicting the channel temperature of a GaN HEMT chip according to claim 6, characterized in that, Constructing a cross-scale initial geometric model using the actual device structure parameters of the GaNHEMT chip and the cross-scale actual device structure parameters specifically includes: A chip-level three-dimensional geometric model is constructed based on the actual device structure parameters of the GaN HEMT chip. When the actual device structure parameters across scales include the actual device structure parameters of package-level chips and the actual device structure parameters of module-level chips, a package module is built using SolidWorks based on the actual device structure parameters of package-level chips; and a module model is built using SolidWorks based on the actual device structure parameters of module-level chips, the module model including a heat dissipation module. The chip-level 3D geometric model is assembled into the packaging module, and the assembled packaging module is then assembled into the module model to obtain cross-scale initial geometric models.

9. The method for predicting the channel temperature of a GaN HEMT chip according to any one of claims 1, 7, or 8, characterized in that, Also includes: The simulated values ​​and measured values ​​of the thermal test data obtained using the three-dimensional thermal model are compared and iterated. When the maximum absolute deviation between the simulated value and the measured value does not exceed 11℃ and the maximum relative deviation does not exceed 10%, the calibration of the three-dimensional thermal model is completed.

10. The method for predicting the channel temperature of a GaN HEMT chip according to claim 1, characterized in that, Based on the aforementioned three-dimensional thermal model and its multi-dimensional experimental dataset, a multi-dimensional parameterized temperature prediction curve is constructed, specifically including: Based on the three-dimensional thermal model and the multi-dimensional experimental dataset of the three-dimensional thermal model, the channel peak temperature and junction-shell thermal resistance under different gate-source voltages, different drain-source voltages, different power densities, and different heat dissipation conditions were extracted. A correlation database was constructed based on the channel peak temperature and junction-shell thermal resistance under different gate-source voltages, different drain-source voltages, different power densities, and different heat dissipation conditions. Based on the aforementioned associated database, using operating status, power density, and heat dissipation conditions as input parameters and channel peak temperature as output parameter, a quadratic polynomial curve fitting is performed to obtain a multidimensional parameterized temperature prediction curve.

11. A channel temperature prediction device for a GaN HEMT chip, characterized in that, The channel temperature prediction device for the GaN HEMT chip includes: The first thermal testing module is used to control the thermal testing of the GaN HEMT chip and obtain a multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the multi-dimensional experimental dataset includes the gate-source voltage V. gs Drain-source voltage V ds Heat dissipation conditions, surface temperature, bottom temperature, drain-source current, and heat dissipation power density per unit gate width; The acquisition module is used to acquire the actual device structure parameters of GaN HEMT chips and the actual device structure parameters across scales. The first construction module is used to construct a thermal model of the thermal testing system based on the actual device structure parameters of the GaN HEMT chip. The simulation module is used to set thermal boundary conditions and channel heat sources for the thermal model under different operating states based on the thermal test experiment and the multi-dimensional experimental dataset corresponding to the GaN HEMT chip; the thermal boundary conditions of the thermal model are the same as those of the thermal test experiment; when the drain-source voltage of the operating state is less than or equal to the knee voltage, the channel heat source in the thermal model is a uniform surface heat source covering the channel; when the drain-source voltage of the operating state is greater than or equal to the knee voltage, the channel heat source in the thermal model is a local surface heat source covering the drain side under the gate. The second construction module is used to construct a cross-scale three-dimensional geometric model based on the actual device structure parameters of the GaN HEMT chip and the actual device structure parameters across scales. An assembly module is used to assemble the thermal model into the multi-scale three-dimensional geometric model to obtain a three-dimensional thermal model. The second thermal testing experiment module is used to conduct thermal testing experiments on the three-dimensional thermal model to obtain a multi-dimensional experimental dataset of the three-dimensional thermal model. The third construction module is used to construct a multi-dimensional parameterized temperature prediction curve based on the three-dimensional thermal model and the multi-dimensional experimental dataset of the three-dimensional thermal model. The multi-dimensional parameterized temperature prediction curve takes the operating state, power density and heat dissipation conditions as input parameters and the channel peak temperature as output parameter. The multi-dimensional parameterized temperature prediction curve is used to predict the channel temperature.

12. The channel temperature prediction device for GaN HEMT chips according to claim 11, characterized in that, The heat dissipation conditions of the three-dimensional thermal model are obtained through either a baseline heat dissipation fixture scenario or a variable heat dissipation fixture scenario. The baseline heat dissipation fixture scenario involves placing a water-cooled plate at the bottom of the GaN HEMT chip, and the variable in the heat dissipation conditions is the temperature of the water-cooled plate. Alternatively, the variable heat dissipation fixture scenario involves assembling the GaN HEMT chip in a heat dissipation module with an embedded microchannel containing a circulating cooling medium, and the variable in the heat dissipation conditions is the flow rate of the cooling medium, which is 60 mL / min to 300 mL / min.

13. A computer device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the channel temperature prediction method for the GaN HEMT chip according to any one of claims 1-10.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the channel temperature prediction method for the GaN HEMT chip according to any one of claims 1-10.

15. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the channel temperature prediction method for the GaN HEMT chip according to any one of claims 1-10.

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