Optical interconnect architecture

Abstract

The invention discloses an optical interconnection architecture, the optical interconnection architecture comprises an XPU board card, the XPU board card comprises a semiconductor chip and an optical I / O module, the optical I / O module comprises an optical driver, an optical detector array and a two-dimensional array light source, and the optical driver is electrically connected to one side of the semiconductor chip through a micro bump or direct bonding technology. The optical interconnection architecture provided by the invention has the advantages of low system complexity, short signal transmission path, low time delay and low energy consumption.

Description

Technical Field

[0001] This invention relates to the field of transmission and bearer technology, and more specifically to an optical interconnect architecture. Background Technology

[0002] With the rapid development of AI, big data, and cloud computing, the demand for high-bandwidth, low-latency, and high-performance computing is constantly increasing, and traditional electrical signal transmission methods can no longer meet these needs. More and more technologies are beginning to explore the use of optical transmission to replace traditional electrical signal transmission, thereby achieving interconnection methods with higher bandwidth and lower latency.

[0003] In related technologies, the connection between the optical transceiver chip and the main functional chips (XPU, switch, etc.) still needs to be achieved through a silicon interposer (containing complex TSV embedded copper lines). This results in a complex structure, long transmission paths, and the openings in the silicon interposer significantly reduce the contact area between the optical transceiver chip and the silicon interposer, thus limiting the data flow between the functional chips and I / O chips. Furthermore, the optical transceiver chip uses a single light source, and the multi-core optical fiber is arranged along the PCB plane and at the bottom of the board, requiring two small-radius 90° bends. This introduces transmission loss and causes inconsistent path lengths for each channel, leading to asynchronous timing issues in parallel transmission. Summary of the Invention

[0004] The present invention aims to at least partially solve one of the technical problems in the related art.

[0005] Therefore, embodiments of the present invention propose an optical interconnect architecture that has the advantages of low system complexity, short signal transmission path, low latency and low power consumption.

[0006] The optical interconnect architecture of this invention includes an XPU board, which includes a semiconductor chip and an optical I / O module. The optical I / O module includes an optical driver, a photodetector array, and a two-dimensional array light source. The optical driver is electrically connected to one side of the semiconductor chip through microbumps or direct bonding technology.

[0007] The optical interconnect architecture of this invention directly interconnects the optical I / O module's optical driver to one side of the semiconductor chip via micro-bumps or direct bonding technology. Compared to related technologies that achieve optical interconnection through a silicon interposer containing complex TSV embedded copper wires, the optical interconnect structure of this embodiment avoids the complex processes of TSV openings and embedded wires and the high requirements for packaging mass production capabilities, reducing manufacturing costs and process difficulty. It also shortens the internal interconnect distance, achieving a more compact chip layout, thereby reducing signal transmission latency and power consumption. It also solves the interconnect performance bottleneck that may be caused by the interposer opening occupying the electrical connection area of ​​the semiconductor chip and limiting the number of connection pins. At the same time, it simplifies the packaging process, improves system consistency and reliability, supports higher bandwidth and higher speed interconnects, and improves the overall performance of the XPU board.

[0008] In some embodiments, the XPU board further includes a PCB board and an optical fiber channel. The semiconductor chip is disposed on a first side of the PCB board. The PCB board has clearance holes opposite to the photodetector array and the two-dimensional array light source. The clearance holes penetrate the PCB board along its thickness direction. The optical fiber channel is disposed on the PCB board and has two guide holes extending along the thickness direction of the PCB board. The first ends of the two guide holes are opposite to the photodetector array and the two-dimensional array light source, respectively, and the second ends of the two guide holes are located on a second side of the PCB board.

[0009] In some embodiments, the XPU board further includes two multi-core fiber bundles, the first ends of which pass through the two guide holes and are respectively coupled to the photodetector array and the two-dimensional array light source.

[0010] In some embodiments, the optical fiber channel is made of metal or graphene, with the first end of the optical fiber channel located on the second side of the PCB board, and the second end of the optical fiber channel passing through the clearance hole and being insulated from and in heat-exchange contact with the semiconductor chip.

[0011] In some embodiments, the two-dimensional array light source includes a Micro-LED two-dimensional array or a VCSEL two-dimensional array; And / or, the photodetector array includes a PD array or an APD array.

[0012] In some embodiments, the semiconductor chip is a SoC chip and includes vertically stacked memory chips and logic chips, with the optical driver located on the side of the logic chip opposite to the memory chips; Alternatively, the semiconductor chip is a SoC chip and includes vertically stacked memory chips, logic chips, and an interposer layer, with the memory chips and logic chips disposed on a first side of the interposer layer and the optical driver disposed on a second side of the interposer layer.

[0013] In some embodiments, a plurality of first contacts are provided at the edge of the first side of the semiconductor chip, and a plurality of second contacts are provided on the first side of the PCB board arranged circumferentially along the clearance hole. The first contacts and the second contacts are electrically connected so that the PCB can power the semiconductor chip.

[0014] In some embodiments, the optical I / O module is one; Alternatively, there may be two optical I / O modules, which are electrically connected to the first and second sides of the semiconductor chip respectively via the optical driver.

[0015] In some embodiments, the optical interconnect architecture further includes a backplane, wherein multiple XPU boards are arranged in an array on the backplane, the backplane is used to power the XPU boards, and the XPU boards are optically interconnected with adjacent XPU boards via multi-core fiber bundles.

[0016] In some embodiments, multiple XPU boards are arranged in multiple rows at intervals along the row direction. Each row of XPU boards includes multiple XPU boards arranged at intervals along the column direction. Multiple XPU boards in any row are optically connected to multiple XPU boards in adjacent rows through multiple multi-core fiber bundles. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of an optical interconnect architecture according to an embodiment of the present invention.

[0018] Figure 2 This is another cross-sectional view of the optical interconnect architecture according to an embodiment of the present invention.

[0019] Figure label: 1. Semiconductor chip; 11. Logic chip; 12. Memory chip; 13. Intermediate layer; 2. Optical I / O module; 21. Optical driver; 22. Photodetector array; 23. Two-dimensional array light source; 3. PCB board; 31. Clearance hole; 4. Fiber optic channel. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0021] The following is combined Figure 1 and Figure 2 An optical interconnect architecture according to an embodiment of the present invention is described.

[0022] The optical interconnect architecture of this invention includes an XPU board, which includes a semiconductor chip 1 and an optical I / O module 2. The optical I / O module 2 includes an optical driver 21, a photodetector array 22 and a two-dimensional array light source 23. The optical driver 21 is electrically connected to one side of the semiconductor chip 1 through microbump or direct bonding technology.

[0023] The optical interconnect architecture of this invention directly optically interconnects the optical driver 21 of the optical I / O module 2 to one side of the semiconductor chip 1 via microbumps or direct bonding technology. Compared with the related technologies that achieve optical interconnection through a silicon interposer containing complex TSV embedded copper wires, the optical interconnect structure of this embodiment avoids the complex process of TSV opening and embedded wires and its high requirements for packaging mass production capabilities, reducing manufacturing costs and process difficulty. It also shortens the internal interconnection distance, achieving a more compact chip layout, thereby reducing signal transmission delay and power consumption. It also solves the interconnection performance bottleneck that may be caused by the interposer opening occupying the electrical connection area of ​​the semiconductor chip 1 and limiting the number of connection pins. At the same time, it simplifies the packaging process, improves system consistency and reliability, supports higher bandwidth and higher speed interconnection, and improves the overall performance of the XPU board.

[0024] It should be noted that in the optical I / O module 2, both the photodetector array 22 and the two-dimensional array light source 23 are located on the side of the optical driver 21 away from the semiconductor chip 1. The semiconductor chip 1 can be a SoC chip. The optical driver 21 achieves electrical interconnection with the SoC chip through micro-bump or direct bonding technology (such as hybrid bonding), without the need for a traditional interposer layer, thereby reducing the interconnection distance and increasing the bandwidth density.

[0025] In some embodiments, the XPU board further includes a PCB board 3 and a fiber optic channel 4. The semiconductor chip 1 is disposed on a first side of the PCB board 3. The PCB board 3 has clearance holes 31 opposite to the photodetector array 22 and the two-dimensional array light source 23. The clearance holes 31 penetrate the PCB board 3 along its thickness direction. The fiber optic channel 4 is disposed on the PCB board 3 and has two guide holes extending along the thickness direction of the PCB board 3. The first ends of the two guide holes are opposite to the photodetector array 22 and the two-dimensional array light source 23, respectively, and the second ends of the two guide holes are located on a second side of the PCB board 3.

[0026] Therefore, the placement of the clearance hole 31 in PCB board 3 exposes the photodetector array 22 and the two-dimensional array light source 23. Furthermore, the fiber optic channel 4 on PCB board 3 supports and positions the multi-core fiber bundle coupled to the photodetector array 22 and the two-dimensional array light source 23, effectively preventing transmission loss caused by bending of the multi-core fiber bundle and ensuring consistent path lengths across channels, thus avoiding asynchronous parallel transmission timing. This also improves the coupling reliability between the multi-core fiber bundle and the photodetector array 22 and the two-dimensional array light source 23.

[0027] For example, such as Figure 1 and Figure 2 As shown, at least a portion of the optical I / O module 2 is disposed within the clearance hole 31 to facilitate direct connection between the semiconductor chip 1 and the PCB board 3. One end of the fiber optic channel 4 can be inserted into the clearance hole 31 so that two guide holes respectively enclose the photodetector array 22 and the two-dimensional array light source 23, allowing the two multi-core fiber bundles to reliably couple with the photodetector array 22 and the two-dimensional array light source 23 under the guidance and support of the two guide holes. In this structure, after the electrical signal is processed inside the semiconductor chip 1, it is directly transmitted to the bottom optical I / O module 2 through vertical interconnection for photoelectric conversion, and high-speed optical transmission between modules is achieved through the fiber optic channel 4 integrated with the packaging structure.

[0028] In some embodiments, the XPU board further includes two multi-core fiber bundles, the first ends of which pass through two guide holes and are coupled to the photodetector array 22 and the two-dimensional array light source 23, respectively.

[0029] This effectively enables high-density fiber optic cabling between XPU boards, breaking through the bandwidth limitations of traditional electrical signal transmission and effectively improving bandwidth density.

[0030] For example, such as Figure 1 and Figure 2 As shown, the area of ​​the outer contour of the cross-section of the fiber optic channel 4 is smaller than the area of ​​the semiconductor chip 1. When the first end of the multi-core fiber bundle passes through the guide hole and is coupled to the photodetector array 22 or the two-dimensional array light source 23, the second end of the multi-core fiber bundle is located outside the guide hole to facilitate optical interconnection with the rest of the board.

[0031] In some embodiments, the fiber optic channel 4 is made of metal or graphene, the first end of the fiber optic channel 4 is located on the second side of the PCB board 3, and the second end of the fiber optic channel 4 passes through the clearance hole 31 and is insulated from and in heat exchange contact with the semiconductor chip 1.

[0032] Therefore, the fiber channel 4 itself has high heat dissipation efficiency. By insulating it from the semiconductor chip 1 and making heat exchange contact with it, the heat emitted by the semiconductor chip 1 can be quickly dissipated, effectively improving the heat dissipation efficiency of the XPU board.

[0033] For example, the fiber channel 4 is mechanically connected to the PCB board 3. The fiber channel 4 can be integrally formed to form two vias, or it can be two independent components, each forming a via.

[0034] In some embodiments, the two-dimensional array light source 23 includes a Micro-LED two-dimensional array or a VCSEL two-dimensional array. That is, the Micro-LED or VCSEL array arrangement has a smaller overall size, higher integration, and simultaneously has the advantages of high brightness, high efficiency and fast response speed, effectively improving the emission efficiency as a light signal emitting end.

[0035] For example, taking a two-dimensional array of Micro-LEDs as the light source, the Micro-LED chips are precisely integrated onto the driving substrate using flip-chip bonding technology to manufacture Micro-LED chips with a size of less than 50μm to meet the requirements of high-density integration.

[0036] And / or, the photodetector array 22 includes a PD array or an APD array. The PD array or APD array is used to receive optical signals, offering high reception efficiency. Taking the PD array as an example, the PD array and the Micro-LED two-dimensional array can be arranged adjacently or correspondingly, as long as they can be used to receive and transmit optical signals respectively. For example, such as... Figure 1 and Figure 2 As shown, the PD array and the Micro-LED two-dimensional array are arranged adjacent to each other.

[0037] In some embodiments, such as Figure 1 As shown, semiconductor chip 1 is a SoC chip and includes a vertically stacked memory chip 12 and a logic chip 11. Optical driver 21 is located on the side of the logic chip 11 opposite to the memory chip 12. Alternatively, as... Figure 2 As shown, semiconductor chip 1 is a SoC chip and includes a vertically stacked memory chip 12, logic chip 11 and an interposer 13. The memory chip 12 and logic chip 11 are disposed on the first side of the interposer 13, and the optical driver 21 is disposed on the second side of the interposer 13.

[0038] Therefore, regardless of the form of the SoC chip, it can be directly optically interconnected with the optical I / O module 2, achieving a compact system structure while avoiding problems such as TSV openings in the interposer layer, increased manufacturing complexity, and bandwidth bottlenecks.

[0039] It should be noted that when the SoC chip includes the interposer layer 13, the bottom of the interposer layer 13 makes full-area contact with the optical driver 21 of the optical I / O module 2 to effectively ensure available bandwidth.

[0040] In some embodiments, a plurality of first contacts are provided at the edge of the first side of the semiconductor chip 1, and a plurality of second contacts are provided on the first side of the PCB board 3 arranged circumferentially along the clearance hole 31. The first contacts and the second contacts are electrically connected so that the PCB can power the semiconductor chip 1.

[0041] This allows the semiconductor chip 1 to be fixedly mounted on the PCB board 3, while the PCB board 3 is only used to power the semiconductor chip 1. The multi-core fiber bundle used for optical interconnection with the optical I / O module 2 is set separately from the PCB board 3. The arrangement of the multi-core fiber bundle is more flexible, further reducing the transmission loss and asynchronous timing of parallel transmission caused by small-radius bending.

[0042] In some embodiments, such as Figure 1 and Figure 2 As shown, there is one optical I / O module 2.

[0043] Alternatively, two optical I / O modules 2 can be electrically connected to the first and second sides of the semiconductor chip 1 respectively via optical drivers 21. This facilitates full interconnection between XPU boards, meeting the needs of future AI servers for ultra-large-scale data parallel processing and high-speed interconnection.

[0044] In some embodiments, the optical interconnect architecture further includes a backplane, with multiple XPU boards arranged in an array on the backplane. The backplane is used to power the XPU boards, and the XPU boards have multi-core fiber bundles for optical interconnection with adjacent XPU boards.

[0045] This fully interconnected architecture simplifies the overall system cabling and significantly reduces signal attenuation and latency issues caused by electrical connections, while avoiding the use of complex packaging technologies such as traditional TSV. By directly leading fiber optic channels 4 from the bottom of the XPU board and then using independently external multi-core fiber bundles to construct the interconnection network, this architecture achieves efficient, direct, and flexible optical interconnection between different XPU boards at the physical level. Furthermore, by utilizing the fiber optic channels 4 reserved on the bottom of each XPU board and the multi-core fiber bundles specifically arranged between the rows of XPU boards, a fully interconnected architecture between XPU boards is achieved, while the backplane only handles power supply functions, completely avoiding the complexity and cost challenges faced by traditional designs involving the transmission of mixed electrical and high-speed optical signals.

[0046] For example, each XPU board has a multi-core fiber bundle optically interconnected with at least one adjacent XPU board.

[0047] In some embodiments, multiple XPU boards are arranged in multiple rows of XPU boards at intervals along the row direction. Each row of XPU boards includes multiple XPU boards arranged at intervals along the column direction. Multiple XPU boards in any row are electrically connected to multiple XPU boards in adjacent rows through multiple multi-core fiber bundles.

[0048] Based on system interconnection requirements, the XPU board can be configured with dual-sided optical I / O modules 2 in a vertical heterogeneous integration structure to support high-speed optical interconnection in both vertical and horizontal directions. Specific designs can choose symmetrical or asymmetrical arrangement schemes based on packaging structure and process feasibility. For example, top and bottom optical I / O can be symmetrically arranged, or a single-sided optical I / O combined with an internal optical path adjustment structure (such as micromirrors or waveguide bending) can be used to achieve full interconnection capability. The specific implementation is as follows: Each XPU board has a pre-integrated fiber optic channel 4 at its bottom. This channel is responsible for directly leading out high-speed optical signals generated inside the XPU board through its bottom, while simultaneously receiving optical signals from the outside, realizing optical transceiver functionality. In this way, the entire XPU board physically possesses an "optical window" facing the interconnection network. The XPU boards are inserted into a dedicated backplane in a row-like manner. This backplane only serves a power supply function, avoiding the design complexity and cost issues associated with traditional backplanes that simultaneously handle electrical interconnection and high-speed data transmission. The backplane does not participate in the transmission of optical signals; all high-speed interconnection tasks are undertaken by the fiber channel 4 and external multi-core fiber bundles that extend from the bottom of the XPU board.

[0049] During installation, the bottom fiber optic channels 4 of adjacent XPU boards directly interface with rows of multi-core fiber optic bundles. These multi-core fiber optic bundles serve as the physical connection medium, tightly connecting the XPU boards in adjacent rows. Each multi-core fiber optic bundle contains multiple individual channels, each channel carrying a high-speed data transmission line, thus achieving full interconnection between rows. In this way, every XPU board in the entire system can interconnect with other XPU boards via fiber optics, forming a non-redundant, low-latency, high-bandwidth interconnection network.

[0050] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0052] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0054] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0055] Although the above embodiments have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any changes, modifications, substitutions and variations made to the above embodiments by those skilled in the art are within the protection scope of the present invention.

Claims

1. An optical interconnect architecture, characterized in that, Includes an XPU board, wherein the XPU board includes: Semiconductor chip (1); Optical I / O module (2), the optical I / O module (2) includes optical driver (21), photodetector array (22) and two-dimensional array light source (23), the optical driver (21) is electrically connected to one side of the semiconductor chip (1) through microbump or direct bonding technology.

2. The optical interconnect architecture according to claim 1, characterized in that, The XPU board also includes: PCB board (3), the semiconductor chip (1) is disposed on the first side of the PCB board (3), the PCB board (3) is provided with a clearance hole (31) opposite to the photodetector array (22) and the two-dimensional array light source (23), the clearance hole (31) penetrates the PCB board (3) along the thickness direction of the PCB board (3); The fiber optic channel (4) is located on the PCB board (3) and has two guide holes extending along the thickness direction of the PCB board (3). The first ends of the two guide holes are respectively opposite to the photodetector array (22) and the two-dimensional array light source (23), and the second ends of the two guide holes are located on the second side of the PCB board (3).

3. The optical interconnect architecture according to claim 2, characterized in that, The XPU board also includes two multi-core fiber bundles, the first ends of which pass through the two guide holes and are coupled to the photodetector array (22) and the two-dimensional array light source (23), respectively.

4. The optical interconnect architecture according to claim 2, characterized in that, The optical fiber channel (4) is made of metal or graphene. The first end of the optical fiber channel (4) is located on the second side of the PCB board (3). The second end of the optical fiber channel (4) passes through the clearance hole (31) and is insulated from and in heat exchange contact with the semiconductor chip (1).

5. The optical interconnect architecture according to claim 1, characterized in that, The two-dimensional array light source (23) includes a Micro-LED two-dimensional array or a VCSEL two-dimensional array; And / or, the photodetector array (22) includes a PD array or an APD array.

6. The optical interconnect architecture according to claim 1, characterized in that, The semiconductor chip (1) is a SoC chip and includes a vertically stacked memory chip (12) and a logic chip (11). The optical driver (21) is located on the side of the logic chip (11) away from the memory chip (12). Alternatively, the semiconductor chip (1) is a SoC chip and includes a vertically stacked memory chip (12), a logic chip (11), and an interposer (13), with the memory chip (12) and the logic chip (11) disposed on the first side of the interposer (13) and the optical driver (21) disposed on the second side of the interposer (13).

7. The optical interconnect architecture according to claim 2, characterized in that, The semiconductor chip (1) has a plurality of first contacts on the edge of the first side, and the PCB board (3) has a plurality of second contacts arranged circumferentially along the clearance hole (31) on the first side. The first contacts are electrically connected to the second contacts so that the PCB can power the semiconductor chip (1).

8. The optical interconnect architecture according to any one of claims 1-7, characterized in that, The optical I / O module (2) consists of one unit; Alternatively, the optical I / O module (2) may be two and electrically connected to the first and second sides of the semiconductor chip (1) respectively via the optical driver (21).

9. The optical interconnect architecture according to claim 8, characterized in that, The optical interconnect architecture also includes a backplane, on which multiple XPU boards are arranged in an array. The backplane is used to power the XPU boards, and each XPU board has a multi-core fiber bundle for optical interconnection with adjacent XPU boards.

10. The optical interconnect architecture according to claim 9, characterized in that, Multiple XPU boards are arranged in multiple rows at intervals along the row direction. Each row of XPU boards includes multiple XPU boards arranged at intervals along the column direction. Multiple XPU boards in any row are optically connected to multiple XPU boards in adjacent rows in a one-to-one correspondence through multiple multi-core fiber bundles.

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