Error correction protection method and system for integrated circuit calibration

Abstract

The invention provides an error correction protection method and system for integrated circuit calibration, and the method comprises the steps: generating an initial N-bit digital calibration code through an external calibration code generator, and inputting the initial N-bit digital calibration code into an external ECC encoder; the external ECC encoder generates M bits of check bits based on the N bits of digital calibration codes, and N + M bits of encrypted words are formed and placed in the internal memory; when the integrated circuit is powered on, triggering calibration, reading N + M bit encryption words in the built-in memory and inputting the N + M bit encryption words into the built-in ECC decoder; and a built-in ECC decoder detects and corrects errors, outputs corrected N-bit calibration codes, and is applied to a calibration implementation module to realize a calibration state. According to the invention, the robustness of system operation is obviously enhanced, the load is prevented from being damaged by abnormal output, and high-precision and high-reliability circuit calibration is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically, to an error correction and protection method and system for integrated circuit calibration. Background Technology

[0002] In the field of modern electronics, the performance stability and accuracy of integrated circuits are the cornerstones of ensuring the normal operation of equipment. Especially in critical applications such as communications, medical devices, and industrial control, the accurate calibration of circuit parameters directly affects the reliability and safety of the system. During use, integrated circuits require calibration systems to adjust the accuracy of their internal key parameters to ensure they operate at their optimal state.

[0003] The calibration system dynamically adjusts internal circuit parameters (such as gain, offset, or frequency) by measuring the deviation between the actual output and the ideal value to continuously compensate for errors introduced by factors such as manufacturing process fluctuations, temperature changes, and device aging. For example, in high-precision ADCs or sensors, the system can run a self-calibration algorithm upon power-up or in the background to correct nonlinearity and temperature drift errors.

[0004] In modern electronic design, when the calibration configuration data (such as Trim Bits) of a chip or system fails, a multi-layered, hardware-software combined protection mechanism is typically employed. The core objective is to prevent catastrophic consequences and maintain basic functionality or a safe state as much as possible. At the hardware level, critical modules often incorporate redundancy designs, such as using error correction codes (ECC) for data protection.

[0005] However, existing technologies still lack sufficient protection for critical configuration, calibration, or fine-tuning components in analog integrated products. For example, in analog circuits such as buck converters, errors in the trim bits used for calibration can lead to abnormal output voltage, thereby damaging the load processor and affecting the system's reliability and lifespan. Summary of the Invention

[0006] The purpose of this invention is to address the technical problem that the lack of effective protection mechanisms for integrated circuit calibration data during storage and transmission in the prior art makes it easy for analog output abnormalities or even damage to the load to occur in harsh environments. This invention provides an error correction protection method and system for integrated circuit calibration.

[0007] The technical solution of this invention is: This invention provides an error correction and protection method for integrated circuit calibration, the method comprising the following steps: S1. Generate an initial N-bit digital calibration code using an external calibration code generator and input it into the external ECC encoder; S2. The external ECC encoder generates an M-bit check bit based on the N-bit digital calibration code, forming an N+M-bit encryption word which is then stored in the built-in memory. S3. When the integrated circuit is powered on, calibration is triggered, and the N+M bit encryption key in the built-in memory is read and input into the built-in ECC decoder. S4, the built-in ECC decoder detects and corrects errors, and outputs the corrected N-bit calibration code, which is applied to the calibration implementation module to realize the calibration status.

[0008] Furthermore, S1 includes: during the production testing phase, acquiring integrated circuit parameter data based on DUT testing, including voltage, current, resistance, and capacitance parameters; selecting a target value for any parameter, acquiring the actual value of that parameter, continuously testing with an external calibration code generator to ensure that the actual value reaches the target value, and generating an N-bit digital calibration code accordingly, which is then input into an external ECC encoder.

[0009] Further, S2 includes: S21, the external ECC encoder generates the M-bit check bit based on the Hamming code algorithm, and combines the M-bit check bit with the initial N-bit digital calibration code to form an N+M-bit encryption word; S22, the N+M-bit encryption word is placed in the built-in memory, wherein the built-in memory is an integrated circuit built-in storage unit.

[0010] Furthermore, the built-in memory is a non-volatile built-in memory, such as FLASH, EEPROM, EPROM, or e-Fuse, used to permanently store the N+M bit encryption key.

[0011] Furthermore, in S4, the built-in ECC decoder uses a Hamming code decoder to process the N+M bit encryption code. If an error is detected, it outputs a corrected N-bit calibration code. At the same time, the built-in ECC decoder outputs a fault indication signal. If the fault indication signal indicates more than a single-bit error, it triggers a shutdown signal to turn off the integrated circuit system power. The Hamming code decoder uses the single-bit error correction and double-bit error detection method SEC-DED.

[0012] Furthermore, in S4, the calibration implementation module includes a control logic module, a driver module, and an analog signal conditioning network; the corrected N-bit calibration code is input to the control logic module, the control logic module generates an N-bit logic control signal and inputs it to the driver module; the driver module generates an N-bit analog control signal and applies it to the analog signal conditioning network.

[0013] Furthermore, when this method is applied to LDOs, reference sources, and DC-DC converters, the analog signal conditioning network adopts a resistor DAC network, wherein the DC-DC converter includes a buck converter, a boost converter, a buck-boost converter, and a charge pump; when this method is applied to operational amplifiers or instrumentation amplifiers, the analog signal conditioning network adopts a gain setting network.

[0014] Furthermore, when the analog signal conditioning network uses a resistor DAC network, the control logic module converts the corrected N-bit calibration code into an N-bit switch enable signal to drive the resistor DAC network. The resistor DAC network includes multiple series resistors and switching elements, wherein the switching elements adjust the voltage division ratio to generate a calibration voltage Vdac in response to an N-bit switch enable signal; The calibration voltage is fed back to the error amplifier corresponding to Vdac. The operational amplifier amplifies the voltage difference between the reference voltage and the calibration voltage, forming a negative feedback system loop. The calibration state of the integrated circuit is realized by adjusting the parameters of the resistor DAC network, and finally the output voltage reaches the target voltage.

[0015] A system used in an error correction and protection method for integrated circuit calibration includes: An external calibration code generation and encoding module is used to generate and solidify calibration information during the integrated circuit packaging and testing phase; it includes an external calibration code generator, an external ECC encoder, and built-in memory. The external calibration code generator is used to generate an initial N-bit digital calibration code; the external ECC encoder is connected to the external calibration code generator and is used to receive the N-bit digital calibration code and generate an M-bit check bit based on the code, thereby forming an N+M-bit encryption word; the built-in memory is connected to the external ECC encoder and is used to store the N+M-bit encryption word. A calibration execution module, integrated within the integrated circuit, is used to read and verify the calibration information during chip power-on operation; it includes a built-in ECC decoder and a calibration execution module. The built-in ECC decoder is triggered when the integrated circuit is powered on. It is used to read the N+M bit encryption code from the built-in memory, perform error detection and correction on it, and output the corrected N-bit calibration code. The calibration implementation module is connected to the built-in ECC decoder and is used to perform the calibration of the analog parameters according to the corrected N-bit calibration code. Furthermore, the calibration implementation module further includes: The control logic module, connected to the built-in ECC decoder, is used to receive the corrected N-bit calibration code and generate the corresponding N-bit logic control signal; A drive module, connected to the control logic module, is used to convert the N-bit logic control signal into an N-bit analog control signal; An analog signal conditioning network, connected to the drive module, is used to adjust its network parameters in response to the N-bit analog control signal, so as to calibrate the performance of the analog circuit inside the integrated circuit.

[0016] This invention provides a novel solution for integrating error correction coding logic to protect the configuration, calibration, and fine-tuning components of analog integrated products. Compared to existing technologies, this invention offers the following advantages: 1. Improve system reliability: By introducing error correction coding to protect critical calibration data, errors in configuration data such as Trim Bits can be effectively detected and corrected, preventing abnormal output voltage or other functional failures caused by data corruption, and significantly improving the operational reliability and lifespan of the chip and system.

[0017] 2. Enhanced security: With integrated ECC coding, the system can take protective measures such as shutting down the power converter when it detects serious data errors that cannot be corrected, so as to avoid damage to the load caused by erroneous output, thereby improving the system's safety and fault tolerance.

[0018] 3. Wide applicability: This invention can be flexibly applied to a variety of analog and mixed-signal circuits, including but not limited to: resistor DAC feedback networks (such as LDOs, reference sources, DC-DC converters); gain setting networks (such as operational amplifiers, instrumentation amplifiers); calibration networks (such as ADCs, DACs, oscillators); configuration data (such as BMS integrated systems); and various circuits that use built-in memory as configuration, calibration, or adjustment elements.

[0019] 4. Improved system startup safety: In power converters with integrated ECC, if damage to the Trim Bits is detected, the system can prevent it from starting with an abnormal output voltage upon power-up and restore a safe state through a power-on cycle, thereby avoiding the risk of continuous failure.

[0020] 5. Low hardware overhead and significant cost-effectiveness: The solution of this invention does not require modification of the existing storage unit structure and analog adjustment path, occupies a very small on-chip area, and has almost no increase in manufacturing cost; at the same time, it can effectively avoid system failure, rework and field failure caused by data errors, greatly reduce the total life cycle maintenance cost, and achieve a significant cost-effectiveness advantage of "low cost investment and high reliability return".

[0021] In summary, this invention solves the critical problem of calibration data being susceptible to interference and affecting system function and security through a hardware-level error correction coding protection mechanism, providing an effective fault-tolerant design method for high-precision, high-reliability analog integrated circuits.

[0022] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0023] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0024] Figure 1 A block diagram illustrating the principle of the error correction code protection system for integrated circuit calibration according to the present invention is shown.

[0025] Figure 2 A flowchart of the error correction protection method for integrated circuit calibration according to the present invention is shown.

[0026] Figure 3 The circuit diagram of the analog signal conditioning network in this invention employing a gain setting network is shown.

[0027] Figure 4 The circuit diagram of the analog signal conditioning network in this invention, which employs a resistor DAC network, is shown. Detailed Implementation

[0028] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0029] Example 1: Figure 2 A flowchart of the error correction protection method for integrated circuit calibration according to the present invention is shown.

[0030] like Figure 2 The present invention provides an error correction and protection method for integrated circuit calibration, the method comprising the following steps: S1. Generate an initial N-bit digital calibration code using an external calibration code generator and input it into the external ECC encoder; Specifically, S1 includes obtaining integrated circuit parameter data, including voltage, current, resistance and capacitance parameters, based on DUT testing during the production testing phase; selecting a target value for any parameter, obtaining the actual value of the parameter, continuously testing with an external calibration code generator to make the actual value reach the target value, and generating an N-bit digital calibration code based on this, which is then input into an external ECC encoder.

[0031] In one embodiment, during the chip production testing or design verification phase, key chip parameters, such as output voltage deviation, gain error, or oscillation frequency offset, are collected using dedicated testing equipment. An external calibration code generator calculates a digital code to compensate for the deviation based on this measurement data. This digital code has a bit width of N bits, typically ranging from 6 to 12 bits, depending on the required calibration accuracy. After generation, this N-bit digital calibration code is directly fed into an external ECC encoder.

[0032] S2. The external ECC encoder generates an M-bit check bit based on the N-bit digital calibration code, forming an N+M-bit encryption word which is then stored in the built-in memory. Specifically, the process includes S21, where an external ECC encoder generates the M-bit check bit based on a Hamming code algorithm, and combines the M-bit check bit with an initial N-bit digital calibration code to form an N+M-bit encryption word; and S22, where the N+M-bit encryption word is placed in an internal memory, which is an integrated circuit's built-in storage unit. The built-in memory is a non-volatile memory, such as FLASH, EEPROM, EPROM, or e-Fuse, used to permanently store the N+M-bit encryption word.

[0033] In one embodiment, Hamming code is selected as the error correction coding method. For N bits of information, the required check bits M satisfy 2. M The condition is ≥N+M+1. For example, when N is 8, M is usually 4, forming a 12-bit codeword, which can achieve single-bit error correction and double-bit error detection. The external ECC encoder performs matrix multiplication on the N-bit calibration code according to the Hamming code generation matrix to generate the corresponding M-bit check bits. Then, the N-bit information bits and the M-bit check bits are concatenated in a predetermined order to form a complete N+M-bit encryption codeword.

[0034] Preferably, the generated N+M bit encryption key is written into a non-volatile built-in memory, such as an EEPROM, so that it remains unchanged throughout the chip's lifespan.

[0035] In one embodiment, for output voltage calibration in a buck DC-DC converter, the N-bit calibration code corresponds to the trim configuration of each switching branch in the resistor divider network. An external ECC encoder generates a 4-bit check bit, forming a 12-bit encryption code, which is then written into the internal fuse array of the chip via a programming device. The fuses are burned out once before leaving the factory to form a permanent code, ensuring that the code will not be lost or tampered with even after multiple power-ups.

[0036] S3. When the integrated circuit is powered on, calibration is triggered, and the N+M bit encryption key in the built-in memory is read and input into the built-in ECC decoder. In one embodiment, after the power-on reset signal is triggered, the chip's internal state machine starts the read sequence, reads N+M bits of encryption code from the non-volatile built-in memory bit by bit, and sends it completely to the built-in ECC decoder.

[0037] S4, the built-in ECC decoder detects and corrects errors, and outputs the corrected N-bit calibration code, which is applied to the calibration implementation module to realize the calibration status.

[0038] Specifically, the built-in ECC decoder uses a Hamming code decoder to process the N+M bit encryption code. If an error is detected, it outputs a corrected N-bit calibration code. At the same time, the built-in ECC decoder outputs a fault indication signal. If the fault indication signal indicates more than a single-bit error, it triggers a shutdown signal to turn off the integrated circuit system power. The Hamming code decoder uses the single-bit error correction and double-bit error detection method SEC-DED.

[0039] In one embodiment, the built-in ECC decoder employs Hamming code decoding logic corresponding to the encoder, determining the error location by calculating the syntactic expression. If the syntactic expression is zero, it indicates no error, and the original N-bit calibration code is directly output; if the syntactic expression is non-zero, the single-bit error location is located, and that bit is flipped. After correction, the correction code is output. If a two-bit error is detected, a fault indication signal is generated, triggering the chip to enter a safe failure state, such as turning off the power switch or cutting off the main output path.

[0040] For example, in a buck converter, the corrected N-bit calibration code is fed into the digital control terminal of the resistor divider network. Specifically, this code controls the switching state of a group of parallel resistor branches, with each bit corresponding to the on / off state of one resistor branch, thereby adjusting the voltage division ratio to make the output voltage approach the target value. If the 3rd bit in the original codeword flips to an incorrect value due to aging of the built-in memory, the built-in ECC decoder locates and corrects the 3rd bit through a synergistic mechanism, outputting the correct codeword. Ultimately, this ensures that the output voltage remains within the design range, preventing load damage due to excessively high or low voltage.

[0041] For example, when applied to gain calibration of a high-precision ADC, the corrected N-bit calibration code is sent to the control register of the adjustable gain amplifier. For example, when N is 10 bits, 1024 levels of gain fine-tuning can be achieved. ECC protection ensures that even if a single bit flip occurs, the gain deviation is still limited to an acceptable range, thereby maintaining the linearity and signal-to-noise ratio of the ADC.

[0042] Through the above-mentioned ECC protection mechanism, even if the built-in memory experiences an accidental single-bit error, the system can still automatically restore the correct calibration state, avoiding catastrophic voltage runaway or functional failure caused by trim code errors, thereby significantly improving the chip's reliability and lifespan.

[0043] In this embodiment, an initial calibration code is input into a Hamming code-based error correction encoder to generate an M-bit check bit, forming an N+M-bit codeword stored in the built-in memory. After reading, the codeword is read by a decoder with single-bit correction and double-bit detection capabilities, outputting a corrected N-bit calibration code and generating a fault indication signal. When the fault frequency exceeds a threshold, a shutdown signal is triggered to turn off the system power, effectively preventing circuit inaccuracies or safety hazards caused by erroneous calibration codes. The corrected calibration code is converted into a logic control signal by control logic, driving an analog signal conditioning network to precisely adjust network parameters to achieve calibration. This invention significantly improves the reliability of calibration codes during storage and use, ensuring long-term stable operation of integrated circuits and providing fault self-protection capabilities.

[0044] Specifically, in S4, the calibration implementation module includes a control logic module, a drive module, and an analog signal conditioning network; The corrected N-bit calibration code is output from the ECC decoder and directly transmitted to the control logic module. This module contains digital logic circuits for preliminary processing of the calibration data to ensure signal integrity.

[0045] The control logic module generates N-bit logic control signals and inputs them to the driver module. For example, in integrated circuit design, the control logic module uses a combinational logic gate array to convert calibration codes into corresponding logic control signals, which represent switch states in binary form.

[0046] The driver module generates an N-bit analog control signal, which is applied to the analog signal conditioning network. For example, the driver module uses a level conversion circuit to amplify the digital logic signal into an analog voltage level, directly driving subsequent network components.

[0047] When the method of the present invention is applied to LDOs, reference sources, and DC-DC converters, the analog signal conditioning network employs a resistor DAC network. The DC-DC converter includes a buck converter, a boost converter, a buck-boost converter, and a charge pump. For example, in buck converter applications, the resistor DAC network consists of a precision resistor trapezoidal structure to generate an adjustable output voltage and improve power supply stability.

[0048] When the method of this invention is applied to an operational amplifier or an instrumentation amplifier, the analog signal conditioning network employs a gain setting network. For example, the gain setting network adjusts the amplification factor through a variable resistor array to ensure signal amplification accuracy.

[0049] In this invention, when the analog signal conditioning network uses a resistor DAC network, the control logic module converts the corrected N-bit calibration code into an N-bit switch enable signal to drive the resistor DAC network. The resistor DAC network includes multiple series resistors and switching elements, wherein the switching elements adjust the voltage division ratio to generate a calibration voltage Vdac in response to an N-bit switch enable signal; The calibration voltage is fed back to the corresponding Vdac of the operational amplifier. The operational amplifier compares the reference voltage and the calibration voltage and outputs the target output voltage. The operational amplifier amplifies the voltage difference between the reference voltage and the calibration voltage to form a negative feedback system loop. The calibration state of the integrated circuit is realized by adjusting the parameters of the resistor DAC network, and finally the output voltage reaches the target voltage.

[0050] For example, a resistor DAC network consists of n series resistors, such as... Figure 1 As shown, each resistor value is R1, R2, ..., Rn, etc., and switching elements C1, C2, ..., Cn are connected between the resistors.

[0051] The switching element selectively short-circuits certain resistors according to the enable signal, changing the overall voltage division ratio and thus generating a precise Vdac value. This adjustment mechanism can effectively compensate for process deviations and improve calibration accuracy.

[0052] Example 2: Figure 1 A block diagram illustrating the principle of the error correction code protection system for integrated circuit calibration according to the present invention is shown.

[0053] like Figure 1 As shown, the present invention provides a system for an error correction and protection method for integrated circuit calibration, comprising: An external calibration code generation and encoding module is used to generate and solidify calibration information during the integrated circuit packaging and testing phase; it includes an external calibration code generator, an external ECC encoder, and built-in memory. The external calibration code generator is used to generate an initial N-bit digital calibration code; the external ECC encoder is connected to the external calibration code generator and is used to receive the N-bit digital calibration code and generate an M-bit check bit based on the code, thereby forming an N+M-bit encryption word; the built-in memory is connected to the external ECC encoder and is used to store the N+M-bit encryption word. A calibration execution module, integrated within the integrated circuit, is used to read and verify the calibration information during chip power-on operation; it includes a built-in ECC decoder and a calibration execution module. The built-in ECC decoder is triggered when the integrated circuit is powered on. It is used to read the N+M bit encryption code from the built-in memory, perform error detection and correction on it, and output the corrected N-bit calibration code. The calibration implementation module is connected to the built-in ECC decoder and is used to perform the calibration of the analog parameters according to the corrected N-bit calibration code.

[0054] The calibration implementation module further includes: The control logic module, connected to the built-in ECC decoder, is used to receive the corrected N-bit calibration code and generate the corresponding N-bit logic control signal; A drive module, connected to the control logic module, is used to convert the N-bit logic control signal into an N-bit analog control signal; An analog signal conditioning network, connected to the drive module, is used to adjust its network parameters in response to the N-bit analog control signal, so as to calibrate the performance of the analog circuit inside the integrated circuit.

[0055] In one embodiment, such as Figure 3 The diagram shows a circuit diagram of an analog signal conditioning network using a gain setting network. The instrumentation amplifier determines the required signal amplification factor through an external resistor Rgain, where Vout = (1 + 2R1 / Rgain) * Vin, and the signal amplification factor Gain = (1 + 2R1 / Rgain). The amplification factor accuracy and error are determined by the external Rgain and the internal R1. The internal R1 requires an absolutely precise theoretical value, obtained through testing, adjustment, and calibration to obtain an N-bit calibration code. The corrected R1 is close enough to the ideal value to keep the amplification factor error within acceptable accuracy. However, if the N-bit calibration code is incorrect for any reason, the value of R1 will be inaccurate, resulting in an inaccurate amplification factor Gain. Therefore, R1 requires ECC protection. By adding an M-bit parity check code, the N-bit calibration code can be protected. If the N-bit parity check code has a problem, the internally integrated Hamming code decoder can detect and correct a 1-bit error within the N-bit parity check; the instrumentation amplifier can continue to be used, improving chip functional safety and lifespan. If the decoder detects a 2-bit error, the fault signal can shut down the instrumentation amplifier and warn that the chip needs to be replaced.

[0056] In one embodiment, such as Figure 4The diagram shows a circuit diagram of an analog signal conditioning network using a resistor-DAC network. The LDO's error amplifier amplifies the voltage difference between the reference voltage Vref and the resistor network's voltage divider Vfb, forming a negative feedback loop that ensures Vout = (Rup + Rdown) / Rdown * Vref. By adjusting the ratio of Rup and Rdown, Vout can reach the set target voltage. An N-bit calibration code is obtained by measuring Vout and adjusting Rup and Rdown. After calibration, Vout is sufficiently close to the target voltage, keeping the error voltage within the accuracy range. If the N-bit calibration code is incorrect, the ratio of Rup and Rdown will be inaccurate, resulting in an inaccurate Vout, which can affect the performance and even function of the load. In this case, Rup and Rdown require ECC protection. By adding an M-bit parity check code, the N-bit calibration code can be protected. If the N-bit parity check code has a problem, the internally integrated Hamming code decoder can detect and correct a 1-bit error within the N-bit parity check; the LDO can continue to be used, improving chip functional safety and lifespan. If the decoder detects a 2-bit error, the fault signal can shut down the LDO to avoid affecting load performance or damaging the load, and the fault warning can be used to request the replacement of the LDO chip.

[0057] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for error correction and protection in integrated circuit calibration, characterized in that, The method includes the following steps: S1. An initial N-bit digital calibration code is generated using an external calibration code generator and input into an external ECC encoder; S2. The external ECC encoder generates an M-bit check bit based on the N-bit digital calibration code, forming an N+M-bit encryption word which is then stored in the built-in memory. S3. When the integrated circuit is powered on, calibration is triggered, and the N+M bit encryption key in the built-in memory is read and input into the built-in ECC decoder. S4, the built-in ECC decoder detects and corrects errors, and outputs the corrected N-bit calibration code, which is applied to the calibration implementation module to realize the calibration status.

2. The method as described in claim 1, characterized in that... S1 includes: During the production testing phase, integrated circuit parameter data, including voltage, current, resistance, and capacitance parameters, are obtained based on DUT testing. Select the target value of any parameter, obtain the actual value of the parameter, use an external calibration code generator to continuously test until the actual value reaches the target value, and generate an N-bit digital calibration code based on this, which is then input into the external ECC encoder.

3. The method as described in claim 1, characterized in that S2 include: S21. The external ECC encoder generates the M-bit check bit based on the Hamming code algorithm, and combines the M-bit check bit with the initial N-bit digital calibration code to form an N+M-bit encryption word. S22. Place the N+M bit encryption word in the built-in memory, where the built-in memory is an integrated circuit built-in storage unit.

4. The method as described in claim 3, characterized in that, The built-in memory is a non-volatile built-in memory, such as FLASH, EEPROM, EPROM, or e-Fuse, used to permanently store the N+M bit encryption key.

5. The method as described in claim 1, characterized in that... In S4, The built-in ECC decoder uses a Hamming code decoder to process the N+M bit encryption code. If an error is detected, it outputs a corrected N-bit calibration code. At the same time, the built-in ECC decoder outputs a fault indication signal. If the fault indication signal indicates more than a single bit error, it triggers a shutdown signal to turn off the integrated circuit system power. The Hamming code decoder employs the SEC-DED method, which involves single-bit error correction and double-bit error detection.

6. The method as described in claim 1, characterized in that... In S4, the calibration implementation module includes a control logic module, a drive module, and an analog signal conditioning network; The corrected N-bit calibration code is input to the control logic module, which generates an N-bit logic control signal and inputs it to the driver module; the driver module generates an N-bit analog control signal, which is applied to the analog signal conditioning network.

7. The method as described in claim 6, characterized in that... ； When this method is applied to LDOs, reference sources, and DC-DC converters, the analog signal conditioning network adopts a resistor DAC network, wherein the DC-DC converter includes a buck converter, a boost converter, a buck-boost converter, and a charge pump; When this method is applied to operational amplifiers or instrumentation amplifiers, the analog signal conditioning network adopts a gain setting network.

8. The method as described in claim 7, characterized in that When the analog signal conditioning network uses a resistor DAC network, the control logic module converts the corrected N-bit calibration code into an N-bit switch enable signal to drive the resistor DAC network. The resistor DAC network includes multiple series resistors and switching elements, wherein the switching elements adjust the voltage division ratio to generate a calibration voltage Vdac in response to an N-bit switch enable signal; The calibration voltage is fed back to the error amplifier corresponding to Vdac. The error amplifier amplifies the voltage difference between the reference voltage and the calibration voltage, forming a negative feedback system loop. The calibration state of the integrated circuit is realized by adjusting the parameters of the resistor DAC network, and finally the output voltage reaches the target voltage.

9. A system used in the error correction protection method for integrated circuit calibration according to any one of claims 1-8, characterized in that, include: An external calibration code generation and encoding module is used to generate and solidify calibration information during the integrated circuit packaging and testing phase. Includes an external calibration code generator, an external ECC encoder, and built-in memory: The external calibration code generator is used to generate an initial N-bit digital calibration code; the external ECC encoder is connected to the external calibration code generator and is used to receive the N-bit digital calibration code and generate an M-bit check bit based on the code, thereby forming an N+M-bit encryption word. The built-in memory is connected to the external ECC encoder and is used to store the N+M bit encryption key; A calibration execution module, integrated within the integrated circuit, is used to read and verify the calibration information when the chip is powered on and running. Includes a built-in ECC decoder and calibration implementation module: The built-in ECC decoder is triggered when the integrated circuit is powered on. It is used to read the N+M bit encryption code from the built-in memory, perform error detection and correction on the N bit calibration code, and output the corrected N bit calibration code. The calibration implementation module is connected to the built-in ECC decoder and is used to perform calibration of analog parameters based on the corrected N-bit calibration code.

10. The system as described in claim 9, characterized in that... The calibration implementation module further includes: The control logic module, connected to the built-in ECC decoder, is used to receive the corrected N-bit calibration code and generate the corresponding N-bit logic control signal; A drive module, connected to the control logic module, is used to convert the N-bit logic control signal into an N-bit analog control signal; An analog signal conditioning network, connected to the drive module, is used to adjust its network parameters in response to the N-bit analog control signal, so as to calibrate the performance of the analog circuit inside the integrated circuit.

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